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authorAndrzej Głąbek <andrzej.glabek@nordicsemi.no>2021-05-19 11:04:30 +0200
committerDavid Hu <david.hu@arm.com>2021-05-20 15:55:05 +0200
commit9d93424a12b8cc2ba56518f76edadeaabc29e143 (patch)
tree5e2b41a36f09c4e391396ea7d2d533f15b4c2045 /platform
parenta0165475447de055b00b7655f2fc573b24173101 (diff)
downloadtrusted-firmware-m-9d93424a12b8cc2ba56518f76edadeaabc29e143.tar.gz
platform: Enable instruction cache on platforms with nRF SoCs
Instruction cache in both nRF5340 and nRF9160 is disabled by default and can be enabled only from secure code. Extend configuration routines in targets that use these SoCs with statements that enable the cache. The affected targets are: - lairdconnectivity/bl5340_dvk_cpuapp - nordic_nrf/nrf5340dk_nrf5340_cpuapp - nordic_nrf/nrf9160dk_nrf9160 Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no> Change-Id: Ic6d6d6c7f5bf1bccee5c4effb9026f21f846217a
Diffstat (limited to 'platform')
-rw-r--r--platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c5
-rw-r--r--platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c5
-rw-r--r--platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c6
3 files changed, 16 insertions, 0 deletions
diff --git a/platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c b/platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c
index a5734e757..8077176af 100644
--- a/platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c
+++ b/platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c
@@ -282,6 +282,11 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
+ /* Enable the instruction and data cache (this can be done only from secure
+ * code; that's why it is placed here).
+ */
+ NRF_CACHE->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
+
return TFM_PLAT_ERR_SUCCESS;
}
diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c b/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
index 8239fd5f4..69bbcaedc 100644
--- a/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
+++ b/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
@@ -274,6 +274,11 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
+ /* Enable the instruction and data cache (this can be done only from secure
+ * code; that's why it is placed here).
+ */
+ NRF_CACHE->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
+
return TFM_PLAT_ERR_SUCCESS;
}
diff --git a/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c b/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
index 277e1829b..17d786170 100644
--- a/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
+++ b/platform/ext/target/nordic_nrf/common/nrf9160/target_cfg.c
@@ -22,6 +22,7 @@
#include <spu.h>
#include <nrfx.h>
+#include <hal/nrf_nvmc.h>
struct platform_data_t tfm_peripheral_timer0 = {
NRF_TIMER0_S_BASE,
@@ -230,6 +231,11 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
/* GPIO pin configuration */
spu_gpio_config_non_secure(0, false);
+ /* Enable the instruction cache (this can be done only from secure code;
+ * that's why it is placed here).
+ */
+ nrf_nvmc_icache_config_set(NRF_NVMC, NRF_NVMC_ICACHE_ENABLE);
+
return TFM_PLAT_ERR_SUCCESS;
}