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authorAndrei Narkevitch <ainh@cypress.com>2020-06-16 19:34:23 -0700
committerDavid Hu <david.hu@arm.com>2020-08-10 02:37:59 +0000
commit76c4d43e994cc927d6a5da226f07cd80b0d73ecb (patch)
treea75beaf6cdd8ebebc47e72552309f357a8769fff /platform
parentae70d8d4633301a807625eb23a0fdae6f378390f (diff)
downloadtrusted-firmware-m-76c4d43e994cc927d6a5da226f07cd80b0d73ecb.tar.gz
Platform: PSoC64: Reintroduce executable SRAM area
In Test Mode (during programming Flash via OOCD) CM0P/CM4 cores should avoid executing code from Flash because it can interfere with erase/program operations. Instead, an executable SRAM area needs to be defined to facilitate Flash erase and write operations. Reserve SMPU9 to override SMPU8 protection settings to give the area code execution permission. Signed-off-by: Andrei Narkevitch <ainh@cypress.com> Change-Id: I94cd8615b418e98fed89fef25f4554ce573a41a3
Diffstat (limited to 'platform')
-rw-r--r--platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/RTE_Device.h2
-rw-r--r--platform/ext/target/cypress/psoc64/partition/region_defs.h14
-rw-r--r--platform/ext/target/cypress/psoc64/smpu_config.h44
3 files changed, 53 insertions, 7 deletions
diff --git a/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/RTE_Device.h b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/RTE_Device.h
index 5e38b0cc48..98dfe362c3 100644
--- a/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/RTE_Device.h
+++ b/platform/ext/target/cypress/psoc64/CMSIS_Driver/Config/RTE_Device.h
@@ -67,7 +67,7 @@
// <e> MPC (Memory Protection Controller) [Driver_SMPU9]
// <i> Configuration settings for Driver_SMPU9 in component ::Drivers:MPC
-#define RTE_SMPU9 0
+#define RTE_SMPU9 1
// </e> MPC (Memory Protection Controller) [Driver_SMPU9]
// <e> MPC (Memory Protection Controller) [Driver_SMPU10]
diff --git a/platform/ext/target/cypress/psoc64/partition/region_defs.h b/platform/ext/target/cypress/psoc64/partition/region_defs.h
index b4616f5bf1..edfb26ec91 100644
--- a/platform/ext/target/cypress/psoc64/partition/region_defs.h
+++ b/platform/ext/target/cypress/psoc64/partition/region_defs.h
@@ -65,7 +65,8 @@
*
* 0x0800_0000 - 0x0802_FFFF Secure (192KB)
* 0x0800_0000 - 0x0800_7FFF Secure unprivileged data (S_UNPRIV_DATA_SIZE, 32KB)
- * 0x0800_8000 - 0x0802_FFFF Secure priviliged data (S_PRIV_DATA_SIZE, 160KB)
+ * 0x0800_8000 - 0x0802_F7FF Secure priviliged data (S_PRIV_DATA_SIZE, 158KB)
+ * 0x0802_F800 - 0x0802_FFFF Secure priv code executable from RAM (S_RAM_CODE_SIZE, 2KB)
*
* 0x0803_0000 - 0x080E_7FFF Non-secure (736KB)
* 0x0803_0000 - 0x080E_6FFF Non-secure OS/App (732KB)
@@ -118,10 +119,12 @@
#define S_DATA_START (S_RAM_ALIAS(0))
#define S_UNPRIV_DATA_SIZE 0x08000
-#define S_PRIV_DATA_SIZE 0x28000
+#define S_PRIV_DATA_SIZE 0x27800
+/* Reserve 2KB for RAM-based executable code */
+#define S_RAM_CODE_SIZE 0x800
/* Secure data area */
-#define S_DATA_SIZE (S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE)
+#define S_DATA_SIZE (S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE + S_RAM_CODE_SIZE)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
/* We need the privileged data area to be aligned so that an SMPU
@@ -142,6 +145,11 @@
#define S_DATA_PRIV_OFFSET (S_DATA_UNPRIV_OFFSET + S_UNPRIV_DATA_SIZE)
#define S_DATA_PRIV_START S_RAM_ALIAS(S_DATA_PRIV_OFFSET)
+/* Reserve area for RAM-based executable code right after secure unprivileged
+ * and privileged data areas*/
+#define S_RAM_CODE_OFFSET (S_DATA_PRIV_OFFSET + S_PRIV_DATA_SIZE)
+#define S_RAM_CODE_START S_RAM_ALIAS(S_RAM_CODE_OFFSET)
+
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
(NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
diff --git a/platform/ext/target/cypress/psoc64/smpu_config.h b/platform/ext/target/cypress/psoc64/smpu_config.h
index faa3f78334..37295f82e9 100644
--- a/platform/ext/target/cypress/psoc64/smpu_config.h
+++ b/platform/ext/target/cypress/psoc64/smpu_config.h
@@ -238,10 +238,48 @@
#error "Flash layout has changed - SMPU8 doesn't immediately follow SMPU7"
#endif
-/* SMPU7 and SMPU8 should exactly cover the privileged secure SRAM */
+/* SMPU7 and SMPU8 should exactly cover the privileged secure SRAM which
+ * consists of S_PRIV_DATA and S_RAM_CODE
+ */
#if ((6*REGIONSIZE_TO_BYTES(SMPU7_REGIONSIZE)/8) + \
- REGIONSIZE_TO_BYTES(SMPU8_REGIONSIZE)) != S_PRIV_DATA_SIZE
-#error "SMPU7_REGIONSIZE+SMPU8_REGIONSIZE should match S_PRIV_DATA_SIZE"
+ REGIONSIZE_TO_BYTES(SMPU8_REGIONSIZE)) != \
+ (S_PRIV_DATA_SIZE + S_RAM_CODE_SIZE)
+#error "SMPU7+SMPU8 REGIONSIZE should match privileged secure SRAM size"
+#endif
+
+/* SMPU9 - 2KB of privileged executable data in SRAM
+ * Note: Region resides in subregion 7 of SMPU 8*/
+#define SMPU9_BASE S_RAM_CODE_START
+#define SMPU9_REGIONSIZE PROT_SIZE_2KB_BIT_SHIFT
+#define SMPU9_SLAVE_CONFIG {\
+ .address = (void *)SMPU9_BASE, \
+ .regionSize = (cy_en_prot_size_t) SMPU9_REGIONSIZE, \
+ .subregions = ALL_ENABLED, \
+ .userPermission = CY_PROT_PERM_DISABLED, \
+ .privPermission = CY_PROT_PERM_RX, \
+ .secure = false, \
+ .pcMatch = false, \
+ .pcMask = SECURE_PCS_MASK, \
+}
+#define SMPU9_MASTER_CONFIG COMMON_SMPU_MASTER_CONFIG
+
+/* SMPU requires base address aligned to size */
+#if SMPU9_BASE % REGIONSIZE_TO_BYTES(SMPU9_REGIONSIZE)
+#error "Flash layout has changed - SMPU9 needs updating"
+#endif
+
+#if S_RAM_CODE_SIZE != REGIONSIZE_TO_BYTES(SMPU9_REGIONSIZE)
+#error "SMPU9_REGIONSIZE is not equal S_RAM_CODE_SIZE"
+#endif
+
+/* SMPU9 should be contained within SMPU8 */
+#if SMPU9_BASE < SMPU8_BASE
+#error "SMPU9 is below SMPU8"
+#endif
+
+#if (SMPU9_BASE + REGIONSIZE_TO_BYTES(SMPU9_REGIONSIZE)) > \
+ (SMPU8_BASE + REGIONSIZE_TO_BYTES(SMPU8_REGIONSIZE))
+#error "SMPU9 is not within SMPU8"
#endif
#endif /* __SMPU_CONFIG_H__ */