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authorIoannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>2021-06-04 10:23:59 +0200
committerAnton Komlev <Anton.Komlev@arm.com>2021-06-08 01:46:58 +0200
commit32a7431436b7ee7110880f128e0519900aede767 (patch)
tree057f0664ccc92142bfe80dc6022953a7c4eb6e4c /platform
parent4d1b7b38e75707c04efba4dc3b73ca8f36cacae2 (diff)
downloadtrusted-firmware-m-32a7431436b7ee7110880f128e0519900aede767.tar.gz
platform: nordic: rearrange veneer placement on builds without BL2
For builds without BL2, or when BL2 will be booting a single combined S and NS image, we force placing the veneers section at the end of the image (position 3), so as not to waste space as a result of the nRF veneer section alignment requirements. For regular builds with BL2 we keep the veneer placement as is (positions 1 or 2 depending on whether PSA_API_TEST_NS is defined). Change-Id: I292f9ec996445b9d7acedd1db24117d9345f3346 Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Diffstat (limited to 'platform')
-rw-r--r--platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld34
1 files changed, 32 insertions, 2 deletions
diff --git a/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld b/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld
index c2fb86803..040dd45e1 100644
--- a/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld
+++ b/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld
@@ -40,6 +40,16 @@ MEMORY
#else
#define VENEERS() \
/* \
+ * We need a dummy section to "reset" the location counter to FLASH if the \
+ * previous section was > RAM. Not sure why. This avoids the error \
+ * "ERROR: CMSE stub ... too far ... from destination" Make a dummy \
+ * assignment so the section is not optimized away. \
+ */ \
+ .sg_start_dummy : ALIGN(4) \
+ { \
+ SG_START_DUMMY_UNUSED = .; \
+ } > FLASH \
+ /* \
* Place the CMSE Veneers (containing the SG instructions) in a correctly \
* aligned region so that the SAU can programmed to just set this region as \
* Non-Secure Callable. \
@@ -67,6 +77,22 @@ MEMORY
<= CMSE_VENEER_REGION_SIZE, "Veneer region overflowed")
#endif
+/* For builds without BL2, or when BL2 will be booting a single
+ * combined S and NS image, we force placing the veneers section
+ * at the end of the image (position 3), so as not to waste space
+ * as a result of the nRF veneer section alignment requirements.
+ * For regular builds with BL2 we keep the veneer placement as is
+ * (positions 1 or 2 depending on whether PSA_API_TEST_NS is
+ * defined).
+ */
+#if !defined(BL2) || (MCUBOOT_IMAGE_NUMBER == 1)
+#define VENEER_POS 3
+#elif defined(PSA_API_TEST_NS)
+#define VENEER_POS 1
+#else
+#define VENEER_POS 2
+#endif
+
__heap_size__ = S_HEAP_SIZE;
__psp_stack_size__ = S_PSP_STACK_SIZE;
__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT;
@@ -248,7 +274,7 @@ SECTIONS
#endif /* TFM_LVL != 1 */
-#ifdef PSA_API_TEST_NS
+#if VENEER_POS == 1
VENEERS()
#endif
@@ -276,7 +302,7 @@ VENEERS()
} > FLASH
-#ifndef PSA_API_TEST_NS
+#if VENEER_POS == 2
VENEERS()
#endif
@@ -595,6 +621,10 @@ VENEERS()
} > RAM AT> FLASH
#endif
+#if VENEER_POS == 3
+VENEERS()
+#endif
+
Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START;
#ifdef BL2