diff options
author | RaymondNgun <raymond.ngun@infineon.com> | 2021-06-23 16:41:46 -0700 |
---|---|---|
committer | David Hu <david.hu@arm.com> | 2021-07-08 09:56:52 +0200 |
commit | fb8926ba1b92c7b40a53980e2981c60d4de1cc3d (patch) | |
tree | 2e60af77d7f688bdf630085952649828b198dd42 /platform/ext | |
parent | 310d8b22bd7819b5db16fbe378647808adf36e22 (diff) | |
download | trusted-firmware-m-fb8926ba1b92c7b40a53980e2981c60d4de1cc3d.tar.gz |
psoc64: Add UART initialization
There was a dependancy on the bootloader initializing UART. This
adds UART initialization to break that dependancy.
Change-Id: Icfd8c5987ba29f2183025a8c157e1175343fb82e
Signed-off-by: Raymond Ngun <raymond.ngun@infineon.com>
Diffstat (limited to 'platform/ext')
-rwxr-xr-x | platform/ext/target/cypress/psoc64/target_cfg.c | 39 | ||||
-rw-r--r-- | platform/ext/target/cypress/psoc64/target_cfg.h | 32 |
2 files changed, 69 insertions, 2 deletions
diff --git a/platform/ext/target/cypress/psoc64/target_cfg.c b/platform/ext/target/cypress/psoc64/target_cfg.c index c305b0c18d..f596b736c8 100755 --- a/platform/ext/target/cypress/psoc64/target_cfg.c +++ b/platform/ext/target/cypress/psoc64/target_cfg.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 Arm Limited - * Copyright (c) 2019-2020, Cypress Semiconductor Corporation. All rights reserved. + * Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -56,6 +56,40 @@ const struct memory_region_limits memory_regions = { REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base); #endif /* BL2 */ +/* UART RX and TX pins */ +const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_UART_RX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_UART_TX_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; + /* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field, * otherwise the processor ignores the write. */ @@ -133,6 +167,9 @@ void platform_init(void) SPMLOG_INFMSG("WARNING: Failed to configure timer1 clock\r\n"); } + Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config); + Cy_GPIO_Pin_Init(CYBSP_UART_TX_PORT, CYBSP_UART_TX_PIN, &CYBSP_UART_TX_config); + Cy_Platform_Init(); #ifdef TFM_ENABLE_SLIH_TEST diff --git a/platform/ext/target/cypress/psoc64/target_cfg.h b/platform/ext/target/cypress/psoc64/target_cfg.h index d2d9c61a5b..e0f9b4e613 100644 --- a/platform/ext/target/cypress/psoc64/target_cfg.h +++ b/platform/ext/target/cypress/psoc64/target_cfg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018-2020 ARM Limited - * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved. + * Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -24,6 +24,36 @@ #define TFM_DRIVER_STDIO Driver_USART5 #define NS_DRIVER_STDIO Driver_USART5 +/* UART pins HSIOM routing */ +#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX +#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX + +/* UART pins configuration */ +#define CYBSP_UART_RX_ENABLED 1U +#define CYBSP_UART_RX_PORT GPIO_PRT5 +#define CYBSP_UART_RX_PORT_NUM 5U +#define CYBSP_UART_RX_PIN 0U +#define CYBSP_UART_RX_NUM 0U +#define CYBSP_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_UART_RX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_0_HSIOM + #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM +#define CYBSP_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn +#define CYBSP_UART_TX_ENABLED 1U +#define CYBSP_UART_TX_PORT GPIO_PRT5 +#define CYBSP_UART_TX_PORT_NUM 5U +#define CYBSP_UART_TX_PIN 1U +#define CYBSP_UART_TX_NUM 1U +#define CYBSP_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_UART_TX_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_5_pin_1_HSIOM + #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM +#define CYBSP_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn + /** * \brief Store the addresses of memory regions */ |