diff options
author | Minos Galanakis <minos.galanakis@arm.com> | 2021-03-11 10:49:58 +0000 |
---|---|---|
committer | Minos Galanakis <minos.galanakis@arm.com> | 2021-03-11 19:09:39 +0100 |
commit | dfefe252cfa954c9075a30037e7cdf05206e50a6 (patch) | |
tree | aa3dfa25e4b2df316d407d1f51eb4b1911ee8fe3 | |
parent | 667995b48471f1480eeea6fce9dc0223c2bc9771 (diff) | |
download | trusted-firmware-m-dfefe252cfa954c9075a30037e7cdf05206e50a6.tar.gz |
Platform: Remove sse200-aws platform code (Deprecation)
This patch removes the platform's
code-base and documentation.
Signed-off-by: Minos Galanakis <minos.galanakis@arm.com>
Change-Id: Ib0f668800dd3571f0f7c10dc3954d1d62a420fb3
59 files changed, 2 insertions, 11571 deletions
diff --git a/docs/getting_started/tfm_build_instruction_iar.rst b/docs/getting_started/tfm_build_instruction_iar.rst index 8a6e00709b..2ee9196565 100644 --- a/docs/getting_started/tfm_build_instruction_iar.rst +++ b/docs/getting_started/tfm_build_instruction_iar.rst @@ -11,7 +11,7 @@ Notes for building with IARARM IAR Embedded Workbench for ARM (EWARM) versions 8.42 or later are required. - Currently the MUSCA_B1, MUSCA_S1 and SSE-200_AWS targets are not supported with IARARM, + Currently the MUSCA_B1 and MUSCA_S1 targets are not supported with IARARM, due to lack of testing. The FVP_SSE300_MPS2 target is currently not supported by IARARM. cmake needs to be version 3.14 or newer. @@ -64,4 +64,4 @@ Alternately using traditional cmake syntax cmake .. -DTFM_PLATFORM=mps2/an521 -DTFM_TOOLCHAIN_FILE=../toolchain_IARARM.cmake -DTEST_S=ON -DTEST_NS=ON make install - *Copyright (c) 2020, Arm Limited. All rights reserved.* + *Copyright (c) 2020-2021, Arm Limited. All rights reserved.* diff --git a/docs/getting_started/tfm_integration_guide.rst b/docs/getting_started/tfm_integration_guide.rst index fd964cdcbf..9c95856fd2 100644 --- a/docs/getting_started/tfm_integration_guide.rst +++ b/docs/getting_started/tfm_integration_guide.rst @@ -27,7 +27,6 @@ The hardware platforms currently supported are: - Musca-B1 test chip board (Cortex-M33 SSE-200 subsystem) - Musca-S1 test chip board (Cortex-M33 SSE-200 subsystem) - CoreLink SSE-200 Subsystem for MPS3 (AN524) -- DesignStart FPGA on Cloud: Cortex-M33 based platform (SSE-200_AWS) - STM32L5xx: Cortex-M33 based platform (STM32L562 and STM32L552 socs) - nRF9160 DK (Cortex-M33) - nRF5340 PDK/DK (Cortex-M33 Application MCU) @@ -53,9 +52,6 @@ More information about the Musca-S1 test chip board can be found in: More information about subsystems supported by the MPS3 board can be found in: `MPS3 homepage <https://www.arm.com/products/development-tools/development-boards/mps3>`__ -More information about the SSE-200_AWS platform can be found in: -`SSE-200_AWS product page <https://aws.amazon.com/marketplace/pp/ARM-DesignStart-FPGA-on-Cloud-Cortex-M33-based-pla/B082DMMTLW>`__ - More information about the Corstone-300 FVPs can be found in: `Arm Ecosystem FVPs homepage <https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps>`__ diff --git a/docs/getting_started/tfm_secure_boot.rst b/docs/getting_started/tfm_secure_boot.rst index eeb2ccac0a..82c1381a28 100644 --- a/docs/getting_started/tfm_secure_boot.rst +++ b/docs/getting_started/tfm_secure_boot.rst @@ -248,8 +248,6 @@ modes are supported by which platforms: +---------------------+-----------------+---------------+----------+----------------+--------------+ | PSoC64 | Yes | No | No | No | No | +---------------------+-----------------+---------------+----------+----------------+--------------+ -| SSE-200_AWS | Yes | Yes | Yes | Yes | No | -+---------------------+-----------------+---------------+----------+----------------+--------------+ | STM_DISCO_L562QE | No | Yes | No | No | No | +---------------------+-----------------+---------------+----------+----------------+--------------+ | STM_NUCLEO_L552ZE_Q | No | Yes | No | No | No | diff --git a/docs/introduction/readme.rst b/docs/introduction/readme.rst index 8b0dd8ef14..3f0cc8598a 100644 --- a/docs/introduction/readme.rst +++ b/docs/introduction/readme.rst @@ -133,8 +133,6 @@ Platforms supported <https://developer.arm.com/tools-and-software/development-boards/iot-test-chips-and-boards/musca-s1-test-chip-board>`_ - `FPGA image loaded on MPS3 board (AN524). <https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3>`_ - - `Arm DesignStart FPGA on AWS Cloud. - <https://developer.arm.com/docs/101965/0102/arm-designstart-fpga-on-cloud-arm-ds-getting-started>`_ - `LPC55S69. <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpcxpresso55s69-development-board:LPC55S69-EVK>`_ - `NUCLEO L552ZE Q. diff --git a/platform/ext/target/mps2/sse-200_aws/CMakeLists.txt b/platform/ext/target/mps2/sse-200_aws/CMakeLists.txt deleted file mode 100644 index 3e24b87f13..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/CMakeLists.txt +++ /dev/null @@ -1,156 +0,0 @@ -#------------------------------------------------------------------------------- -# Copyright (c) 2020-2021, Arm Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# -#------------------------------------------------------------------------------- - -cmake_policy(SET CMP0076 NEW) -set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) - -message(DEPRECATION "${TFM_PLATFORM} has been marked for deprecation.") - -#========================= Platform region defs ===============================# - -target_include_directories(platform_region_defs - INTERFACE - partition -) - -#========================= Platform common defs ===============================# - -# Specify the location of platform specific build dependencies. -target_sources(tfm_s - PRIVATE - $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/armclang/startup_cmsdk_sse-200_aws_s.s> - $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/gcc/startup_cmsdk_sse-200_aws_s.S> - $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/iar/startup_cmsdk_sse-200_aws_s.s> -) -target_add_scatter_file(tfm_s - $<$<C_COMPILER_ID:ARMClang>:${CMAKE_SOURCE_DIR}/platform/ext/common/armclang/tfm_common_s.sct> - $<$<C_COMPILER_ID:GNU>:${CMAKE_SOURCE_DIR}/platform/ext/common/gcc/tfm_common_s.ld> - $<$<C_COMPILER_ID:IAR>:${CMAKE_SOURCE_DIR}/platform/ext/common/iar/tfm_common_s.icf> -) - -if(NS) - target_sources(tfm_ns - PRIVATE - $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/armclang/startup_cmsdk_sse-200_aws_ns.s> - $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/gcc/startup_cmsdk_sse-200_aws_ns.S> - $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/iar/startup_cmsdk_sse-200_aws_ns.s> - ) - target_add_scatter_file(tfm_ns - $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/armclang/sse-200_aws_ns.sct> - $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/gcc/sse-200_aws_ns.ld> - $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/iar/sse-200_aws_ns.icf> - ) - target_link_libraries(CMSIS_5_tfm_ns - INTERFACE - CMSIS_5_RTX_V8MBN - ) -endif() - -if(BL2) - target_sources(bl2 - PRIVATE - $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/armclang/startup_cmsdk_sse-200_aws_bl2.s> - $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/gcc/startup_cmsdk_sse-200_aws_bl2.S> - $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/iar/startup_cmsdk_sse-200_aws_bl2.s> - ) - target_add_scatter_file(bl2 - $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/armclang/sse-200_aws_bl2.sct> - $<$<C_COMPILER_ID:GNU>:${CMAKE_CURRENT_SOURCE_DIR}/gcc/sse-200_aws_bl2.ld> - $<$<C_COMPILER_ID:IAR>:${CMAKE_CURRENT_SOURCE_DIR}/iar/sse-200_aws_bl2.icf> - ) -endif() - -#========================= Platform Secure ====================================# - -target_include_directories(platform_s - PUBLIC - . - ../common - cmsis_drivers - native_drivers - partition - retarget - cmsis_core - native_drivers/timer_cmsdk - ${PLATFORM_DIR}/.. -) - -target_sources(platform_s - PRIVATE - cmsis_drivers/Driver_Flash.c - cmsis_drivers/Driver_SSE-200_AWS_MPC.c - cmsis_drivers/Driver_PPC.c - cmsis_drivers/Driver_USART.c - retarget/platform_retarget_dev.c - cmsis_core/system_cmsdk_sse-200_aws.c - native_drivers/mpc_sie_drv.c - native_drivers/mpu_armv8m_drv.c - native_drivers/ppc_sse200_drv.c - spm_hal.c - tfm_hal_isolation.c - target_cfg.c - native_drivers/ppc_sse200_drv.c - native_drivers/uart_cmsdk_drv.c - native_drivers/timer_cmsdk/timer_cmsdk_drv.c - ${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_isolation_mpu_v8m.c - $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/plat_test.c> - $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> -) - -target_compile_options(platform_s - PUBLIC - ${COMPILER_CMSE_FLAG} -) - -#========================= Platform Non-Secure ================================# - -target_sources(platform_ns - PRIVATE - native_drivers/uart_cmsdk_drv.c - native_drivers/timer_cmsdk/timer_cmsdk_drv.c - cmsis_drivers/Driver_USART.c - retarget/platform_retarget_dev.c - cmsis_core/system_cmsdk_sse-200_aws.c - $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/plat_test.c> - $<$<BOOL:${TFM_PARTITION_PLATFORM}>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> -) - -target_include_directories(platform_ns - PUBLIC - . - ../common - ${PLATFORM_DIR}/.. - retarget - cmsis_core - native_drivers - native_drivers/timer_cmsdk -) - -#========================= Platform BL2 =======================================# - -if(BL2) - target_sources(platform_bl2 - PRIVATE - boot_hal.c - retarget/platform_retarget_dev.c - cmsis_core/system_cmsdk_sse-200_aws.c - cmsis_drivers/Driver_Flash.c - native_drivers/uart_cmsdk_drv.c - cmsis_drivers/Driver_USART.c - ) - - target_include_directories(platform_bl2 - PUBLIC - partition - cmsis_core - retarget - PRIVATE - . - ${PLATFORM_DIR}/.. - native_drivers - ) -endif() diff --git a/platform/ext/target/mps2/sse-200_aws/RTE_Device.h b/platform/ext/target/mps2/sse-200_aws/RTE_Device.h deleted file mode 100644 index 43787170aa..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/RTE_Device.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] -// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART -#define RTE_USART0 1 -// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] - -// <e> FLASH (Flash Memory) [Driver_FLASH0] -// <i> Configuration settings for Driver_FLASH0 in component ::Drivers:FLASH -#define RTE_FLASH0 1 -// </e> FLASH (Flash Memory) [Driver_FLASH0] - -// <e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] -// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC -#define RTE_ISRAM0_MPC 0 -// </e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] - -// <e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] -// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC -#define RTE_ISRAM1_MPC 0 -// </e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] - -// <e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC] -// <i> Configuration settings for Driver_ISRAM2_MPC in component ::Drivers:MPC -#define RTE_ISRAM2_MPC 0 -// </e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC] - -// <e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC] -// <i> Configuration settings for Driver_ISRAM3_MPC in component ::Drivers:MPC -#define RTE_ISRAM3_MPC 0 -// </e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC] - -// <e> MPC (Memory Protection Controller) [Driver_SSRAM1_MPC] -// <i> Configuration settings for Driver_SSRAM1_MPC in component ::Drivers:MPC -#define RTE_SSRAM1_MPC 1 -// </e> MPC (Memory Protection Controller) [Driver_SSRAM1_MPC] - -// <e> MPC (Memory Protection Controller) [Driver_SSRAM2_MPC] -// <i> Configuration settings for Driver_SSRAM2_MPC in component ::Drivers:MPC -#define RTE_SSRAM2_MPC 1 -// </e> MPC (Memory Protection Controller) [Driver_SSRAM2_MPC] - -// <e> MPC (Memory Protection Controller) [Driver_SSRAM3_MPC] -// <i> Configuration settings for Driver_SSRAM3_MPC in component ::Drivers:MPC -#define RTE_SSRAM3_MPC 0 -// </e> MPC (Memory Protection Controller) [Driver_SSRAM3_MPC] - -// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0] -// <i> Configuration settings for Driver_AHB_PPCEXP0 in component ::Drivers:MPC -#define RTE_AHB_PPCEXP0 0 -// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0] - -// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP1] -// <i> Configuration settings for Driver_AHB_PPCEXP1 in component ::Drivers:MPC -#define RTE_AHB_PPCEXP1 0 -// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP1] - -// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP2] -// <i> Configuration settings for Driver_AHB_PPCEXP2 in component ::Drivers:MPC -#define RTE_AHB_PPCEXP2 0 -// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP2] - -// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP3] -// <i> Configuration settings for Driver_AHB_PPCEXP3 in component ::Drivers:MPC -#define RTE_AHB_PPCEXP3 0 -// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP3] - -// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0] -// <i> Configuration settings for Driver_APB_PPC0 in component ::Drivers:MPC -#define RTE_APB_PPC0 0 -// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0] - -// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1] -// <i> Configuration settings for Driver_APB_PPC1 in component ::Drivers:MPC -#define RTE_APB_PPC1 0 -// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1] - -// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0] -// <i> Configuration settings for Driver_APB_PPCEXP0 in component ::Drivers:MPC -#define RTE_APB_PPCEXP0 0 -// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0] - -// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1] -// <i> Configuration settings for Driver_APB_PPCEXP1 in component ::Drivers:MPC -#define RTE_APB_PPCEXP1 0 -// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1] - -// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2] -// <i> Configuration settings for Driver_APB_PPCEXP2 in component ::Drivers:MPC -#define RTE_APB_PPCEXP2 1 -// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2] - -// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3] -// <i> Configuration settings for Driver_APB_PPCEXP3 in component ::Drivers:MPC -#define RTE_APB_PPCEXP3 0 -// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP3] - -#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/mps2/sse-200_aws/armclang/sse-200_aws_bl2.sct b/platform/ext/target/mps2/sse-200_aws/armclang/sse-200_aws_bl2.sct deleted file mode 100644 index 309bddfdae..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/armclang/sse-200_aws_bl2.sct +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "region_defs.h" - -LR_CODE BL2_CODE_START { - ER_CODE BL2_CODE_START BL2_CODE_SIZE { - *.o (RESET +First) - * (+RO) - } - - /* Base address of bootloader data area */ - BL2_DATA_START S_DATA_START { - } - - TFM_SHARED_DATA +0 ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE { - } - - ER_DATA +0 { - * (+ZI +RW) - } - - /* MSP */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE { - } - - ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE { - } - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - SRAM_WATERMARK +0 EMPTY 0x0 { - } - - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(SRAM_WATERMARK) <= BL2_DATA_START + BL2_DATA_SIZE) -} diff --git a/platform/ext/target/mps2/sse-200_aws/armclang/sse-200_aws_ns.sct b/platform/ext/target/mps2/sse-200_aws/armclang/sse-200_aws_ns.sct deleted file mode 100644 index e25b2d72fe..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/armclang/sse-200_aws_ns.sct +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "region_defs.h" - -LR_CODE NS_CODE_START { - ER_CODE NS_CODE_START NS_CODE_SIZE { - *.o (RESET +First) - * (+RO) - } - - ER_DATA NS_DATA_START { - * (+ZI +RW) - } - - /* MSP */ - ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE { - } - - /* PSP */ - ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE { - } - - ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE { - } - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - SRAM_WATERMARK +0 EMPTY 0x0 { - } - - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(SRAM_WATERMARK) <= NS_DATA_START + NS_DATA_SIZE) -} diff --git a/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_bl2.s b/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_bl2.s deleted file mode 100644 index a7bf729c30..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_bl2.s +++ /dev/null @@ -1,232 +0,0 @@ -;/* -; * Copyright (c) 2016-2019 Arm Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -; -; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s - -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD SecureFault_Handler ; Secure Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Core IoT Interrupts - DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler - DCD TIMER0_Handler ; - 3 TIMER 0 Handler - DCD TIMER1_Handler ; - 4 TIMER 1 Handler - DCD DUALTIMER_Handler ; - 5 Dual Timer Handler - DCD MHU0_Handler ; - 6 Message Handling Unit 0 - DCD MHU1_Handler ; - 7 Message Handling Unit 1 - DCD 0 ; Reserved - 8 - DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler - DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler - DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler - DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler - DCD 0 ; Reserved - 13 - DCD 0 ; Reserved - 14 - DCD 0 ; Reserved - 15 - DCD 0 ; Reserved - 16 - DCD 0 ; Reserved - 17 - DCD 0 ; Reserved - 18 - DCD 0 ; Reserved - 19 - DCD 0 ; Reserved - 20 - DCD 0 ; Reserved - 21 - DCD 0 ; Reserved - 22 - DCD 0 ; Reserved - 23 - DCD 0 ; Reserved - 24 - DCD 0 ; Reserved - 25 - DCD 0 ; Reserved - 26 - DCD 0 ; Reserved - 27 - DCD 0 ; Reserved - 28 - DCD 0 ; Reserved - 29 - DCD 0 ; Reserved - 30 - DCD 0 ; Reserved - 31 - ; External Interrupts - DCD UARTRX0_Handler ; 32 UART 0 RX Handler - DCD UARTTX0_Handler ; 33 UART 0 TX Handler - DCD 0 ; 34 Reserved - DCD 0 ; 35 Reserved - DCD 0 ; 36 Reserved - DCD 0 ; 37 Reserved - DCD 0 ; 38 Reserved - DCD 0 ; 39 Reserved - DCD 0 ; 40 Reserved - DCD 0 ; 41 Reserved - DCD UART0_Handler ; 42 UART 0 combined Handler - DCD 0 ; 43 Reserved - DCD 0 ; 44 Reserved - DCD 0 ; 45 Reserved - DCD 0 ; 46 Reserved - DCD UARTOVF_Handler ; 47 UART 0 Overflow Handler - DCD 0 ; 48 Reserved - DCD 0 ; 49 Reserved - DCD 0 ; 50 Reserved - DCD 0 ; 51 Reserved - DCD 0 ; 52 Reserved - DCD 0 ; 53 Reserved - DCD 0 ; 54 Reserved - DCD 0 ; 55 Reserved - DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - DCD DMA0_Handler ; 58 DMA 0 Combined Handler - DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - DCD DMA1_Handler ; 61 DMA 1 Combined Handler - DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - DCD DMA2_Handler ; 64 DMA 2 Combined Handler - DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - DCD DMA3_Handler ; 67 DMA 3 Combined Handler - DCD 0 ; 68 Reserved - DCD 0 ; 69 Reserved - DCD 0 ; 70 Reserved - DCD 0 ; 71 Reserved - DCD 0 ; 72 Reserved - DCD 0 ; 73 Reserved - DCD 0 ; 74 Reserved - DCD 0 ; 75 Reserved - DCD 0 ; 76 Reserved - DCD 0 ; 77 Reserved - DCD 0 ; 78 Reserved - DCD 0 ; 79 Reserved - DCD 0 ; 80 Reserved - DCD 0 ; 81 Reserved - DCD 0 ; 82 Reserved - DCD 0 ; 83 Reserved - DCD 0 ; 84 Reserved - DCD 0 ; 85 Reserved - DCD 0 ; 86 Reserved - DCD 0 ; 87 Reserved - DCD 0 ; 88 Reserved - DCD 0 ; 89 Reserved - DCD 0 ; 90 Reserved - DCD 0 ; 91 Reserved - DCD 0 ; 92 Reserved - DCD 0 ; 93 Reserved - DCD 0 ; 94 Reserved - DCD 0 ; 95 Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - ; Only run on core 0 - MOV r0, #0x50000000 - ADD r0, #0x0001F000 - LDR r0, [r0] - CMP r0,#0 -not_the_core_to_run_on - BNE not_the_core_to_run_on - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - MACRO - Default_Handler $handler_name -$handler_name PROC - EXPORT $handler_name [WEAK] - B . - ENDP - MEND - - Default_Handler NMI_Handler - Default_Handler HardFault_Handler - Default_Handler MemManage_Handler - Default_Handler BusFault_Handler - Default_Handler UsageFault_Handler - Default_Handler SecureFault_Handler - Default_Handler SVC_Handler - Default_Handler DebugMon_Handler - Default_Handler PendSV_Handler - Default_Handler SysTick_Handler - -; Core IoT Interrupts - Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler - Default_Handler TIMER0_Handler ; - 3 TIMER 0 Handler - Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler - Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler - Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0 - Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1 - Default_Handler MPC_Handler ; - 9 MPC Combined (Secure) Handler - Default_Handler PPC_Handler ; - 10 PPC Combined (Secure) Handler - Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler - Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler -; External Interrupts - Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler - Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler - Default_Handler UART0_Handler ; 42 UART 0 combined Handler - Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler - Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler - Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler - Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler - Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler - - ALIGN - - END diff --git a/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_ns.s b/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_ns.s deleted file mode 100644 index f450776c06..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_ns.s +++ /dev/null @@ -1,223 +0,0 @@ -;/* -; * Copyright (c) 2016-2020 Arm Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -; -; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s - -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Core IoT Interrupts - DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler - DCD TIMER0_Handler ; - 3 TIMER 0 Handler - DCD TIMER1_Handler ; - 4 TIMER 1 Handler - DCD DUALTIMER_Handler ; - 5 Dual Timer Handler - DCD MHU0_Handler ; - 6 Message Handling Unit 0 - DCD MHU1_Handler ; - 7 Message Handling Unit 1 - DCD 0 ; Reserved - 8 - DCD 0 ; Reserved - 9 - DCD 0 ; Reserved - 10 - DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler - DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler - DCD 0 ; Reserved - 13 - DCD 0 ; Reserved - 14 - DCD 0 ; Reserved - 15 - DCD 0 ; Reserved - 16 - DCD 0 ; Reserved - 17 - DCD 0 ; Reserved - 18 - DCD 0 ; Reserved - 19 - DCD 0 ; Reserved - 20 - DCD 0 ; Reserved - 21 - DCD 0 ; Reserved - 22 - DCD 0 ; Reserved - 23 - DCD 0 ; Reserved - 24 - DCD 0 ; Reserved - 25 - DCD 0 ; Reserved - 26 - DCD 0 ; Reserved - 27 - DCD 0 ; Reserved - 28 - DCD 0 ; Reserved - 29 - DCD 0 ; Reserved - 30 - DCD 0 ; Reserved - 31 - ; External Interrupts - DCD UARTRX0_Handler ; 32 UART 0 RX Handler - DCD UARTTX0_Handler ; 33 UART 0 TX Handler - DCD 0 ; 34 Reserved - DCD 0 ; 35 Reserved - DCD 0 ; 36 Reserved - DCD 0 ; 37 Reserved - DCD 0 ; 38 Reserved - DCD 0 ; 39 Reserved - DCD 0 ; 40 Reserved - DCD 0 ; 41 Reserved - DCD UART0_Handler ; 42 UART 0 combined Handler - DCD 0 ; 43 Reserved - DCD 0 ; 44 Reserved - DCD 0 ; 45 Reserved - DCD 0 ; 46 Reserved - DCD UARTOVF_Handler ; 47 UART 0 Overflow Handler - DCD 0 ; 48 Reserved - DCD 0 ; 49 Reserved - DCD 0 ; 50 Reserved - DCD 0 ; 51 Reserved - DCD 0 ; 52 Reserved - DCD 0 ; 53 Reserved - DCD 0 ; 54 Reserved - DCD 0 ; 55 Reserved - DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - DCD DMA0_Handler ; 58 DMA 0 Combined Handler - DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - DCD DMA1_Handler ; 61 DMA 1 Combined Handler - DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - DCD DMA2_Handler ; 64 DMA 2 Combined Handler - DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - DCD DMA3_Handler ; 67 DMA 3 Combined Handler - DCD 0 ; 68 Reserved - DCD 0 ; 69 Reserved - DCD 0 ; 70 Reserved - DCD 0 ; 71 Reserved - DCD 0 ; 72 Reserved - DCD 0 ; 73 Reserved - DCD 0 ; 74 Reserved - DCD 0 ; 75 Reserved - DCD 0 ; 76 Reserved - DCD 0 ; 77 Reserved - DCD 0 ; 78 Reserved - DCD 0 ; 79 Reserved - DCD 0 ; 80 Reserved - DCD 0 ; 81 Reserved - DCD 0 ; 82 Reserved - DCD 0 ; 83 Reserved - DCD 0 ; 84 Reserved - DCD 0 ; 85 Reserved - DCD 0 ; 86 Reserved - DCD 0 ; 87 Reserved - DCD 0 ; 88 Reserved - DCD 0 ; 89 Reserved - DCD 0 ; 90 Reserved - DCD 0 ; 91 Reserved - DCD 0 ; 92 Reserved - DCD 0 ; 93 Reserved - DCD 0 ; 94 Reserved - DCD 0 ; 95 Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - MACRO - Default_Handler $handler_name -$handler_name PROC - EXPORT $handler_name [WEAK] - B . - ENDP - MEND - - Default_Handler NMI_Handler - Default_Handler HardFault_Handler - Default_Handler MemManage_Handler - Default_Handler BusFault_Handler - Default_Handler UsageFault_Handler - Default_Handler SecureFault_Handler - Default_Handler SVC_Handler - Default_Handler DebugMon_Handler - Default_Handler PendSV_Handler - Default_Handler SysTick_Handler - -; Core IoT Interrupts - Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler - Default_Handler TIMER0_Handler ; - 3 TIMER 0 Handler - Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler - Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler - Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0 - Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1 - Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler - Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler -; External Interrupts - Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler - Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler - Default_Handler UART0_Handler ; 42 UART 0 combined Handler - Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler - Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler - Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler - Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler - Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler - - ALIGN - - END diff --git a/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_s.s b/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_s.s deleted file mode 100644 index 2410ef5dd3..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/armclang/startup_cmsdk_sse-200_aws_s.s +++ /dev/null @@ -1,229 +0,0 @@ -;/* -; * Copyright (c) 2016-2019 Arm Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -; -; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s - -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - - IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD SecureFault_Handler ; Secure Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Core IoT Interrupts - DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler - DCD TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler - DCD TIMER1_Handler ; - 4 TIMER 1 Handler - DCD DUALTIMER_Handler ; - 5 Dual Timer Handler - DCD MHU0_Handler ; - 6 Message Handling Unit 0 - DCD MHU1_Handler ; - 7 Message Handling Unit 1 - DCD 0 ; Reserved - 8 - DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler - DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler - DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler - DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler - DCD 0 ; Reserved - 13 - DCD 0 ; Reserved - 14 - DCD 0 ; Reserved - 15 - DCD 0 ; Reserved - 16 - DCD 0 ; Reserved - 17 - DCD 0 ; Reserved - 18 - DCD 0 ; Reserved - 19 - DCD 0 ; Reserved - 20 - DCD 0 ; Reserved - 21 - DCD 0 ; Reserved - 22 - DCD 0 ; Reserved - 23 - DCD 0 ; Reserved - 24 - DCD 0 ; Reserved - 25 - DCD 0 ; Reserved - 26 - DCD 0 ; Reserved - 27 - DCD 0 ; Reserved - 28 - DCD 0 ; Reserved - 29 - DCD 0 ; Reserved - 30 - DCD 0 ; Reserved - 31 - ; External Interrupts - DCD UARTRX0_Handler ; 32 UART 0 RX Handler - DCD UARTTX0_Handler ; 33 UART 0 TX Handler - DCD 0 ; 34 Reserved - DCD 0 ; 35 Reserved - DCD 0 ; 36 Reserved - DCD 0 ; 37 Reserved - DCD 0 ; 38 Reserved - DCD 0 ; 39 Reserved - DCD 0 ; 40 Reserved - DCD 0 ; 41 Reserved - DCD UART0_Handler ; 42 UART 0 combined Handler - DCD 0 ; 43 Reserved - DCD 0 ; 44 Reserved - DCD 0 ; 45 Reserved - DCD 0 ; 46 Reserved - DCD UARTOVF_Handler ; 47 UART 0 Overflow Handler - DCD 0 ; 48 Reserved - DCD 0 ; 49 Reserved - DCD 0 ; 50 Reserved - DCD 0 ; 51 Reserved - DCD 0 ; 52 Reserved - DCD 0 ; 53 Reserved - DCD 0 ; 54 Reserved - DCD 0 ; 55 Reserved - DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - DCD DMA0_Handler ; 58 DMA 0 Combined Handler - DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - DCD DMA1_Handler ; 61 DMA 1 Combined Handler - DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - DCD DMA2_Handler ; 64 DMA 2 Combined Handler - DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - DCD DMA3_Handler ; 67 DMA 3 Combined Handler - DCD 0 ; 68 Reserved - DCD 0 ; 69 Reserved - DCD 0 ; 70 Reserved - DCD 0 ; 71 Reserved - DCD 0 ; 72 Reserved - DCD 0 ; 73 Reserved - DCD 0 ; 74 Reserved - DCD 0 ; 75 Reserved - DCD 0 ; 76 Reserved - DCD 0 ; 77 Reserved - DCD 0 ; 78 Reserved - DCD 0 ; 79 Reserved - DCD 0 ; 80 Reserved - DCD 0 ; 81 Reserved - DCD 0 ; 82 Reserved - DCD 0 ; 83 Reserved - DCD 0 ; 84 Reserved - DCD 0 ; 85 Reserved - DCD 0 ; 86 Reserved - DCD 0 ; 87 Reserved - DCD 0 ; 88 Reserved - DCD 0 ; 89 Reserved - DCD 0 ; 90 Reserved - DCD 0 ; 91 Reserved - DCD 0 ; 92 Reserved - DCD 0 ; 93 Reserved - DCD 0 ; 94 Reserved - DCD 0 ; 95 Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - CPSID i ; Disable IRQs - LDR R0, =SystemInit - BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - MACRO - Default_Handler $handler_name -$handler_name PROC - EXPORT $handler_name [WEAK] - B . - ENDP - MEND - - Default_Handler NMI_Handler - Default_Handler HardFault_Handler - Default_Handler MemManage_Handler - Default_Handler BusFault_Handler - Default_Handler UsageFault_Handler - Default_Handler SecureFault_Handler - Default_Handler SVC_Handler - Default_Handler DebugMon_Handler - Default_Handler PendSV_Handler - Default_Handler SysTick_Handler - -; Core IoT Interrupts - Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler - Default_Handler TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler - Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler - Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler - Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0 - Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1 - Default_Handler MPC_Handler ; - 9 MPC Combined (Secure) Handler - Default_Handler PPC_Handler ; - 10 PPC Combined (Secure) Handler - Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler - Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler -; External Interrupts - Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler - Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler - Default_Handler UART0_Handler ; 42 UART 0 combined Handler - Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler - Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler - Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler - Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler - Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler - - ALIGN - - END diff --git a/platform/ext/target/mps2/sse-200_aws/boot_hal.c b/platform/ext/target/mps2/sse-200_aws/boot_hal.c deleted file mode 100644 index 9e93972487..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/boot_hal.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2019-2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "cmsis.h" -#include "region.h" -#include "target_cfg.h" -#include "boot_hal.h" -#include "Driver_Flash.h" -#include "flash_layout.h" - -/* Flash device name must be specified by target */ -extern ARM_DRIVER_FLASH FLASH_DEV_NAME; - -REGION_DECLARE(Image$$, ER_DATA, $$Base)[]; -REGION_DECLARE(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)[]; -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); - -__attribute__((naked)) void boot_clear_bl2_ram_area(void) -{ - __ASM volatile( - "mov r0, #0 \n" - "subs %1, %1, %0 \n" - "Loop: \n" - "subs %1, #4 \n" - "itt ge \n" - "strge r0, [%0, %1] \n" - "bge Loop \n" - "bx lr \n" - : - : "r" (REGION_NAME(Image$$, ER_DATA, $$Base)), - "r" (REGION_NAME(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)) - : "r0", "memory" - ); -} - -int32_t boot_platform_init(void) -{ - int32_t result; - - /* Initialize stack limit register */ - uint32_t msp_stack_bottom = - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base); - - __set_MSPLIM(msp_stack_bottom); - - result = FLASH_DEV_NAME.Initialize(NULL); - if (result != ARM_DRIVER_OK) { - return 1; - } - - return 0; -} - -void boot_platform_quit(struct boot_arm_vector_table *vt) -{ - /* Clang at O0, stores variables on the stack with SP relative addressing. - * When manually set the SP then the place of reset vector is lost. - * Static variables are stored in 'data' or 'bss' section, change of SP has - * no effect on them. - */ - static struct boot_arm_vector_table *vt_cpy; - int32_t result; - - result = FLASH_DEV_NAME.Uninitialize(); - if (result != ARM_DRIVER_OK) { - while (1); - } - - vt_cpy = vt; - - __set_MSPLIM(0); - __set_MSP(vt->msp); - __DSB(); - __ISB(); - - boot_jump_to_next_image(vt_cpy->reset); -} - diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_core/cmsis.h b/platform/ext/target/mps2/sse-200_aws/cmsis_core/cmsis.h deleted file mode 100644 index 4970d08acc..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_core/cmsis.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2017-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SSE_200_AWS_CMSIS_H__ -#define __SSE_200_AWS_CMSIS_H__ - -/* SMM-SSE-200 */ -#include "sse-200_aws.h" - -#endif /*__SSE_200_AWS_CMSIS_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_core/cmsis_cpu.h b/platform/ext/target/mps2/sse-200_aws/cmsis_core/cmsis_cpu.h deleted file mode 100644 index fae26ab279..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_core/cmsis_cpu.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_CPU_H__ -#define __CMSIS_CPU_H__ - -/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ -#define __CM33_REV 0x0002U /* Core revision r0p2 */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ - -#include "core_cm33.h" - -#endif /* __CMSIS_CPU_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_core/platform_irq.h b/platform/ext/target/mps2/sse-200_aws/cmsis_core/platform_irq.h deleted file mode 100644 index 6a20eba777..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_core/platform_irq.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __ARM_LTD_SSE_200_AWS_IRQN_H__ -#define __ARM_LTD_SSE_200_AWS_IRQN_H__ - -typedef enum _IRQn_Type { - NonMaskableInt_IRQn = -14, /* Non Maskable Interrupt */ - HardFault_IRQn = -13, /* HardFault Interrupt */ - MemoryManagement_IRQn = -12, /* Memory Management Interrupt */ - BusFault_IRQn = -11, /* Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* Usage Fault Interrupt */ - SecureFault_IRQn = -9, /* Secure Fault Interrupt */ - SVCall_IRQn = -5, /* SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* Pend SV Interrupt */ - SysTick_IRQn = -1, /* System Tick Interrupt */ - NONSEC_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset - * Interrupt */ - NONSEC_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */ - S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */ - TIMER0_IRQn = 3, /* TIMER 0 Interrupt */ - TIMER1_IRQn = 4, /* TIMER 1 Interrupt */ - DUALTIMER_IRQn = 5, /* Dual Timer Interrupt */ - MHU0_IRQn = 6, /* Message Handling Unit 0 */ - MHU1_IRQn = 7, /* Message Handling Unit 1 */ - /* Reserved = 8, Reserved */ - MPC_IRQn = 9, /* MPC Combined (Secure) Interrupt */ - PPC_IRQn = 10, /* PPC Combined (Secure) Interrupt */ - MSC_IRQn = 11, /* MSC Combined (Secure) Interrput */ - BRIDGE_ERROR_IRQn = 12, /* Bridge Error Combined - * (Secure) Interrupt */ - /* Reserved = 13:31, Reserved */ - UARTRX0_IRQn = 32, /* UART 0 RX Interrupt */ - UARTTX0_IRQn = 33, /* UART 0 TX Interrupt */ - /* Reserved = 34:41, Reserved */ - UART0_IRQn = 42, /* UART 0 combined Interrupt */ - /* Reserved = 43:46, Reserved */ - UARTOVF_IRQn = 47, /* UART Overflow (0, 1, 2, 3 & 4) */ - /* Reserved = 48:55, Reserved */ - DMA0_ERROR_IRQn = 56, /* DMA 0 Error Interrupt */ - DMA0_TC_IRQn = 57, /* DMA 0 Terminal Count Interrupt */ - DMA0_IRQn = 58, /* DMA 0 Combined Interrupt */ - DMA1_ERROR_IRQn = 59, /* DMA 1 Error Interrupt */ - DMA1_TC_IRQn = 60, /* DMA 1 Terminal Count Interrupt */ - DMA1_IRQn = 61, /* DMA 1 Combined Interrupt */ - DMA2_ERROR_IRQn = 62, /* DMA 2 Error Interrupt */ - DMA2_TC_IRQn = 63, /* DMA 2 Terminal Count Interrupt */ - DMA2_IRQn = 64, /* DMA 2 Combined Interrupt */ - DMA3_ERROR_IRQn = 65, /* DMA 3 Error Interrupt */ - DMA3_TC_IRQn = 66, /* DMA 3 Terminal Count Interrupt */ - DMA3_IRQn = 67, /* DMA 3 Combined Interrupt */ - /* Reserved = 68:123, Reserved */ -}IRQn_Type; - -#endif /* __ARM_LTD_SSE_200_AWS_IRQN_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_core/platform_regs.h b/platform/ext/target/mps2/sse-200_aws/cmsis_core/platform_regs.h deleted file mode 100644 index a1c950743a..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_core/platform_regs.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __ARM_LTD_SSE_200_AWS_REGS_H__ -#define __ARM_LTD_SSE_200_AWS_REGS_H__ - -#include <stdint.h> - -/* System information (SYSINFO) */ -#define CMSDK_SYSINFO_BASE_NS 0x40020000 -#define CMSDK_SYSINFO_BASE_S 0x50020000 - -/* System info memory mapped register access structure */ -struct sysinfo_t { - volatile uint32_t sys_version; /* (R/ ) System version */ - volatile uint32_t sys_config; /* (R/ ) System configuration */ - volatile uint32_t reserved0[1008]; - volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */ - volatile uint32_t reserved1[3]; - volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */ - volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */ - volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */ - volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */ - volatile uint32_t cidr0; /* (R/ ) Component ID 0 */ - volatile uint32_t cidr1; /* (R/ ) Component ID 1 */ - volatile uint32_t cidr2; /* (R/ ) Component ID 2 */ - volatile uint32_t cidr3; /* (R/ ) Component ID 3 */ -}; - -/* System Control (SYSCTRL) */ -#define CMSDK_SYSCTRL_BASE_S 0x50021000 - -/* System control memory mapped register access structure */ -struct sysctrl_t { - volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration - * Status Register */ - volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration - * Set Register */ - volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration - * Clear Register */ - volatile uint32_t scsecctrl; /* (R/W) System Control Security - * Control Register */ - volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider - * Configuration Register */ - volatile uint32_t sysclk_div; /* (R/W) System Clock Divider - * Configuration Register */ - volatile uint32_t clockforce; /* (R/W) Clock Forces */ - volatile uint32_t reserved0[57]; - volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */ - volatile uint32_t resetmask; /* (R/W) Reset MASK */ - volatile uint32_t swreset; /* ( /W) Software Reset */ - volatile uint32_t gretreg; /* (R/W) General Purpose Retention - * Register */ - volatile uint32_t initsvtor0; /* (R/W) Initial Secure Reset Vector - * Register For CPU 0 */ - volatile uint32_t initsvtor1; /* (R/W) Initial Secure Reset - * Vector Register For CPU 1*/ - volatile uint32_t cpuwait; /* (R/W) CPU Boot wait control - * after reset */ - volatile uint32_t nmi_enable; /* (R/W) NAMI Enable Register */ - volatile uint32_t wicctrl; /* (R/W) CPU WIC Request and - * Acknowledgement */ - volatile uint32_t ewctrl; /* (R/W) External Wakeup Control */ - volatile uint32_t reserved1[54]; - volatile uint32_t pdcm_pd_sys_sense; /* (R/W) Power Control Dependency - * Matrix PD_SYS - * Power Domain Sensitivity.*/ - volatile uint32_t reserved2[2]; /* Reserved */ - volatile uint32_t pdcm_pd_sram0_sense; /* (R/W) Power Control Dependency - * Matrix PD_SRAM0 Power - * Domain Sensitivity.*/ - volatile uint32_t pdcm_pd_sram1_sense; /* (R/W) Power Control Dependency - * Matrix PD_SRAM1 Power - * Domain Sensitivity.*/ - volatile uint32_t pdcm_pd_sram2_sense; /* (R/W) Power Control Dependency - * Matrix PD_SRAM2 Power - * Domain Sensitivity.*/ - volatile uint32_t pdcm_pd_sram3_sense; /* (R/W) Power Control Dependency - * Matrix PD_SRAM3 Power - * Domain Sensitivity.*/ - volatile uint32_t reserved3[877]; /* Reserved */ - volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */ - volatile uint32_t reserved4[3]; - volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */ - volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */ - volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */ - volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */ - volatile uint32_t cidr0; /* (R/ ) Component ID 0 */ - volatile uint32_t cidr1; /* (R/ ) Component ID 1 */ - volatile uint32_t cidr2; /* (R/ ) Component ID 2 */ - volatile uint32_t cidr3; /* (R/ ) Component ID 3 */ -}; - -/* Secure Privilege Control */ -#define CMSDK_SPCTRL_BASE_S 0x50080000 -#define CMSDK_SPCTRL ((struct spctrl_def*)CMSDK_SPCTRL_BASE_S) - -/* SPCTRL memory mapped register access structure */ -struct spctrl_def { - volatile uint32_t reserved[4]; - volatile uint32_t secrespcfg; - volatile uint32_t nsccfg; - volatile uint32_t reserved2; - volatile uint32_t secmpcintstatus; - volatile uint32_t secppcintstat; - volatile uint32_t secppcintclr; - volatile uint32_t secppcinten; - volatile uint32_t reserved3; - volatile uint32_t secmscintstat; - volatile uint32_t secmscintclr; - volatile uint32_t secmscinten; - volatile uint32_t reserved4; - volatile uint32_t brgintstat; - volatile uint32_t brgintclr; - volatile uint32_t brginten; - volatile uint32_t reserved5; - volatile uint32_t ahbnsppc0; - volatile uint32_t reserved6[3]; - volatile uint32_t ahbnsppcexp0; - volatile uint32_t ahbnsppcexp1; - volatile uint32_t ahbnsppcexp2; - volatile uint32_t ahbnsppcexp3; - volatile uint32_t apbnsppc0; - volatile uint32_t apbnsppc1; - volatile uint32_t reserved7[2]; - volatile uint32_t apbnsppcexp0; - volatile uint32_t apbnsppcexp1; - volatile uint32_t apbnsppcexp2; - volatile uint32_t apbnsppcexp3; - volatile uint32_t ahbspppc0; - volatile uint32_t reserved8[3]; - volatile uint32_t ahbspppcexp0; - volatile uint32_t ahbspppcexp1; - volatile uint32_t ahbspppcexp2; - volatile uint32_t ahbspppcexp3; - volatile uint32_t apbspppc0; - volatile uint32_t apbspppc1; - volatile uint32_t reserved9[2]; - volatile uint32_t apbspppcexp0; - volatile uint32_t apbspppcexp1; - volatile uint32_t apbspppcexp2; - volatile uint32_t apbspppcexp3; - volatile uint32_t nsmscexp; - volatile uint32_t reserved10[959]; - volatile uint32_t pid4; - volatile uint32_t pid5; - volatile uint32_t pid6; - volatile uint32_t pid7; - volatile uint32_t pid0; - volatile uint32_t pid1; - volatile uint32_t pid2; - volatile uint32_t pid3; - volatile uint32_t cid0; - volatile uint32_t cid1; - volatile uint32_t cid2; - volatile uint32_t cid3; -}; - -/* PPC interrupt position mask */ -#define CMSDK_APB_PPC0_INT_POS_MASK (1UL << 0) -#define CMSDK_APB_PPC1_INT_POS_MASK (1UL << 1) -#define CMSDK_APB_PPCEXP0_INT_POS_MASK (1UL << 4) -#define CMSDK_APB_PPCEXP1_INT_POS_MASK (1UL << 5) -#define CMSDK_APB_PPCEXP2_INT_POS_MASK (1UL << 6) -#define CMSDK_APB_PPCEXP3_INT_POS_MASK (1UL << 7) -#define CMSDK_AHB_PPC0_INT_POS_MASK (1UL << 16) -#define CMSDK_AHB_PPCEXP0_INT_POS_MASK (1UL << 20) -#define CMSDK_AHB_PPCEXP1_INT_POS_MASK (1UL << 21) -#define CMSDK_AHB_PPCEXP2_INT_POS_MASK (1UL << 22) -#define CMSDK_AHB_PPCEXP3_INT_POS_MASK (1UL << 23) - -/* Non-Secure Access slave PPCs register addresses */ -#define CMSDK_SPCTRL_AHB_NS_PPC0 (CMSDK_SPCTRL_BASE_S + 0x050) -#define CMSDK_SPCTRL_AHB_NS_PPCEXP0 (CMSDK_SPCTRL_BASE_S + 0x060) -#define CMSDK_SPCTRL_AHB_NS_PPCEXP1 (CMSDK_SPCTRL_BASE_S + 0x064) -#define CMSDK_SPCTRL_AHB_NS_PPCEXP2 (CMSDK_SPCTRL_BASE_S + 0x068) -#define CMSDK_SPCTRL_AHB_NS_PPCEXP3 (CMSDK_SPCTRL_BASE_S + 0x06C) -#define CMSDK_SPCTRL_APB_NS_PPC0 (CMSDK_SPCTRL_BASE_S + 0x070) -#define CMSDK_SPCTRL_APB_NS_PPC1 (CMSDK_SPCTRL_BASE_S + 0x074) -#define CMSDK_SPCTRL_APB_NS_PPCEXP0 (CMSDK_SPCTRL_BASE_S + 0x080) -#define CMSDK_SPCTRL_APB_NS_PPCEXP1 (CMSDK_SPCTRL_BASE_S + 0x084) -#define CMSDK_SPCTRL_APB_NS_PPCEXP2 (CMSDK_SPCTRL_BASE_S + 0x088) -#define CMSDK_SPCTRL_APB_NS_PPCEXP3 (CMSDK_SPCTRL_BASE_S + 0x08C) - -/* Secure Unprivileged (SP) Access slave PPCs register addresses */ -#define CMSDK_SPCTRL_AHB_PPC0_SP (CMSDK_SPCTRL_BASE_S + 0x090) -#define CMSDK_SPCTRL_AHB_PPCEXP0_SP (CMSDK_SPCTRL_BASE_S + 0x0A0) -#define CMSDK_SPCTRL_AHB_PPCEXP1_SP (CMSDK_SPCTRL_BASE_S + 0x0A4) -#define CMSDK_SPCTRL_AHB_PPCEXP2_SP (CMSDK_SPCTRL_BASE_S + 0x0A8) -#define CMSDK_SPCTRL_AHB_PPCEXP3_SP (CMSDK_SPCTRL_BASE_S + 0x0AC) -#define CMSDK_SPCTRL_APB_PPC0_SP (CMSDK_SPCTRL_BASE_S + 0x0B0) -#define CMSDK_SPCTRL_APB_PPC1_SP (CMSDK_SPCTRL_BASE_S + 0x0B4) -#define CMSDK_SPCTRL_APB_PPCEXP0_SP (CMSDK_SPCTRL_BASE_S + 0x0C0) -#define CMSDK_SPCTRL_APB_PPCEXP1_SP (CMSDK_SPCTRL_BASE_S + 0x0C4) -#define CMSDK_SPCTRL_APB_PPCEXP2_SP (CMSDK_SPCTRL_BASE_S + 0x0C8) -#define CMSDK_SPCTRL_APB_PPCEXP3_SP (CMSDK_SPCTRL_BASE_S + 0x0CC) - -/* Non-Secure Privilege Control */ -#define CMSDK_NSPCTRL_BASE_NS 0x40080000 -#define CMSDK_NSPCTRL ((struct nspctrl_def*)CMSDK_NSPCTRL_BASE_NS) - -/* NSPCTRL memory mapped register access structure */ -struct nspctrl_def { - volatile uint32_t reserved[36]; - volatile uint32_t ahbnspppc0; - volatile uint32_t reserved3[3]; - volatile uint32_t ahbnspppcexp0; - volatile uint32_t ahbnspppcexp1; - volatile uint32_t ahbnspppcexp2; - volatile uint32_t ahbnspppcexp3; - volatile uint32_t apbnspppc0; - volatile uint32_t apbnspppc1; - volatile uint32_t reserved4[2]; - volatile uint32_t apbnspppcexp0; - volatile uint32_t apbnspppcexp1; - volatile uint32_t apbnspppcexp2; - volatile uint32_t apbnspppcexp3; - volatile uint32_t reserved5[960]; - volatile uint32_t pidr4; - volatile uint32_t reserved7; /* pidr5 */ - volatile uint32_t reserved8; /* pidr6 */ - volatile uint32_t reserved9; /* pidr7 */ - volatile uint32_t pidr0; - volatile uint32_t pidr1; - volatile uint32_t pidr2; - volatile uint32_t pidr3; - volatile uint32_t cidr0; - volatile uint32_t cidr1; - volatile uint32_t cidr2; - volatile uint32_t cidr3; -}; - -/* Non-Secure Unprivileged Access (NSP) Access slave PPCs register addresses */ -#define CMSDK_NSPCTRL_AHB_PPC0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x090) -#define CMSDK_NSPCTRL_AHB_PPCEXP0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A0) -#define CMSDK_NSPCTRL_AHB_PPCEXP1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A4) -#define CMSDK_NSPCTRL_AHB_PPCEXP2_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0A8) -#define CMSDK_NSPCTRL_AHB_PPCEXP3_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0AC) -#define CMSDK_NSPCTRL_APB_PPC0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0B0) -#define CMSDK_NSPCTRL_APB_PPC1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0B4) -#define CMSDK_NSPCTRL_APB_PPCEXP0_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C0) -#define CMSDK_NSPCTRL_APB_PPCEXP1_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C4) -#define CMSDK_NSPCTRL_APB_PPCEXP2_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0C8) -#define CMSDK_NSPCTRL_APB_PPCEXP3_NSP (CMSDK_NSPCTRL_BASE_NS + 0x0CC) - -/* ARM APB PPC0 peripherals definition */ -#define CMSDK_TIMER0_APB_PPC_POS 0U -#define CMSDK_TIMER1_APB_PPC_POS 1U -#define CMSDK_DTIMER_APB_PPC_POS 2U -#define CMSDK_MHU0_APB_PPC_POS 3U -#define CMSDK_MHU1_APB_PPC_POS 4U -/* The bits 31:5 are reserved */ -/* End ARM APB PPC0 peripherals definition */ - -/* ARM APB PPC1 peripherals definition */ -#define CMSDK_S32K_TIMER_PPC_POS 0U -/* The bits 31:1 are reserved */ -/* End ARM APB PPC1 peripherals definition */ - -/* ARM APB PPCEXP0 peripherals definition */ -#define CMSDK_SSRAM1_APB_PPC_POS 0U -#define CMSDK_SSRAM2_APB_PPC_POS 1U -#define CMSDK_SSRAM3_APB_PPC_POS 2U -/* The bits 31:3 are reserved */ -/* End ARM APB PPCEXP0 peripherals definition */ - -/* ARM APB PPCEXP1 peripherals definition */ -#define CMSDK_UART0_APB_PPC_POS 5U -/* The bits 31:6 and 4:0 are reserved */ -/* End ARM APB PPCEXP1 peripherals definition */ - -/* ARM APB PPCEXP2 peripherals definition */ -#define CMSDK_FPGA_SCC_PPC_POS 0U -#define CMSDK_FPGA_IO_PPC_POS 2U -/* The bits 31:3 and bit 1 are reserved */ -/* End ARM APB PPCEXP2 peripherals definition */ - -/* ARM APB PPCEXP3 peripherals definition */ -/* The bits 31:0 are reserved */ -/* End ARM APB PPCEXP3 peripherals definition */ - -/* ARM AHB PPC0 peripherals definition */ -/* The bits 31:0 are reserved */ -/* End of ARM AHB PPC0 peripherals definition */ - -/* ARM AHB PPCEXP0 peripherals definition */ -/* The bits 31:0 are reserved */ -/* End of ARM AHB PPCEXP0 peripherals definition */ - -/* ARM AHB PPCEXP1 peripherals definition */ -#define CMSDK_DMA0_PPC_POS 0U -#define CMSDK_DMA1_PPC_POS 1U -#define CMSDK_DMA2_PPC_POS 2U -#define CMSDK_DMA3_PPC_POS 3U -/* The bits 31:4 are reserved */ -/* End of ARM AHB PPCEXP1 peripherals definition */ - -/* ARM AHB PPCEXP2 peripherals definition */ -/* The bits 31:0 are reserved */ -/* End of ARM AHB PPCEXP2 peripherals definition */ - -/* ARM AHB PPCEXP3 peripherals definition */ -/* The bits 31:0 are reserved */ - -/* End of ARM AHB PPCEXP3 peripherals definition */ - -#endif /* __ARM_LTD_SSE_200_AWS_REGS_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_core/sse-200_aws.h b/platform/ext/target/mps2/sse-200_aws/cmsis_core/sse-200_aws.h deleted file mode 100644 index 98e2201504..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_core/sse-200_aws.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SSE_200_AWS_H__ -#define __SSE_200_AWS_H__ - -#include "platform_irq.h" /* Platform IRQ numbers */ - -#include "cmsis_cpu.h" /* Processor and core peripherals */ -#include "system_cmsdk_sse-200_aws.h" /* System Header */ - -#include "platform_regs.h" /* Platform registers */ -#include "platform_retarget.h" /* Peripherals base addresses */ - -#endif /* __SSE_200_AWS_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_core/system_cmsdk_sse-200_aws.c b/platform/ext/target/mps2/sse-200_aws/cmsis_core/system_cmsdk_sse-200_aws.c deleted file mode 100644 index 4bd95533a9..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_core/system_cmsdk_sse-200_aws.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis.h" - -/* - * SSE-200_AWS has different frequencies for system core clock (20MHz) and - * peripherals clock (25MHz). - */ - -#define SYSTEM_CLOCK (62500000UL) -#define PERIPHERAL_CLOCK (62500000UL) - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __Vectors; -#endif - -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/* System Core Clock update function */ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/* System initialization function */ -void SystemInit (void) -{ -#if __DOMAIN_NS != 1U -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &__Vectors; -#endif -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif -#endif /* __DOMAIN_NS != 1U */ - - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_core/system_cmsdk_sse-200_aws.h b/platform/ext/target/mps2/sse-200_aws/cmsis_core/system_cmsdk_sse-200_aws.h deleted file mode 100644 index bd1d4c1097..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_core/system_cmsdk_sse-200_aws.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __SYSTEM_CMSDK_SSE_200_AWS_H__ -#define __SYSTEM_CMSDK_SSE_200_AWS_H__ - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ - -/** - * \brief Initializes the system - */ -void SystemInit(void); - -/** - * \brief Restores system core clock - */ -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_CMSDK_SSE_200_AWS_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_driver_config.h b/platform/ext/target/mps2/sse-200_aws/cmsis_driver_config.h deleted file mode 100644 index ff4d1f055a..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_driver_config.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_DRIVER_CONFIG_H__ -#define __CMSIS_DRIVER_CONFIG_H__ - -#include "platform_retarget_dev.h" -#include "RTE_Device.h" -#include "target_cfg.h" - -#ifdef RTE_USART0 -#define UART0_DEV UART0_CMSDK_DEV_NS -#endif - -#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_Flash.c b/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_Flash.c deleted file mode 100644 index 525956d4a8..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_Flash.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) 2013-2018 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include <string.h> -#include <stdint.h> -#include "Driver_Flash.h" -#include "platform_retarget.h" -#include "RTE_Device.h" - -#ifndef ARG_UNUSED -#define ARG_UNUSED(arg) ((void)arg) -#endif - -/* Driver version */ -#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 1) -#define ARM_FLASH_DRV_ERASE_VALUE 0xFF - -/* - * ARM FLASH device structure - * - * There is no real flash memory for code on MPS2 board. Instead a code SRAM is - * used for code storage: ZBT SSRAM1. This driver just emulates a flash - * interface and behaviour on top of the SRAM memory. - */ -struct arm_flash_dev_t { - const uint32_t memory_base; /*!< FLASH memory base address */ - ARM_FLASH_INFO *data; /*!< FLASH data */ -}; - -/* Flash Status */ -static ARM_FLASH_STATUS FlashStatus = {0, 0, 0}; - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_FLASH_API_VERSION, - ARM_FLASH_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_FLASH_CAPABILITIES DriverCapabilities = { - 0, /* event_ready */ - 2, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */ - 1 /* erase_chip */ -}; - -static int32_t is_range_valid(struct arm_flash_dev_t *flash_dev, - uint32_t offset) -{ - uint32_t flash_limit = 0; - int32_t rc = 0; - - flash_limit = (flash_dev->data->sector_count * flash_dev->data->sector_size) - - 1; - - if (offset > flash_limit) { - rc = -1; - } - return rc; -} - -static int32_t is_write_aligned(struct arm_flash_dev_t *flash_dev, - uint32_t param) -{ - int32_t rc = 0; - - if ((param % flash_dev->data->program_unit) != 0) { - rc = -1; - } - return rc; -} - -static int32_t is_sector_aligned(struct arm_flash_dev_t *flash_dev, - uint32_t offset) -{ - int32_t rc = 0; - - if ((offset % flash_dev->data->sector_size) != 0) { - rc = -1; - } - return rc; -} - -static int32_t is_flash_ready_to_write(const uint8_t *start_addr, uint32_t cnt) -{ - int32_t rc = 0; - uint32_t i; - - for (i = 0; i < cnt; i++) { - if(start_addr[i] != ARM_FLASH_DRV_ERASE_VALUE) { - rc = -1; - break; - } - } - - return rc; -} - -#if (RTE_FLASH0) -static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = { - .sector_info = NULL, /* Uniform sector layout */ - .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE, - .sector_size = FLASH0_SECTOR_SIZE, - .page_size = FLASH0_PAGE_SIZE, - .program_unit = FLASH0_PROGRAM_UNIT, - .erased_value = ARM_FLASH_DRV_ERASE_VALUE}; - -static struct arm_flash_dev_t ARM_FLASH0_DEV = { -#if (__DOMAIN_NS == 1) - .memory_base = FLASH0_BASE_NS, -#else - .memory_base = FLASH0_BASE_S, -#endif /* __DOMAIN_NS == 1 */ - .data = &(ARM_FLASH0_DEV_DATA)}; - -struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV; - -/* - * Functions - */ - -static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void) -{ - return DriverVersion; -} - -static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void) -{ - return DriverCapabilities; -} - -static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) -{ - ARG_UNUSED(cb_event); - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t ARM_Flash_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state) -{ - switch (state) { - case ARM_POWER_FULL: - /* Nothing to be done */ - return ARM_DRIVER_OK; - break; - - case ARM_POWER_OFF: - case ARM_POWER_LOW: - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } -} - -static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt) -{ - uint32_t start_addr = FLASH0_DEV->memory_base + addr; - int32_t rc = 0; - - /* Check flash memory boundaries */ - rc = is_range_valid(FLASH0_DEV, addr + cnt); - if (rc != 0) { - return ARM_DRIVER_ERROR_PARAMETER; - } - - /* Flash interface just emulated over SRAM, use memcpy */ - memcpy(data, (void *)start_addr, cnt); - return ARM_DRIVER_OK; -} - -static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, - uint32_t cnt) -{ - uint32_t start_addr = FLASH0_DEV->memory_base + addr; - int32_t rc = 0; - - /* Check flash memory boundaries and alignment with minimal write size */ - rc = is_range_valid(FLASH0_DEV, addr + cnt); - rc |= is_write_aligned(FLASH0_DEV, addr); - rc |= is_write_aligned(FLASH0_DEV, cnt); - if (rc != 0) { - return ARM_DRIVER_ERROR_PARAMETER; - } - - /* Check if the flash area to write the data was erased previously */ - rc = is_flash_ready_to_write((const uint8_t*)start_addr, cnt); - if (rc != 0) { - return ARM_DRIVER_ERROR; - } - - /* Flash interface just emulated over SRAM, use memcpy */ - memcpy((void *)start_addr, data, cnt); - return ARM_DRIVER_OK; -} - -static int32_t ARM_Flash_EraseSector(uint32_t addr) -{ - uint32_t start_addr = FLASH0_DEV->memory_base + addr; - uint32_t rc = 0; - - rc = is_range_valid(FLASH0_DEV, addr); - rc |= is_sector_aligned(FLASH0_DEV, addr); - if (rc != 0) { - return ARM_DRIVER_ERROR_PARAMETER; - } - - /* Flash interface just emulated over SRAM, use memset */ - memset((void *)start_addr, - FLASH0_DEV->data->erased_value, - FLASH0_DEV->data->sector_size); - return ARM_DRIVER_OK; -} - -static int32_t ARM_Flash_EraseChip(void) -{ - uint32_t i; - uint32_t addr = FLASH0_DEV->memory_base; - int32_t rc = ARM_DRIVER_ERROR_UNSUPPORTED; - - /* Check driver capability erase_chip bit */ - if (DriverCapabilities.erase_chip == 1) { - for (i = 0; i < FLASH0_DEV->data->sector_count; i++) { - /* Flash interface just emulated over SRAM, use memset */ - memset((void *)addr, - FLASH0_DEV->data->erased_value, - FLASH0_DEV->data->sector_size); - - addr += FLASH0_DEV->data->sector_size; - rc = ARM_DRIVER_OK; - } - } - return rc; -} - -static ARM_FLASH_STATUS ARM_Flash_GetStatus(void) -{ - return FlashStatus; -} - -static ARM_FLASH_INFO * ARM_Flash_GetInfo(void) -{ - return FLASH0_DEV->data; -} - -ARM_DRIVER_FLASH Driver_FLASH0 = { - ARM_Flash_GetVersion, - ARM_Flash_GetCapabilities, - ARM_Flash_Initialize, - ARM_Flash_Uninitialize, - ARM_Flash_PowerControl, - ARM_Flash_ReadData, - ARM_Flash_ProgramData, - ARM_Flash_EraseSector, - ARM_Flash_EraseChip, - ARM_Flash_GetStatus, - ARM_Flash_GetInfo -}; -#endif /* RTE_FLASH0 */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_PPC.c b/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_PPC.c deleted file mode 100644 index 2695a50253..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_PPC.c +++ /dev/null @@ -1,970 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_PPC.h" - -#include "cmsis_driver_config.h" -#include "RTE_Device.h" - -/* Driver version */ -#define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_PPC_API_VERSION, - ARM_PPC_DRV_VERSION -}; - -static ARM_DRIVER_VERSION ARM_PPC_GetVersion(void) -{ - return DriverVersion; -} - -#if (RTE_AHB_PPC0) -/* AHB PPC0 Driver wrapper functions */ -static int32_t AHB_PPC0_Initialize(void) -{ - ppc_sse200_init(&AHB_PPC0_DEV, AHB_PPC0); - - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPC0_Uninitialize(void) -{ - /* Nothing to be done*/ - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&AHB_PPC0_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t AHB_PPC0_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&AHB_PPC0_DEV, periph); -} - -static uint32_t AHB_PPC0_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&AHB_PPC0_DEV, periph); -} - -static int32_t AHB_PPC0_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&AHB_PPC0_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void AHB_PPC0_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&AHB_PPC0_DEV); -} - -static void AHB_PPC0_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&AHB_PPC0_DEV); -} - -static uint32_t AHB_PPC0_InterruptState(void) -{ - return ppc_sse200_irq_state(&AHB_PPC0_DEV); -} - -/* AHB PPC0 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_AHB_PPC0; -ARM_DRIVER_PPC Driver_AHB_PPC0 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = AHB_PPC0_Initialize, - .Uninitialize = AHB_PPC0_Uninitialize, - .ConfigPeriph = AHB_PPC0_ConfigPeriph, - .IsPeriphSecure = AHB_PPC0_IsPeriphSecure, - .IsPeriphPrivOnly = AHB_PPC0_IsPeriphPrivOnly, - .EnableInterrupt = AHB_PPC0_EnableInterrupt, - .DisableInterrupt = AHB_PPC0_DisableInterrupt, - .ClearInterrupt = AHB_PPC0_ClearInterrupt, - .InterruptState = AHB_PPC0_InterruptState -}; -#endif /* RTE_AHB_PPC0 */ - -#if (RTE_AHB_PPCEXP0) -/* AHB PPCEXP0 Driver wrapper functions */ -static int32_t AHB_PPCEXP0_Initialize(void) -{ - ppc_sse200_init(&AHB_PPCEXP0_DEV, AHB_PPC_EXP0); - - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPCEXP0_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPCEXP0_ConfigPeriph(uint8_t periph, - ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&AHB_PPCEXP0_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t AHB_PPCEXP0_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&AHB_PPCEXP0_DEV, periph); -} - -static uint32_t AHB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP0_DEV, periph); -} - -static int32_t AHB_PPCEXP0_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&AHB_PPCEXP0_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void AHB_PPCEXP0_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&AHB_PPCEXP0_DEV); -} - -static void AHB_PPCEXP0_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&AHB_PPCEXP0_DEV); -} - -static uint32_t AHB_PPCEXP0_InterruptState(void) -{ - return ppc_sse200_irq_state(&AHB_PPCEXP0_DEV); -} - -/* AHB PPCEXP0 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_AHB_PPCEXP0; -ARM_DRIVER_PPC Driver_AHB_PPCEXP0 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = AHB_PPCEXP0_Initialize, - .Uninitialize = AHB_PPCEXP0_Uninitialize, - .ConfigPeriph = AHB_PPCEXP0_ConfigPeriph, - .IsPeriphSecure = AHB_PPCEXP0_IsPeriphSecure, - .IsPeriphPrivOnly = AHB_PPCEXP0_IsPeriphPrivOnly, - .EnableInterrupt = AHB_PPCEXP0_EnableInterrupt, - .DisableInterrupt = AHB_PPCEXP0_DisableInterrupt, - .ClearInterrupt = AHB_PPCEXP0_ClearInterrupt, - .InterruptState = AHB_PPCEXP0_InterruptState -}; -#endif /* RTE_AHB_PPCEXP0 */ - -#if (RTE_AHB_PPCEXP1) -/* AHB PPCEXP1 Driver wrapper functions */ -static int32_t AHB_PPCEXP1_Initialize(void) -{ - ppc_sse200_init(&AHB_PPCEXP1_DEV, AHB_PPC_EXP1); - - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPCEXP1_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPCEXP1_ConfigPeriph(uint8_t periph, - ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&AHB_PPCEXP1_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t AHB_PPCEXP1_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&AHB_PPCEXP1_DEV, periph); -} - -static uint32_t AHB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP1_DEV, periph); -} - -static int32_t AHB_PPCEXP1_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&AHB_PPCEXP1_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void AHB_PPCEXP1_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&AHB_PPCEXP1_DEV); -} - -static void AHB_PPCEXP1_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&AHB_PPCEXP1_DEV); -} - -static uint32_t AHB_PPCEXP1_InterruptState(void) -{ - return ppc_sse200_irq_state(&AHB_PPCEXP1_DEV); -} - -/* AHB PPCEXP1 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_AHB_PPCEXP1; -ARM_DRIVER_PPC Driver_AHB_PPCEXP1 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = AHB_PPCEXP1_Initialize, - .Uninitialize = AHB_PPCEXP1_Uninitialize, - .ConfigPeriph = AHB_PPCEXP1_ConfigPeriph, - .IsPeriphSecure = AHB_PPCEXP1_IsPeriphSecure, - .IsPeriphPrivOnly = AHB_PPCEXP1_IsPeriphPrivOnly, - .EnableInterrupt = AHB_PPCEXP1_EnableInterrupt, - .DisableInterrupt = AHB_PPCEXP1_DisableInterrupt, - .ClearInterrupt = AHB_PPCEXP1_ClearInterrupt, - .InterruptState = AHB_PPCEXP1_InterruptState -}; -#endif /* RTE_AHB_PPCEXP1 */ - -#if (RTE_AHB_PPCEXP2) -/* AHB PPCEXP2 Driver wrapper functions */ -static int32_t AHB_PPCEXP2_Initialize(void) -{ - ppc_sse200_init(&AHB_PPCEXP2_DEV, AHB_PPC_EXP2); - - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPCEXP2_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPCEXP2_ConfigPeriph(uint8_t periph, - ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&AHB_PPCEXP2_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t AHB_PPCEXP2_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&AHB_PPCEXP2_DEV, periph); -} - -static uint32_t AHB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP2_DEV, periph); -} - -static int32_t AHB_PPCEXP2_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&AHB_PPCEXP2_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void AHB_PPCEXP2_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&AHB_PPCEXP2_DEV); -} - -static void AHB_PPCEXP2_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&AHB_PPCEXP2_DEV); -} - -static uint32_t AHB_PPCEXP2_InterruptState(void) -{ - return ppc_sse200_irq_state(&AHB_PPCEXP2_DEV); -} - -/* AHB PPCEXP2 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_AHB_PPCEXP2; -ARM_DRIVER_PPC Driver_AHB_PPCEXP2 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = AHB_PPCEXP2_Initialize, - .Uninitialize = AHB_PPCEXP2_Uninitialize, - .ConfigPeriph = AHB_PPCEXP2_ConfigPeriph, - .IsPeriphSecure = AHB_PPCEXP2_IsPeriphSecure, - .IsPeriphPrivOnly = AHB_PPCEXP2_IsPeriphPrivOnly, - .EnableInterrupt = AHB_PPCEXP2_EnableInterrupt, - .DisableInterrupt = AHB_PPCEXP2_DisableInterrupt, - .ClearInterrupt = AHB_PPCEXP2_ClearInterrupt, - .InterruptState = AHB_PPCEXP2_InterruptState -}; -#endif /* RTE_AHB_PPCEXP2 */ - -#if (RTE_AHB_PPCEXP3) -/* AHB PPCEXP3 Driver wrapper functions */ -static int32_t AHB_PPCEXP3_Initialize(void) -{ - ppc_sse200_init(&AHB_PPCEXP3_DEV, AHB_PPC_EXP3); - - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPCEXP3_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t AHB_PPCEXP3_ConfigPeriph(uint8_t periph, - ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&AHB_PPCEXP3_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t AHB_PPCEXP3_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&AHB_PPCEXP3_DEV, periph); -} - -static uint32_t AHB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP3_DEV, periph); -} - -static int32_t AHB_PPCEXP3_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&AHB_PPCEXP3_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void AHB_PPCEXP3_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&AHB_PPCEXP3_DEV); -} - -static void AHB_PPCEXP3_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&AHB_PPCEXP3_DEV); -} - -static uint32_t AHB_PPCEXP3_InterruptState(void) -{ - return ppc_sse200_irq_state(&AHB_PPCEXP3_DEV); -} - -/* AHB PPCEXP3 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_AHB_PPCEXP3; -ARM_DRIVER_PPC Driver_AHB_PPCEXP3 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = AHB_PPCEXP3_Initialize, - .Uninitialize = AHB_PPCEXP3_Uninitialize, - .ConfigPeriph = AHB_PPCEXP3_ConfigPeriph, - .IsPeriphSecure = AHB_PPCEXP3_IsPeriphSecure, - .IsPeriphPrivOnly = AHB_PPCEXP3_IsPeriphPrivOnly, - .EnableInterrupt = AHB_PPCEXP3_EnableInterrupt, - .DisableInterrupt = AHB_PPCEXP3_DisableInterrupt, - .ClearInterrupt = AHB_PPCEXP3_ClearInterrupt, - .InterruptState = AHB_PPCEXP3_InterruptState -}; -#endif /* RTE_AHB_PPCEXP3 */ - -#if (RTE_APB_PPC0) -/* APB PPC0 Driver wrapper functions */ -static int32_t APB_PPC0_Initialize(void) -{ - ppc_sse200_init(&APB_PPC0_DEV, APB_PPC0); - - return ARM_DRIVER_OK; -} - -static int32_t APB_PPC0_Uninitialize(void) -{ - /* Nothing to be done*/ - return ARM_DRIVER_OK; -} - -static int32_t APB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&APB_PPC0_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t APB_PPC0_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&APB_PPC0_DEV, periph); -} - -static uint32_t APB_PPC0_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&APB_PPC0_DEV, periph); -} - -static int32_t APB_PPC0_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&APB_PPC0_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void APB_PPC0_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&APB_PPC0_DEV); -} - -static void APB_PPC0_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&APB_PPC0_DEV); -} - -static uint32_t APB_PPC0_InterruptState(void) -{ - return ppc_sse200_irq_state(&APB_PPC0_DEV); -} - -/* APB PPC0 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_APB_PPC0; -ARM_DRIVER_PPC Driver_APB_PPC0 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = APB_PPC0_Initialize, - .Uninitialize = APB_PPC0_Uninitialize, - .ConfigPeriph = APB_PPC0_ConfigPeriph, - .IsPeriphSecure = APB_PPC0_IsPeriphSecure, - .IsPeriphPrivOnly = APB_PPC0_IsPeriphPrivOnly, - .EnableInterrupt = APB_PPC0_EnableInterrupt, - .DisableInterrupt = APB_PPC0_DisableInterrupt, - .ClearInterrupt = APB_PPC0_ClearInterrupt, - .InterruptState = APB_PPC0_InterruptState -}; -#endif /* RTE_APB_PPC0 */ - -#if (RTE_APB_PPC1) -/* APB PPC1 Driver wrapper functions */ -static int32_t APB_PPC1_Initialize(void) -{ - ppc_sse200_init(&APB_PPC1_DEV, APB_PPC1); - - return ARM_DRIVER_OK; -} - -static int32_t APB_PPC1_Uninitialize(void) -{ - /* Nothing to be done*/ - return ARM_DRIVER_OK; -} - -static int32_t APB_PPC1_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&APB_PPC1_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t APB_PPC1_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&APB_PPC1_DEV, periph); -} - -static uint32_t APB_PPC1_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&APB_PPC1_DEV, periph); -} -static int32_t APB_PPC1_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&APB_PPC1_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void APB_PPC1_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&APB_PPC1_DEV); -} - -static void APB_PPC1_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&APB_PPC1_DEV); -} - -static uint32_t APB_PPC1_InterruptState(void) -{ - return ppc_sse200_irq_state(&APB_PPC1_DEV); -} - -/* APB PPC1 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_APB_PPC1; -ARM_DRIVER_PPC Driver_APB_PPC1 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = APB_PPC1_Initialize, - .Uninitialize = APB_PPC1_Uninitialize, - .ConfigPeriph = APB_PPC1_ConfigPeriph, - .IsPeriphSecure = APB_PPC1_IsPeriphSecure, - .IsPeriphPrivOnly = APB_PPC1_IsPeriphPrivOnly, - .EnableInterrupt = APB_PPC1_EnableInterrupt, - .DisableInterrupt = APB_PPC1_DisableInterrupt, - .ClearInterrupt = APB_PPC1_ClearInterrupt, - .InterruptState = APB_PPC1_InterruptState -}; -#endif /* RTE_APB_PPC1 */ - -#if (RTE_APB_PPCEXP0) -/* APB PPCEXP0 Driver wrapper functions */ -static int32_t APB_PPCEXP0_Initialize(void) -{ - ppc_sse200_init(&APB_PPCEXP0_DEV, APB_PPC_EXP0); - - return ARM_DRIVER_OK; -} - -static int32_t APB_PPCEXP0_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t APB_PPCEXP0_ConfigPeriph(uint8_t periph, - ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&APB_PPCEXP0_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t APB_PPCEXP0_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&APB_PPCEXP0_DEV, periph); -} - -static uint32_t APB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&APB_PPCEXP0_DEV, periph); -} - -static int32_t APB_PPCEXP0_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&APB_PPCEXP0_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void APB_PPCEXP0_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&APB_PPCEXP0_DEV); -} - -static void APB_PPCEXP0_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&APB_PPCEXP0_DEV); -} - -static uint32_t APB_PPCEXP0_InterruptState(void) -{ - return ppc_sse200_irq_state(&APB_PPCEXP0_DEV); -} - -/* APB PPCEXP0 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_APB_PPCEXP0; -ARM_DRIVER_PPC Driver_APB_PPCEXP0 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = APB_PPCEXP0_Initialize, - .Uninitialize = APB_PPCEXP0_Uninitialize, - .ConfigPeriph = APB_PPCEXP0_ConfigPeriph, - .IsPeriphSecure = APB_PPCEXP0_IsPeriphSecure, - .IsPeriphPrivOnly = APB_PPCEXP0_IsPeriphPrivOnly, - .EnableInterrupt = APB_PPCEXP0_EnableInterrupt, - .DisableInterrupt = APB_PPCEXP0_DisableInterrupt, - .ClearInterrupt = APB_PPCEXP0_ClearInterrupt, - .InterruptState = APB_PPCEXP0_InterruptState -}; -#endif /* RTE_APB_PPCEXP0 */ - -#if (RTE_APB_PPCEXP1) -/* APB PPCEXP1 Driver wrapper functions */ -static int32_t APB_PPCEXP1_Initialize(void) -{ - ppc_sse200_init(&APB_PPCEXP1_DEV, APB_PPC_EXP1); - - return ARM_DRIVER_OK; -} - -static int32_t APB_PPCEXP1_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t APB_PPCEXP1_ConfigPeriph(uint8_t periph, - ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&APB_PPCEXP1_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t APB_PPCEXP1_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&APB_PPCEXP1_DEV, periph); -} - -static uint32_t APB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&APB_PPCEXP1_DEV, periph); -} - -static int32_t APB_PPCEXP1_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&APB_PPCEXP1_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void APB_PPCEXP1_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&APB_PPCEXP1_DEV); -} - -static void APB_PPCEXP1_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&APB_PPCEXP1_DEV); -} - -static uint32_t APB_PPCEXP1_InterruptState(void) -{ - return ppc_sse200_irq_state(&APB_PPCEXP1_DEV); -} - -/* APB PPCEXP1 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_APB_PPCEXP1; -ARM_DRIVER_PPC Driver_APB_PPCEXP1 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = APB_PPCEXP1_Initialize, - .Uninitialize = APB_PPCEXP1_Uninitialize, - .ConfigPeriph = APB_PPCEXP1_ConfigPeriph, - .IsPeriphSecure = APB_PPCEXP1_IsPeriphSecure, - .IsPeriphPrivOnly = APB_PPCEXP1_IsPeriphPrivOnly, - .EnableInterrupt = APB_PPCEXP1_EnableInterrupt, - .DisableInterrupt = APB_PPCEXP1_DisableInterrupt, - .ClearInterrupt = APB_PPCEXP1_ClearInterrupt, - .InterruptState = APB_PPCEXP1_InterruptState -}; -#endif /* RTE_APB_PPCEXP1 */ - -#if (RTE_APB_PPCEXP2) -/* APB PPCEXP2 Driver wrapper functions */ -static int32_t APB_PPCEXP2_Initialize(void) -{ - ppc_sse200_init(&APB_PPCEXP2_DEV, APB_PPC_EXP2); - - return ARM_DRIVER_OK; -} - -static int32_t APB_PPCEXP2_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t APB_PPCEXP2_ConfigPeriph(uint8_t periph, - ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t APB_PPCEXP2_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&APB_PPCEXP2_DEV, periph); -} - -static uint32_t APB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&APB_PPCEXP2_DEV, periph); -} - -static int32_t APB_PPCEXP2_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&APB_PPCEXP2_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void APB_PPCEXP2_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&APB_PPCEXP2_DEV); -} - -static void APB_PPCEXP2_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&APB_PPCEXP2_DEV); -} - -static uint32_t APB_PPCEXP2_InterruptState(void) -{ - return ppc_sse200_irq_state(&APB_PPCEXP2_DEV); -} - -/* APB PPCEXP2 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_APB_PPCEXP2; -ARM_DRIVER_PPC Driver_APB_PPCEXP2 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = APB_PPCEXP2_Initialize, - .Uninitialize = APB_PPCEXP2_Uninitialize, - .ConfigPeriph = APB_PPCEXP2_ConfigPeriph, - .IsPeriphSecure = APB_PPCEXP2_IsPeriphSecure, - .IsPeriphPrivOnly = APB_PPCEXP2_IsPeriphPrivOnly, - .EnableInterrupt = APB_PPCEXP2_EnableInterrupt, - .DisableInterrupt = APB_PPCEXP2_DisableInterrupt, - .ClearInterrupt = APB_PPCEXP2_ClearInterrupt, - .InterruptState = APB_PPCEXP2_InterruptState -}; -#endif /* RTE_APB_PPCEXP2 */ - -#if (RTE_APB_PPCEXP3) -/* APB PPCEXP3 Driver wrapper functions */ -static int32_t APB_PPCEXP3_Initialize(void) -{ - ppc_sse200_init(&APB_PPCEXP3_DEV, APB_PPC_EXP3); - - return ARM_DRIVER_OK; -} - -static int32_t APB_PPCEXP3_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t APB_PPCEXP3_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr, - ARM_PPC_PrivAttr priv_attr) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_config_peripheral(&APB_PPCEXP3_DEV, periph, - (enum ppc_sse200_sec_attr_t)sec_attr, - (enum ppc_sse200_priv_attr_t)priv_attr); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static uint32_t APB_PPCEXP3_IsPeriphSecure(uint8_t periph) -{ - return ppc_sse200_is_periph_secure(&APB_PPCEXP3_DEV, periph); -} - -static uint32_t APB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph) -{ - return ppc_sse200_is_periph_priv_only(&APB_PPCEXP3_DEV, periph); -} - -static int32_t APB_PPCEXP3_EnableInterrupt(void) -{ - enum ppc_sse200_error_t ret; - - ret = ppc_sse200_irq_enable(&APB_PPCEXP3_DEV); - - if (ret != PPC_SSE200_ERR_NONE) { - return ARM_DRIVER_ERROR; - } - - return ARM_DRIVER_OK; -} - -static void APB_PPCEXP3_DisableInterrupt(void) -{ - ppc_sse200_irq_disable(&APB_PPCEXP3_DEV); -} - -static void APB_PPCEXP3_ClearInterrupt(void) -{ - ppc_sse200_clear_irq(&APB_PPCEXP3_DEV); -} - -static uint32_t APB_PPCEXP3_InterruptState(void) -{ - return ppc_sse200_irq_state(&APB_PPCEXP3_DEV); -} - -/* APB PPCEXP3 Driver CMSIS access structure */ -extern ARM_DRIVER_PPC Driver_APB_PPCEXP3; -ARM_DRIVER_PPC Driver_APB_PPCEXP3 = { - .GetVersion = ARM_PPC_GetVersion, - .Initialize = APB_PPCEXP3_Initialize, - .Uninitialize = APB_PPCEXP3_Uninitialize, - .ConfigPeriph = APB_PPCEXP3_ConfigPeriph, - .IsPeriphSecure = APB_PPCEXP3_IsPeriphSecure, - .IsPeriphPrivOnly = APB_PPCEXP3_IsPeriphPrivOnly, - .EnableInterrupt = APB_PPCEXP3_EnableInterrupt, - .DisableInterrupt = APB_PPCEXP3_DisableInterrupt, - .ClearInterrupt = APB_PPCEXP3_ClearInterrupt, - .InterruptState = APB_PPCEXP3_InterruptState -}; -#endif /* RTE_APB_PPCEXP3 */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_SSE-200_AWS_MPC.c b/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_SSE-200_AWS_MPC.c deleted file mode 100644 index ae0b672a18..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_SSE-200_AWS_MPC.c +++ /dev/null @@ -1,1045 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_MPC.h" - -#include "mpc_sie_drv.h" -#include "cmsis_driver_config.h" -#include "RTE_Device.h" -#include "platform_retarget.h" - -/* Driver version */ -#define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_MPC_API_VERSION, - ARM_MPC_DRV_VERSION -}; - -static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void) -{ - return DriverVersion; -} - -/* - * \brief Translates error codes from native API to CMSIS API. - * - * \param[in] err Error code to translate (\ref mpc_sie_error_t). - * - * \return Returns CMSIS error code. - */ -static int32_t error_trans(enum mpc_sie_error_t err) -{ - switch(err) { - case MPC_SIE_ERR_NONE: - return ARM_DRIVER_OK; - case MPC_SIE_INVALID_ARG: - return ARM_DRIVER_ERROR_PARAMETER; - case MPC_SIE_NOT_INIT: - return ARM_MPC_ERR_NOT_INIT; - case MPC_SIE_ERR_NOT_IN_RANGE: - return ARM_MPC_ERR_NOT_IN_RANGE; - case MPC_SIE_ERR_NOT_ALIGNED: - return ARM_MPC_ERR_NOT_ALIGNED; - case MPC_SIE_ERR_INVALID_RANGE: - return ARM_MPC_ERR_INVALID_RANGE; - case MPC_SIE_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE: - return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE; - default: - return ARM_MPC_ERR_UNSPECIFIED; - } -} - -#if (RTE_ISRAM0_MPC) -/* Ranges controlled by this ISRAM0_MPC */ -static const struct mpc_sie_memory_range_t MPC_ISRAM0_RANGE_S = { - .base = MPC_ISRAM0_RANGE_BASE_S, - .limit = MPC_ISRAM0_RANGE_LIMIT_S, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_SECURE -}; - -static const struct mpc_sie_memory_range_t MPC_ISRAM0_RANGE_NS = { - .base = MPC_ISRAM0_RANGE_BASE_NS, - .limit = MPC_ISRAM0_RANGE_LIMIT_NS, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_NONSECURE -}; - -#define MPC_ISRAM0_RANGE_LIST_LEN 2u -static const struct mpc_sie_memory_range_t* - MPC_ISRAM0_RANGE_LIST[MPC_ISRAM0_RANGE_LIST_LEN] = { - &MPC_ISRAM0_RANGE_S, - &MPC_ISRAM0_RANGE_NS - }; - -/* ISRAM0_MPC Driver wrapper functions */ -static int32_t ISRAM0_MPC_Initialize(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_init(&MPC_ISRAM0_DEV, - MPC_ISRAM0_RANGE_LIST, - MPC_ISRAM0_RANGE_LIST_LEN); - - return error_trans(ret); -} - -static int32_t ISRAM0_MPC_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t ISRAM0_MPC_GetBlockSize(uint32_t *blk_size) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_block_size(&MPC_ISRAM0_DEV, blk_size); - - return error_trans(ret); -} - -static int32_t ISRAM0_MPC_GetCtrlConfig(uint32_t *ctrl_val) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_ctrl(&MPC_ISRAM0_DEV, ctrl_val); - - return error_trans(ret); -} - -static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_set_ctrl(&MPC_ISRAM0_DEV, ctrl); - - return error_trans(ret); -} - -static int32_t ISRAM0_MPC_GetRegionConfig(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR *attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_region_config(&MPC_ISRAM0_DEV, base, limit, - (enum mpc_sie_sec_attr_t*)attr); - - return error_trans(ret); -} - -static int32_t ISRAM0_MPC_ConfigRegion(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_config_region(&MPC_ISRAM0_DEV, base, limit, - (enum mpc_sie_sec_attr_t)attr); - - return error_trans(ret); -} - -static int32_t ISRAM0_MPC_EnableInterrupt(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_irq_enable(&MPC_ISRAM0_DEV); - - return error_trans(ret); -} - -static void ISRAM0_MPC_DisableInterrupt(void) -{ - mpc_sie_irq_disable(&MPC_ISRAM0_DEV); -} - - -static void ISRAM0_MPC_ClearInterrupt(void) -{ - mpc_sie_clear_irq(&MPC_ISRAM0_DEV); -} - -static uint32_t ISRAM0_MPC_InterruptState(void) -{ - return mpc_sie_irq_state(&MPC_ISRAM0_DEV); -} - -static int32_t ISRAM0_MPC_LockDown(void) -{ - return mpc_sie_lock_down(&MPC_ISRAM0_DEV); -} - -/* ISRAM0_MPC Driver CMSIS access structure */ -ARM_DRIVER_MPC Driver_ISRAM0_MPC = { - .GetVersion = ARM_MPC_GetVersion, - .Initialize = ISRAM0_MPC_Initialize, - .Uninitialize = ISRAM0_MPC_Uninitialize, - .GetBlockSize = ISRAM0_MPC_GetBlockSize, - .GetCtrlConfig = ISRAM0_MPC_GetCtrlConfig, - .SetCtrlConfig = ISRAM0_MPC_SetCtrlConfig, - .ConfigRegion = ISRAM0_MPC_ConfigRegion, - .GetRegionConfig = ISRAM0_MPC_GetRegionConfig, - .EnableInterrupt = ISRAM0_MPC_EnableInterrupt, - .DisableInterrupt = ISRAM0_MPC_DisableInterrupt, - .ClearInterrupt = ISRAM0_MPC_ClearInterrupt, - .InterruptState = ISRAM0_MPC_InterruptState, - .LockDown = ISRAM0_MPC_LockDown, -}; -#endif /* RTE_ISRAM0_MPC */ - -#if (RTE_ISRAM1_MPC) -/* Ranges controlled by this ISRAM1_MPC */ -static const struct mpc_sie_memory_range_t MPC_ISRAM1_RANGE_S = { - .base = MPC_ISRAM1_RANGE_BASE_S, - .limit = MPC_ISRAM1_RANGE_LIMIT_S, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_SECURE -}; - -static const struct mpc_sie_memory_range_t MPC_ISRAM1_RANGE_NS = { - .base = MPC_ISRAM1_RANGE_BASE_NS, - .limit = MPC_ISRAM1_RANGE_LIMIT_NS, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_NONSECURE -}; - -#define MPC_ISRAM1_RANGE_LIST_LEN 2u -static const struct mpc_sie_memory_range_t* - MPC_ISRAM1_RANGE_LIST[MPC_ISRAM1_RANGE_LIST_LEN] = { - &MPC_ISRAM1_RANGE_S, - &MPC_ISRAM1_RANGE_NS - }; - -/* ISRAM1_MPC Driver wrapper functions */ -static int32_t ISRAM1_MPC_Initialize(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_init(&MPC_ISRAM1_DEV, - MPC_ISRAM1_RANGE_LIST, - MPC_ISRAM1_RANGE_LIST_LEN); - - return error_trans(ret); -} - -static int32_t ISRAM1_MPC_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t ISRAM1_MPC_GetBlockSize(uint32_t *blk_size) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_block_size(&MPC_ISRAM1_DEV, blk_size); - - return error_trans(ret); -} - -static int32_t ISRAM1_MPC_GetCtrlConfig(uint32_t *ctrl_val) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_ctrl(&MPC_ISRAM1_DEV, ctrl_val); - - return error_trans(ret); -} - -static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_set_ctrl(&MPC_ISRAM1_DEV, ctrl); - - return error_trans(ret); -} - -static int32_t ISRAM1_MPC_GetRegionConfig(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR *attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_region_config(&MPC_ISRAM1_DEV, base, limit, - (enum mpc_sie_sec_attr_t*)attr); - - return error_trans(ret); -} - -static int32_t ISRAM1_MPC_ConfigRegion(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_config_region(&MPC_ISRAM1_DEV, base, limit, - (enum mpc_sie_sec_attr_t)attr); - - return error_trans(ret); -} - -static int32_t ISRAM1_MPC_EnableInterrupt(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_irq_enable(&MPC_ISRAM1_DEV); - - return error_trans(ret); -} - -static void ISRAM1_MPC_DisableInterrupt(void) -{ - mpc_sie_irq_disable(&MPC_ISRAM1_DEV); -} - - -static void ISRAM1_MPC_ClearInterrupt(void) -{ - mpc_sie_clear_irq(&MPC_ISRAM1_DEV); -} - -static uint32_t ISRAM1_MPC_InterruptState(void) -{ - return mpc_sie_irq_state(&MPC_ISRAM1_DEV); -} - -static int32_t ISRAM1_MPC_LockDown(void) -{ - return mpc_sie_lock_down(&MPC_ISRAM1_DEV); -} - -/* ISRAM1_MPC Driver CMSIS access structure */ -ARM_DRIVER_MPC Driver_ISRAM1_MPC = { - .GetVersion = ARM_MPC_GetVersion, - .Initialize = ISRAM1_MPC_Initialize, - .Uninitialize = ISRAM1_MPC_Uninitialize, - .GetBlockSize = ISRAM1_MPC_GetBlockSize, - .GetCtrlConfig = ISRAM1_MPC_GetCtrlConfig, - .SetCtrlConfig = ISRAM1_MPC_SetCtrlConfig, - .ConfigRegion = ISRAM1_MPC_ConfigRegion, - .GetRegionConfig = ISRAM1_MPC_GetRegionConfig, - .EnableInterrupt = ISRAM1_MPC_EnableInterrupt, - .DisableInterrupt = ISRAM1_MPC_DisableInterrupt, - .ClearInterrupt = ISRAM1_MPC_ClearInterrupt, - .InterruptState = ISRAM1_MPC_InterruptState, - .LockDown = ISRAM1_MPC_LockDown, -}; -#endif /* RTE_ISRAM1_MPC */ - -#if (RTE_ISRAM2_MPC) -/* Ranges controlled by this ISRAM2_MPC */ -static const struct mpc_sie_memory_range_t MPC_ISRAM2_RANGE_S = { - .base = MPC_ISRAM2_RANGE_BASE_S, - .limit = MPC_ISRAM2_RANGE_LIMIT_S, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_SECURE -}; - -static const struct mpc_sie_memory_range_t MPC_ISRAM2_RANGE_NS = { - .base = MPC_ISRAM2_RANGE_BASE_NS, - .limit = MPC_ISRAM2_RANGE_LIMIT_NS, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_NONSECURE -}; - -#define MPC_ISRAM2_RANGE_LIST_LEN 2u -static const struct mpc_sie_memory_range_t* - MPC_ISRAM2_RANGE_LIST[MPC_ISRAM2_RANGE_LIST_LEN] = { - &MPC_ISRAM2_RANGE_S, - &MPC_ISRAM2_RANGE_NS - }; - -/* ISRAM2_MPC Driver wrapper functions */ -static int32_t ISRAM2_MPC_Initialize(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_init(&MPC_ISRAM2_DEV, - MPC_ISRAM2_RANGE_LIST, - MPC_ISRAM2_RANGE_LIST_LEN); - - return error_trans(ret); -} - -static int32_t ISRAM2_MPC_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t ISRAM2_MPC_GetBlockSize(uint32_t *blk_size) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_block_size(&MPC_ISRAM2_DEV, blk_size); - - return error_trans(ret); -} - -static int32_t ISRAM2_MPC_GetCtrlConfig(uint32_t *ctrl_val) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_ctrl(&MPC_ISRAM2_DEV, ctrl_val); - - return error_trans(ret); -} - -static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_set_ctrl(&MPC_ISRAM2_DEV, ctrl); - - return error_trans(ret); -} - -static int32_t ISRAM2_MPC_GetRegionConfig(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR *attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_region_config(&MPC_ISRAM2_DEV, base, limit, - (enum mpc_sie_sec_attr_t*)attr); - - return error_trans(ret); -} - -static int32_t ISRAM2_MPC_ConfigRegion(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_config_region(&MPC_ISRAM2_DEV, base, limit, - (enum mpc_sie_sec_attr_t)attr); - - return error_trans(ret); -} - -static int32_t ISRAM2_MPC_EnableInterrupt(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_irq_enable(&MPC_ISRAM2_DEV); - - return error_trans(ret); -} - -static void ISRAM2_MPC_DisableInterrupt(void) -{ - mpc_sie_irq_disable(&MPC_ISRAM2_DEV); -} - - -static void ISRAM2_MPC_ClearInterrupt(void) -{ - mpc_sie_clear_irq(&MPC_ISRAM2_DEV); -} - -static uint32_t ISRAM2_MPC_InterruptState(void) -{ - return mpc_sie_irq_state(&MPC_ISRAM2_DEV); -} - -static int32_t ISRAM2_MPC_LockDown(void) -{ - return mpc_sie_lock_down(&MPC_ISRAM2_DEV); -} - -/* ISRAM2_MPC Driver CMSIS access structure */ -ARM_DRIVER_MPC Driver_ISRAM2_MPC = { - .GetVersion = ARM_MPC_GetVersion, - .Initialize = ISRAM2_MPC_Initialize, - .Uninitialize = ISRAM2_MPC_Uninitialize, - .GetBlockSize = ISRAM2_MPC_GetBlockSize, - .GetCtrlConfig = ISRAM2_MPC_GetCtrlConfig, - .SetCtrlConfig = ISRAM2_MPC_SetCtrlConfig, - .ConfigRegion = ISRAM2_MPC_ConfigRegion, - .GetRegionConfig = ISRAM2_MPC_GetRegionConfig, - .EnableInterrupt = ISRAM2_MPC_EnableInterrupt, - .DisableInterrupt = ISRAM2_MPC_DisableInterrupt, - .ClearInterrupt = ISRAM2_MPC_ClearInterrupt, - .InterruptState = ISRAM2_MPC_InterruptState, - .LockDown = ISRAM2_MPC_LockDown, -}; -#endif /* RTE_ISRAM2_MPC */ - -#if (RTE_ISRAM3_MPC) -/* Ranges controlled by this ISRAM3_MPC */ -static const struct mpc_sie_memory_range_t MPC_ISRAM3_RANGE_S = { - .base = MPC_ISRAM3_RANGE_BASE_S, - .limit = MPC_ISRAM3_RANGE_LIMIT_S, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_SECURE -}; - -static const struct mpc_sie_memory_range_t MPC_ISRAM3_RANGE_NS = { - .base = MPC_ISRAM3_RANGE_BASE_NS, - .limit = MPC_ISRAM3_RANGE_LIMIT_NS, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_NONSECURE -}; - -#define MPC_ISRAM3_RANGE_LIST_LEN 2u -static const struct mpc_sie_memory_range_t* - MPC_ISRAM3_RANGE_LIST[MPC_ISRAM3_RANGE_LIST_LEN] = { - &MPC_ISRAM3_RANGE_S, - &MPC_ISRAM3_RANGE_NS - }; - -/* ISRAM3_MPC Driver wrapper functions */ -static int32_t ISRAM3_MPC_Initialize(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_init(&MPC_ISRAM3_DEV, - MPC_ISRAM3_RANGE_LIST, - MPC_ISRAM3_RANGE_LIST_LEN); - - return error_trans(ret); -} - -static int32_t ISRAM3_MPC_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t ISRAM3_MPC_GetBlockSize(uint32_t *blk_size) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_block_size(&MPC_ISRAM3_DEV, blk_size); - - return error_trans(ret); -} - -static int32_t ISRAM3_MPC_GetCtrlConfig(uint32_t *ctrl_val) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_ctrl(&MPC_ISRAM3_DEV, ctrl_val); - - return error_trans(ret); -} - -static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_set_ctrl(&MPC_ISRAM3_DEV, ctrl); - - return error_trans(ret); -} - -static int32_t ISRAM3_MPC_GetRegionConfig(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR *attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_region_config(&MPC_ISRAM3_DEV, base, limit, - (enum mpc_sie_sec_attr_t*)attr); - - return error_trans(ret); -} - -static int32_t ISRAM3_MPC_ConfigRegion(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_config_region(&MPC_ISRAM3_DEV, base, limit, - (enum mpc_sie_sec_attr_t)attr); - - return error_trans(ret); -} - -static int32_t ISRAM3_MPC_EnableInterrupt(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_irq_enable(&MPC_ISRAM3_DEV); - - return error_trans(ret); -} - -static void ISRAM3_MPC_DisableInterrupt(void) -{ - mpc_sie_irq_disable(&MPC_ISRAM3_DEV); -} - - -static void ISRAM3_MPC_ClearInterrupt(void) -{ - mpc_sie_clear_irq(&MPC_ISRAM3_DEV); -} - -static uint32_t ISRAM3_MPC_InterruptState(void) -{ - return mpc_sie_irq_state(&MPC_ISRAM3_DEV); -} - -static int32_t ISRAM3_MPC_LockDown(void) -{ - return mpc_sie_lock_down(&MPC_ISRAM3_DEV); -} - -/* ISRAM3_MPC Driver CMSIS access structure */ -ARM_DRIVER_MPC Driver_ISRAM3_MPC = { - .GetVersion = ARM_MPC_GetVersion, - .Initialize = ISRAM3_MPC_Initialize, - .Uninitialize = ISRAM3_MPC_Uninitialize, - .GetBlockSize = ISRAM3_MPC_GetBlockSize, - .GetCtrlConfig = ISRAM3_MPC_GetCtrlConfig, - .SetCtrlConfig = ISRAM3_MPC_SetCtrlConfig, - .ConfigRegion = ISRAM3_MPC_ConfigRegion, - .GetRegionConfig = ISRAM3_MPC_GetRegionConfig, - .EnableInterrupt = ISRAM3_MPC_EnableInterrupt, - .DisableInterrupt = ISRAM3_MPC_DisableInterrupt, - .ClearInterrupt = ISRAM3_MPC_ClearInterrupt, - .InterruptState = ISRAM3_MPC_InterruptState, - .LockDown = ISRAM3_MPC_LockDown, -}; -#endif /* RTE_ISRAM3_MPC */ - -#if (RTE_SSRAM1_MPC) -/* Ranges controlled by this SSRAM1_MPC */ -static const struct mpc_sie_memory_range_t MPC_SSRAM1_RANGE_S = { - .base = MPC_SSRAM1_RANGE_BASE_S, - .limit = MPC_SSRAM1_RANGE_LIMIT_S, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_SECURE -}; - -static const struct mpc_sie_memory_range_t MPC_SSRAM1_RANGE_NS = { - .base = MPC_SSRAM1_RANGE_BASE_NS, - .limit = MPC_SSRAM1_RANGE_LIMIT_NS, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_NONSECURE -}; - -#define MPC_SSRAM1_RANGE_LIST_LEN 2u -static const struct mpc_sie_memory_range_t* - MPC_SSRAM1_RANGE_LIST[MPC_SSRAM1_RANGE_LIST_LEN] = { - &MPC_SSRAM1_RANGE_S, - &MPC_SSRAM1_RANGE_NS - }; - -/* SSRAM1_MPC Driver wrapper functions */ -static int32_t SSRAM1_MPC_Initialize(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_init(&MPC_SSRAM1_DEV, - MPC_SSRAM1_RANGE_LIST, - MPC_SSRAM1_RANGE_LIST_LEN); - - return error_trans(ret); -} - -static int32_t SSRAM1_MPC_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t SSRAM1_MPC_GetBlockSize(uint32_t *blk_size) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_block_size(&MPC_SSRAM1_DEV, blk_size); - - return error_trans(ret); -} - -static int32_t SSRAM1_MPC_GetCtrlConfig(uint32_t *ctrl_val) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_ctrl(&MPC_SSRAM1_DEV, ctrl_val); - - return error_trans(ret); -} - -static int32_t SSRAM1_MPC_SetCtrlConfig(uint32_t ctrl) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_set_ctrl(&MPC_SSRAM1_DEV, ctrl); - - return error_trans(ret); -} - -static int32_t SSRAM1_MPC_GetRegionConfig(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR *attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_region_config(&MPC_SSRAM1_DEV, base, limit, - (enum mpc_sie_sec_attr_t*)attr); - - return error_trans(ret); -} - -static int32_t SSRAM1_MPC_ConfigRegion(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_config_region(&MPC_SSRAM1_DEV, base, limit, - (enum mpc_sie_sec_attr_t)attr); - - return error_trans(ret); -} - -static int32_t SSRAM1_MPC_EnableInterrupt(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_irq_enable(&MPC_SSRAM1_DEV); - - return error_trans(ret); -} - -static void SSRAM1_MPC_DisableInterrupt(void) -{ - mpc_sie_irq_disable(&MPC_SSRAM1_DEV); -} - - -static void SSRAM1_MPC_ClearInterrupt(void) -{ - mpc_sie_clear_irq(&MPC_SSRAM1_DEV); -} - -static uint32_t SSRAM1_MPC_InterruptState(void) -{ - return mpc_sie_irq_state(&MPC_SSRAM1_DEV); -} - -static int32_t SSRAM1_MPC_LockDown(void) -{ - return mpc_sie_lock_down(&MPC_SSRAM1_DEV); -} - -/* SSRAM1_MPC Driver CMSIS access structure */ -ARM_DRIVER_MPC Driver_SSRAM1_MPC = { - .GetVersion = ARM_MPC_GetVersion, - .Initialize = SSRAM1_MPC_Initialize, - .Uninitialize = SSRAM1_MPC_Uninitialize, - .GetBlockSize = SSRAM1_MPC_GetBlockSize, - .GetCtrlConfig = SSRAM1_MPC_GetCtrlConfig, - .SetCtrlConfig = SSRAM1_MPC_SetCtrlConfig, - .ConfigRegion = SSRAM1_MPC_ConfigRegion, - .GetRegionConfig = SSRAM1_MPC_GetRegionConfig, - .EnableInterrupt = SSRAM1_MPC_EnableInterrupt, - .DisableInterrupt = SSRAM1_MPC_DisableInterrupt, - .ClearInterrupt = SSRAM1_MPC_ClearInterrupt, - .InterruptState = SSRAM1_MPC_InterruptState, - .LockDown = SSRAM1_MPC_LockDown, -}; -#endif /* RTE_SSRAM1_MPC */ - -#if (RTE_SSRAM2_MPC) -/* Ranges controlled by this SSRAM2_MPC */ -static const struct mpc_sie_memory_range_t MPC_SSRAM2_RANGE_S = { - .base = MPC_SSRAM2_RANGE_BASE_S, - .limit = MPC_SSRAM2_RANGE_LIMIT_S, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_SECURE -}; - -static const struct mpc_sie_memory_range_t MPC_SSRAM2_RANGE_NS = { - .base = MPC_SSRAM2_RANGE_BASE_NS, - .limit = MPC_SSRAM2_RANGE_LIMIT_NS, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_NONSECURE -}; - -#define MPC_SSRAM2_RANGE_LIST_LEN 2u -static const struct mpc_sie_memory_range_t* - MPC_SSRAM2_RANGE_LIST[MPC_SSRAM2_RANGE_LIST_LEN] = { - &MPC_SSRAM2_RANGE_S, - &MPC_SSRAM2_RANGE_NS - }; - -/* SSRAM2_MPC Driver wrapper functions */ -static int32_t SSRAM2_MPC_Initialize(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_init(&MPC_SSRAM2_DEV, - MPC_SSRAM2_RANGE_LIST, - MPC_SSRAM2_RANGE_LIST_LEN); - - return error_trans(ret); -} - -static int32_t SSRAM2_MPC_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t SSRAM2_MPC_GetBlockSize(uint32_t *blk_size) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_block_size(&MPC_SSRAM2_DEV, blk_size); - - return error_trans(ret); -} - -static int32_t SSRAM2_MPC_GetCtrlConfig(uint32_t *ctrl_val) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_ctrl(&MPC_SSRAM2_DEV, ctrl_val); - - return error_trans(ret); -} - -static int32_t SSRAM2_MPC_SetCtrlConfig(uint32_t ctrl) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_set_ctrl(&MPC_SSRAM2_DEV, ctrl); - - return error_trans(ret); -} - -static int32_t SSRAM2_MPC_GetRegionConfig(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR *attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_region_config(&MPC_SSRAM2_DEV, base, limit, - (enum mpc_sie_sec_attr_t*)attr); - - return error_trans(ret); -} - -static int32_t SSRAM2_MPC_ConfigRegion(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_config_region(&MPC_SSRAM2_DEV, base, limit, - (enum mpc_sie_sec_attr_t)attr); - - return error_trans(ret); -} - -static int32_t SSRAM2_MPC_EnableInterrupt(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_irq_enable(&MPC_SSRAM2_DEV); - - return error_trans(ret); -} - -static void SSRAM2_MPC_DisableInterrupt(void) -{ - mpc_sie_irq_disable(&MPC_SSRAM2_DEV); -} - - -static void SSRAM2_MPC_ClearInterrupt(void) -{ - mpc_sie_clear_irq(&MPC_SSRAM2_DEV); -} - -static uint32_t SSRAM2_MPC_InterruptState(void) -{ - return mpc_sie_irq_state(&MPC_SSRAM2_DEV); -} - -static int32_t SSRAM2_MPC_LockDown(void) -{ - return mpc_sie_lock_down(&MPC_SSRAM2_DEV); -} - -/* SSRAM2_MPC Driver CMSIS access structure */ -ARM_DRIVER_MPC Driver_SSRAM2_MPC = { - .GetVersion = ARM_MPC_GetVersion, - .Initialize = SSRAM2_MPC_Initialize, - .Uninitialize = SSRAM2_MPC_Uninitialize, - .GetBlockSize = SSRAM2_MPC_GetBlockSize, - .GetCtrlConfig = SSRAM2_MPC_GetCtrlConfig, - .SetCtrlConfig = SSRAM2_MPC_SetCtrlConfig, - .ConfigRegion = SSRAM2_MPC_ConfigRegion, - .GetRegionConfig = SSRAM2_MPC_GetRegionConfig, - .EnableInterrupt = SSRAM2_MPC_EnableInterrupt, - .DisableInterrupt = SSRAM2_MPC_DisableInterrupt, - .ClearInterrupt = SSRAM2_MPC_ClearInterrupt, - .InterruptState = SSRAM2_MPC_InterruptState, - .LockDown = SSRAM2_MPC_LockDown, -}; -#endif /* RTE_SSRAM2_MPC */ - -#if (RTE_SSRAM3_MPC) -/* Ranges controlled by this SSRAM3_MPC */ -static const struct mpc_sie_memory_range_t MPC_SSRAM3_RANGE_S = { - .base = MPC_SSRAM3_RANGE_BASE_S, - .limit = MPC_SSRAM3_RANGE_LIMIT_S, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_SECURE -}; - -static const struct mpc_sie_memory_range_t MPC_SSRAM3_RANGE_NS = { - .base = MPC_SSRAM3_RANGE_BASE_NS, - .limit = MPC_SSRAM3_RANGE_LIMIT_NS, - .range_offset = 0, - .attr = MPC_SIE_SEC_ATTR_NONSECURE -}; - -#define MPC_SSRAM3_RANGE_LIST_LEN 2u -static const struct mpc_sie_memory_range_t* - MPC_SSRAM3_RANGE_LIST[MPC_SSRAM3_RANGE_LIST_LEN] = { - &MPC_SSRAM3_RANGE_S, - &MPC_SSRAM3_RANGE_NS - }; - -/* SSRAM3_MPC Driver wrapper functions */ -static int32_t SSRAM3_MPC_Initialize(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_init(&MPC_SSRAM3_DEV, - MPC_SSRAM3_RANGE_LIST, - MPC_SSRAM3_RANGE_LIST_LEN); - - return error_trans(ret); -} - -static int32_t SSRAM3_MPC_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t SSRAM3_MPC_GetBlockSize(uint32_t *blk_size) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_block_size(&MPC_SSRAM3_DEV, blk_size); - - return error_trans(ret); -} - -static int32_t SSRAM3_MPC_GetCtrlConfig(uint32_t *ctrl_val) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_ctrl(&MPC_SSRAM3_DEV, ctrl_val); - - return error_trans(ret); -} - -static int32_t SSRAM3_MPC_SetCtrlConfig(uint32_t ctrl) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_set_ctrl(&MPC_SSRAM3_DEV, ctrl); - - return error_trans(ret); -} - -static int32_t SSRAM3_MPC_GetRegionConfig(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR *attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_get_region_config(&MPC_SSRAM3_DEV, base, limit, - (enum mpc_sie_sec_attr_t*)attr); - - return error_trans(ret); -} - -static int32_t SSRAM3_MPC_ConfigRegion(uintptr_t base, - uintptr_t limit, - ARM_MPC_SEC_ATTR attr) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_config_region(&MPC_SSRAM3_DEV, base, limit, - (enum mpc_sie_sec_attr_t)attr); - - return error_trans(ret); -} - -static int32_t SSRAM3_MPC_EnableInterrupt(void) -{ - enum mpc_sie_error_t ret; - - ret = mpc_sie_irq_enable(&MPC_SSRAM3_DEV); - - return error_trans(ret); -} - -static void SSRAM3_MPC_DisableInterrupt(void) -{ - mpc_sie_irq_disable(&MPC_SSRAM3_DEV); -} - - -static void SSRAM3_MPC_ClearInterrupt(void) -{ - mpc_sie_clear_irq(&MPC_SSRAM3_DEV); -} - -static uint32_t SSRAM3_MPC_InterruptState(void) -{ - return mpc_sie_irq_state(&MPC_SSRAM3_DEV); -} - -static int32_t SSRAM3_MPC_LockDown(void) -{ - return mpc_sie_lock_down(&MPC_SSRAM3_DEV); -} - -/* SSRAM3_MPC Driver CMSIS access structure */ -ARM_DRIVER_MPC Driver_SSRAM3_MPC = { - .GetVersion = ARM_MPC_GetVersion, - .Initialize = SSRAM3_MPC_Initialize, - .Uninitialize = SSRAM3_MPC_Uninitialize, - .GetBlockSize = SSRAM3_MPC_GetBlockSize, - .GetCtrlConfig = SSRAM3_MPC_GetCtrlConfig, - .SetCtrlConfig = SSRAM3_MPC_SetCtrlConfig, - .ConfigRegion = SSRAM3_MPC_ConfigRegion, - .GetRegionConfig = SSRAM3_MPC_GetRegionConfig, - .EnableInterrupt = SSRAM3_MPC_EnableInterrupt, - .DisableInterrupt = SSRAM3_MPC_DisableInterrupt, - .ClearInterrupt = SSRAM3_MPC_ClearInterrupt, - .InterruptState = SSRAM3_MPC_InterruptState, - .LockDown = SSRAM3_MPC_LockDown, -}; -#endif /* RTE_SSRAM3_MPC */ diff --git a/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_USART.c b/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_USART.c deleted file mode 100644 index 1cada7737d..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/cmsis_drivers/Driver_USART.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (c) 2013-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "Driver_USART.h" - -#include "cmsis_driver_config.h" -#include "RTE_Device.h" -#include "system_cmsdk_sse-200_aws.h" -#include "device_cfg.h" - -#ifndef ARG_UNUSED -#define ARG_UNUSED(arg) (void)arg -#endif - -/* Driver version */ -#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) - -/* Driver Version */ -static const ARM_DRIVER_VERSION DriverVersion = { - ARM_USART_API_VERSION, - ARM_USART_DRV_VERSION -}; - -/* Driver Capabilities */ -static const ARM_USART_CAPABILITIES DriverCapabilities = { - 1, /* supports UART (Asynchronous) mode */ - 0, /* supports Synchronous Master mode */ - 0, /* supports Synchronous Slave mode */ - 0, /* supports UART Single-wire mode */ - 0, /* supports UART IrDA mode */ - 0, /* supports UART Smart Card mode */ - 0, /* Smart Card Clock generator available */ - 0, /* RTS Flow Control available */ - 0, /* CTS Flow Control available */ - 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */ - 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */ - 0, /* RTS Line: 0=not available, 1=available */ - 0, /* CTS Line: 0=not available, 1=available */ - 0, /* DTR Line: 0=not available, 1=available */ - 0, /* DSR Line: 0=not available, 1=available */ - 0, /* DCD Line: 0=not available, 1=available */ - 0, /* RI Line: 0=not available, 1=available */ - 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */ - 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */ - 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */ - 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */ - 0 /* Reserved */ -}; - -static ARM_DRIVER_VERSION ARM_USART_GetVersion(void) -{ - return DriverVersion; -} - -static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void) -{ - return DriverCapabilities; -} - -typedef struct { - struct uart_cmsdk_dev_t *dev; /* UART device structure */ - uint32_t tx_nbr_bytes; /* Number of bytes transfered */ - uint32_t rx_nbr_bytes; /* Number of bytes recevied */ - ARM_USART_SignalEvent_t cb_event; /* Callback function for events */ -} UARTx_Resources; - -static int32_t ARM_USARTx_Initialize(UARTx_Resources *uart_dev) -{ - /* Initializes generic UART driver */ - uart_cmsdk_init(uart_dev->dev, PeripheralClock); - - return ARM_DRIVER_OK; -} - -static int32_t ARM_USARTx_PowerControl(UARTx_Resources *uart_dev, - ARM_POWER_STATE state) -{ - ARG_UNUSED(uart_dev); - - switch (state) { - case ARM_POWER_OFF: - case ARM_POWER_LOW: - return ARM_DRIVER_ERROR_UNSUPPORTED; - case ARM_POWER_FULL: - /* Nothing to be done */ - return ARM_DRIVER_OK; - /* default: The default is not defined intentionally to force the - * compiler to check that all the enumeration values are - * covered in the switch.*/ - } -} - -static int32_t ARM_USARTx_Send(UARTx_Resources *uart_dev, const void *data, - uint32_t num) -{ - const uint8_t *p_data = (const uint8_t *)data; - - if ((data == NULL) || (num == 0U)) { - /* Invalid parameters */ - return ARM_DRIVER_ERROR_PARAMETER; - } - - /* Resets previous TX counter */ - uart_dev->tx_nbr_bytes = 0; - - while (uart_dev->tx_nbr_bytes != num) { - /* Waits until UART is ready to transmit */ - while (!uart_cmsdk_tx_ready(uart_dev->dev)) { - }; - - /* As UART is ready to transmit at this point, the write function can - * not return any transmit error */ - (void)uart_cmsdk_write(uart_dev->dev, *p_data); - - uart_dev->tx_nbr_bytes++; - p_data++; - } - - /* Waits until character is transmited */ - while (!uart_cmsdk_tx_ready(uart_dev->dev)) { - }; - - return ARM_DRIVER_OK; -} - -static int32_t ARM_USARTx_Receive(UARTx_Resources *uart_dev, - void *data, uint32_t num) -{ - uint8_t *p_data = (uint8_t *)data; - - if ((data == NULL) || (num == 0U)) { - // Invalid parameters - return ARM_DRIVER_ERROR_PARAMETER; - } - - /* Resets previous RX counter */ - uart_dev->rx_nbr_bytes = 0; - - while (uart_dev->rx_nbr_bytes != num) { - /* Waits until one character is received */ - while (!uart_cmsdk_rx_ready(uart_dev->dev)){}; - - /* As UART has received one byte, the read can not - * return any receive error at this point */ - (void)uart_cmsdk_read(uart_dev->dev, p_data); - - uart_dev->rx_nbr_bytes++; - p_data++; - } - - return ARM_DRIVER_OK; -} - -static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources *uart_dev) -{ - return uart_dev->tx_nbr_bytes; -} - -static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources *uart_dev) -{ - return uart_dev->rx_nbr_bytes; -} - -static int32_t ARM_USARTx_Control(UARTx_Resources *uart_dev, uint32_t control, - uint32_t arg) -{ - switch (control & ARM_USART_CONTROL_Msk) { - case ARM_USART_MODE_ASYNCHRONOUS: - if (uart_cmsdk_set_baudrate(uart_dev->dev, arg) != UART_CMSDK_ERR_NONE) { - return ARM_USART_ERROR_BAUDRATE; - } - break; - /* Unsupported command */ - default: - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - /* UART Data bits */ - if (control & ARM_USART_DATA_BITS_Msk) { - /* Data bit is not configurable */ - return ARM_DRIVER_ERROR_UNSUPPORTED; - } - - /* UART Parity */ - if (control & ARM_USART_PARITY_Msk) { - /* Parity is not configurable */ - return ARM_USART_ERROR_PARITY; - } - - /* USART Stop bits */ - if (control & ARM_USART_STOP_BITS_Msk) { - /* Stop bit is not configurable */ - return ARM_USART_ERROR_STOP_BITS; - } - - return ARM_DRIVER_OK; -} - -#if (RTE_USART0) -/* USART0 Driver wrapper functions */ -static UARTx_Resources USART0_DEV = { - .dev = &UART0_CMSDK_DEV, - .tx_nbr_bytes = 0, - .rx_nbr_bytes = 0, - .cb_event = NULL, -}; - -static int32_t ARM_USART0_Initialize(ARM_USART_SignalEvent_t cb_event) -{ - USART0_DEV.cb_event = cb_event; - - return ARM_USARTx_Initialize(&USART0_DEV); -} - -static int32_t ARM_USART0_Uninitialize(void) -{ - /* Nothing to be done */ - return ARM_DRIVER_OK; -} - -static int32_t ARM_USART0_PowerControl(ARM_POWER_STATE state) -{ - return ARM_USARTx_PowerControl(&USART0_DEV, state); -} - -static int32_t ARM_USART0_Send(const void *data, uint32_t num) -{ - return ARM_USARTx_Send(&USART0_DEV, data, num); -} - -static int32_t ARM_USART0_Receive(void *data, uint32_t num) -{ - return ARM_USARTx_Receive(&USART0_DEV, data, num); -} - -static int32_t ARM_USART0_Transfer(const void *data_out, void *data_in, - uint32_t num) -{ - ARG_UNUSED(data_out); - ARG_UNUSED(data_in); - ARG_UNUSED(num); - - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static uint32_t ARM_USART0_GetTxCount(void) -{ - return ARM_USARTx_GetTxCount(&USART0_DEV); -} - -static uint32_t ARM_USART0_GetRxCount(void) -{ - return ARM_USARTx_GetRxCount(&USART0_DEV); -} -static int32_t ARM_USART0_Control(uint32_t control, uint32_t arg) -{ - return ARM_USARTx_Control(&USART0_DEV, control, arg); -} - -static ARM_USART_STATUS ARM_USART0_GetStatus(void) -{ - ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; - return status; -} - -static int32_t ARM_USART0_SetModemControl(ARM_USART_MODEM_CONTROL control) -{ - ARG_UNUSED(control); - return ARM_DRIVER_ERROR_UNSUPPORTED; -} - -static ARM_USART_MODEM_STATUS ARM_USART0_GetModemStatus(void) -{ - ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; - return modem_status; -} - -extern ARM_DRIVER_USART Driver_USART0; -ARM_DRIVER_USART Driver_USART0 = { - ARM_USART_GetVersion, - ARM_USART_GetCapabilities, - ARM_USART0_Initialize, - ARM_USART0_Uninitialize, - ARM_USART0_PowerControl, - ARM_USART0_Send, - ARM_USART0_Receive, - ARM_USART0_Transfer, - ARM_USART0_GetTxCount, - ARM_USART0_GetRxCount, - ARM_USART0_Control, - ARM_USART0_GetStatus, - ARM_USART0_SetModemControl, - ARM_USART0_GetModemStatus -}; -#endif /* RTE_USART0 */ diff --git a/platform/ext/target/mps2/sse-200_aws/config.cmake b/platform/ext/target/mps2/sse-200_aws/config.cmake deleted file mode 100644 index a81c8a1137..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/config.cmake +++ /dev/null @@ -1,6 +0,0 @@ -#------------------------------------------------------------------------------- -# Copyright (c) 2020, Arm Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# -#------------------------------------------------------------------------------- diff --git a/platform/ext/target/mps2/sse-200_aws/device_cfg.h b/platform/ext/target/mps2/sse-200_aws/device_cfg.h deleted file mode 100644 index 42f1e7cf05..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/device_cfg.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __ARM_LTD_DEVICE_CFG_H__ -#define __ARM_LTD_DEVICE_CFG_H__ - -/** - * \file device_cfg.h - * \brief - * This is the default device configuration file with all peripherals - * defined and configured to be use via the secure and/or non-secure base - * address. This file is an example of how to define your own configuration - * file with the peripherals required for your application. - */ - -/* ARM Memory Protection Controller (MPC) */ -#define MPC_SSRAM1_S -#define MPC_SSRAM1_DEV MPC_SSRAM1_DEV_S -#define MPC_SSRAM2_S -#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S - -/* ARM Peripheral Protection Controllers (PPC) */ -#define APB_PPCEXP2_S -#define APB_PPCEXP2_DEV APB_PPCEXP2_DEV_S - -/* ARM UART */ -#define DEFAULT_UART_BAUDRATE 38400 -#define UART0_CMSDK_NS -#define UART0_CMSDK_DEV UART0_CMSDK_DEV_NS - -/* CMSDK Timers */ -#define CMSDK_TIMER0_S -#define CMSDK_TIMER0_NS -#define CMSDK_TIMER1_S -#define CMSDK_TIMER1_NS - -#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/gcc/sse-200_aws_bl2.ld b/platform/ext/target/mps2/sse-200_aws/gcc/sse-200_aws_bl2.ld deleted file mode 100644 index a9092f4c8f..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/gcc/sse-200_aws_bl2.ld +++ /dev/null @@ -1,190 +0,0 @@ -;/* -; * Copyright (c) 2017-2019 Arm Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; * -; * This file is derivative of CMSIS V5.00 gcc_arm.ld -; */ - -/* Linker script to configure memory regions. */ -/* This file will be run trough the pre-processor. */ - -#include "region_defs.h" - -MEMORY -{ - FLASH (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE - RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE -} - -__heap_size__ = BL2_HEAP_SIZE; -__msp_stack_size__ = BL2_MSP_STACK_SIZE; - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * define etext2/data2_start/data2_end and - * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_sse-200_aws_bl2.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (DEFINED(__etext2) ? __etext2 : 0) - LONG (DEFINED(__data2_start__) ? __data2_start__ : 0) - LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0) - __copy_table_end__ = .; - } > FLASH - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_sse-200_aws_bl2.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0) - LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0) - __zero_table_end__ = .; - } > FLASH - - __etext = .; - - .tfm_bl2_shared_data : ALIGN(32) - { - . += BOOT_TFM_SHARED_DATA_SIZE; - } > RAM - Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data); - Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - Image$$ER_DATA$$Base = ADDR(.data); - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - bss_size = __bss_end__ - __bss_start__; - - .msp_stack : ALIGN(32) - { - . += __msp_stack_size__; - } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - - .heap : ALIGN(8) - { - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += __heap_size__; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > RAM - Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap); - - PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); -} diff --git a/platform/ext/target/mps2/sse-200_aws/gcc/sse-200_aws_ns.ld b/platform/ext/target/mps2/sse-200_aws/gcc/sse-200_aws_ns.ld deleted file mode 100644 index 783ee106c5..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/gcc/sse-200_aws_ns.ld +++ /dev/null @@ -1,189 +0,0 @@ -;/* -; * Copyright (c) 2017-2019 Arm Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; * -; * This file is derivative of CMSIS V5.00 gcc_arm.ld -; */ - -/* Linker script to configure memory regions. */ -/* This file will be run trough the pre-processor. */ - -#include "region_defs.h" - -MEMORY -{ - FLASH (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE - RAM (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE -} - -__heap_size__ = NS_HEAP_SIZE; -__psp_stack_size__ = NS_PSP_STACK_SIZE; -__msp_stack_size__ = NS_MSP_STACK_SIZE; - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * define etext2/data2_start/data2_end and - * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_sse-200_aws_ns.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (DEFINED(__etext2) ? __etext2 : 0) - LONG (DEFINED(__data2_start__) ? __data2_start__ : 0) - LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0) - __copy_table_end__ = .; - } > FLASH - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_sse-200_aws_ns.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0) - LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0) - __zero_table_end__ = .; - } > FLASH - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - bss_size = __bss_end__ - __bss_start__; - - .msp_stack : ALIGN(32) - { - . += __msp_stack_size__; - } > RAM - Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack); - Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - - .psp_stack : ALIGN(32) - { - . += __psp_stack_size__; - } > RAM - Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); - Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); - - .heap : ALIGN(8) - { - __end__ = .; - PROVIDE(end = .); - __HeapBase = .; - . += __heap_size__; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > RAM - - PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); -} diff --git a/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_bl2.S b/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_bl2.S deleted file mode 100644 index 11181d44a3..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_bl2.S +++ /dev/null @@ -1,340 +0,0 @@ -;/* -; * Copyright (c) 2009-2019 Arm Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; * -; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S -; */ - - .syntax unified - .arch armv8-m.main - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - - /* Core interrupts */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long SecureFault_Handler /* Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */ - .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */ - .long S32K_TIMER_Handler /* 2: S32K Timer Handler */ - .long TIMER0_Handler /* 3: TIMER 0 Handler */ - .long TIMER1_Handler /* 4: TIMER 1 Handler */ - .long DUALTIMER_Handler /* 5: Dual Timer Handler */ - .long MHU0_Handler /* 6: Message Handling Unit 0 */ - .long MHU1_Handler /* 7: Message Handling Unit 1 */ - .long 0 /* 8: Reserved */ - .long MPC_Handler /* 9: MPC Combined (Secure) Handler */ - .long PPC_Handler /* 10: PPC Combined (Secure) Handler */ - .long MSC_Handler /* 11: MSC Combined (Secure) Handler */ - .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */ - .long 0 /* 13: Reserved */ - .long 0 /* 14: Reserved */ - .long 0 /* 15: Reserved */ - .long 0 /* 16: Reserved */ - .long 0 /* 17: Reserved */ - .long 0 /* 18: Reserved */ - .long 0 /* 19: Reserved */ - .long 0 /* 20: Reserved */ - .long 0 /* 21: Reserved */ - .long 0 /* 22: Reserved */ - .long 0 /* 23: Reserved */ - .long 0 /* 24: Reserved */ - .long 0 /* 25: Reserved */ - .long 0 /* 26: Reserved */ - .long 0 /* 27: Reserved */ - .long 0 /* 28: Reserved */ - .long 0 /* 29: Reserved */ - .long 0 /* 30: Reserved */ - .long 0 /* 31: Reserved */ - .long UARTRX0_Handler /* 32: UART 0 RX Handler */ - .long UARTTX0_Handler /* 33: UART 0 TX Handler */ - .long 0 /* 34: Reserved */ - .long 0 /* 35: Reserved */ - .long 0 /* 36: Reserved */ - .long 0 /* 37: Reserved */ - .long 0 /* 38: Reserved */ - .long 0 /* 39: Reserved */ - .long 0 /* 40: Reserved */ - .long 0 /* 41: Reserved */ - .long UART0_Handler /* 42: UART 0 combined Handler */ - .long 0 /* 43: Reserved */ - .long 0 /* 44: Reserved */ - .long 0 /* 45: Reserved */ - .long 0 /* 46: Reserved */ - .long UARTOVF_Handler /* 47: UART 0 Overflow Handler */ - .long 0 /* 48: Reserved */ - .long 0 /* 49: Reserved */ - .long 0 /* 50: Reserved */ - .long 0 /* 51: Reserved */ - .long 0 /* 52: Reserved */ - .long 0 /* 53: Reserved */ - .long 0 /* 54: Reserved */ - .long 0 /* 55: Reserved */ - .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */ - .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */ - .long DMA0_Handler /* 58: DMA 0 Combined Handler */ - .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */ - .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */ - .long DMA1_Handler /* 61: DMA 1 Combined Handler */ - .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */ - .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */ - .long DMA2_Handler /* 64: DMA 2 Combined Handler */ - .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */ - .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */ - .long DMA3_Handler /* 67: DMA 3 Combined Handler */ - .long 0 /* 68: Reserved */ - .long 0 /* 69: Reserved */ - .long 0 /* 70: Reserved */ - .long 0 /* 71: Reserved */ - .long 0 /* 72: Reserved */ - .long 0 /* 73: Reserved */ - .long 0 /* 74: Reserved */ - .long 0 /* 75: Reserved */ - .long 0 /* 76: Reserved */ - .long 0 /* 77: Reserved */ - .long 0 /* 78: Reserved */ - .long 0 /* 79: Reserved */ - .long 0 /* 80: Reserved */ - .long 0 /* 81: Reserved */ - .long 0 /* 82: Reserved */ - .long 0 /* 83: Reserved */ - .long 0 /* 84: Reserved */ - .long 0 /* 85: Reserved */ - .long 0 /* 86: Reserved */ - .long 0 /* 87: Reserved */ - .long 0 /* 88: Reserved */ - .long 0 /* 89: Reserved */ - .long 0 /* 90: Reserved */ - .long 0 /* 91: Reserved */ - .long 0 /* 92: Reserved */ - .long 0 /* 93: Reserved */ - .long 0 /* 94: Reserved */ - .long 0 /* 95: Reserved */ - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - - /* Only run on core 0 */ - mov r0, #0x50000000 - add r0, #0x0001F000 - ldr r0, [r0] - cmp r0,#0 -not_the_core_to_run_on: - bne not_the_core_to_run_on - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - bl SystemInit - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - -/* Macro to define default handlers. */ - .macro def_irq_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - \handler_name: - b \handler_name - .endm - - /* Core interrupts */ - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - /* External interrupts */ - def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */ - def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */ - def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */ - def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */ - def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */ - def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */ - def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */ - def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */ - def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */ - def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */ - def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */ - def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */ - def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */ - def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */ - def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */ - def_irq_handler UARTOVF_Handler /* 47: UART 0 Overflow Handler */ - def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */ - def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */ - def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */ - def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */ - def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */ - def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */ - def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */ - def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */ - def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */ - def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */ - def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */ - def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */ - - .end diff --git a/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_ns.S b/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_ns.S deleted file mode 100644 index af3c94a094..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_ns.S +++ /dev/null @@ -1,333 +0,0 @@ -;/* -; * Copyright (c) 2009-2020 Arm Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; * -; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S -; */ - - .syntax unified - .arch armv8-m.main - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ - - /* Core interrupts */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */ - .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */ - .long S32K_TIMER_Handler /* 2: S32K Timer Handler */ - .long TIMER0_Handler /* 3: TIMER 0 Handler */ - .long TIMER1_Handler /* 4: TIMER 1 Handler */ - .long DUALTIMER_Handler /* 5: Dual Timer Handler */ - .long MHU0_Handler /* 6: Message Handling Unit 0 */ - .long MHU1_Handler /* 7: Message Handling Unit 1 */ - .long 0 /* 8: Reserved */ - .long 0 /* 9: Reserved */ - .long 0 /* 10: Reserved */ - .long MSC_Handler /* 11: MSC Combined (Secure) Handler */ - .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */ - .long 0 /* 13: Reserved */ - .long 0 /* 14: Reserved */ - .long 0 /* 15: Reserved */ - .long 0 /* 16: Reserved */ - .long 0 /* 17: Reserved */ - .long 0 /* 18: Reserved */ - .long 0 /* 19: Reserved */ - .long 0 /* 20: Reserved */ - .long 0 /* 21: Reserved */ - .long 0 /* 22: Reserved */ - .long 0 /* 23: Reserved */ - .long 0 /* 24: Reserved */ - .long 0 /* 25: Reserved */ - .long 0 /* 26: Reserved */ - .long 0 /* 27: Reserved */ - .long 0 /* 28: Reserved */ - .long 0 /* 29: Reserved */ - .long 0 /* 30: Reserved */ - .long 0 /* 31: Reserved */ - .long UARTRX0_Handler /* 32: UART 0 RX Handler */ - .long UARTTX0_Handler /* 33: UART 0 TX Handler */ - .long 0 /* 34: Reserved */ - .long 0 /* 35: Reserved */ - .long 0 /* 36: Reserved */ - .long 0 /* 37: Reserved */ - .long 0 /* 38: Reserved */ - .long 0 /* 39: Reserved */ - .long 0 /* 40: Reserved */ - .long 0 /* 41: Reserved */ - .long UART0_Handler /* 42: UART 0 combined Handler */ - .long 0 /* 43: Reserved */ - .long 0 /* 44: Reserved */ - .long 0 /* 45: Reserved */ - .long 0 /* 46: Reserved */ - .long UARTOVF_Handler /* 47: UART 0 Overflow Handler */ - .long 0 /* 48: Reserved */ - .long 0 /* 49: Reserved */ - .long 0 /* 50: Reserved */ - .long 0 /* 51: Reserved */ - .long 0 /* 52: Reserved */ - .long 0 /* 53: Reserved */ - .long 0 /* 54: Reserved */ - .long 0 /* 55: Reserved */ - .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */ - .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */ - .long DMA0_Handler /* 58: DMA 0 Combined Handler */ - .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */ - .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */ - .long DMA1_Handler /* 61: DMA 1 Combined Handler */ - .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */ - .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */ - .long DMA2_Handler /* 64: DMA 2 Combined Handler */ - .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */ - .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */ - .long DMA3_Handler /* 67: DMA 3 Combined Handler */ - .long 0 /* 68: Reserved */ - .long 0 /* 69: Reserved */ - .long 0 /* 70: Reserved */ - .long 0 /* 71: Reserved */ - .long 0 /* 72: Reserved */ - .long 0 /* 73: Reserved */ - .long 0 /* 74: Reserved */ - .long 0 /* 75: Reserved */ - .long 0 /* 76: Reserved */ - .long 0 /* 77: Reserved */ - .long 0 /* 78: Reserved */ - .long 0 /* 79: Reserved */ - .long 0 /* 80: Reserved */ - .long 0 /* 81: Reserved */ - .long 0 /* 82: Reserved */ - .long 0 /* 83: Reserved */ - .long 0 /* 84: Reserved */ - .long 0 /* 85: Reserved */ - .long 0 /* 86: Reserved */ - .long 0 /* 87: Reserved */ - .long 0 /* 88: Reserved */ - .long 0 /* 89: Reserved */ - .long 0 /* 90: Reserved */ - .long 0 /* 91: Reserved */ - .long 0 /* 92: Reserved */ - .long 0 /* 93: Reserved */ - .long 0 /* 94: Reserved */ - .long 0 /* 95: Reserved */ - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - -/* Macro to define default handlers. */ - .macro def_irq_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - \handler_name: - b \handler_name - .endm - - /* Core interrupts */ - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - /* External interrupts */ - def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */ - def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */ - def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */ - def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */ - def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */ - def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */ - def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */ - def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */ - def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */ - def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */ - def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */ - def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */ - def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */ - def_irq_handler UARTOVF_Handler /* 47: UART 0 Overflow Handler */ - def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */ - def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */ - def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */ - def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */ - def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */ - def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */ - def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */ - def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */ - def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */ - def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */ - def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */ - def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */ - - .end diff --git a/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_s.S b/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_s.S deleted file mode 100644 index 2584242e8f..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/gcc/startup_cmsdk_sse-200_aws_s.S +++ /dev/null @@ -1,341 +0,0 @@ -;/* -; * Copyright (c) 2009-2020 Arm Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; * -; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S -; */ - -#include "tfm_plat_config.h" - - .syntax unified - .arch armv8-m.main - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ - - /* Core interrupts */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long SecureFault_Handler /* Secure Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */ - .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */ - .long S32K_TIMER_Handler /* 2: S32K Timer Handler */ - .long TFM_TIMER0_IRQ_Handler /* 3: TIMER 0 Handler */ - .long TIMER1_Handler /* 4: TIMER 1 Handler */ - .long DUALTIMER_Handler /* 5: Dual Timer Handler */ - .long MHU0_Handler /* 6: Message Handling Unit 0 */ - .long MHU1_Handler /* 7: Message Handling Unit 1 */ - .long 0 /* 8: Reserved */ - .long MPC_Handler /* 9: MPC Combined (Secure) Handler */ - .long PPC_Handler /* 10: PPC Combined (Secure) Handler */ - .long MSC_Handler /* 11: MSC Combined (Secure) Handler */ - .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */ - .long 0 /* 13: Reserved */ - .long 0 /* 14: Reserved */ - .long 0 /* 15: Reserved */ - .long 0 /* 16: Reserved */ - .long 0 /* 17: Reserved */ - .long 0 /* 18: Reserved */ - .long 0 /* 19: Reserved */ - .long 0 /* 20: Reserved */ - .long 0 /* 21: Reserved */ - .long 0 /* 22: Reserved */ - .long 0 /* 23: Reserved */ - .long 0 /* 24: Reserved */ - .long 0 /* 25: Reserved */ - .long 0 /* 26: Reserved */ - .long 0 /* 27: Reserved */ - .long 0 /* 28: Reserved */ - .long 0 /* 29: Reserved */ - .long 0 /* 30: Reserved */ - .long 0 /* 31: Reserved */ - .long UARTRX0_Handler /* 32: UART 0 RX Handler */ - .long UARTTX0_Handler /* 33: UART 0 TX Handler */ - .long 0 /* 34: Reserved */ - .long 0 /* 35: Reserved */ - .long 0 /* 36: Reserved */ - .long 0 /* 37: Reserved */ - .long 0 /* 38: Reserved */ - .long 0 /* 39: Reserved */ - .long 0 /* 40: Reserved */ - .long 0 /* 41: Reserved */ - .long UART0_Handler /* 42: UART 0 combined Handler */ - .long 0 /* 43: Reserved */ - .long 0 /* 44: Reserved */ - .long 0 /* 45: Reserved */ - .long 0 /* 46: Reserved */ - .long UARTOVF_Handler /* 47: UART 0 Overflow Handler */ - .long 0 /* 48: Reserved */ - .long 0 /* 49: Reserved */ - .long 0 /* 50: Reserved */ - .long 0 /* 51: Reserved */ - .long 0 /* 52: Reserved */ - .long 0 /* 53: Reserved */ - .long 0 /* 54: Reserved */ - .long 0 /* 55: Reserved */ - .long DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */ - .long DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */ - .long DMA0_Handler /* 58: DMA 0 Combined Handler */ - .long DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */ - .long DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */ - .long DMA1_Handler /* 61: DMA 1 Combined Handler */ - .long DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */ - .long DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */ - .long DMA2_Handler /* 64: DMA 2 Combined Handler */ - .long DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */ - .long DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */ - .long DMA3_Handler /* 67: DMA 3 Combined Handler */ - .long 0 /* 68: Reserved */ - .long 0 /* 69: Reserved */ - .long 0 /* 70: Reserved */ - .long 0 /* 71: Reserved */ - .long 0 /* 72: Reserved */ - .long 0 /* 73: Reserved */ - .long 0 /* 74: Reserved */ - .long 0 /* 75: Reserved */ - .long 0 /* 76: Reserved */ - .long 0 /* 77: Reserved */ - .long 0 /* 78: Reserved */ - .long 0 /* 79: Reserved */ - .long 0 /* 80: Reserved */ - .long 0 /* 81: Reserved */ - .long 0 /* 82: Reserved */ - .long 0 /* 83: Reserved */ - .long 0 /* 84: Reserved */ - .long 0 /* 85: Reserved */ - .long 0 /* 86: Reserved */ - .long 0 /* 87: Reserved */ - .long 0 /* 88: Reserved */ - .long 0 /* 89: Reserved */ - .long 0 /* 90: Reserved */ - .long 0 /* 91: Reserved */ - .long 0 /* 92: Reserved */ - .long 0 /* 93: Reserved */ - .long 0 /* 94: Reserved */ - .long 0 /* 95: Reserved */ - - .size __Vectors, . - __Vectors - - .text - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - cpsid i /* Disable IRQs */ - bl SystemInit - - mrs r0, control /* Get control value */ - orr r0, r0, #2 /* Select switch to PSP */ - msr control, r0 - ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit - msr psp, r0 - -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler, . - Reset_Handler - - -/* Macro to define default handlers. */ - .macro def_irq_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - \handler_name: - b \handler_name - .endm - - /* Core interrupts */ - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler SecureFault_Handler - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - /* External interrupts */ - def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */ - def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */ - def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */ - def_irq_handler TFM_TIMER0_IRQ_Handler /* 3: TIMER 0 Handler */ - def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */ - def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */ - def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */ - def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */ - def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */ - def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */ - def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */ - def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */ - def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */ - def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */ - def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */ - def_irq_handler UARTOVF_Handler /* 47: UART 0 Overflow Handler */ - def_irq_handler DMA0_ERROR_Handler /* 56: DMA 0 Error Handler */ - def_irq_handler DMA0_TC_Handler /* 57: DMA 0 Terminal Count Handler */ - def_irq_handler DMA0_Handler /* 58: DMA 0 Combined Handler */ - def_irq_handler DMA1_ERROR_Handler /* 59: DMA 1 Error Handler */ - def_irq_handler DMA1_TC_Handler /* 60: DMA 1 Terminal Count Handler */ - def_irq_handler DMA1_Handler /* 61: DMA 1 Combined Handler */ - def_irq_handler DMA2_ERROR_Handler /* 62: DMA 2 Error Handler */ - def_irq_handler DMA2_TC_Handler /* 63: DMA 2 Terminal Count Handler */ - def_irq_handler DMA2_Handler /* 64: DMA 2 Combined Handler */ - def_irq_handler DMA3_ERROR_Handler /* 65: DMA 3 Error Handler */ - def_irq_handler DMA3_TC_Handler /* 66: DMA 3 Terminal Count Handler */ - def_irq_handler DMA3_Handler /* 67: DMA 3 Combined Handler */ - - .end diff --git a/platform/ext/target/mps2/sse-200_aws/iar/sse-200_aws_bl2.icf b/platform/ext/target/mps2/sse-200_aws/iar/sse-200_aws_bl2.icf deleted file mode 100644 index 203a119eb2..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/iar/sse-200_aws_bl2.icf +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * - * This file is derivative of ../armclang/sse-200_aws_bl2.sct - */ - -/* Linker script to configure memory regions. */ -/* This file will be run trough the pre-processor. */ - -#include "region_defs.h" - -do not initialize { section .noinit }; -initialize by copy { readwrite }; - -define block ER_CODE with fixed order, alignment = 8 { - section .intvec, - readonly - }; -define block LR_CODE with fixed order, maximum size = BL2_CODE_SIZE {block ER_CODE}; -place at address BL2_CODE_START {block LR_CODE}; - -define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { }; -define block ER_DATA with alignment = 32 {readwrite}; -define block ARM_LIB_STACK with alignment = 32, size = BL2_MSP_STACK_SIZE { }; -define block HEAP with alignment = 8, size = BL2_HEAP_SIZE { }; -define block ARM_LIB_HEAP with alignment = 8, size = BL2_HEAP_SIZE { }; -define overlay HEAP_OVL {block HEAP}; -define overlay HEAP_OVL {block ARM_LIB_HEAP}; -keep {block TFM_SHARED_DATA, block ER_DATA, block ARM_LIB_STACK, - block HEAP, block ARM_LIB_HEAP}; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -define block DATA with fixed order, maximum size = BL2_DATA_SIZE { - block TFM_SHARED_DATA, - block ER_DATA, - block ARM_LIB_STACK, - overlay HEAP_OVL -}; -place at address BL2_DATA_START {block DATA}; - diff --git a/platform/ext/target/mps2/sse-200_aws/iar/sse-200_aws_ns.icf b/platform/ext/target/mps2/sse-200_aws/iar/sse-200_aws_ns.icf deleted file mode 100644 index 039f491292..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/iar/sse-200_aws_ns.icf +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * - * This file is derivative of ../armclang/sse-200_aws_ns.sct - */ - -/* Linker script to configure memory regions. */ -/* This file will be run trough the pre-processor. */ - -#include "region_defs.h" - -define block ER_CODE with fixed order, alignment = 8 { - section .intvec, - readonly}; -define block LR_CODE with fixed order, maximum size = NS_CODE_SIZE {block ER_CODE}; -place at address NS_CODE_START {block LR_CODE}; - -define block ER_DATA with alignment = 8 {readwrite}; -define block ARM_LIB_STACK_MSP with alignment = 32, size = NS_MSP_STACK_SIZE { }; -define block ARM_LIB_STACK with alignment = 32, size = NS_PSP_STACK_SIZE { }; -define block HEAP with alignment = 8, size = NS_HEAP_SIZE { }; -define block ARM_LIB_HEAP with alignment = 8, size = NS_HEAP_SIZE { }; -define overlay HEAP_OVL {block HEAP}; -define overlay HEAP_OVL {block ARM_LIB_HEAP}; -keep {block ARM_LIB_STACK_MSP, block ARM_LIB_STACK, - block HEAP, block ARM_LIB_HEAP}; - -do not initialize { section .noinit }; -initialize by copy { readwrite }; -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -define block DATA with fixed order, maximum size = NS_DATA_SIZE {block ER_DATA, - block ARM_LIB_STACK_MSP, - block ARM_LIB_STACK, - overlay HEAP_OVL}; -place at address NS_DATA_START {block DATA}; diff --git a/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_bl2.s b/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_bl2.s deleted file mode 100644 index 60d68b4c9d..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_bl2.s +++ /dev/null @@ -1,229 +0,0 @@ -;/* -; * Copyright (c) 2016-2020 ARM Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -; -; This file is derivative of ../armclang/startup_cmsdk_mps2_an519_bl2.s - -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION ARM_LIB_STACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - DATA - - -__vector_table DCD sfe(ARM_LIB_STACK) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD SecureFault_Handler ; Secure Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Core IoT Interrupts - DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler - DCD TIMER0_Handler ; - 3 TIMER 0 Handler - DCD TIMER1_Handler ; - 4 TIMER 1 Handler - DCD DUALTIMER_Handler ; - 5 Dual Timer Handler - DCD MHU0_Handler ; - 6 Message Handling Unit 0 - DCD MHU1_Handler ; - 7 Message Handling Unit 1 - DCD 0 ; Reserved - 8 - DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler - DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler - DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler - DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler - DCD 0 ; Reserved - 13 - DCD 0 ; Reserved - 14 - DCD 0 ; Reserved - 15 - DCD 0 ; Reserved - 16 - DCD 0 ; Reserved - 17 - DCD 0 ; Reserved - 18 - DCD 0 ; Reserved - 19 - DCD 0 ; Reserved - 20 - DCD 0 ; Reserved - 21 - DCD 0 ; Reserved - 22 - DCD 0 ; Reserved - 23 - DCD 0 ; Reserved - 24 - DCD 0 ; Reserved - 25 - DCD 0 ; Reserved - 26 - DCD 0 ; Reserved - 27 - DCD 0 ; Reserved - 28 - DCD 0 ; Reserved - 29 - DCD 0 ; Reserved - 30 - DCD 0 ; Reserved - 31 - ; External Interrupts - DCD UARTRX0_Handler ; 32 UART 0 RX Handler - DCD UARTTX0_Handler ; 33 UART 0 TX Handler - DCD 0 ; 34 Reserved - DCD 0 ; 35 Reserved - DCD 0 ; 36 Reserved - DCD 0 ; 37 Reserved - DCD 0 ; 38 Reserved - DCD 0 ; 39 Reserved - DCD 0 ; 40 Reserved - DCD 0 ; 41 Reserved - DCD UART0_Handler ; 42 UART 0 combined Handler - DCD 0 ; 43 Reserved - DCD 0 ; 44 Reserved - DCD 0 ; 45 Reserved - DCD 0 ; 46 Reserved - DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler - DCD 0 ; 48 Reserved - DCD 0 ; 49 Reserved - DCD 0 ; 50 Reserved - DCD 0 ; 51 Reserved - DCD 0 ; 52 Reserved - DCD 0 ; 53 Reserved - DCD 0 ; 54 Reserved - DCD 0 ; 55 Reserved - DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - DCD DMA0_Handler ; 58 DMA 0 Combined Handler - DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - DCD DMA1_Handler ; 61 DMA 1 Combined Handler - DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - DCD DMA2_Handler ; 64 DMA 2 Combined Handler - DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - DCD DMA3_Handler ; 67 DMA 3 Combined Handler - DCD 0 ; 68 Reserved - DCD 0 ; 69 Reserved - DCD 0 ; 70 Reserved - DCD 0 ; 71 Reserved - DCD 0 ; 72 Reserved - DCD 0 ; 73 Reserved - DCD 0 ; 74 Reserved - DCD 0 ; 75 Reserved - DCD 0 ; 76 Reserved - DCD 0 ; 77 Reserved - DCD 0 ; 78 Reserved - DCD 0 ; 79 Reserved - DCD 0 ; 80 Reserved - DCD 0 ; 81 Reserved - DCD 0 ; 82 Reserved - DCD 0 ; 83 Reserved - DCD 0 ; 84 Reserved - DCD 0 ; 85 Reserved - DCD 0 ; 86 Reserved - DCD 0 ; 87 Reserved - DCD 0 ; 88 Reserved - DCD 0 ; 89 Reserved - DCD 0 ; 90 Reserved - DCD 0 ; 91 Reserved - DCD 0 ; 92 Reserved - DCD 0 ; 93 Reserved - DCD 0 ; 94 Reserved - DCD 0 ; 95 Reserved -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -; Reset Handler - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - ; Only run on core 0 - MOV r0, #0x50000000 - ADD r0, #0x0001F000 - LDR r0, [r0] - CMP r0,#0 -not_the_core_to_run_on - BNE not_the_core_to_run_on - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - -; Dummy Exception Handlers (infinite loops which can be modified) -Default_Handler MACRO handler_name - PUBWEAK handler_name -handler_name - B . - ENDM - - Default_Handler NMI_Handler - Default_Handler HardFault_Handler - Default_Handler MemManage_Handler - Default_Handler BusFault_Handler - Default_Handler UsageFault_Handler - Default_Handler SecureFault_Handler - Default_Handler SVC_Handler - Default_Handler DebugMon_Handler - Default_Handler PendSV_Handler - Default_Handler SysTick_Handler - -; Core IoT Interrupts - Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler - Default_Handler TIMER0_Handler ; - 3 TIMER 0 Handler - Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler - Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler - Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0 - Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1 - Default_Handler MPC_Handler ; - 9 MPC Combined (Secure) Handler - Default_Handler PPC_Handler ; - 10 PPC Combined (Secure) Handler - Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler - Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler -; External Interrupts - Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler - Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler - Default_Handler UART0_Handler ; 42 UART 0 combined Handler - Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler - Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler - Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler - Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler - Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler - - END diff --git a/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_ns.s b/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_ns.s deleted file mode 100644 index 64b48d0a41..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_ns.s +++ /dev/null @@ -1,222 +0,0 @@ -;/* -; * Copyright (c) 2016-2020 ARM Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -; -; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_ns.s - -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Core IoT Interrupts - DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler - DCD TIMER0_Handler ; - 3 TIMER 0 Handler - DCD TIMER1_Handler ; - 4 TIMER 1 Handler - DCD DUALTIMER_Handler ; - 5 Dual Timer Handler - DCD MHU0_Handler ; - 6 Message Handling Unit 0 - DCD MHU1_Handler ; - 7 Message Handling Unit 1 - DCD 0 ; Reserved - 8 - DCD 0 ; Reserved - 9 - DCD 0 ; Reserved - 10 - DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler - DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler - DCD 0 ; Reserved - 13 - DCD 0 ; Reserved - 14 - DCD 0 ; Reserved - 15 - DCD 0 ; Reserved - 16 - DCD 0 ; Reserved - 17 - DCD 0 ; Reserved - 18 - DCD 0 ; Reserved - 19 - DCD 0 ; Reserved - 20 - DCD 0 ; Reserved - 21 - DCD 0 ; Reserved - 22 - DCD 0 ; Reserved - 23 - DCD 0 ; Reserved - 24 - DCD 0 ; Reserved - 25 - DCD 0 ; Reserved - 26 - DCD 0 ; Reserved - 27 - DCD 0 ; Reserved - 28 - DCD 0 ; Reserved - 29 - DCD 0 ; Reserved - 30 - DCD 0 ; Reserved - 31 - ; External Interrupts - DCD UARTRX0_Handler ; 32 UART 0 RX Handler - DCD UARTTX0_Handler ; 33 UART 0 TX Handler - DCD 0 ; 34 Reserved - DCD 0 ; 35 Reserved - DCD 0 ; 36 Reserved - DCD 0 ; 37 Reserved - DCD 0 ; 38 Reserved - DCD 0 ; 39 Reserved - DCD 0 ; 40 Reserved - DCD 0 ; 41 Reserved - DCD UART0_Handler ; 42 UART 0 combined Handler - DCD 0 ; 43 Reserved - DCD 0 ; 44 Reserved - DCD 0 ; 45 Reserved - DCD 0 ; 46 Reserved - DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler - DCD 0 ; 48 Reserved - DCD 0 ; 49 Reserved - DCD 0 ; 50 Reserved - DCD 0 ; 51 Reserved - DCD 0 ; 52 Reserved - DCD 0 ; 53 Reserved - DCD 0 ; 54 Reserved - DCD 0 ; 55 Reserved - DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - DCD DMA0_Handler ; 58 DMA 0 Combined Handler - DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - DCD DMA1_Handler ; 61 DMA 1 Combined Handler - DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - DCD DMA2_Handler ; 64 DMA 2 Combined Handler - DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - DCD DMA3_Handler ; 67 DMA 3 Combined Handler - DCD 0 ; 68 Reserved - DCD 0 ; 69 Reserved - DCD 0 ; 70 Reserved - DCD 0 ; 71 Reserved - DCD 0 ; 72 Reserved - DCD 0 ; 73 Reserved - DCD 0 ; 74 Reserved - DCD 0 ; 75 Reserved - DCD 0 ; 76 Reserved - DCD 0 ; 77 Reserved - DCD 0 ; 78 Reserved - DCD 0 ; 79 Reserved - DCD 0 ; 80 Reserved - DCD 0 ; 81 Reserved - DCD 0 ; 82 Reserved - DCD 0 ; 83 Reserved - DCD 0 ; 84 Reserved - DCD 0 ; 85 Reserved - DCD 0 ; 86 Reserved - DCD 0 ; 87 Reserved - DCD 0 ; 88 Reserved - DCD 0 ; 89 Reserved - DCD 0 ; 90 Reserved - DCD 0 ; 91 Reserved - DCD 0 ; 92 Reserved - DCD 0 ; 93 Reserved - DCD 0 ; 94 Reserved - DCD 0 ; 95 Reserved -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -; Reset Handler - -Reset_Handler - MRS R0, control ; Get control value - ORR R0, R0, #1 ; Select switch to unprivilage mode - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 - LDR R0, =__iar_program_start - BX R0 - -; Dummy Exception Handlers (infinite loops which can be modified) - -Default_Handler MACRO handler_name - PUBWEAK handler_name -handler_name - B . - ENDM - - Default_Handler NMI_Handler - Default_Handler HardFault_Handler - Default_Handler MemManage_Handler - Default_Handler BusFault_Handler - Default_Handler UsageFault_Handler - Default_Handler SecureFault_Handler - Default_Handler SVC_Handler - Default_Handler DebugMon_Handler - Default_Handler PendSV_Handler - Default_Handler SysTick_Handler - -; Core IoT Interrupts - Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler - Default_Handler TIMER0_Handler ; - 3 TIMER 0 Handler - Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler - Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler - Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0 - Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1 - Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler - Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler -; External Interrupts - Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler - Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler - Default_Handler UART0_Handler ; 42 UART 0 combined Handler - Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler - Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler - Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler - Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler - Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler - - END diff --git a/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_s.s b/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_s.s deleted file mode 100644 index 76e131fe3c..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/iar/startup_cmsdk_sse-200_aws_s.s +++ /dev/null @@ -1,228 +0,0 @@ -;/* -; * Copyright (c) 2016-2020 ARM Limited -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -; -; This file is derivative of ../armclang/startup_cmsdk_mps2_an521_s.s - -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION ARM_LIB_STACK_MSP:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table ;Core Interrupts - DCD sfe(ARM_LIB_STACK_MSP) ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD SecureFault_Handler ; Secure Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Core IoT Interrupts - DCD NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - DCD NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - DCD S32K_TIMER_Handler ; - 2 S32K Timer Handler - DCD TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler - DCD TIMER1_Handler ; - 4 TIMER 1 Handler - DCD DUALTIMER_Handler ; - 5 Dual Timer Handler - DCD MHU0_Handler ; - 6 Message Handling Unit 0 - DCD MHU1_Handler ; - 7 Message Handling Unit 1 - DCD 0 ; Reserved - 8 - DCD MPC_Handler ; - 9 MPC Combined (Secure) Handler - DCD PPC_Handler ; - 10 PPC Combined (Secure) Handler - DCD MSC_Handler ; - 11 MSC Combined (Secure) Handler - DCD BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler - DCD 0 ; Reserved - 13 - DCD 0 ; Reserved - 14 - DCD 0 ; Reserved - 15 - DCD 0 ; Reserved - 16 - DCD 0 ; Reserved - 17 - DCD 0 ; Reserved - 18 - DCD 0 ; Reserved - 19 - DCD 0 ; Reserved - 20 - DCD 0 ; Reserved - 21 - DCD 0 ; Reserved - 22 - DCD 0 ; Reserved - 23 - DCD 0 ; Reserved - 24 - DCD 0 ; Reserved - 25 - DCD 0 ; Reserved - 26 - DCD 0 ; Reserved - 27 - DCD 0 ; Reserved - 28 - DCD 0 ; Reserved - 29 - DCD 0 ; Reserved - 30 - DCD 0 ; Reserved - 31 - ; External Interrupts - DCD UARTRX0_Handler ; 32 UART 0 RX Handler - DCD UARTTX0_Handler ; 33 UART 0 TX Handler - DCD 0 ; 34 Reserved - DCD 0 ; 35 Reserved - DCD 0 ; 36 Reserved - DCD 0 ; 37 Reserved - DCD 0 ; 38 Reserved - DCD 0 ; 39 Reserved - DCD 0 ; 40 Reserved - DCD 0 ; 41 Reserved - DCD UART0_Handler ; 42 UART 0 combined Handler - DCD 0 ; 43 Reserved - DCD 0 ; 44 Reserved - DCD 0 ; 45 Reserved - DCD 0 ; 46 Reserved - DCD UARTOVF_Handler ; 47 UART 0,1,2,3,4 Overflow Handler - DCD 0 ; 48 Reserved - DCD 0 ; 49 Reserved - DCD 0 ; 50 Reserved - DCD 0 ; 51 Reserved - DCD 0 ; 52 Reserved - DCD 0 ; 53 Reserved - DCD 0 ; 54 Reserved - DCD 0 ; 55 Reserved - DCD DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - DCD DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - DCD DMA0_Handler ; 58 DMA 0 Combined Handler - DCD DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - DCD DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - DCD DMA1_Handler ; 61 DMA 1 Combined Handler - DCD DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - DCD DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - DCD DMA2_Handler ; 64 DMA 2 Combined Handler - DCD DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - DCD DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - DCD DMA3_Handler ; 67 DMA 3 Combined Handler - DCD 0 ; 68 Reserved - DCD 0 ; 69 Reserved - DCD 0 ; 70 Reserved - DCD 0 ; 71 Reserved - DCD 0 ; 72 Reserved - DCD 0 ; 73 Reserved - DCD 0 ; 74 Reserved - DCD 0 ; 75 Reserved - DCD 0 ; 76 Reserved - DCD 0 ; 77 Reserved - DCD 0 ; 78 Reserved - DCD 0 ; 79 Reserved - DCD 0 ; 80 Reserved - DCD 0 ; 81 Reserved - DCD 0 ; 82 Reserved - DCD 0 ; 83 Reserved - DCD 0 ; 84 Reserved - DCD 0 ; 85 Reserved - DCD 0 ; 86 Reserved - DCD 0 ; 87 Reserved - DCD 0 ; 88 Reserved - DCD 0 ; 89 Reserved - DCD 0 ; 90 Reserved - DCD 0 ; 91 Reserved - DCD 0 ; 92 Reserved - DCD 0 ; 93 Reserved - DCD 0 ; 94 Reserved - DCD 0 ; 95 Reserved -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -; Reset Handler - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID i ; Disable IRQs - LDR R0, =SystemInit - BLX R0 - MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP - MSR control, R0 - LDR R0, =__iar_program_start - BX R0 - -; Dummy Exception Handlers (infinite loops which can be modified) -Default_Handler MACRO handler_name - PUBWEAK handler_name -handler_name - B . - ENDM - - Default_Handler NMI_Handler - Default_Handler HardFault_Handler - Default_Handler MemManage_Handler - Default_Handler BusFault_Handler - Default_Handler UsageFault_Handler - Default_Handler SecureFault_Handler - Default_Handler SVC_Handler - Default_Handler DebugMon_Handler - Default_Handler PendSV_Handler - Default_Handler SysTick_Handler - -; Core IoT Interrupts - Default_Handler NONSEC_WATCHDOG_RESET_Handler ; - 0 Non-Secure Watchdog Reset Handler - Default_Handler NONSEC_WATCHDOG_Handler ; - 1 Non-Secure Watchdog Handler - Default_Handler S32K_TIMER_Handler ; - 2 S32K Timer Handler - Default_Handler TFM_TIMER0_IRQ_Handler ; - 3 TIMER 0 Handler - Default_Handler TIMER1_Handler ; - 4 TIMER 1 Handler - Default_Handler DUALTIMER_Handler ; - 5 Dual Timer Handler - Default_Handler MHU0_Handler ; - 6 Message Handling Unit 0 - Default_Handler MHU1_Handler ; - 7 Message Handling Unit 1 - Default_Handler MPC_Handler ; - 9 MPC Combined (Secure) Handler - Default_Handler PPC_Handler ; - 10 PPC Combined (Secure) Handler - Default_Handler MSC_Handler ; - 11 MSC Combined (Secure) Handler - Default_Handler BRIDGE_ERROR_Handler ; - 12 Bridge Error Combined (Secure) Handler -; External Interrupts - Default_Handler UARTRX0_Handler ; 32 UART 0 RX Handler - Default_Handler UARTTX0_Handler ; 33 UART 0 TX Handler - Default_Handler UART0_Handler ; 42 UART 0 combined Handler - Default_Handler UARTOVF_Handler ; 47 UART 0 Overflow Handler - Default_Handler DMA0_ERROR_Handler ; 56 DMA 0 Error Handler - Default_Handler DMA0_TC_Handler ; 57 DMA 0 Terminal Count Handler - Default_Handler DMA0_Handler ; 58 DMA 0 Combined Handler - Default_Handler DMA1_ERROR_Handler ; 59 DMA 1 Error Handler - Default_Handler DMA1_TC_Handler ; 60 DMA 1 Terminal Count Handler - Default_Handler DMA1_Handler ; 61 DMA 1 Combined Handler - Default_Handler DMA2_ERROR_Handler ; 62 DMA 2 Error Handler - Default_Handler DMA2_TC_Handler ; 63 DMA 2 Terminal Count Handler - Default_Handler DMA2_Handler ; 64 DMA 2 Combined Handler - Default_Handler DMA3_ERROR_Handler ; 65 DMA 3 Error Handler - Default_Handler DMA3_TC_Handler ; 66 DMA 3 Terminal Count Handler - Default_Handler DMA3_Handler ; 67 DMA 3 Combined Handler - - END diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/mpc_sie_drv.c b/platform/ext/target/mps2/sse-200_aws/native_drivers/mpc_sie_drv.c deleted file mode 100644 index a3dcd3d602..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/mpc_sie_drv.c +++ /dev/null @@ -1,791 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mpc_sie_drv.h" - -#include <stddef.h> -#include <stdbool.h> - -#include "cmsis_compiler.h" - -/* Values for hardware version in PIDR0 reg */ -#define SIE200 0x60 -#define SIE300 0x65 - -#define MPC_SIE_BLK_CFG_OFFSET 5U - -/* Defines with numbering (eg: SIE300) are only relevant to the given SIE - * version. Defines without the numbering are applicable to all SIE versions. - */ - -/* CTRL register bit indexes */ -#define MPC_SIE200_CTRL_SEC_RESP (1UL << 4UL) /* MPC fault triggers a - * bus error - */ -#define MPC_SIE300_CTRL_GATE_REQ (1UL << 6UL) /* Request for gating - * incoming transfers - */ -#define MPC_SIE300_CTRL_GATE_ACK (1UL << 7UL) /* Acknowledge for gating - * incoming transfers - */ -#define MPC_SIE_CTRL_AUTOINCREMENT (1UL << 8UL) /* BLK_IDX auto increment */ -#define MPC_SIE300_CTRL_SEC_RESP (1UL << 16UL) /* Response type when SW - * asks to gate the transfer - */ -#define MPC_SIE300_CTRL_GATE_PRESENT (1UL << 23UL) /* Gating feature present */ -#define MPC_SIE_CTRL_SEC_LOCK_DOWN (1UL << 31UL) /* MPC Security lock down */ - -/* PIDR register bit masks */ -#define MPC_PIDR0_SIE_VERSION_MASK ((1UL << 8UL) - 1UL) - -/* ARM MPC interrupt */ -#define MPC_SIE_INT_BIT (1UL) - -/* Error code returned by the internal driver functions */ -enum mpc_sie_intern_error_t { - MPC_SIE_INTERN_ERR_NONE = MPC_SIE_ERR_NONE, - MPC_SIE_INTERN_ERR_NOT_IN_RANGE = MPC_SIE_ERR_NOT_IN_RANGE, - MPC_SIE_INTERN_ERR_NOT_ALIGNED = MPC_SIE_ERR_NOT_ALIGNED, - MPC_SIE_INTERN_ERR_INVALID_RANGE = MPC_SIE_ERR_INVALID_RANGE, - MPC_INTERN_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE = - MPC_SIE_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, - /* Calculated block index - * is higher than the maximum allowed by the MPC. It should never - * happen unless the controlled ranges of the MPC are misconfigured - * in the driver or if the IP has not enough LUTs to cover the - * range, due to wrong reported block size for example. - */ - MPC_SIE_INTERN_ERR_BLK_IDX_TOO_HIGH = -1, - -}; - -/* ARM MPC memory mapped register access structure */ -struct mpc_sie_reg_map_t { - volatile uint32_t ctrl; /* (R/W) MPC Control */ - volatile uint32_t reserved[3];/* Reserved */ - volatile uint32_t blk_max; /* (R/ ) Maximum value of block based index */ - volatile uint32_t blk_cfg; /* (R/ ) Block configuration */ - volatile uint32_t blk_idx; /* (R/W) Index value for accessing block - * based look up table - */ - volatile uint32_t blk_lutn; /* (R/W) Block based gating - * Look Up Table (LUT) - */ - volatile uint32_t int_stat; /* (R/ ) Interrupt state */ - volatile uint32_t int_clear; /* ( /W) Interrupt clear */ - volatile uint32_t int_en; /* (R/W) Interrupt enable */ - volatile uint32_t int_info1; /* (R/ ) Interrupt information 1 */ - volatile uint32_t int_info2; /* (R/ ) Interrupt information 2 */ - volatile uint32_t int_set; /* ( /W) Interrupt set. Debug purpose only */ - volatile uint32_t reserved2[998]; /* Reserved */ - volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */ - volatile uint32_t pidr5; /* (R/ ) Peripheral ID 5 */ - volatile uint32_t pidr6; /* (R/ ) Peripheral ID 6 */ - volatile uint32_t pidr7; /* (R/ ) Peripheral ID 7 */ - volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */ - volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */ - volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */ - volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */ - volatile uint32_t cidr0; /* (R/ ) Component ID 0 */ - volatile uint32_t cidr1; /* (R/ ) Component ID 1 */ - volatile uint32_t cidr2; /* (R/ ) Component ID 2 */ - volatile uint32_t cidr3; /* (R/ ) Component ID 3 */ -}; - -/* - * Checks if the address is controlled by the MPC and returns - * the range index in which it is contained. - * - * \param[in] dev MPC device to initialize \ref mpc_sie_dev_t - * \param[in] addr Address to check if it is controlled by MPC. - * \param[out] addr_range Range index in which it is contained. - * - * \return True if the base is controller by the range list, false otherwise. - */ -static uint32_t is_ctrl_by_range_list( - struct mpc_sie_dev_t* dev, - uint32_t addr, - const struct mpc_sie_memory_range_t** addr_range) -{ - uint32_t i; - const struct mpc_sie_memory_range_t* range; - - for(i = 0; i < dev->data->nbr_of_ranges; i++) { - range = dev->data->range_list[i]; - if(addr >= range->base && addr <= range->limit) { - *addr_range = range; - return 1; - } - } - return 0; -} - -/* - * Gets the masks selecting the bits in the LUT of the MPC corresponding - * to the base address (included) up to the limit address (included) - * - * \param[in] mpc_dev The MPC device. - * \param[in] base Address in a range controlled by this MPC - * (included), aligned on block size. - * \param[in] limit Address in a range controlled by this MPC - * (included), aligned on block size. - * \param[out] range Memory range in which the base address and - * limit are. - * \param[out] first_word_idx Index of the first touched word in the LUT. - * \param[out] nr_words Number of words used in the LUT. If 1, only - * first_word_mask is valid and limit_word_mask - * must not be used. - * \param[out] first_word_mask First word mask in the LUT will be stored here. - * \param[out] limit_word_mask Limit word mask in the LUT will be stored here. - * - * \return Returns error code as specified in \ref mpc_sie_intern_error_t - */ -static enum mpc_sie_intern_error_t get_lut_masks( - struct mpc_sie_dev_t* dev, - const uint32_t base, const uint32_t limit, - const struct mpc_sie_memory_range_t** range, - uint32_t *first_word_idx, - uint32_t *nr_words, - uint32_t *first_word_mask, - uint32_t *limit_word_mask) -{ - const struct mpc_sie_memory_range_t* base_range; - uint32_t block_size; - uint32_t base_block_idx; - uint32_t base_word_idx; - uint32_t blk_max; - const struct mpc_sie_memory_range_t* limit_range; - uint32_t limit_block_idx; - uint32_t limit_word_idx; - uint32_t mask; - uint32_t norm_base; - uint32_t norm_limit; - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - /* - * Check that the addresses are within the controlled regions - * of this MPC - */ - if(!is_ctrl_by_range_list(dev, base, &base_range) || - !is_ctrl_by_range_list(dev, limit, &limit_range)) { - return MPC_SIE_INTERN_ERR_NOT_IN_RANGE; - } - - /* Base and limit should be part of the same range */ - if(base_range != limit_range) { - return MPC_SIE_INTERN_ERR_INVALID_RANGE; - } - *range = base_range; - - block_size = (1 << (p_mpc->blk_cfg + MPC_SIE_BLK_CFG_OFFSET)); - - /* Base and limit+1 addresses must be aligned on the MPC block size */ - if(base % block_size || (limit+1) % block_size) { - return MPC_SIE_INTERN_ERR_NOT_ALIGNED; - } - - /* - * Get a normalized address that is an offset from the beginning - * of the lowest range controlled by the MPC - */ - norm_base = (base - base_range->base) + base_range->range_offset; - norm_limit = (limit - base_range->base) + base_range->range_offset; - - /* - * Calculate block index and to which 32 bits word it belongs - */ - limit_block_idx = norm_limit/block_size; - limit_word_idx = limit_block_idx/32; - - base_block_idx = norm_base/block_size; - base_word_idx = base_block_idx/32; - - if(base_block_idx > limit_block_idx) { - return MPC_SIE_INTERN_ERR_INVALID_RANGE; - } - - /* Transmit the information to the caller */ - *nr_words = limit_word_idx - base_word_idx + 1; - *first_word_idx = base_word_idx; - - /* Limit to the highest block that can be configured */ - blk_max = p_mpc->blk_max; - - if((limit_word_idx > blk_max) || (base_word_idx > blk_max)) { - return MPC_SIE_INTERN_ERR_BLK_IDX_TOO_HIGH; - } - - /* - * Create the mask for the first word to only select the limit N bits - */ - *first_word_mask = ~((1 << (base_block_idx % 32)) - 1); - - /* - * Create the mask for the limit word to select only the first M bits. - */ - *limit_word_mask = (1 << ((limit_block_idx+1) % 32)) - 1; - /* - * If limit_word_mask is 0, it means that the limit touched block index is - * the limit in its word, so the limit word mask has all its bits selected - */ - if(*limit_word_mask == 0) { - *limit_word_mask = 0xFFFFFFFF; - } - - /* - * If the blocks to configure are all packed in one word, only - * touch this word. - * Code using the computed masks should test if this mask - * is non-zero, and if so, only use this one instead of the limit_word_mask - * and first_word_mask. - * As the only bits that are the same in both masks are the 1 that we want - * to select, just use XOR to extract them. - */ - if(base_word_idx == limit_word_idx) { - mask = ~(*first_word_mask ^ *limit_word_mask); - *first_word_mask = mask; - *limit_word_mask = mask; - } - - return MPC_SIE_INTERN_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_init(struct mpc_sie_dev_t* dev, - const struct mpc_sie_memory_range_t** range_list, - uint8_t nbr_of_ranges) -{ - if((range_list == NULL) || (nbr_of_ranges == 0)) { - return MPC_SIE_INVALID_ARG; - } - - dev->data->sie_version = get_sie_version(dev); - - if ((dev->data->sie_version != SIE200) && - (dev->data->sie_version != SIE300)) { - return MPC_SIE_UNSUPPORTED_HARDWARE_VERSION; - } - - dev->data->range_list = range_list; - dev->data->nbr_of_ranges = nbr_of_ranges; - dev->data->is_initialized = true; - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_get_block_size(struct mpc_sie_dev_t* dev, - uint32_t* blk_size) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - if(blk_size == 0) { - return MPC_SIE_INVALID_ARG; - } - - /* Calculate the block size in byte according to the manual */ - *blk_size = (1 << (p_mpc->blk_cfg + MPC_SIE_BLK_CFG_OFFSET)); - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_config_region(struct mpc_sie_dev_t* dev, - const uint32_t base, - const uint32_t limit, - enum mpc_sie_sec_attr_t attr) -{ - enum mpc_sie_intern_error_t error; - uint32_t first_word_idx; - uint32_t first_word_mask; - uint32_t i; - uint32_t limit_word_mask; - uint32_t limit_word_idx; - uint32_t nr_words; - const struct mpc_sie_memory_range_t* range; - uint32_t word_value; - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - /* Get the bitmasks used to select the bits in the LUT */ - error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words, - &first_word_mask, &limit_word_mask); - - limit_word_idx = first_word_idx + nr_words - 1; - - if(error != MPC_SIE_INTERN_ERR_NONE) { - /* Map internal error code lower than 0 to a generic errpr */ - if(error < 0) { - return MPC_SIE_ERR_INVALID_RANGE; - } - return (enum mpc_sie_error_t)error; - } - - /* - * The memory range should allow accesses in with the wanted security - * attribute if it requires special attribute for successful accesses - */ - if(range->attr != attr) { - return MPC_SIE_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE; - } - - /* - * Starts changing actual configuration so issue DMB to ensure every - * transaction has completed by now - */ - __DMB(); - - /* Set the block index to the first word that will be updated */ - p_mpc->blk_idx = first_word_idx; - - /* If only one word needs to be touched in the LUT */ - if(nr_words == 1) { - word_value = p_mpc->blk_lutn; - if(attr == MPC_SIE_SEC_ATTR_NONSECURE) { - word_value |= first_word_mask; - } else { - word_value &= ~first_word_mask; - } - - /* - * Set the index again because full word read or write could have - * incremented it - */ - p_mpc->blk_idx = first_word_idx; - p_mpc->blk_lutn = word_value; - - /* Commit the configuration change */ - __DSB(); - __ISB(); - - return MPC_SIE_ERR_NONE; - } - - /* First word */ - word_value = p_mpc->blk_lutn; - if(attr == MPC_SIE_SEC_ATTR_NONSECURE) { - word_value |= first_word_mask; - } else { - word_value &= ~first_word_mask; - } - /* - * Set the index again because full word read or write could have - * incremented it - */ - p_mpc->blk_idx = first_word_idx; - /* Partially configure the first word */ - p_mpc->blk_lutn = word_value; - - /* Fully configure the intermediate words if there are any */ - for(i=first_word_idx+1; i<limit_word_idx; i++) { - p_mpc->blk_idx = i; - if(attr == MPC_SIE_SEC_ATTR_NONSECURE) { - p_mpc->blk_lutn = 0xFFFFFFFF; - } else { - p_mpc->blk_lutn = 0x00000000; - } - } - - /* Partially configure the limit word */ - p_mpc->blk_idx = limit_word_idx; - word_value = p_mpc->blk_lutn; - if(attr == MPC_SIE_SEC_ATTR_NONSECURE) { - word_value |= limit_word_mask; - } else { - word_value &= ~limit_word_mask; - } - p_mpc->blk_idx = limit_word_idx; - p_mpc->blk_lutn = word_value; - - /* Commit the configuration change */ - __DSB(); - __ISB(); - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_get_region_config( - struct mpc_sie_dev_t* dev, - uint32_t base, uint32_t limit, - enum mpc_sie_sec_attr_t* attr) -{ - enum mpc_sie_sec_attr_t attr_prev; - uint32_t block_size; - uint32_t block_size_mask; - enum mpc_sie_intern_error_t error; - uint32_t first_word_idx; - uint32_t first_word_mask; - uint32_t i; - uint32_t limit_word_idx; - uint32_t limit_word_mask; - uint32_t nr_words; - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - const struct mpc_sie_memory_range_t* range; - uint32_t word_value; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - if(attr == 0) { - return MPC_SIE_INVALID_ARG; - } - - /* - * Initialize the security attribute to mixed in case of early - * termination of this function. A caller that does not check the - * returned error will act as if it does not know anything about the - * region queried, which is the safest bet - */ - *attr = MPC_SIE_SEC_ATTR_MIXED; - - /* - * If the base and limit are not aligned, align them and make sure - * that the resulting region fully includes the original region - */ - block_size = (1 << (p_mpc->blk_cfg + MPC_SIE_BLK_CFG_OFFSET)); - - block_size_mask = block_size - 1; - base &= ~(block_size_mask); - limit &= ~(block_size_mask); - limit += block_size - 1; /* Round to the upper block address, - * and then remove one to get the preceding - * address. - */ - - /* Get the bitmasks used to select the bits in the LUT */ - error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words, - &first_word_mask, &limit_word_mask); - - limit_word_idx = first_word_idx+nr_words - 1; - - if(error != MPC_SIE_INTERN_ERR_NONE) { - /* Map internal error code lower than 0 to generic error */ - if(error < 0) { - return MPC_SIE_ERR_INVALID_RANGE; - } - return (enum mpc_sie_error_t)error; - } - - /* Set the block index to the first word that will be updated */ - p_mpc->blk_idx = first_word_idx; - - /* If only one word needs to be touched in the LUT */ - if(nr_words == 1) { - word_value = p_mpc->blk_lutn; - word_value &= first_word_mask; - if(word_value == 0) { - *attr = MPC_SIE_SEC_ATTR_SECURE; - /* - * If there are differences between the mask and the word value, - * it means that the security attributes of blocks are mixed - */ - } else if(word_value ^ first_word_mask) { - *attr = MPC_SIE_SEC_ATTR_MIXED; - } else { - *attr = MPC_SIE_SEC_ATTR_NONSECURE; - } - return MPC_SIE_ERR_NONE; - } - - /* Get the partial configuration of the first word */ - word_value = p_mpc->blk_lutn & first_word_mask; - if(word_value == 0x00000000) { - *attr = MPC_SIE_SEC_ATTR_SECURE; - } else if(word_value ^ first_word_mask) { - *attr = MPC_SIE_SEC_ATTR_MIXED; - /* - * Bail out as the security attribute will be the same regardless - * of the configuration of other blocks - */ - return MPC_SIE_ERR_NONE; - } else { - *attr = MPC_SIE_SEC_ATTR_NONSECURE; - } - /* - * Store the current found attribute, to check that all the blocks indeed - * have the same security attribute. - */ - attr_prev = *attr; - - /* Get the configuration of the intermediate words if there are any */ - for(i=first_word_idx+1; i<limit_word_idx; i++) { - p_mpc->blk_idx = i; - word_value = p_mpc->blk_lutn; - if(word_value == 0x00000000) { - *attr = MPC_SIE_SEC_ATTR_SECURE; - } else if(word_value == 0xFFFFFFFF) { - *attr = MPC_SIE_SEC_ATTR_NONSECURE; - } else { - *attr = MPC_SIE_SEC_ATTR_MIXED; - return MPC_SIE_ERR_NONE; - } - - /* If the attribute is different than the one found before, bail out */ - if(*attr != attr_prev) { - *attr = MPC_SIE_SEC_ATTR_MIXED; - return MPC_SIE_ERR_NONE; - } - attr_prev = *attr; - } - - /* Get the partial configuration of the limit word */ - p_mpc->blk_idx = limit_word_idx; - word_value = p_mpc->blk_lutn & limit_word_mask; - if(word_value == 0x00000000) { - *attr = MPC_SIE_SEC_ATTR_SECURE; - } else if(word_value ^ first_word_mask) { - *attr = MPC_SIE_SEC_ATTR_MIXED; - return MPC_SIE_ERR_NONE; - } else { - *attr = MPC_SIE_SEC_ATTR_NONSECURE; - } - - if(*attr != attr_prev) { - *attr = MPC_SIE_SEC_ATTR_MIXED; - return MPC_SIE_ERR_NONE; - } - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_get_ctrl(struct mpc_sie_dev_t* dev, - uint32_t* ctrl_val) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - if(ctrl_val == 0) { - return MPC_SIE_INVALID_ARG; - } - - *ctrl_val = p_mpc->ctrl; - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_set_ctrl(struct mpc_sie_dev_t* dev, - uint32_t mpc_ctrl) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - p_mpc->ctrl = mpc_ctrl; - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_get_sec_resp(struct mpc_sie_dev_t* dev, - enum mpc_sie_sec_resp_t* sec_rep) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - bool gating_present = false; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - if(sec_rep == NULL) { - return MPC_SIE_INVALID_ARG; - } - - if (dev->data->sie_version == SIE200) { - if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) { - *sec_rep = MPC_SIE_RESP_BUS_ERROR; - } else { - *sec_rep = MPC_SIE_RESP_RAZ_WI; - } - - } else if (dev->data->sie_version == SIE300) { - mpc_sie_is_gating_present(dev, &gating_present); - if (!gating_present) { - return MPC_SIE_ERR_GATING_NOT_PRESENT; - } - - if(p_mpc->ctrl & MPC_SIE300_CTRL_SEC_RESP) { - /* MPC returns a BUS ERROR response */ - *sec_rep = MPC_SIE_RESP_BUS_ERROR; - } else { - /* MPC sets the ready signals LOW, which stalls any transactions */ - *sec_rep = MPC_SIE_RESP_WAIT_GATING_DISABLED; - } - } else { - return MPC_SIE_UNSUPPORTED_HARDWARE_VERSION; - } - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_set_sec_resp(struct mpc_sie_dev_t* dev, - enum mpc_sie_sec_resp_t sec_rep) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - bool gating_present = false; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - if (dev->data->sie_version == SIE200) { - if (sec_rep == MPC_SIE_RESP_BUS_ERROR) { - p_mpc->ctrl |= MPC_SIE200_CTRL_SEC_RESP; - } else if (sec_rep == MPC_SIE_RESP_RAZ_WI) { - p_mpc->ctrl &= ~MPC_SIE200_CTRL_SEC_RESP; - } else { - return MPC_SIE_INVALID_ARG; - } - - } else if (dev->data->sie_version == SIE300) { - mpc_sie_is_gating_present(dev, &gating_present); - if (!gating_present) { - return MPC_SIE_ERR_GATING_NOT_PRESENT; - } - - if (sec_rep == MPC_SIE_RESP_BUS_ERROR) { - p_mpc->ctrl |= MPC_SIE300_CTRL_SEC_RESP; - } else if (sec_rep == MPC_SIE_RESP_WAIT_GATING_DISABLED) { - p_mpc->ctrl &= ~MPC_SIE300_CTRL_SEC_RESP; - } else { - return MPC_SIE_INVALID_ARG; - } - - } else { - return MPC_SIE_UNSUPPORTED_HARDWARE_VERSION; - } - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_irq_enable(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - p_mpc->int_en |= MPC_SIE_INT_BIT; - - return MPC_SIE_ERR_NONE; -} - -void mpc_sie_irq_disable(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - p_mpc->int_en &= ~MPC_SIE_INT_BIT; -} - -void mpc_sie_clear_irq(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - p_mpc->int_clear = MPC_SIE_INT_BIT; -} - -uint32_t mpc_sie_irq_state(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - return (p_mpc->int_stat & MPC_SIE_INT_BIT); -} - -enum mpc_sie_error_t mpc_sie_lock_down(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - p_mpc->ctrl |= (MPC_SIE_CTRL_AUTOINCREMENT - | MPC_SIE_CTRL_SEC_LOCK_DOWN); - - return MPC_SIE_ERR_NONE; -} - -enum mpc_sie_error_t mpc_sie_is_gating_present(struct mpc_sie_dev_t* dev, - bool* gating_present) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - if(dev->data->is_initialized != true) { - return MPC_SIE_NOT_INIT; - } - - if (dev->data->sie_version != SIE300) { - return MPC_SIE_UNSUPPORTED_HARDWARE_VERSION; - } - - *gating_present = (bool)(p_mpc->ctrl & MPC_SIE300_CTRL_GATE_PRESENT); - - return MPC_SIE_ERR_NONE; -} - -uint32_t get_sie_version(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - return p_mpc->pidr0 & MPC_PIDR0_SIE_VERSION_MASK; -} - -bool mpc_sie_get_gate_ack(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - return (bool)(p_mpc->ctrl & MPC_SIE300_CTRL_GATE_ACK); -} - -void mpc_sie_request_gating(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - p_mpc->ctrl |= MPC_SIE300_CTRL_GATE_REQ; -} - -void mpc_sie_release_gating(struct mpc_sie_dev_t* dev) -{ - struct mpc_sie_reg_map_t* p_mpc = - (struct mpc_sie_reg_map_t*)dev->cfg->base; - - p_mpc->ctrl &= ~MPC_SIE300_CTRL_GATE_REQ; -} diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/mpc_sie_drv.h b/platform/ext/target/mps2/sse-200_aws/native_drivers/mpc_sie_drv.h deleted file mode 100644 index 927d0a80d5..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/mpc_sie_drv.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file mpc_sie_drv.h - * \brief Generic driver for ARM SIE Memory Protection - * Controllers (MPC). - */ - -#ifndef __MPC_SIE__DRV_H__ -#define __MPC_SIE__DRV_H__ - -#include <stdint.h> -#include <stdbool.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Error code returned by the driver functions */ -enum mpc_sie_error_t { - MPC_SIE_ERR_NONE, /*!< No error */ - MPC_SIE_INVALID_ARG, /*!< MPC invalid input arguments */ - MPC_SIE_NOT_INIT, /*!< MPC not initialized */ - MPC_SIE_ERR_NOT_IN_RANGE, /*!< Address does not belong to a range - * controlled by the MPC */ - MPC_SIE_ERR_NOT_ALIGNED, /*!< Address is not aligned on the block size - * of this MPC - */ - MPC_SIE_ERR_INVALID_RANGE, /*!< The given address range to configure - * is invalid. This could be because: - * - The base and limit swapped - * - The base and limit addresses - * are in different ranges - */ - MPC_SIE_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, /*!< The given range cannot be - * accessed with the wanted - * security attributes - */ - MPC_SIE_UNSUPPORTED_HARDWARE_VERSION, /*!< MPC hardware version read from - * PIDR0 is not supported - */ - MPC_SIE_ERR_GATING_NOT_PRESENT /*!< MPC gating not present in HW */ -}; - -/* Security attribute used in various place of the API */ -enum mpc_sie_sec_attr_t { - MPC_SIE_SEC_ATTR_SECURE, /*!< Secure attribute */ - MPC_SIE_SEC_ATTR_NONSECURE, /*!< Non-secure attribute */ - /*!< Used when getting the configuration of a memory range and some blocks - * are secure whereas some other are non secure - */ - MPC_SIE_SEC_ATTR_MIXED, -}; - -/* What can happen when trying to do an illegal memory access */ -enum mpc_sie_sec_resp_t { - MPC_SIE_RESP_RAZ_WI, /*!< Read As Zero, Write Ignored */ - MPC_SIE_RESP_BUS_ERROR, /*!< Bus error */ - MPC_SIE_RESP_WAIT_GATING_DISABLED /*!< Wait until gating is disabled */ -}; - -/* Description of a memory range controlled by the MPC */ -struct mpc_sie_memory_range_t { - const uint32_t base; /*!< Base address (included in the range) */ - const uint32_t limit; /*!< Limit address (included in the range) */ - const uint32_t range_offset; /*!< Offset of current range area to the 0 - * point of the whole area (the sum of the - * sizes of the previous memory ranges - * covered by the same MPC) - */ - const enum mpc_sie_sec_attr_t attr; /*!< Optional security attribute - * needed to be matched when - * accessing this range. - * For example, the non-secure - * alias of a memory region can not - * be accessed using secure access, - * and configuring the MPC to - * secure using that range will not - * be permitted by the driver. - */ -}; - -/* ARM MPC SIE device configuration structure */ -struct mpc_sie_dev_cfg_t { - const uint32_t base; /*!< MPC base address */ -}; - -/* ARM MPC SIE device data structure */ -struct mpc_sie_dev_data_t { - /*!< Array of pointers to memory ranges controlled by the MPC */ - const struct mpc_sie_memory_range_t** range_list; - uint8_t nbr_of_ranges; /*!< Number of memory ranges in the list */ - bool is_initialized; /*!< Indicates if the MPC driver - * is initialized and enabled - */ - uint32_t sie_version; /*!< SIE version */ -}; - -/* ARM MPC SIE device structure */ -struct mpc_sie_dev_t { - const struct mpc_sie_dev_cfg_t* const cfg; /*!< MPC configuration */ - struct mpc_sie_dev_data_t* const data; /*!< MPC data */ -}; - -/** - * \brief Initializes a MPC device. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[in] range_list List of memory ranges controller by the MPC - * (\ref mpc_sie_memory_range_t). This list can not - * freed after the initializations. - * \param[in] nbr_of_ranges Number of memory ranges - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_init(struct mpc_sie_dev_t* dev, - const struct mpc_sie_memory_range_t** range_list, - uint8_t nbr_of_ranges); - -/** - * \brief Gets MPC block size. All regions must be aligned on this block - * size (base address and limit+1 address). - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[out] blk_size MPC block size - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_get_block_size(struct mpc_sie_dev_t* dev, - uint32_t* blk_size); - -/** - * \brief Configures a memory region (base and limit included). - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[in] base Base address of the region to poll. This bound is - * included. It does not need to be aligned in any way. - * - * \param[in] limit Limit address of the region to poll. This bound is - * included. (limit+1) does not need to be aligned - * in any way. - * \param[in] attr Security attribute of the region. If the region has mixed - * secure/non-secure, a special value is returned - * (\ref mpc_sie_sec_attr_t). - * - * In case base and limit+1 addresses are not aligned on - * the block size, the enclosing region with base and - * limit+1 aligned on block size will be queried. - * In case of early termination of the function (error), the - * security attribute will be set to MPC_SIE_ATTR_MIXED. - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_config_region(struct mpc_sie_dev_t* dev, - const uint32_t base, - const uint32_t limit, - enum mpc_sie_sec_attr_t attr); - -/** - * \brief Gets a memory region configuration(base and limit included). - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[in] base Base address of the region to get the configuration. - * \param[in] limit Limit address of the region to get the configuration. - * \param[out] attr Security attribute of the region - * \ref mpc_sie_sec_attr_t - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_get_region_config(struct mpc_sie_dev_t* dev, - uint32_t base, - uint32_t limit, - enum mpc_sie_sec_attr_t* attr); - -/** - * \brief Gets the MPC control value. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[out] ctrl_val Current MPC control value. - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_get_ctrl(struct mpc_sie_dev_t* dev, - uint32_t* ctrl_val); - -/** - * \brief Sets the MPC control value. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[in] mpc_ctrl New MPC control value - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_set_ctrl(struct mpc_sie_dev_t* dev, - uint32_t mpc_ctrl); - -/** - * \brief Gets the configured secure response. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[out] sec_rep Configured secure response (\ref mpc_sie_sec_resp_t). - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_get_sec_resp(struct mpc_sie_dev_t* dev, - enum mpc_sie_sec_resp_t* sec_rep); - -/** - * \brief Sets the response type when SW asks to gate the incoming transfers. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[in] sec_rep Secure response to configure (\ref mpc_sie_sec_resp_t). - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_set_sec_resp(struct mpc_sie_dev_t* dev, - enum mpc_sie_sec_resp_t sec_rep); - -/** - * \brief Enables MPC interrupt. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_irq_enable(struct mpc_sie_dev_t* dev); - -/** - * \brief Disables MPC interrupt - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \note This function doesn't check if dev is NULL. - */ -void mpc_sie_irq_disable(struct mpc_sie_dev_t* dev); - -/** - * \brief Clears MPC interrupt. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \note This function doesn't check if dev is NULL. - */ -void mpc_sie_clear_irq(struct mpc_sie_dev_t* dev); - -/** - * \brief Returns the MPC interrupt state. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \return Returns 1 if the interrupt is active, 0 otherwise. - * - * \note This function doesn't check if dev is NULL. - */ -uint32_t mpc_sie_irq_state(struct mpc_sie_dev_t* dev); - -/** - * \brief Locks down the MPC configuration. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_lock_down(struct mpc_sie_dev_t* dev); - -/** - * \brief Returns if gating is present in hardware. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * \param[out] gating_present Returns if gating is present in hardware. - * - * \return Returns error code as specified in \ref mpc_sie_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpc_sie_error_t mpc_sie_is_gating_present(struct mpc_sie_dev_t* dev, - bool* gating_present); - -/** - * \brief Returns the value of Peripheral ID 0 register. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \return Returns the value of Peripheral ID 0 register. - * - * \note This function doesn't check if dev is NULL. - */ -uint32_t get_sie_version(struct mpc_sie_dev_t* dev); - -/** - * \brief Reads bit indicating acknowledge for gating incoming transfers. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \return True if acknowledge is set. - * - * \note This function doesn't check if dev is NULL. - */ -bool mpc_sie_get_gate_ack(struct mpc_sie_dev_t* dev); - -/** - * \brief Sets bit to request for gating incoming transfers. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \note This function doesn't check if dev is NULL. - */ -void mpc_sie_request_gating(struct mpc_sie_dev_t* dev); - -/** - * \brief Clears bit to request for gating incoming transfers. - * - * \param[in] dev MPC device \ref mpc_sie_dev_t - * - * \note This function doesn't check if dev is NULL. - */ -void mpc_sie_release_gating(struct mpc_sie_dev_t* dev); - -#ifdef __cplusplus -} -#endif -#endif /* __MPC_SIE_DRV_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/mpu_armv8m_drv.c b/platform/ext/target/mps2/sse-200_aws/native_drivers/mpu_armv8m_drv.c deleted file mode 100644 index ad9efab9ce..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/mpu_armv8m_drv.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2017-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "mpu_armv8m_drv.h" -#include "cmsis.h" - -/* - * FixMe: - * This is a beta quality driver for MPU in v8M. To be finalized. - */ - -enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev, - uint32_t privdef_en, - uint32_t hfnmi_en) -{ - /*No error checking*/ - - MPU_Type *mpu = (MPU_Type *)dev->base; - - /* - * FixMe: Set 3 pre-defined MAIR_ATTR for memory. The attributes come - * from default memory map, need to check if fine-tune is necessary. - * - * MAIR0_0: Peripheral, Device-nGnRE. - * MAIR0_1: Code, WT RA. Same attr for Outer and Inner. - * MAIR0_2: SRAM, WBWA RA. Same attr for Outer and Inner. - */ - mpu->MAIR0 = (MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL << MPU_MAIR0_Attr0_Pos) | - (MPU_ARMV8M_MAIR_ATTR_CODE_VAL << MPU_MAIR0_Attr1_Pos) | - (MPU_ARMV8M_MAIR_ATTR_DATA_VAL << MPU_MAIR0_Attr2_Pos); - - mpu->CTRL = - (privdef_en ? MPU_CTRL_PRIVDEFENA_Msk : 0) | - (hfnmi_en ? MPU_CTRL_HFNMIENA_Msk : 0); - - /*Ensure all configuration is written before enable*/ - - mpu->CTRL |= MPU_CTRL_ENABLE_Msk; - - /* Enable MPU before next instruction */ - __DSB(); - __ISB(); - return MPU_ARMV8M_OK; -} - -enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev) -{ - MPU_Type *mpu = (MPU_Type *)dev->base; - - /* Reset all fields as enable does full setup */ - mpu->CTRL = 0; - - return MPU_ARMV8M_OK; -} - - -enum mpu_armv8m_error_t mpu_armv8m_region_enable( - struct mpu_armv8m_dev_t *dev, - struct mpu_armv8m_region_cfg_t *region_cfg) -{ - MPU_Type *mpu = (MPU_Type *)dev->base; - - enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK; - uint32_t ctrl_before; - uint32_t base_cfg; - uint32_t limit_cfg; - - /*FIXME : Add complete error checking*/ - if ((region_cfg->region_base & ~MPU_RBAR_BASE_Msk) != 0) { - return MPU_ARMV8M_ERROR; - } - /* region_limit doesn't need to be aligned but the scatter - * file needs to be setup to ensure that partitions do not overlap. - */ - - ctrl_before = mpu->CTRL; - mpu->CTRL = 0; - - mpu->RNR = region_cfg->region_nr & MPU_RNR_REGION_Msk; - - /* This 0s the lower bits of the base address */ - base_cfg = region_cfg->region_base & MPU_RBAR_BASE_Msk; - base_cfg |= (region_cfg->attr_sh << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk; - base_cfg |= (region_cfg->attr_access << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk; - base_cfg |= (region_cfg->attr_exec << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk; - - mpu->RBAR = base_cfg; - - /*This 0s the lower bits of base address but they are treated as 1 */ - limit_cfg = (region_cfg->region_limit-1) & MPU_RLAR_LIMIT_Msk; - - limit_cfg |= (region_cfg->region_attridx << MPU_RLAR_AttrIndx_Pos) & - MPU_RLAR_AttrIndx_Msk; - - limit_cfg |= MPU_RLAR_EN_Msk; - - mpu->RLAR = limit_cfg; - - /*Restore main MPU control*/ - mpu->CTRL = ctrl_before; - - /* Enable MPU before the next instruction */ - __DSB(); - __ISB(); - - return ret_val; -} - - -enum mpu_armv8m_error_t mpu_armv8m_region_disable( - struct mpu_armv8m_dev_t *dev, - uint32_t region_nr) -{ - - MPU_Type *mpu = (MPU_Type *)dev->base; - - enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK; - uint32_t ctrl_before; - - /*FIXME : Add complete error checking*/ - - ctrl_before = mpu->CTRL; - mpu->CTRL = 0; - - mpu->RNR = region_nr & MPU_RNR_REGION_Msk; - - mpu->RBAR = 0; - mpu->RLAR = 0; - - /*Restore main MPU control*/ - mpu->CTRL = ctrl_before; - - return ret_val; -} - -enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev) -{ - MPU_Type *mpu = (MPU_Type *)dev->base; - uint32_t i = (mpu->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; - - while (i > 0) { - mpu_armv8m_region_disable(dev, i-1); - i--; - } - - return MPU_ARMV8M_OK; - -} diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/mpu_armv8m_drv.h b/platform/ext/target/mps2/sse-200_aws/native_drivers/mpu_armv8m_drv.h deleted file mode 100644 index d427604f38..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/mpu_armv8m_drv.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2017-2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __MPU_ARMV8M_DRV_H__ -#define __MPU_ARMV8M_DRV_H__ - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define PRIVILEGED_DEFAULT_ENABLE 1 -#define HARDFAULT_NMI_ENABLE 1 - -/* MAIR_ATTR */ -#define MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL 0x04 -#define MPU_ARMV8M_MAIR_ATTR_DEVICE_IDX 0 -#define MPU_ARMV8M_MAIR_ATTR_CODE_VAL 0xAA -#define MPU_ARMV8M_MAIR_ATTR_CODE_IDX 1 -#define MPU_ARMV8M_MAIR_ATTR_DATA_VAL 0xFF -#define MPU_ARMV8M_MAIR_ATTR_DATA_IDX 2 - -struct mpu_armv8m_dev_t { - const uint32_t base; -}; - -enum mpu_armv8m_error_t { - MPU_ARMV8M_OK, - MPU_ARMV8M_ERROR -}; - -enum mpu_armv8m_attr_exec_t { - MPU_ARMV8M_XN_EXEC_OK, - MPU_ARMV8M_XN_EXEC_NEVER -}; - -enum mpu_armv8m_attr_access_t { - MPU_ARMV8M_AP_RW_PRIV_ONLY, - MPU_ARMV8M_AP_RW_PRIV_UNPRIV, - MPU_ARMV8M_AP_RO_PRIV_ONLY, - MPU_ARMV8M_AP_RO_PRIV_UNPRIV -}; - -enum mpu_armv8m_attr_shared_t { - MPU_ARMV8M_SH_NONE, - MPU_ARMV8M_SH_UNUSED, - MPU_ARMV8M_SH_OUTER, - MPU_ARMV8M_SH_INNER -}; - -struct mpu_armv8m_region_cfg_t { - uint32_t region_nr; - uint32_t region_base; - uint32_t region_limit; - uint32_t region_attridx; - enum mpu_armv8m_attr_exec_t attr_exec; - enum mpu_armv8m_attr_access_t attr_access; - enum mpu_armv8m_attr_shared_t attr_sh; -}; - -struct mpu_armv8m_region_cfg_raw_t { - uint32_t region_nr; - uint32_t region_base; - uint32_t region_limit; -}; - - -/** - * \brief Enable MPU - * - * \param[in] dev MPU device \ref mpu_armv8m_dev_t - * \param[in] privdef_en privilege default region 1:enable 0:disable - * \param[in] hfnmi_en mpu for hard fault & nmi 1:enable 0:disable - * - * \return Error code \ref mpu_armv8m_error_t - * - * \note This function doesn't check if dev is NULL. - */ - -enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev, - uint32_t privdef_en, - uint32_t hfnmi_en); - -/** - * \brief Disable MPU - * - * \param[in] dev MPU device \ref mpu_armv8m_dev_t - * - * \return Error code \ref arm_mpu_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev); - -/** - * \brief Disable MPU and clean all regions - * - * \param[in] dev MPU device \ref mpu_armv8m_dev_t - * - * \return Error code \ref arm_mpu_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev); - -/** - * \brief Enable MPU Region - * - * \param[in] dev MPU device \ref mpu_armv8m_dev_t - * \param[in] region_cfg MPU region config \ref mpu_armv8m_region_cfg_t - * - * \return Error code \ref arm_mpu_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpu_armv8m_error_t mpu_armv8m_region_enable( - struct mpu_armv8m_dev_t *dev, - struct mpu_armv8m_region_cfg_t *region_cfg); - -/** - * \brief Disable MPU Region - * - * \param[in] dev MPU device \ref mpu_armv8m_dev_t - * \param[in] region_nr Region number - * - * \return Error code \ref arm_mpu_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum mpu_armv8m_error_t mpu_armv8m_region_disable( - struct mpu_armv8m_dev_t *dev, - uint32_t region_nr); - -#ifdef __cplusplus -} -#endif - -#endif /* __MPU_ARMV8M_DRV_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/ppc_sse200_drv.c b/platform/ext/target/mps2/sse-200_aws/native_drivers/ppc_sse200_drv.c deleted file mode 100644 index dda05506db..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/ppc_sse200_drv.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright (c) 2017-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "ppc_sse200_drv.h" - -/* SPCTRL PPCs control memory mapped registers access structure */ -struct arm_spctrl_ppc_sse200_t { - volatile uint32_t reserved[8]; - volatile uint32_t secppcintstat; /* Secure PPC Interrupt Status */ - volatile uint32_t secppcintclr; /* Secure PPC Interrupt Clear */ - volatile uint32_t secppcinten; /* Secure PPC Interrupt Enable */ - volatile uint32_t reserved1[9]; - volatile uint32_t ahbnsppc0; /* Non-Secure Access AHB slave Peripheral - * Protection Control #0 - */ - volatile uint32_t reserved2[3]; /* Reserved for Future Non-secure Access - * AHB Slave Peripheral Protection Control - */ - volatile uint32_t ahbnsppcexp0; /* Expansion 0 Non_Secure Access AHB - * slave Peripheral Protection Control - */ - volatile uint32_t ahbnsppcexp1; /* Expansion 1 Non_Secure Access AHB - * slave Peripheral Protection Control - */ - volatile uint32_t ahbnsppcexp2; /* Expansion 2 Non_Secure Access AHB - * slave Peripheral Protection Control - */ - volatile uint32_t ahbnsppcexp3; /* Expansion 3 Non_Secure Access AHB - * slave Peripheral Protection Control - */ - volatile uint32_t apbnsppc0; /* Non-Secure Access APB slave Peripheral - * Protection Control 0 - */ - volatile uint32_t apbnsppc1; /* Non-Secure Access APB slave Peripheral - * Protection Control 1 - */ - volatile uint32_t reserved3[2]; /* Non-Secure Access APB slave Peripheral - * Protection Control [3:1] - */ - volatile uint32_t apbnsppcexp0; /* Expansion 0 Non_Secure Access APB - * slave Peripheral Protection Control - */ - volatile uint32_t apbnsppcexp1; /* Expansion 1 Non_Secure Access APB - * slave Peripheral Protection Control - */ - volatile uint32_t apbnsppcexp2; /* Expansion 2 Non_Secure Access APB - * slave Peripheral Protection Control - */ - volatile uint32_t apbnsppcexp3; /* Expansion 3 Non_Secure Access APB - * slave Peripheral Protection Control - */ - volatile uint32_t ahbspppc0; /* Secure Unprivileged Access AHB slave - * Peripheral Protection Control 0 - */ - volatile uint32_t reserved4[3]; /* Reserved for Future Secure Unprivileged - * Access AHB slave Peripheral Protection - * Control - */ - volatile uint32_t ahbspppcexp0; /* Expansion 0 Secure Unprivileged Access - * AHB slave Peripheral Protection Control - */ - volatile uint32_t ahbspppcexp1; /* Expansion 1 Secure Unprivileged Access - * AHB slave Peripheral Protection Control - */ - volatile uint32_t ahbspppcexp2; /* Expansion 2 Secure Unprivileged Access - * AHB slave Peripheral Protection Control - */ - volatile uint32_t ahbspppcexp3; /* Expansion 3 Secure Unprivileged Access - * AHB slave Peripheral Protection Control - */ - volatile uint32_t apbspppc0; /* Secure Unprivileged Access APB slave - * Peripheral 0 - */ - volatile uint32_t apbspppc1; /* Secure Unprivileged Access APB slave - * Peripheral 1 - */ - volatile uint32_t reserved5[2]; /* Reserved for Future Secure Unprivileged - * Access APB slave Peripheral Protection - * Control - */ - volatile uint32_t apbspppcexp0; /* Expansion 0 Secure Unprivileged Access - * APB slave Peripheral Protection - * Control - */ - volatile uint32_t apbspppcexp1; /* Expansion 1 Secure Unprivileged Access - * APB slave Peripheral Protection - * Control - */ - volatile uint32_t apbspppcexp2; /* Expansion 2 Secure Unprivileged Access - * APB slave Peripheral Protection - * Control - */ - volatile uint32_t apbspppcexp3; /* Expansion 3 Secure Unprivileged Access - * APB slave Peripheral Protection - * Control - */ -}; - -/* NSPCTRL PPCs memory mapped register access structure */ -struct arm_nspctrl_ppc_sse200_t { - volatile uint32_t reserved[36]; - volatile uint32_t ahbnspppc0; - volatile uint32_t reserved1[3]; - volatile uint32_t ahbnspppcexp0; - volatile uint32_t ahbnspppcexp1; - volatile uint32_t ahbnspppcexp2; - volatile uint32_t ahbnspppcexp3; - volatile uint32_t apbnspppc0; - volatile uint32_t apbnspppc1; - volatile uint32_t reserved2[2]; - volatile uint32_t apbnspppcexp0; - volatile uint32_t apbnspppcexp1; - volatile uint32_t apbnspppcexp2; - volatile uint32_t apbnspppcexp3; -}; - -/* PPC interrupt position mask */ -#define APB_PPC0_INT_POS_MASK (1UL << 0) -#define APB_PPC1_INT_POS_MASK (1UL << 1) -/* Reserved bits 2:3 */ -#define APB_PPCEXP0_INT_POS_MASK (1UL << 4) -#define APB_PPCEXP1_INT_POS_MASK (1UL << 5) -#define APB_PPCEXP2_INT_POS_MASK (1UL << 6) -#define APB_PPCEXP3_INT_POS_MASK (1UL << 7) -/* Reserved bits 8:15 */ -#define AHB_PPC0_INT_POS_MASK (1UL << 16) -/* Reserved bits 17:19 */ -#define AHB_PPCEXP0_INT_POS_MASK (1UL << 20) -#define AHB_PPCEXP1_INT_POS_MASK (1UL << 21) -#define AHB_PPCEXP2_INT_POS_MASK (1UL << 22) -#define AHB_PPCEXP3_INT_POS_MASK (1UL << 23) -/* Reserved bits 24:31 */ - -/* ARM PPC state definitions */ -#define PPC_SSE200_INITIALIZED (1 << 0) - -/* Default peripheral states */ -#define SECURE_AS_DEFAULT_PERIPHERAL_STATE 1 -#define PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE 1 - -void ppc_sse200_init(struct ppc_sse200_dev_t* dev, - enum ppc_sse200_name_t ppc_name) -{ - struct arm_spctrl_ppc_sse200_t* p_spctrl = - (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; - struct arm_nspctrl_ppc_sse200_t* p_nspctrl = - (struct arm_nspctrl_ppc_sse200_t*)dev->cfg->nspctrl_base; - - switch(ppc_name) { - case AHB_PPC0: - dev->data->p_ns_ppc = &p_spctrl->ahbnsppc0; - dev->data->p_sp_ppc = &p_spctrl->ahbspppc0; - dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppc0; - dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK; - break; - case AHB_PPC_EXP0: - dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp0; - dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp0; - dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp0; - dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK; - break; - case AHB_PPC_EXP1: - dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp1; - dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp1; - dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp1; - dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK; - break; - case AHB_PPC_EXP2: - dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp2; - dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp2; - dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp2; - dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK; - break; - case AHB_PPC_EXP3: - dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp3; - dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp3; - dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp3; - dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK; - break; - case APB_PPC0: - dev->data->p_ns_ppc = &p_spctrl->apbnsppc0; - dev->data->p_sp_ppc = &p_spctrl->apbspppc0; - dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc0; - dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK; - break; - case APB_PPC1: - dev->data->p_ns_ppc = &p_spctrl->apbnsppc1; - dev->data->p_sp_ppc = &p_spctrl->apbspppc1; - dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc1; - dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK; - break; - case APB_PPC_EXP0: - dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp0; - dev->data->p_sp_ppc = &p_spctrl->apbspppcexp0; - dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp0; - dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK; - break; - case APB_PPC_EXP1: - dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp1; - dev->data->p_sp_ppc = &p_spctrl->apbspppcexp1; - dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp1; - dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK; - break; - case APB_PPC_EXP2: - dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp2; - dev->data->p_sp_ppc = &p_spctrl->apbspppcexp2; - dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp2; - dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK; - break; - case APB_PPC_EXP3: - dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp3; - dev->data->p_sp_ppc = &p_spctrl->apbspppcexp3; - dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp3; - dev->data->int_bit_mask = APB_PPCEXP3_INT_POS_MASK; - break; - /* default: The default is not defined intentionally to force the - * compiler to check that all enumeration values are - * covered in the switch. - */ - } - - dev->data->state = PPC_SSE200_INITIALIZED; -} - -enum ppc_sse200_error_t ppc_sse200_config_peripheral( - struct ppc_sse200_dev_t* dev, - uint8_t periph, - enum ppc_sse200_sec_attr_t sec_attr, - enum ppc_sse200_priv_attr_t priv_attr) -{ - if(dev->data->state != PPC_SSE200_INITIALIZED) { - return PPC_SSE200_NOT_INIT; - } - - if(sec_attr == PPC_SSE200_SECURE_ONLY) { - /* Sets secure attribute */ - *(dev->data->p_ns_ppc) &= ~(1U << periph); - - /* Uses secure unprivileged access address (SPCTRL) to set privilege - * attribute - */ - if(priv_attr == PPC_SSE200_PRIV_ONLY) { - *(dev->data->p_sp_ppc) &= ~(1U << periph); - } else { - *(dev->data->p_sp_ppc) |= (1U << periph); - } - } else { - /* Sets secure attribute */ - *(dev->data->p_ns_ppc) |= (1U << periph); - - /* Uses non-secure unprivileged access address (NSPCTRL) to set - * privilege attribute - */ - if(priv_attr == PPC_SSE200_PRIV_ONLY) { - *(dev->data->p_nsp_ppc) &= ~(1U << periph); - } else { - *(dev->data->p_nsp_ppc) |= (1U << periph); - } - } - - return PPC_SSE200_ERR_NONE; -} - -uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev, - uint8_t periph) -{ - if(dev->data->state != PPC_SSE200_INITIALIZED) { - return SECURE_AS_DEFAULT_PERIPHERAL_STATE; - } - - return ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0); -} - -uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev, - uint8_t periph) -{ - if(dev->data->state != PPC_SSE200_INITIALIZED) { - return PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE; - } - - if ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0) { - /* Returns secure unprivileged access address (SPCTRL) */ - return ((*(dev->data->p_sp_ppc) & (1U << periph)) == 0); - } else { - /* Returns non-secure unprivileged access address (NSPCTRL) */ - return ((*(dev->data->p_nsp_ppc) & (1U << periph)) == 0); - } -} - -enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev) -{ - struct arm_spctrl_ppc_sse200_t* p_spctrl = - (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; - - if(dev->data->state != PPC_SSE200_INITIALIZED) { - return PPC_SSE200_NOT_INIT; - } - - p_spctrl->secppcinten |= dev->data->int_bit_mask; - - return PPC_SSE200_ERR_NONE; -} - -void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev) -{ - struct arm_spctrl_ppc_sse200_t* p_spctrl = - (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; - - if(dev->data->state == PPC_SSE200_INITIALIZED) { - p_spctrl->secppcinten &= ~(dev->data->int_bit_mask); - } -} - -void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev) -{ - struct arm_spctrl_ppc_sse200_t* p_spctrl = - (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; - - if(dev->data->state == PPC_SSE200_INITIALIZED) { - p_spctrl->secppcintclr = dev->data->int_bit_mask; - } -} - -uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev) -{ - struct arm_spctrl_ppc_sse200_t* p_spctrl = - (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base; - - if(dev->data->state != PPC_SSE200_INITIALIZED) { - return 0; - } - - return ((p_spctrl->secppcintstat & dev->data->int_bit_mask) != 0); -} diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/ppc_sse200_drv.h b/platform/ext/target/mps2/sse-200_aws/native_drivers/ppc_sse200_drv.h deleted file mode 100644 index 7a08a8f9fe..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/ppc_sse200_drv.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2017-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file ppc_sse200_drv.h - * \brief Generic driver for ARM SEE 200 Peripheral Protection - * Controllers (PPC). - */ - -#ifndef __PPC_SSE_200_DRV_H__ -#define __PPC_SSE_200_DRV_H__ - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Secure Privilege Control Block aka SPCTRL */ -/* Non-Secure Privilege Control Block aka NSPCTRL */ - -/* ARM TrustZone PPC device configuration structure */ -struct ppc_sse200_dev_cfg_t { - uint32_t const spctrl_base; /*!< SPCTRL base address */ - uint32_t const nspctrl_base; /*!< NSPCTRL base address */ -}; - -/* ARM TrustZone PPC device data structure */ -struct ppc_sse200_dev_data_t { - volatile uint32_t* p_ns_ppc; /*!< Pointer to non-secure register */ - volatile uint32_t* p_sp_ppc; /*!< Pointer to secure unprivileged - * register - */ - volatile uint32_t* p_nsp_ppc; /*!< Pointer to non-secure unprivileged - * register - */ - uint32_t int_bit_mask; /*!< Interrupt bit mask */ - uint8_t state; /*!< Indicates if the PPC driver - * is initialized - */ - uint8_t reserved[3]; /*!< 32 bits alignment */ -}; - -/* ARM PPC device structure */ -struct ppc_sse200_dev_t { - const struct ppc_sse200_dev_cfg_t* const cfg; /*!< PPC configuration */ - struct ppc_sse200_dev_data_t* const data; /*!< PPC data */ -}; - -/* Security attribute used to configure the peripheral */ -enum ppc_sse200_sec_attr_t { - PPC_SSE200_SECURE_ONLY, /*! Secure access */ - PPC_SSE200_NONSECURE_ONLY, /*! Non-secure access */ -}; - -/* Privilege attribute used to configure the peripheral */ -enum ppc_sse200_priv_attr_t { - PPC_SSE200_PRIV_AND_NONPRIV, /*! Privilege and non-Privilege access */ - PPC_SSE200_PRIV_ONLY, /*! Privilege only access */ -}; - -/* ARM PPC error codes */ -enum ppc_sse200_error_t { - PPC_SSE200_ERR_NONE = 0, /*!< No error */ - PPC_SSE200_NOT_INIT, /*!< PPC not initialized */ -}; - -/* ARM PPC names */ -enum ppc_sse200_name_t { - AHB_PPC0 = 0, /*!< AHB PPC0 */ - AHB_PPC_EXP0, /*!< Expansion 0 AHB PPC */ - AHB_PPC_EXP1, /*!< Expansion 1 AHB PPC */ - AHB_PPC_EXP2, /*!< Expansion 2 AHB PPC */ - AHB_PPC_EXP3, /*!< Expansion 3 AHB PPC */ - APB_PPC0, /*!< APB PPC0 */ - APB_PPC1, /*!< APB PPC1 */ - APB_PPC_EXP0, /*!< Expansion 0 APB PPC */ - APB_PPC_EXP1, /*!< Expansion 1 APB PPC */ - APB_PPC_EXP2, /*!< Expansion 2 APB PPC */ - APB_PPC_EXP3 /*!< Expansion 3 APB PPC */ -}; - -/** - * \brief Initialize the PPC device. - * - * \param[in] dev PPC device \ref ppc_sse200_dev_t - * \param[in] ppc_name PPC name \ref ppc_sse200_name_t - * - * \note This function doesn't check if dev is NULL. - */ -void ppc_sse200_init(struct ppc_sse200_dev_t* dev, - enum ppc_sse200_name_t ppc_name); - -/** - * \brief Configures the PPC device. - * - * \param[in] dev PPC device \ref ppc_sse200_dev_t - * \param[in] periph Peripheral position in the PPC. - * \param[in] sec_attr Secure attribute value. - * \param[in] priv_attr Privilege attribute value. - * - * \return Returns error code as specified in \ref ppc_sse200_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum ppc_sse200_error_t ppc_sse200_config_peripheral( - struct ppc_sse200_dev_t* dev, - uint8_t periph, - enum ppc_sse200_sec_attr_t sec_attr, - enum ppc_sse200_priv_attr_t priv_attr); -/** - * \brief Checks if the peripheral is configured as secure or non-secure. - * - * \param[in] dev PPC device \ref ppc_sse200_dev_t - * \param[in] periph Peripheral position in the PPC. - * - * \return Returns 1 for secure and 0 for non-secure. - * If the driver is not initialized the return value is 1 (secure) as - * it is the default system configuration. - * - * \note This function doesn't check if dev is NULL. - */ -uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev, - uint8_t periph); - -/** - * \brief Checks if the peripheral is configured as Privilege only or - * Privilege and non-Privilege access mode. - * - * \param[in] dev PPC device \ref ppc_sse200_dev_t - * \param[in] periph Peripheral position in the PPC. - * - * \return Returns 1 for Privilege only configuration and 0 for Privilege and - * non-Privilege access. - * If the driver is not initialized the return of this function is - * 1 (Privilege only) as it is the default system configuration. - * - * \note This function doesn't check if dev is NULL. - */ -uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev, - uint8_t periph); -/** - * \brief Enables PPC interrupt. - * - * \param[in] dev PPC device \ref ppc_sse200_dev_t - * - * \return Returns error code as specified in \ref ppc_sse200_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev); - -/** - * \brief Disables PPC interrupt. - * - * \param[in] dev PPC device \ref ppc_sse200_dev_t - * - * \note This function doesn't check if dev is NULL. - */ -void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev); - -/** - * \brief Clears PPC interrupt. - * - * \param[in] dev PPC device \ref ppc_sse200_dev_t - * - * \note This function doesn't check if dev is NULL. - */ -void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev); - -/** - * \brief Returns the PPC interrupt state. - * - * \param[in] dev PPC device \ref ppc_sse200_dev_t - * - * \return Returns 1 if the interrupt is active and otherwise 0. - * If the driver is not initialized the return of this function is - * 0 (not active) as it is the default system configuration. - * - * \note This function doesn't check if dev is NULL. - */ -uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev); - -#ifdef __cplusplus -} -#endif - -#endif /* __PPC_SSE_200_DRV_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/timer_cmsdk/timer_cmsdk_drv.c b/platform/ext/target/mps2/sse-200_aws/native_drivers/timer_cmsdk/timer_cmsdk_drv.c deleted file mode 100644 index b051909b29..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/timer_cmsdk/timer_cmsdk_drv.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file timer_cmsdk_drv.c - * \brief Generic driver for CMSDK APB Timers. - * The timer is a 32-bit down-counter with the following features: - * - optional programmable external clock source - * - programmable interrupt source, triggered if counter reaches 0 - * - automatic reload if counter reaches 0 - */ - -#include "timer_cmsdk_drv.h" - -/** Setter bit manipulation macro */ -#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) -/** Clearing bit manipulation macro */ -#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) -/** Getter bit manipulation macro */ -#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX)))) - -/** - * \brief Timer register map structure - * - */ -struct timer_cmsdk_reg_map_t { - volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */ - volatile uint32_t value; /* Offset: 0x004 (R/W) current value register */ - volatile uint32_t reload; /* Offset: 0x008 (R/W) reload value register */ - union { - volatile uint32_t intstatus; /* Offset: 0x00C (R/ ) interrupt - * status register - */ - volatile uint32_t intclear; /* Offset: 0x00C ( /W) interrupt - * clear register - */ - }intreg; -}; - -/** - * \brief CTRL register bit definitions - * - */ -enum ctrl_reg_bits_t { - CTRL_REG_ENUM_ENABLE_INDEX = 0, - CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX = 1, - CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX = 2, - CTRL_REG_ENUM_IRQ_ENABLE_INDEX = 3 -}; - -/** - * \brief INTSTATUS/INTCLEAR register bit definitions - * - */ -enum interrupt_reg_bits_t { - INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX = 0 -}; - -void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - - if (dev->data->is_initialized == 0) { - register_map->ctrl = 0; - register_map->reload = TIMER_CMSDK_DEFAULT_RELOAD; - dev->data->is_initialized = 1; - } -} - -bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev) -{ - return dev->data->is_initialized; -} - -void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); -} - -void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); -} - -bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - return GET_BIT(register_map->ctrl, - CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); -} - -void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); -} - -void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); -} - -bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - return GET_BIT(register_map->ctrl, - CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); -} - -void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); -} - -void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); -} - -bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); -} - -void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); -} - -void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); -} - -bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); -} - -bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - return GET_BIT(register_map->intreg.intstatus, - INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX); -} - -void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - SET_BIT(register_map->intreg.intclear, - INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX); -} - -uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - return register_map->value; -} - -void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev, - uint32_t reload) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - register_map->reload = reload; -} - -void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - register_map->value = register_map->reload; -} - -uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - return register_map->reload; -} - -uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev) -{ - struct timer_cmsdk_reg_map_t* register_map = - (struct timer_cmsdk_reg_map_t*)dev->cfg->base; - return register_map->reload - register_map->value; -} diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/timer_cmsdk/timer_cmsdk_drv.h b/platform/ext/target/mps2/sse-200_aws/native_drivers/timer_cmsdk/timer_cmsdk_drv.h deleted file mode 100644 index a374e63b0d..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/timer_cmsdk/timer_cmsdk_drv.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file timer_cmsdk_drv.h - * \brief Generic driver for CMSDK APB Timers. - * The timer is a 32-bit down-counter with the following features: - * - optional programmable external clock source - * - programmable interrupt source, triggered if counter reaches 0 - * - automatic reload if counter reaches 0 - */ - -#ifndef __TIMER_CMSDK_DRV_H__ -#define __TIMER_CMSDK_DRV_H__ - -#include <stdint.h> -#include <stdbool.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Maximum reload value */ -#define TIMER_CMSDK_MAX_RELOAD UINT32_MAX /* max of 32-bit */ -#define TIMER_CMSDK_DEFAULT_RELOAD TIMER_CMSDK_MAX_RELOAD - -/** CMSDK timer device configuration structure */ -struct timer_cmsdk_dev_cfg_t { - const uintptr_t base; /*!< Timer base address */ -}; - -/** CMSDK timer device data structure */ -struct timer_cmsdk_dev_data_t { - bool is_initialized; /*!< Indicates if the timer is initialized */ -}; - -/* CMSDK timer device structure */ -struct timer_cmsdk_dev_t { - const struct timer_cmsdk_dev_cfg_t* const cfg; /*!< Timer configuration */ - struct timer_cmsdk_dev_data_t* const data; /*!< Timer data */ -}; - -/** - * \brief Initializes timer to a known default state, which is: - * - timer disabled - * - timer interrupt disabled - * - clock source set to internal - * - external input disabled - * - reload value maxed out - * Init should be called prior to any other process and - * it's the caller's responsibility to follow proper call order. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Checks if a timer is initialized. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * \return true if initialized, false otherwise - */ -bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Enables external input, which could be used as clock source - * by calling \ref timer_cmsdk_set_clock_to_external. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Disables external input. - * Make sure if the timer is explicitly wanted to be stopped or set - * the clock source to internal by \ref timer_cmsdk_set_clock_to_internal - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Checks if external input is enabled. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * \return true if enabled, false otherwise - */ -bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Sets the clock source to internal. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Sets the clock source to external. - * Make sure external input is enabled correspondingly - * by \ref timer_cmsdk_enable_external_input. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Checks if clock source is external input. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * \return true if external, false if internal - */ -bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Enables timer operation. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Disables the given hardware timer. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Checks if a timer is enabled. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * \return true if enabled, false otherwise - */ -bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Enables timer interrupt. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Disables timer interrupt. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Checks if a timer interrupt is enabled. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * \return true if enabled, false otherwise - */ -bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Gets timer interrupt status - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * * \return true if active, false otherwise - */ -bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Clears timer interrupt - * The interrupt request is held until it is cleared. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Reads timer current value. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * \return Timer value - */ -uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Sets the reload value of the selected timer. - * - * New reload value takes effect when: - * - timer is restarted - * - on timer underflow - * - when timer_cmsdk_reset is called - * - * \note In r1p0 technical reference manual it's incorrectly stated - * writing the reload value automatically sets the current value also. - * r1p1 technical reference manual includes the fix. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * \param[in] reload Timer reload value to set. - * This is the start value of the 32-bit down counter, - * which automatically reloaded if 0 is reached. - */ -void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev, - uint32_t reload); - -/** - * \brief Resets the timer counter to the reload value instantly - * (i.e. without waiting for underflow). - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - */ -void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Gets the reload value of the selected timer. - * This is the start value of the 32-bit down counter, - * which is automatically reloaded if 0 is reached by the counter. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * \return Reload value of the selected timer. - */ -uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev); - -/** - * \brief Reads the number of ticks elapsed in the current cycle. - * - * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t - * - * \return Get elapsed number of ticks since last reload was set. - * Elapsed = (Reload value - Current value) - */ -uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev); - -#ifdef __cplusplus -} -#endif -#endif /* __TIMER_CMSDK_DRV_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/uart_cmsdk_drv.c b/platform/ext/target/mps2/sse-200_aws/native_drivers/uart_cmsdk_drv.c deleted file mode 100644 index c3d1230052..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/uart_cmsdk_drv.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "uart_cmsdk_drv.h" - -#include <stddef.h> - -/* UART register map structure */ -struct _uart_cmsdk_reg_map_t { - volatile uint32_t data; /* Offset: 0x000 (R/W) data register */ - volatile uint32_t state; /* Offset: 0x004 (R/W) status register */ - volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */ - union { - volatile uint32_t intrstatus; /* Offset: 0x00c (R/ ) interrupt status - * register - */ - volatile uint32_t intrclear; /* Offset: 0x00c ( /W) interrupt clear - * register - */ - }intr_reg; - volatile uint32_t bauddiv; /* Offset: 0x010 (R/W) Baudrate divider - * register - */ -}; - -/* CTRL Register */ -#define UART_CMSDK_TX_EN (1ul << 0) -#define UART_CMSDK_RX_EN (1ul << 1) -#define UART_CMSDK_TX_INTR_EN (1ul << 2) -#define UART_CMSDK_RX_INTR_EN (1ul << 3) - -/* STATE Register */ -#define UART_CMSDK_TX_BF (1ul << 0) -#define UART_CMSDK_RX_BF (1ul << 1) - -/* INTSTATUS Register */ -#define UART_CMSDK_TX_INTR (1ul << 0) -#define UART_CMSDK_RX_INTR (1ul << 1) - -/* UART state definitions */ -#define UART_CMSDK_INITIALIZED (1ul << 0) - -enum uart_cmsdk_error_t uart_cmsdk_init(struct uart_cmsdk_dev_t* dev, - uint32_t system_clk) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - if(system_clk == 0) { - return UART_CMSDK_ERR_INVALID_ARG; - } - - /* Sets baudrate and system clock */ - dev->data->system_clk = system_clk; - dev->data->baudrate = dev->cfg->default_baudrate; - - /* Sets baudrate */ - p_uart->bauddiv = (dev->data->system_clk / dev->cfg->default_baudrate); - - /* Enables receiver and transmitter */ - p_uart->ctrl = UART_CMSDK_RX_EN | UART_CMSDK_TX_EN; - - dev->data->state = UART_CMSDK_INITIALIZED; - - return UART_CMSDK_ERR_NONE; -} - -enum uart_cmsdk_error_t uart_cmsdk_set_baudrate(struct uart_cmsdk_dev_t* dev, - uint32_t baudrate) -{ - uint32_t bauddiv; - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(baudrate == 0) { - return UART_CMSDK_ERR_INVALID_BAUD; - } - - if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { - return UART_CMSDK_ERR_NOT_INIT; - } - - /* Sets baudrate */ - bauddiv = (dev->data->system_clk / baudrate); - dev->data->baudrate = baudrate; - - /* Minimum bauddiv value */ - if(bauddiv < 16) { - return UART_CMSDK_ERR_INVALID_BAUD; - } - - p_uart->bauddiv = bauddiv; - - return UART_CMSDK_ERR_NONE; -} - -uint32_t uart_cmsdk_get_baudrate(struct uart_cmsdk_dev_t* dev) -{ - return dev->data->baudrate; -} - -enum uart_cmsdk_error_t uart_cmsdk_set_clock(struct uart_cmsdk_dev_t* dev, - uint32_t system_clk) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(system_clk == 0) { - return UART_CMSDK_ERR_INVALID_ARG; - } - - if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { - return UART_CMSDK_ERR_NOT_INIT; - } - - /* Sets system clock */ - dev->data->system_clk = system_clk; - - /* Updates baudrate divider */ - p_uart->bauddiv = (dev->data->system_clk / dev->data->baudrate); - - /* Enables receiver and transmitter */ - return UART_CMSDK_ERR_NONE; -} - -enum uart_cmsdk_error_t uart_cmsdk_read(struct uart_cmsdk_dev_t* dev, - uint8_t* byte) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(!(p_uart->state & UART_CMSDK_RX_BF)) { - return UART_CMSDK_ERR_NOT_READY; - } - - /* Reads data */ - *byte = (uint8_t)p_uart->data; - - return UART_CMSDK_ERR_NONE; -} - -enum uart_cmsdk_error_t uart_cmsdk_write(struct uart_cmsdk_dev_t* dev, - uint8_t byte) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(p_uart->state & UART_CMSDK_TX_BF) { - return UART_CMSDK_ERR_NOT_READY; - } - - /* Sends data */ - p_uart->data = byte; - - return UART_CMSDK_ERR_NONE; -} - -enum uart_cmsdk_error_t uart_cmsdk_irq_tx_enable(struct uart_cmsdk_dev_t* dev) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { - return UART_CMSDK_ERR_NOT_INIT; - } - - p_uart->ctrl |= UART_CMSDK_TX_INTR_EN; - - return UART_CMSDK_ERR_NONE; -} - -void uart_cmsdk_irq_tx_disable(struct uart_cmsdk_dev_t* dev) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(dev->data->state & UART_CMSDK_INITIALIZED ) { - p_uart->ctrl &= ~UART_CMSDK_TX_INTR_EN; - } -} - -uint32_t uart_cmsdk_tx_ready(struct uart_cmsdk_dev_t* dev) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { - return 0; - } - - return !(p_uart->state & UART_CMSDK_TX_BF); -} - -enum uart_cmsdk_error_t uart_cmsdk_irq_rx_enable(struct uart_cmsdk_dev_t* dev) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { - return UART_CMSDK_ERR_NOT_INIT; - } - - p_uart->ctrl |= UART_CMSDK_RX_INTR_EN; - - return UART_CMSDK_ERR_NONE; -} - -void uart_cmsdk_irq_rx_disable(struct uart_cmsdk_dev_t* dev) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(dev->data->state & UART_CMSDK_INITIALIZED) { - p_uart->ctrl &= ~UART_CMSDK_RX_INTR_EN; - } -} - -uint32_t uart_cmsdk_rx_ready(struct uart_cmsdk_dev_t* dev) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(!(dev->data->state & UART_CMSDK_INITIALIZED)) { - return 0; - } - - return (p_uart->state & UART_CMSDK_RX_BF); -} - -void uart_cmsdk_clear_interrupt(struct uart_cmsdk_dev_t* dev, - enum uart_cmsdk_irq_t irq) -{ - struct _uart_cmsdk_reg_map_t* p_uart = - (struct _uart_cmsdk_reg_map_t*)dev->cfg->base; - - if(dev->data->state & UART_CMSDK_INITIALIZED) { - /* Clears pending interrupts */ - switch(irq) { - case UART_CMSDK_IRQ_RX: - p_uart->intr_reg.intrclear = UART_CMSDK_RX_INTR; - break; - case UART_CMSDK_IRQ_TX: - p_uart->intr_reg.intrclear = UART_CMSDK_TX_INTR; - break; - case UART_CMSDK_IRQ_COMBINED: - p_uart->intr_reg.intrclear = - (UART_CMSDK_RX_INTR | UART_CMSDK_TX_INTR); - break; - /* default: not defined to force all cases to be handled */ - } - } -} diff --git a/platform/ext/target/mps2/sse-200_aws/native_drivers/uart_cmsdk_drv.h b/platform/ext/target/mps2/sse-200_aws/native_drivers/uart_cmsdk_drv.h deleted file mode 100644 index 2d3278ef65..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/native_drivers/uart_cmsdk_drv.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file uart_cmsdk_drv.h - * \brief Generic driver for ARM UART. - */ - -#ifndef __UART_CMSDK_DRV_H__ -#define __UART_CMSDK_DRV_H__ - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* ARM UART device configuration structure */ -struct uart_cmsdk_dev_cfg_t { - const uint32_t base; /*!< UART base address */ - const uint32_t default_baudrate; /*!< Default baudrate */ -}; - -/* ARM UART device data structure */ -struct uart_cmsdk_dev_data_t { - uint32_t state; /*!< Indicates if the uart driver - * is initialized and enabled - */ - uint32_t system_clk; /*!< System clock */ - uint32_t baudrate; /*!< Baudrate */ -}; - -/* ARM UART device structure */ -struct uart_cmsdk_dev_t { - const struct uart_cmsdk_dev_cfg_t* const cfg; /*!< UART configuration */ - struct uart_cmsdk_dev_data_t* const data; /*!< UART data */ -}; - -/* ARM UART enumeration types */ -enum uart_cmsdk_error_t { - UART_CMSDK_ERR_NONE = 0, /*!< No error */ - UART_CMSDK_ERR_INVALID_ARG, /*!< Error invalid input argument */ - UART_CMSDK_ERR_INVALID_BAUD, /*!< Invalid baudrate */ - UART_CMSDK_ERR_NOT_INIT, /*!< Error UART not initialized */ - UART_CMSDK_ERR_NOT_READY, /*!< Error UART not ready */ -}; - -enum uart_cmsdk_irq_t { - UART_CMSDK_IRQ_RX, /*!< RX interrupt source */ - UART_CMSDK_IRQ_TX, /*!< TX interrupt source */ - UART_CMSDK_IRQ_COMBINED /*!< RX-TX combined interrupt source */ -}; - -/** - * \brief Initializes UART. It uses the default baudrate to configure - * the peripheral at this point. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * \param[in] system_clk System clock used by the device. - * - * \return Returns error code as specified in \ref uart_cmsdk_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum uart_cmsdk_error_t uart_cmsdk_init(struct uart_cmsdk_dev_t* dev, - uint32_t system_clk); - -/** - * \brief Sets the UART baudrate. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * \param[in] baudrate New baudrate. - * - * \return Returns error code as specified in \ref uart_cmsdk_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum uart_cmsdk_error_t uart_cmsdk_set_baudrate(struct uart_cmsdk_dev_t* dev, - uint32_t baudrate); - -/** - * \brief Gets the UART baudrate. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * - * \return Returns the UART baudrate. - * - * \note This function doesn't check if dev is NULL. - */ -uint32_t uart_cmsdk_get_baudrate(struct uart_cmsdk_dev_t* dev); - -/** - * \brief Sets system clock. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * \param[in] system_clk System clock used by the device. - * - * \return Returns error code as specified in \ref uart_cmsdk_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum uart_cmsdk_error_t uart_cmsdk_set_clock(struct uart_cmsdk_dev_t* dev, - uint32_t system_clk); -/** - * \brief Reads one byte from UART dev. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * \param[in] byte Pointer to byte. - * - * \return Returns error code as specified in \ref uart_cmsdk_error_t - * - * \note For better performance, this function doesn't check if dev and byte - * pointer are NULL, and if the driver is initialized. - */ -enum uart_cmsdk_error_t uart_cmsdk_read(struct uart_cmsdk_dev_t* dev, - uint8_t* byte); - -/** - * \brief Writes a byte to UART dev. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * \param[in] byte Byte to write. - * - * \return Returns error code as specified in \ref uart_cmsdk_error_t - * - * \note For better performance, this function doesn't check if dev is NULL and - * if the driver is initialized to have better performance. - */ -enum uart_cmsdk_error_t uart_cmsdk_write(struct uart_cmsdk_dev_t* dev, - uint8_t byte); - -/** - * \brief Enables TX interrupt. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * - * \return Returns error code as specified in \ref uart_cmsdk_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum uart_cmsdk_error_t uart_cmsdk_irq_tx_enable(struct uart_cmsdk_dev_t* dev); - -/** - * \brief Disables TX interrupt. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * - * \note This function doesn't check if dev is NULL. - */ -void uart_cmsdk_irq_tx_disable(struct uart_cmsdk_dev_t* dev); - -/** - * \brief Verifies if Tx is ready to send more data. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * - * \return 1 if TX is ready, 0 otherwise. - * - * \note This function doesn't check if dev is NULL. - */ -uint32_t uart_cmsdk_tx_ready(struct uart_cmsdk_dev_t* dev); - -/** - * \brief Enables RX interrupt. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * - * \return Returns error code as specified in \ref uart_cmsdk_error_t - * - * \note This function doesn't check if dev is NULL. - */ -enum uart_cmsdk_error_t uart_cmsdk_irq_rx_enable(struct uart_cmsdk_dev_t* dev); - -/** - * \brief Disables RX interrupt - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * - * \note This function doesn't check if dev is NULL. - */ -void uart_cmsdk_irq_rx_disable(struct uart_cmsdk_dev_t* dev); - -/** - * \brief Verifies if Rx has data. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * - * \return 1 if RX has data, 0 otherwise. - * - * \note This function doesn't check if dev is NULL. - */ -uint32_t uart_cmsdk_rx_ready(struct uart_cmsdk_dev_t* dev); - -/** - * \brief Clears UART interrupt. - * - * \param[in] dev UART device struct \ref uart_cmsdk_dev_t - * \param[in] irq IRQ source to clean \ref uart_cmsdk_irq_t - * - * \note This function doesn't check if dev is NULL. - */ -void uart_cmsdk_clear_interrupt(struct uart_cmsdk_dev_t* dev, - enum uart_cmsdk_irq_t irq); - -#ifdef __cplusplus -} -#endif -#endif /* __UART_CMSDK_DRV_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/partition/flash_layout.h b/platform/ext/target/mps2/sse-200_aws/partition/flash_layout.h deleted file mode 100644 index b2f043bc89..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/partition/flash_layout.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2017-2021 Arm Limited. All rights reserved. - * Copyright (c) 2020 Cypress Semiconductor Corporation. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __FLASH_LAYOUT_H__ -#define __FLASH_LAYOUT_H__ - -/* Flash layout on SSE-200_AWS with BL2 (multiple image boot): - * - * 0x0000_0000 BL2 - MCUBoot (0.5 MB) - * 0x0008_0000 Secure image primary slot (0.5 MB) - * 0x0010_0000 Non-secure image primary slot (0.5 MB) - * 0x0018_0000 Secure image secondary slot (0.5 MB) - * 0x0020_0000 Non-secure image secondary slot (0.5 MB) - * 0x0028_0000 Scratch area (0.5 MB) - * 0x0030_0000 Protected Storage Area (20 KB) - * 0x0030_5000 Internal Trusted Storage Area (16 KB) - * 0x0030_9000 NV counters area (4 KB) - * 0x0030_A000 Unused (984 KB) - * - * Flash layout on SSE-200_AWS with BL2 (single image boot): - * - * 0x0000_0000 BL2 - MCUBoot (0.5 MB) - * 0x0008_0000 Primary image area (1 MB): - * 0x0008_0000 Secure image primary - * 0x0010_0000 Non-secure image primary - * 0x0018_0000 Secondary image area (1 MB): - * 0x0018_0000 Secure image secondary - * 0x0020_0000 Non-secure image secondary - * 0x0028_0000 Scratch area (1 MB) - * 0x0038_0000 Protected Storage Area (20 KB) - * 0x0038_5000 Internal Trusted Storage Area (16 KB) - * 0x0038_9000 NV counters area (4 KB) - * 0x0038_A000 Unused (472 KB) - * - * Flash layout on SSE-200_AWS, if BL2 not defined: - * - * 0x0000_0000 Secure image (1 MB) - * 0x0010_0000 Non-secure image (1 MB) - */ - -/* This header file is included from linker scatter file as well, where only a - * limited C constructs are allowed. Therefore it is not possible to include - * here the platform_retarget.h to access flash related defines. To resolve this - * some of the values are redefined here with different names, these are marked - * with comment. - */ - -/* Size of a Secure and of a Non-secure image */ -#define FLASH_S_PARTITION_SIZE (0x80000) /* S partition: 512 KB */ -#define FLASH_NS_PARTITION_SIZE (0x80000) /* NS partition: 512 KB */ -#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \ - FLASH_NS_PARTITION_SIZE) ? \ - FLASH_S_PARTITION_SIZE : \ - FLASH_NS_PARTITION_SIZE) - -/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ -#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB */ -/* Same as FLASH0_SIZE */ -#define FLASH_TOTAL_SIZE (0x00400000) /* 4 MB */ - -/* Flash layout info for BL2 bootloader */ -/* Same as FLASH0_BASE_S */ -#define FLASH_BASE_ADDRESS (0x10000000) - -/* Offset and size definitions of the flash partitions that are handled by the - * bootloader. The image swapping is done between IMAGE_PRIMARY and - * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image - * swapping. - */ -#define FLASH_AREA_BL2_OFFSET (0x0) -#define FLASH_AREA_BL2_SIZE (0x80000) /* 512 KB */ - -#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) -/* Secure + Non-secure image primary slot */ -#define FLASH_AREA_0_ID (1) -#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) -#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + \ - FLASH_NS_PARTITION_SIZE) -/* Secure + Non-secure secondary slot */ -#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1) -#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) -#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE + \ - FLASH_NS_PARTITION_SIZE) -/* Scratch area */ -#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) -#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) -#define FLASH_AREA_SCRATCH_SIZE (FLASH_S_PARTITION_SIZE + \ - FLASH_NS_PARTITION_SIZE) -/* The maximum number of status entries supported by the bootloader. */ -#define MCUBOOT_STATUS_MAX_ENTRIES ((FLASH_S_PARTITION_SIZE + \ - FLASH_NS_PARTITION_SIZE) / \ - FLASH_AREA_SCRATCH_SIZE) -/* Maximum number of image sectors supported by the bootloader. */ -#define MCUBOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \ - FLASH_NS_PARTITION_SIZE) / \ - FLASH_AREA_IMAGE_SECTOR_SIZE) -#elif (MCUBOOT_IMAGE_NUMBER == 2) -/* Secure image primary slot */ -#define FLASH_AREA_0_ID (1) -#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) -#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE) -/* Non-secure image primary slot */ -#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1) -#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) -#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE) -/* Secure image secondary slot */ -#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1) -#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE) -#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE) -/* Non-secure image secondary slot */ -#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1) -#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) -#define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE) -/* Scratch area */ -#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) -#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE) -#define FLASH_AREA_SCRATCH_SIZE (FLASH_MAX_PARTITION_SIZE) -/* The maximum number of status entries supported by the bootloader. */ -#define MCUBOOT_STATUS_MAX_ENTRIES (FLASH_MAX_PARTITION_SIZE / \ - FLASH_AREA_SCRATCH_SIZE) -/* Maximum number of image sectors supported by the bootloader. */ -#define MCUBOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / \ - FLASH_AREA_IMAGE_SECTOR_SIZE) -#else /* MCUBOOT_IMAGE_NUMBER > 2 */ -#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!" -#endif /* MCUBOOT_IMAGE_NUMBER */ - -/* Protected Storage (PS) Service definitions */ -#define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \ - FLASH_AREA_SCRATCH_SIZE) -#define FLASH_PS_AREA_SIZE (0x5000) /* 20 KB */ - -/* Internal Trusted Storage (ITS) Service definitions */ -#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + \ - FLASH_PS_AREA_SIZE) -#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ - -/* NV Counters definitions */ -#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \ - FLASH_ITS_AREA_SIZE) -#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) - -/* Offset and size definition in flash area used by assemble.py */ -#define SECURE_IMAGE_OFFSET (0x0) -#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE - -#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \ - SECURE_IMAGE_MAX_SIZE) -#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE - -/* Flash device name used by BL2 - * Name is defined in flash driver file: Driver_Flash.c - */ -#define FLASH_DEV_NAME Driver_FLASH0 - -/* Protected Storage (PS) Service definitions - * Note: Further documentation of these definitions can be found in the - * TF-M PS Integration Guide. - */ -#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 - -/* In this target the CMSIS driver requires only the offset from the base - * address instead of the full memory address. - */ -/* Base address of dedicated flash area for PS */ -#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET -/* Size of dedicated flash area for PS */ -#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE -#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE -/* Number of physical erase sectors per logical FS block */ -#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) -/* Smallest flash programmable unit in bytes */ -#define TFM_HAL_PS_PROGRAM_UNIT (0x1) - -/* Internal Trusted Storage (ITS) Service definitions - * Note: Further documentation of these definitions can be found in the - * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is - * allocated in the external flash just for development platforms that don't - * have internal flash available. - */ -#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 - -/* In this target the CMSIS driver requires only the offset from the base - * address instead of the full memory address. - */ -/* Base address of dedicated flash area for ITS */ -#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET -/* Size of dedicated flash area for ITS */ -#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE -#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE -/* Number of physical erase sectors per logical FS block */ -#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) -/* Smallest flash programmable unit in bytes */ -#define TFM_HAL_ITS_PROGRAM_UNIT (0x1) - -/* NV Counters definitions */ -#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET -#define TFM_NV_COUNTERS_AREA_SIZE (0x18) /* 24 Bytes */ -#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET -#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE - -/* Use SRAM1 memory to store Code data */ -#define S_ROM_ALIAS_BASE (0x10000000) -#define NS_ROM_ALIAS_BASE (0x00000000) - -/* FIXME: Use SRAM2 memory to store RW data */ -#define S_RAM_ALIAS_BASE (0x38000000) -#define NS_RAM_ALIAS_BASE (0x28000000) - -#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE -#define TOTAL_RAM_SIZE (0x200000) /* 2 MB */ - -#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/partition/region_defs.h b/platform/ext/target/mps2/sse-200_aws/partition/region_defs.h deleted file mode 100644 index 274ae160e1..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/partition/region_defs.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "flash_layout.h" - -#define BL2_HEAP_SIZE (0x0001000) -#define BL2_MSP_STACK_SIZE (0x0001800) - -#define S_HEAP_SIZE (0x0001000) -#define S_MSP_STACK_SIZE_INIT (0x0000400) -#define S_MSP_STACK_SIZE (0x0000800) -#define S_PSP_STACK_SIZE (0x0000800) - -#define NS_HEAP_SIZE (0x0001000) -#define NS_MSP_STACK_SIZE (0x00000A0) -#define NS_PSP_STACK_SIZE (0x0000140) - -/* This size of buffer is big enough to store an attestation - * token produced by initial attestation service - */ -#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE (0x250) - -/* MPC granularity is 128 KB on SSE-200_AWS platform. Alignment - * of partitions is defined in accordance with this constraint. - */ - -#ifdef BL2 -#ifndef LINK_TO_SECONDARY_PARTITION -#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) -#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) -#else -#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) -#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) -#endif /* !LINK_TO_SECONDARY_PARTITION */ -#else -#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) -#endif /* BL2 */ - -#ifndef LINK_TO_SECONDARY_PARTITION -#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \ - + FLASH_S_PARTITION_SIZE) -#else -#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \ - + FLASH_S_PARTITION_SIZE) -#endif /* !LINK_TO_SECONDARY_PARTITION */ - -/* Boot partition structure if MCUBoot is used: - * 0x0_0000 Bootloader header - * 0x0_0400 Image area - * 0x7_0000 Trailer - */ -/* IMAGE_CODE_SIZE is the space available for the software binary image. - * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE - * because we reserve space for the image header and trailer introduced - * by the bootloader. - */ -#ifdef BL2 -#define BL2_HEADER_SIZE (0x400) /* 1 KB */ -#define BL2_TRAILER_SIZE (0x10000) /* 64 KB */ -#else -/* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */ -#define BL2_HEADER_SIZE (0x0) -#define BL2_TRAILER_SIZE (0x10400) -#endif /* BL2 */ - -#define IMAGE_S_CODE_SIZE \ - (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) -#define IMAGE_NS_CODE_SIZE \ - (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) - -#define CMSE_VENEER_REGION_SIZE (0x340) - -/* Alias definitions for secure and non-secure areas*/ -#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) -#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) - -#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) -#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) - -/* Secure regions */ -#define S_IMAGE_PRIMARY_AREA_OFFSET \ - (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) -#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) -#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE) -#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) - -#define S_DATA_START (S_RAM_ALIAS(0x0)) -#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) -#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) - -/* CMSE Veneers region */ -#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1) - -/* Non-secure regions */ -#define NS_IMAGE_PRIMARY_AREA_OFFSET \ - (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) -#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) -#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) -#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) - -#define NS_DATA_START (NS_RAM_ALIAS(TOTAL_RAM_SIZE / 2)) -#define NS_DATA_SIZE (TOTAL_RAM_SIZE / 2) -#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) - -/* NS partition information is used for MPC and SAU configuration */ -#define NS_PARTITION_START \ - (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) -#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) - -/* Secondary partition for new images in case of firmware upgrade */ -#define SECONDARY_PARTITION_START \ - (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) -#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \ - FLASH_NS_PARTITION_SIZE) - -#ifdef BL2 -/* Bootloader regions */ -#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) -#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) -#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) - -#define BL2_DATA_START (S_RAM_ALIAS(0x0)) -#define BL2_DATA_SIZE (TOTAL_RAM_SIZE) -#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) -#endif /* BL2 */ - -/* Shared data area between bootloader and runtime firmware. - * Shared data area is allocated at the beginning of the RAM, it is overlapping - * with TF-M Secure code's MSP stack - */ -#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE -#define BOOT_TFM_SHARED_DATA_SIZE (0x400) -#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ - BOOT_TFM_SHARED_DATA_SIZE - 1) - -#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/plat_test.c b/platform/ext/target/mps2/sse-200_aws/plat_test.c deleted file mode 100644 index 90da929993..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/plat_test.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2019, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "platform_retarget.h" -#include "platform_retarget_dev.h" -#include "timer_cmsdk_drv.h" -#include "tfm_plat_test.h" - -#include "smm_mps2.h" - -#define TIMER_RELOAD_VALUE (16*1024*1024) -#define USERLED_MASK (0x3) -#define MPS2_USERPB0_BASE (0x50302008) -#define MPS2_USERPB0_MASK (0x1) - -void tfm_plat_test_wait_user_button_pressed(void) -{ - volatile uint32_t *p_btn = (volatile uint32_t *) MPS2_USERPB0_BASE; - - /* Wait until user button 0 is pressed */ - while (!(*p_btn & MPS2_USERPB0_MASK)) { - ; - } -} - -void tfm_plat_test_wait_user_button_released(void) -{ - volatile uint32_t *p_btn = (volatile uint32_t *) MPS2_USERPB0_BASE; - - /* Wait until user button 0 is released */ - while ((*p_btn & MPS2_USERPB0_MASK)) { - ; - } -} - -uint32_t tfm_plat_test_get_led_status(void) -{ - struct arm_mps2_fpgaio_t *fpgaio = SEC_MPS2_FPGAIO; - return fpgaio->LED; -} - -void tfm_plat_test_set_led_status(uint32_t status) -{ - struct arm_mps2_fpgaio_t *fpgaio = SEC_MPS2_FPGAIO; - fpgaio->LED = status; -} - -uint32_t tfm_plat_test_get_userled_mask(void) -{ - return USERLED_MASK; -} - -void tfm_plat_test_secure_timer_start(void) -{ - if (!timer_cmsdk_is_initialized(&CMSDK_TIMER0_DEV_S)) { - timer_cmsdk_init(&CMSDK_TIMER0_DEV_S); - } - timer_cmsdk_set_reload_value(&CMSDK_TIMER0_DEV_S, TIMER_RELOAD_VALUE); - timer_cmsdk_enable(&CMSDK_TIMER0_DEV_S); - timer_cmsdk_enable_interrupt(&CMSDK_TIMER0_DEV_S); -} - -void tfm_plat_test_secure_timer_stop(void) -{ - timer_cmsdk_disable(&CMSDK_TIMER0_DEV_S); - timer_cmsdk_disable_interrupt(&CMSDK_TIMER0_DEV_S); - timer_cmsdk_clear_interrupt(&CMSDK_TIMER0_DEV_S); -} - -void tfm_plat_test_non_secure_timer_start(void) -{ - if (!timer_cmsdk_is_initialized(&CMSDK_TIMER1_DEV_NS)) { - timer_cmsdk_init(&CMSDK_TIMER1_DEV_NS); - } - timer_cmsdk_set_reload_value(&CMSDK_TIMER1_DEV_NS, TIMER_RELOAD_VALUE); - timer_cmsdk_enable(&CMSDK_TIMER1_DEV_NS); - timer_cmsdk_enable_interrupt(&CMSDK_TIMER1_DEV_NS); -} - -void tfm_plat_test_non_secure_timer_stop(void) -{ - timer_cmsdk_disable(&CMSDK_TIMER1_DEV_NS); - timer_cmsdk_disable_interrupt(&CMSDK_TIMER1_DEV_NS); - timer_cmsdk_clear_interrupt(&CMSDK_TIMER1_DEV_NS); -} diff --git a/platform/ext/target/mps2/sse-200_aws/preload.cmake b/platform/ext/target/mps2/sse-200_aws/preload.cmake deleted file mode 100644 index 641e6f1067..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/preload.cmake +++ /dev/null @@ -1,15 +0,0 @@ -#------------------------------------------------------------------------------- -# Copyright (c) 2020, Arm Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# -#------------------------------------------------------------------------------- - -# preload.cmake is used to set things that related to the platform that are both -# immutable and global, which is to say they should apply to any kind of project -# that uses this platform. In practise this is normally compiler definitions and -# variables related to hardware. - -# Set architecture and CPU -set(TFM_SYSTEM_PROCESSOR cortex-m33) -set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) diff --git a/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget.h b/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget.h deleted file mode 100644 index c56a1a0698..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_retarget.h - * \brief This file defines all the peripheral base addresses for MPS2/SSE-200 platform. - */ - -#ifndef __ARM_LTD_SSE_200_AWS_RETARGET_H__ -#define __ARM_LTD_SSE_200_AWS_RETARGET_H__ - -#include "platform_regs.h" /* Platform registers */ -#include "platform_irq.h" /* IRQ numbers */ - -/* ======= Defines peripherals memory map addresses ======= */ -/* Non-secure memory map addresses */ -#define CMSDK_TIMER0_BASE_NS 0x40000000 -#define CMSDK_TIMER1_BASE_NS 0x40001000 -#define APB_DUALTIMER_BASE_NS 0x40002000 -#define MHU0_BASE_NS 0x40003000 -#define MHU1_BASE_NS 0x40004000 -#define S32K_TIMER_BASE_NS 0x4002F000 -#define S32K_WATCHDOG_BASE_NS 0x4002E000 -#define APB_WATCHDOG_BASE_NS 0x40081000 -#define UART0_BASE_NS 0x40200000 -#define MPS2_IO_SCC_BASE_NS 0x40300000 -#define MPS2_IO_FPGAIO_BASE_NS 0x40302000 - -/* Secure memory map addresses */ -#define CMSDK_TIMER0_BASE_S 0x50000000 -#define CMSDK_TIMER1_BASE_S 0x50001000 -#define APB_DUALTIMER_BASE_S 0x50002000 -#define MHU0_BASE_S 0x50003000 -#define MHU1_BASE_S 0x50004000 -#define S32K_TIMER_BASE_S 0x5002F000 -#define S32K_WATCHDOG_BASE_S 0x5002E000 -#define APB_WATCHDOG_BASE_S 0x50081000 -#define UART0_BASE_S 0x50200000 -#define MPS2_IO_SCC_BASE_S 0x50300000 -#define MPS2_IO_FPGAIO_BASE_S 0x50302000 -#define MPC_ISRAM0_BASE_S 0x50083000 -#define MPC_ISRAM1_BASE_S 0x50084000 -#define MPC_ISRAM2_BASE_S 0x50085000 -#define MPC_ISRAM3_BASE_S 0x50086000 -#define MPC_SSRAM1_BASE_S 0x58007000 -#define MPC_SSRAM2_BASE_S 0x58008000 -#define MPC_SSRAM3_BASE_S 0x58009000 - -/* SRAM MPC ranges and limits */ -/* Internal memory */ -#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000 -#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF -#define MPC_ISRAM0_RANGE_BASE_S 0x30000000 -#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF - -#define MPC_ISRAM1_RANGE_BASE_NS 0x20008000 -#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF -#define MPC_ISRAM1_RANGE_BASE_S 0x30008000 -#define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF - -#define MPC_ISRAM2_RANGE_BASE_NS 0x20010000 -#define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF -#define MPC_ISRAM2_RANGE_BASE_S 0x30010000 -#define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF - -#define MPC_ISRAM3_RANGE_BASE_NS 0x20018000 -#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF -#define MPC_ISRAM3_RANGE_BASE_S 0x30018000 -#define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF - -/* External SSRAM memory */ -#define MPC_SSRAM1_RANGE_BASE_NS 0x00000000 -#define MPC_SSRAM1_RANGE_LIMIT_NS 0x003FFFFF -#define MPC_SSRAM1_RANGE_BASE_S 0x10000000 -#define MPC_SSRAM1_RANGE_LIMIT_S 0x103FFFFF - -#define MPC_SSRAM2_RANGE_BASE_NS 0x28000000 -#define MPC_SSRAM2_RANGE_LIMIT_NS 0x281FFFFF -#define MPC_SSRAM2_RANGE_BASE_S 0x38000000 -#define MPC_SSRAM2_RANGE_LIMIT_S 0x381FFFFF - -#define MPC_SSRAM3_RANGE_BASE_NS 0x28200000 -#define MPC_SSRAM3_RANGE_LIMIT_NS 0x283FFFFF -#define MPC_SSRAM3_RANGE_BASE_S 0x38200000 -#define MPC_SSRAM3_RANGE_LIMIT_S 0x383FFFFF - -/* Flash memory emulated over external SSRAM memory */ -#define FLASH0_BASE_S 0x10000000 -#define FLASH0_BASE_NS 0x00000000 -#define FLASH0_SIZE 0x00400000 /* 4 MB */ -#define FLASH0_SECTOR_SIZE 0x00001000 /* 4 kB */ -#define FLASH0_PAGE_SIZE 0x00001000 /* 4 kB */ -#define FLASH0_PROGRAM_UNIT 0x1 /* Minimum write size */ - -#endif /* __ARM_LTD_SSE_200_AWS_RETARGET_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget_dev.c b/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget_dev.c deleted file mode 100644 index f2804928c1..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget_dev.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) 2016-2021 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_retarget_dev.c - * \brief This file defines exports the structures based on the peripheral - * definitions from device_cfg.h. - * This retarget file is meant to be used as a helper for baremetal - * applications and/or as an example of how to configure the generic - * driver structures. - */ - -#include "platform_retarget_dev.h" -#include "platform_retarget.h" -#include "system_cmsdk_sse-200_aws.h" -#include "tfm_plat_defs.h" - -/* ARM UART driver structures */ -#ifdef UART0_CMSDK_S -static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_S = { - .base = UART0_BASE_S, - .default_baudrate = DEFAULT_UART_BAUDRATE}; -static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_S = { - .state = 0, - .system_clk = 0, - .baudrate = 0}; -struct uart_cmsdk_dev_t UART0_CMSDK_DEV_S = {&(UART0_CMSDK_DEV_CFG_S), - &(UART0_CMSDK_DEV_DATA_S)}; -#endif -#ifdef UART0_CMSDK_NS -static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_NS = { - .base = UART0_BASE_NS, - .default_baudrate = DEFAULT_UART_BAUDRATE}; -static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_NS = { - .state = 0, - .system_clk = 0, - .baudrate = 0}; -struct uart_cmsdk_dev_t UART0_CMSDK_DEV_NS = {&(UART0_CMSDK_DEV_CFG_NS), - &(UART0_CMSDK_DEV_DATA_NS)}; -#endif - -/* ARM PPC SIE 200 driver structures */ -#ifdef AHB_PPC0_S -static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t AHB_PPC0_DEV_S = { - &AHB_PPC0_DEV_CFG_S, &AHB_PPC0_DEV_DATA_S }; -#endif - -#ifdef AHB_PPCEXP0_S -static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = { - &AHB_PPCEXP0_DEV_CFG_S, &AHB_PPCEXP0_DEV_DATA_S }; -#endif - -#ifdef AHB_PPCEXP1_S -static struct ppc_sse200_dev_cfg_t AHB_PPCEXP1_DEV_CFG_S = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t AHB_PPCEXP1_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sie200_dev_t AHB_PPCEXP1_DEV_S = { - &AHB_PPCEXP1_DEV_CFG_S, &AHB_PPCEXP1_DEV_DATA_S }; -#endif - -#ifdef AHB_PPCEXP2_S -static struct ppc_sse200_dev_cfg_t AHB_PPCEXP2_DEV_CFG_S = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t AHB_PPCEXP2_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S = { - &AHB_PPCEXP2_DEV_CFG_S, &AHB_PPCEXP2_DEV_DATA_S }; -#endif - -#ifdef AHB_PPCEXP3_S -static struct ppc_sse200_dev_cfg_t AHB_PPCEXP3_DEV_CFG_S = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t AHB_PPCEXP3_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S = { - &AHB_PPCEXP3_DEV_CFG_S, &AHB_PPCEXP3_DEV_DATA_S }; -#endif - -#ifdef APB_PPC0_S -static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t APB_PPC0_DEV_S = { - &APB_PPC0_DEV_CFG_S, &APB_PPC0_DEV_DATA_S }; -#endif - -#ifdef APB_PPC1_S -static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t APB_PPC1_DEV_S = { - &APB_PPC1_DEV_CFG_S, &APB_PPC1_DEV_DATA_S}; -#endif - -#ifdef APB_PPCEXP0_S -static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = { - &APB_PPCEXP0_DEV_CFG_S, &APB_PPCEXP0_DEV_DATA_S }; -#endif - -#ifdef APB_PPCEXP1_S -static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = { - &APB_PPCEXP1_DEV_CFG, &APB_PPCEXP1_DEV_DATA_S }; -#endif - -#ifdef APB_PPCEXP2_S -static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = { - &APB_PPCEXP2_DEV_CFG, &APB_PPCEXP2_DEV_DATA_S }; -#endif - -#ifdef APB_PPCEXP3_S -static struct ppc_sse200_dev_cfg_t APB_PPCEXP3_DEV_CFG = { - .spctrl_base = CMSDK_SPCTRL_BASE_S, - .nspctrl_base = CMSDK_NSPCTRL_BASE_NS }; -static struct ppc_sse200_dev_data_t APB_PPCEXP3_DEV_DATA_S = { - .p_ns_ppc = 0, - .p_sp_ppc = 0, - .p_nsp_ppc = 0, - .int_bit_mask = 0, - .state = 0 }; -struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S = { - &APB_PPCEXP3_DEV_CFG, &APB_PPCEXP3_DEV_DATA_S }; -#endif - -/* CMSDK Timer driver structures */ -#ifdef CMSDK_TIMER0_S -static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S - TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_IRQ_TEST_1", "APP-ROT") - = {.base = CMSDK_TIMER0_BASE_S}; -static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S - TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_IRQ_TEST_1", "APP-ROT") - = {.is_initialized = 0}; - -struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S - TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_IRQ_TEST_1", "APP-ROT") - = {&(CMSDK_TIMER0_DEV_CFG_S), &(CMSDK_TIMER0_DEV_DATA_S)}; -#endif -#ifdef CMSDK_TIMER0_NS -static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = { - .base = CMSDK_TIMER0_BASE_NS}; -static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = { - .is_initialized = 0}; -struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS), - &(CMSDK_TIMER0_DEV_DATA_NS)}; -#endif - -#ifdef CMSDK_TIMER1_S -static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = { - .base = CMSDK_TIMER1_BASE_S}; -static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = { - .is_initialized = 0}; -struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S), - &(CMSDK_TIMER1_DEV_DATA_S)}; -#endif -#ifdef CMSDK_TIMER1_NS -static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = { - .base = CMSDK_TIMER1_BASE_NS}; -static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = { - .is_initialized = 0}; -struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS), - &(CMSDK_TIMER1_DEV_DATA_NS)}; -#endif - -/* ARM MPC SSE 200 driver structures */ -#ifdef MPC_ISRAM0_S -static const struct mpc_sie_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = { - .base = MPC_ISRAM0_BASE_S}; -static struct mpc_sie_dev_data_t MPC_ISRAM0_DEV_DATA_S = { - .range_list = 0, - .nbr_of_ranges = 0, - .is_initialized = false }; -struct mpc_sie_dev_t MPC_ISRAM0_DEV_S = { - &(MPC_ISRAM0_DEV_CFG_S), - &(MPC_ISRAM0_DEV_DATA_S)}; -#endif - -#ifdef MPC_ISRAM1_S -static const struct mpc_sie_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = { - .base = MPC_ISRAM1_BASE_S}; -static struct mpc_sie_dev_data_t MPC_ISRAM1_DEV_DATA_S = { - .range_list = 0, - .nbr_of_ranges = 0, - .is_initialized = false }; -struct mpc_sie_dev_t MPC_ISRAM1_DEV_S = { - &(MPC_ISRAM1_DEV_CFG_S), - &(MPC_ISRAM1_DEV_DATA_S)}; -#endif - -#ifdef MPC_ISRAM2_S -static const struct mpc_sie_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = { - .base = MPC_ISRAM2_BASE_S}; -static struct mpc_sie_dev_data_t MPC_ISRAM2_DEV_DATA_S = { - .range_list = 0, - .nbr_of_ranges = 0, - .is_initialized = false }; -struct mpc_sie_dev_t MPC_ISRAM2_DEV_S = { - &(MPC_ISRAM2_DEV_CFG_S), - &(MPC_ISRAM2_DEV_DATA_S)}; -#endif - -#ifdef MPC_ISRAM3_S -static const struct mpc_sie_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = { - .base = MPC_ISRAM3_BASE_S}; -static struct mpc_sie_dev_data_t MPC_ISRAM3_DEV_DATA_S = { - .range_list = 0, - .nbr_of_ranges = 0, - .is_initialized = false }; -struct mpc_sie_dev_t MPC_ISRAM3_DEV_S = { - &(MPC_ISRAM3_DEV_CFG_S), - &(MPC_ISRAM3_DEV_DATA_S)}; -#endif - -#ifdef MPC_SSRAM1_S -static const struct mpc_sie_dev_cfg_t MPC_SSRAM1_DEV_CFG_S = { - .base = MPC_SSRAM1_BASE_S}; -static struct mpc_sie_dev_data_t MPC_SSRAM1_DEV_DATA_S = { - .range_list = 0, - .nbr_of_ranges = 0, - .is_initialized = false }; -struct mpc_sie_dev_t MPC_SSRAM1_DEV_S = { - &(MPC_SSRAM1_DEV_CFG_S), - &(MPC_SSRAM1_DEV_DATA_S)}; -#endif - -#ifdef MPC_SSRAM2_S -static const struct mpc_sie_dev_cfg_t MPC_SSRAM2_DEV_CFG_S = { - .base = MPC_SSRAM2_BASE_S}; -static struct mpc_sie_dev_data_t MPC_SSRAM2_DEV_DATA_S = { - .range_list = 0, - .nbr_of_ranges = 0, - .is_initialized = false }; -struct mpc_sie_dev_t MPC_SSRAM2_DEV_S = { - &(MPC_SSRAM2_DEV_CFG_S), - &(MPC_SSRAM2_DEV_DATA_S)}; -#endif - -#ifdef MPC_SSRAM3_S -static const struct mpc_sie_dev_cfg_t MPC_SSRAM3_DEV_CFG_S = { - .base = MPC_SSRAM3_BASE_S}; -static struct mpc_sie_dev_data_t MPC_SSRAM3_DEV_DATA_S = { - .range_list = 0, - .nbr_of_ranges = 0, - .is_initialized = false }; -struct mpc_sie_dev_t MPC_SSRAM3_DEV_S = { - &(MPC_SSRAM3_DEV_CFG_S), - &(MPC_SSRAM3_DEV_DATA_S)}; -#endif diff --git a/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget_dev.h b/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget_dev.h deleted file mode 100644 index 95f94f59ad..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/retarget/platform_retarget_dev.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2016-2019 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_retarget_dev.h - * \brief The structure definitions in this file are exported based on the peripheral - * definitions from device_cfg.h. - * This retarget file is meant to be used as a helper for baremetal - * applications and/or as an example of how to configure the generic - * driver structures. - */ - -#ifndef __ARM_LTD_SSE_200_AWS_RETARGET_DEV_H__ -#define __ARM_LTD_SSE_200_AWS_RETARGET_DEV_H__ - -#include "device_cfg.h" - -/* ======= Includes generic driver headers ======= */ -#include "mpc_sie_drv.h" -#include "ppc_sse200_drv.h" -#include "uart_cmsdk_drv.h" -#include "timer_cmsdk/timer_cmsdk_drv.h" - -/* ======= Defines peripheral configuration structures ======= */ -/* ARM UART driver structures */ -#ifdef UART0_CMSDK_S -extern struct uart_cmsdk_dev_t UART0_CMSDK_DEV_S; -#endif -#ifdef UART0_CMSDK_NS -extern struct uart_cmsdk_dev_t UART0_CMSDK_DEV_NS; -#endif - -/* ARM PPC driver structures */ -#ifdef AHB_PPC0_S -extern struct ppc_sse200_dev_t AHB_PPC0_DEV_S; -#endif - -#ifdef AHB_PPCEXP0_S -extern struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S; -#endif - -#ifdef AHB_PPCEXP1_S -extern struct ppc_sie200_dev_t AHB_PPCEXP1_DEV_S; -#endif - -#ifdef AHB_PPCEXP2_S -extern struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S; -#endif - -#ifdef AHB_PPCEXP3_S -extern struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S; -#endif - -#ifdef APB_PPC0_S -extern struct ppc_sse200_dev_t APB_PPC0_DEV_S; -#endif - -#ifdef APB_PPC1_S -extern struct ppc_sse200_dev_t APB_PPC1_DEV_S; -#endif - -#ifdef APB_PPCEXP0_S -extern struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S; -#endif - -#ifdef APB_PPCEXP1_S -extern struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S; -#endif - -#ifdef APB_PPCEXP2_S -extern struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S; -#endif - -#ifdef APB_PPCEXP3_S -extern struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S; -#endif - -/* CMSDK Timer driver structures */ -#ifdef CMSDK_TIMER0_S -extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S; -#endif -#ifdef CMSDK_TIMER0_NS -extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS; -#endif - -#ifdef CMSDK_TIMER1_S -extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S; -#endif -#ifdef CMSDK_TIMER1_NS -extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS; -#endif - -/* ARM MPC SSE 200 driver structures */ -#ifdef MPC_ISRAM0_S -extern struct mpc_sie_dev_t MPC_ISRAM0_DEV_S; -#endif - -#ifdef MPC_ISRAM1_S -extern struct mpc_sie_dev_t MPC_ISRAM1_DEV_S; -#endif - -#ifdef MPC_ISRAM2_S -extern struct mpc_sie_dev_t MPC_ISRAM2_DEV_S; -#endif - -#ifdef MPC_ISRAM3_S -extern struct mpc_sie_dev_t MPC_ISRAM3_DEV_S; -#endif - -#ifdef MPC_SSRAM1_S -extern struct mpc_sie_dev_t MPC_SSRAM1_DEV_S; -#endif - -#ifdef MPC_SSRAM2_S -extern struct mpc_sie_dev_t MPC_SSRAM2_DEV_S; -#endif - -#ifdef MPC_SSRAM3_S -extern struct mpc_sie_dev_t MPC_SSRAM3_DEV_S; -#endif - -#endif /* __ARM_LTD_SSE_200_AWS_RETARGET_DEV_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/services/src/tfm_platform_system.c b/platform/ext/target/mps2/sse-200_aws/services/src/tfm_platform_system.c deleted file mode 100644 index 44fafbccd1..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/services/src/tfm_platform_system.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018-2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "tfm_platform_system.h" -#include "cmsis.h" - -void tfm_platform_hal_system_reset(void) -{ - /* Reset the system */ - NVIC_SystemReset(); -} - -enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, - psa_invec *in_vec, - psa_outvec *out_vec) -{ - (void)request; - (void)in_vec; - (void)out_vec; - - /* Not needed for this platform */ - return TFM_PLATFORM_ERR_NOT_SUPPORTED; -} - diff --git a/platform/ext/target/mps2/sse-200_aws/spm_hal.c b/platform/ext/target/mps2/sse-200_aws/spm_hal.c deleted file mode 100644 index d69a879171..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/spm_hal.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2018-2021, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include <stdio.h> -#include "cmsis.h" -#include "tfm_spm_hal.h" -#include "tfm_platform_core_api.h" -#include "target_cfg.h" -#include "Driver_MPC.h" -#include "mpu_armv8m_drv.h" -#include "region_defs.h" -#include "utilities.h" -#include "region.h" -#include "tfm_hal_platform.h" -#include "interface/include/log/tfm_log.h" - - -/* Import MPC driver */ -extern ARM_DRIVER_MPC Driver_SSRAM1_MPC; - -/* Get address of memory regions to configure MPU */ -extern const struct memory_region_limits memory_regions; - -struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE }; - -enum tfm_plat_err_t tfm_spm_hal_configure_default_isolation( - uint32_t partition_idx, - const struct platform_data_t *platform_data) -{ - bool privileged = tfm_is_partition_privileged(partition_idx); - - if (!platform_data) { - return TFM_PLAT_ERR_INVALID_INPUT; - } - - if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) { - ppc_configure_to_secure(platform_data->periph_ppc_bank, - platform_data->periph_ppc_loc); - if (privileged) { - ppc_clr_secure_unpriv(platform_data->periph_ppc_bank, - platform_data->periph_ppc_loc); - } else { - ppc_en_secure_unpriv(platform_data->periph_ppc_bank, - platform_data->periph_ppc_loc); - } - } - return TFM_PLAT_ERR_SUCCESS; -} - -void MPC_Handler(void) -{ - /* Clear MPC interrupt flag and pending MPC IRQ */ - Driver_SSRAM1_MPC.ClearInterrupt(); - NVIC_ClearPendingIRQ(MPC_IRQn); - - /* Print fault message and block execution */ - ERROR_MSG("Oops... MPC fault!!!"); - - /* Inform TF-M core that isolation boundary has been violated */ - tfm_access_violation_handler(); -} - -void PPC_Handler(void) -{ - /* - * Due to an issue on the FVP, the PPC fault doesn't trigger a - * PPC IRQ which is handled by the PPC_handler. - * In the FVP execution, this code is not execute. - */ - - /* Clear PPC interrupt flag and pending PPC IRQ */ - ppc_clear_irq(); - NVIC_ClearPendingIRQ(PPC_IRQn); - - /* Print fault message*/ - ERROR_MSG("Oops... PPC fault!!!"); - - /* Inform TF-M core that isolation boundary has been violated */ - tfm_access_violation_handler(); -} - -uint32_t tfm_spm_hal_get_ns_VTOR(void) -{ - return memory_regions.non_secure_code_start; -} - -uint32_t tfm_spm_hal_get_ns_MSP(void) -{ - return *((uint32_t *)memory_regions.non_secure_code_start); -} - -uint32_t tfm_spm_hal_get_ns_entry_point(void) -{ - return *((uint32_t *)(memory_regions.non_secure_code_start+ 4)); -} - -enum tfm_plat_err_t tfm_spm_hal_set_secure_irq_priority(IRQn_Type irq_line, - uint32_t priority) -{ - uint32_t quantized_priority = priority >> (8U - __NVIC_PRIO_BITS); - NVIC_SetPriority(irq_line, quantized_priority); - return TFM_PLAT_ERR_SUCCESS; -} - -void tfm_spm_hal_clear_pending_irq(IRQn_Type irq_line) -{ - NVIC_ClearPendingIRQ(irq_line); -} - -void tfm_spm_hal_enable_irq(IRQn_Type irq_line) -{ - NVIC_EnableIRQ(irq_line); -} - -void tfm_spm_hal_disable_irq(IRQn_Type irq_line) -{ - NVIC_DisableIRQ(irq_line); -} - -enum irq_target_state_t tfm_spm_hal_set_irq_target_state( - IRQn_Type irq_line, - enum irq_target_state_t target_state) -{ - uint32_t result; - - if (target_state == TFM_IRQ_TARGET_STATE_SECURE) { - result = NVIC_ClearTargetState(irq_line); - } else { - result = NVIC_SetTargetState(irq_line); - } - - if (result) { - return TFM_IRQ_TARGET_STATE_NON_SECURE; - } else { - return TFM_IRQ_TARGET_STATE_SECURE; - } -} - -enum tfm_plat_err_t tfm_spm_hal_enable_fault_handlers(void) -{ - return enable_fault_handlers(); -} - -enum tfm_plat_err_t tfm_spm_hal_system_reset_cfg(void) -{ - return system_reset_cfg(); -} - -enum tfm_plat_err_t tfm_spm_hal_init_debug(void) -{ - return init_debug(); -} - -enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_target_state_cfg(void) -{ - return nvic_interrupt_target_state_cfg(); -} - -enum tfm_plat_err_t tfm_spm_hal_nvic_interrupt_enable(void) -{ - return nvic_interrupt_enable(); -} - -enum tfm_hal_status_t tfm_hal_platform_init(void) -{ - __enable_irq(); - stdio_init(); - LOG_MSG("\033[1;34m[Platform] sse-200_aws is marked for \ - deprecation!\033[0m\r\n"); - - return TFM_HAL_SUCCESS; -} diff --git a/platform/ext/target/mps2/sse-200_aws/target_cfg.c b/platform/ext/target/mps2/sse-200_aws/target_cfg.c deleted file mode 100644 index 880aeeb89c..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/target_cfg.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * Copyright (c) 2017-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis.h" -#include "target_cfg.h" -#include "Driver_MPC.h" -#include "platform_retarget_dev.h" -#include "region_defs.h" -#include "tfm_plat_defs.h" -#include "region.h" - -#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) - -/* The section names come from the scatter file */ -REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base); -REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base); -REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit); -#ifdef BL2 -REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base); -#endif /* BL2 */ - -const struct memory_region_limits memory_regions = { - .non_secure_code_start = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + - BL2_HEADER_SIZE, - - .non_secure_partition_base = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base), - - .non_secure_partition_limit = - (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + - NS_PARTITION_SIZE - 1, - - .veneer_base = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base), - .veneer_limit = (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit), - -#ifdef BL2 - .secondary_partition_base = - (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base), - - .secondary_partition_limit = - (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) + - SECONDARY_PARTITION_SIZE - 1, -#endif /* BL2 */ -}; - -/* Allows software, via SAU, to define the code region as a NSC */ -#define NSCCFG_CODENSC 1 - -/* Import MPC driver */ -extern ARM_DRIVER_MPC Driver_SSRAM1_MPC, Driver_SSRAM2_MPC; - -/* Define Peripherals NS address range for the platform */ -#define PERIPHERALS_BASE_NS_START (0x40000000) -#define PERIPHERALS_BASE_NS_END (0x4FFFFFFF) - -/* Enable system reset request for CPU 0 */ -#define ENABLE_CPU0_SYSTEM_RESET_REQUEST (1U << 4U) - -/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field, - * otherwise the processor ignores the write. - */ -#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)) - -/* Debug configuration flags */ -#define SPNIDEN_SEL_STATUS (0x01u << 7) -#define SPNIDEN_STATUS (0x01u << 6) -#define SPIDEN_SEL_STATUS (0x01u << 5) -#define SPIDEN_STATUS (0x01u << 4) -#define NIDEN_SEL_STATUS (0x01u << 3) -#define NIDEN_STATUS (0x01u << 2) -#define DBGEN_SEL_STATUS (0x01u << 1) -#define DBGEN_STATUS (0x01u << 0) - -#define All_SEL_STATUS (SPNIDEN_SEL_STATUS | SPIDEN_SEL_STATUS | \ - NIDEN_SEL_STATUS | DBGEN_SEL_STATUS) - -struct platform_data_t tfm_peripheral_std_uart = { - UART0_BASE_NS, - UART0_BASE_NS + 0xFFF, - PPC_SP_DO_NOT_CONFIGURE, - -1 -}; - -struct platform_data_t tfm_peripheral_fpga_io = { - MPS2_IO_FPGAIO_BASE_S, - MPS2_IO_FPGAIO_BASE_S + 0xFFF, - PPC_SP_APB_PPC_EXP2, - CMSDK_FPGA_IO_PPC_POS -}; - -struct platform_data_t tfm_peripheral_timer0 = { - CMSDK_TIMER0_BASE_S, - CMSDK_TIMER1_BASE_S - 1, - PPC_SP_APB_PPC0, - CMSDK_TIMER0_APB_PPC_POS -}; - -enum tfm_plat_err_t enable_fault_handlers(void) -{ - /* Explicitly set secure fault priority to the highest */ - NVIC_SetPriority(SecureFault_IRQn, 0); - - /* Enables BUS, MEM, USG and Secure faults */ - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk - | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk - | SCB_SHCSR_SECUREFAULTENA_Msk; - return TFM_PLAT_ERR_SUCCESS; -} - -enum tfm_plat_err_t system_reset_cfg(void) -{ - struct sysctrl_t *sysctrl = (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S; - uint32_t reg_value = SCB->AIRCR; - - /* Enable system reset request for CPU 0, to be triggered via - * NVIC_SystemReset function. - */ - sysctrl->resetmask |= ENABLE_CPU0_SYSTEM_RESET_REQUEST; - - /* Clear SCB_AIRCR_VECTKEY value */ - reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk); - - /* Enable system reset request only to the secure world */ - reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk); - - SCB->AIRCR = reg_value; - - return TFM_PLAT_ERR_SUCCESS; -} - -enum tfm_plat_err_t init_debug(void) -{ - volatile struct sysctrl_t *sys_ctrl = - (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S; - -#if defined(DAUTH_NONE) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set all the debug enable bits to 0 */ - sys_ctrl->secdbgclr = - DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS; -#elif defined(DAUTH_NS_ONLY) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set the debug enable bits to 1 for NS, and 0 for S mode */ - sys_ctrl->secdbgset = DBGEN_STATUS | NIDEN_STATUS; - sys_ctrl->secdbgclr = SPIDEN_STATUS | SPNIDEN_STATUS; -#elif defined(DAUTH_FULL) - /* Set all the debug enable selector bits to 1 */ - sys_ctrl->secdbgset = All_SEL_STATUS; - /* Set all the debug enable bits to 1 */ - sys_ctrl->secdbgset = - DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS; -#else - -#if !defined(DAUTH_CHIP_DEFAULT) -#error "No debug authentication setting is provided." -#endif - - /* Set all the debug enable selector bits to 0 */ - sys_ctrl->secdbgclr = All_SEL_STATUS; - - /* No need to set any enable bits because the value depends on - * input signals. - */ -#endif - return TFM_PLAT_ERR_SUCCESS; -} - -/*----------------- NVIC interrupt target state to NS configuration ----------*/ -enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) -{ - /* Target every interrupt to NS; unimplemented interrupts will be WI */ - for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) { - NVIC->ITNS[i] = 0xFFFFFFFF; - } - - /* Make sure that MPC and PPC are targeted to S state */ - NVIC_ClearTargetState(MPC_IRQn); - NVIC_ClearTargetState(PPC_IRQn); - - return TFM_PLAT_ERR_SUCCESS; -} - -/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ -enum tfm_plat_err_t nvic_interrupt_enable(void) -{ - struct spctrl_def* spctrl = CMSDK_SPCTRL; - int32_t ret = ARM_DRIVER_OK; - - /* MPC interrupt enabling */ - ret = Driver_SSRAM1_MPC.EnableInterrupt(); - if (ret != ARM_DRIVER_OK) { - return TFM_PLAT_ERR_SYSTEM_ERR; - } - ret = Driver_SSRAM2_MPC.EnableInterrupt(); - if (ret != ARM_DRIVER_OK) { - return TFM_PLAT_ERR_SYSTEM_ERR; - } - NVIC_EnableIRQ(MPC_IRQn); - - /* PPC interrupt enabling */ - /* Clear pending PPC interrupts */ - /* In the PPC configuration function, we have used the Non-Secure - * Privilege Control Block to grant unprivilged NS access to some - * peripherals used by NS. That triggers a PPC0 exception as that - * register is meant for NS privileged access only. Clear it here - */ - spctrl->secppcintclr = CMSDK_APB_PPC0_INT_POS_MASK; - - /* Enable PPC interrupts for APB PPC */ - spctrl->secppcinten |= CMSDK_APB_PPC0_INT_POS_MASK | - CMSDK_APB_PPC1_INT_POS_MASK | - CMSDK_APB_PPCEXP0_INT_POS_MASK | - CMSDK_APB_PPCEXP1_INT_POS_MASK | - CMSDK_APB_PPCEXP2_INT_POS_MASK | - CMSDK_APB_PPCEXP3_INT_POS_MASK; - - NVIC_EnableIRQ(PPC_IRQn); - - return TFM_PLAT_ERR_SUCCESS; -} - -/*------------------- SAU/IDAU configuration functions -----------------------*/ -struct sau_cfg_t { - uint32_t RBAR; - uint32_t RLAR; - bool nsc; -}; - -const struct sau_cfg_t sau_cfg[] = { - { - ((uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base)), - ((uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + - NS_PARTITION_SIZE - 1), - false, - }, - { - NS_DATA_START, - NS_DATA_LIMIT, - false, - }, - { - (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base), - (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit), - true, - }, - { - PERIPHERALS_BASE_NS_START, - PERIPHERALS_BASE_NS_END, - false, - }, -#ifdef BL2 - { - (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base), - (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) + - SECONDARY_PARTITION_SIZE - 1, - false, - }, -#endif -}; - -void sau_and_idau_cfg(void) -{ - struct spctrl_def *spctrl = CMSDK_SPCTRL; - uint32_t i; - - /* Enables SAU */ - TZ_SAU_Enable(); - - for (i = 0; i < ARRAY_SIZE(sau_cfg); i++) { - SAU->RNR = i; - SAU->RBAR = sau_cfg[i].RBAR & SAU_RBAR_BADDR_Msk; - SAU->RLAR = (sau_cfg[i].RLAR & SAU_RLAR_LADDR_Msk) | - (sau_cfg[i].nsc ? SAU_RLAR_NSC_Msk : 0U) | - SAU_RLAR_ENABLE_Msk; - } - - /* Allows SAU to define the code region as a NSC */ - spctrl->nsccfg |= NSCCFG_CODENSC; -} - -/*------------------- Memory configuration functions -------------------------*/ - -int32_t mpc_init_cfg(void) -{ - int32_t ret = ARM_DRIVER_OK; - - ret = Driver_SSRAM1_MPC.Initialize(); - if (ret != ARM_DRIVER_OK) { - return ret; - } - - ret = Driver_SSRAM1_MPC.ConfigRegion( - memory_regions.non_secure_partition_base, - memory_regions.non_secure_partition_limit, - ARM_MPC_ATTR_NONSECURE); - if (ret != ARM_DRIVER_OK) { - return ret; - } - -#ifdef BL2 - /* Secondary image region */ - ret = Driver_SSRAM1_MPC.ConfigRegion(memory_regions.secondary_partition_base, - memory_regions.secondary_partition_limit, - ARM_MPC_ATTR_NONSECURE); - if (ret != ARM_DRIVER_OK) { - return ret; - } -#endif /* BL2 */ - - ret = Driver_SSRAM2_MPC.Initialize(); - if (ret != ARM_DRIVER_OK) { - return ret; - } - - ret = Driver_SSRAM2_MPC.ConfigRegion(NS_DATA_START, NS_DATA_LIMIT, - ARM_MPC_ATTR_NONSECURE); - if (ret != ARM_DRIVER_OK) { - return ret; - } - - /* Lock down the MPC configuration */ - ret = Driver_SSRAM1_MPC.LockDown(); - if (ret != ARM_DRIVER_OK) { - return ret; - } - - ret = Driver_SSRAM2_MPC.LockDown(); - if (ret != ARM_DRIVER_OK) { - return ret; - } - - /* Add barriers to assure the MPC configuration is done before continue - * the execution. - */ - __DSB(); - __ISB(); - - return ARM_DRIVER_OK; -} - -/*---------------------- PPC configuration functions -------------------------*/ - -void ppc_init_cfg(void) -{ - struct spctrl_def* spctrl = CMSDK_SPCTRL; - struct nspctrl_def* nspctrl = CMSDK_NSPCTRL; - - /* Grant non-secure access to peripherals in the PPC0 - * (timer0 and 1, dualtimer, watchdog, mhu 0 and 1) - */ - spctrl->apbnsppc0 |= (1U << CMSDK_TIMER0_APB_PPC_POS) | - (1U << CMSDK_TIMER1_APB_PPC_POS) | - (1U << CMSDK_DTIMER_APB_PPC_POS)| - (1U << CMSDK_MHU0_APB_PPC_POS) | - (1U << CMSDK_MHU1_APB_PPC_POS); - /* Grant non-secure access to S32K Timer in PPC1*/ - spctrl->apbnsppc1 |= (1U << CMSDK_S32K_TIMER_PPC_POS); - /* Grant non-secure access for APB peripherals on EXP1 */ - spctrl->apbnsppcexp1 |= (1U << CMSDK_UART0_APB_PPC_POS); - /* Grant non-secure access for APB peripherals on EXP2 */ - spctrl->apbnsppcexp2 |= (1U << CMSDK_FPGA_SCC_PPC_POS) | - (1U << CMSDK_FPGA_IO_PPC_POS); - - /* Grant non-secure access to all peripherals on AHB EXP: - * Make sure that all possible peripherals are enabled by default - */ - - spctrl->ahbnsppcexp1 |= (1U << CMSDK_DMA0_PPC_POS) | - (1U << CMSDK_DMA1_PPC_POS) | - (1U << CMSDK_DMA2_PPC_POS) | - (1U << CMSDK_DMA3_PPC_POS); - - /* in NS, grant un-privileged for UART0 */ - nspctrl->apbnspppcexp1 |= (1U << CMSDK_UART0_APB_PPC_POS); - - /* in NS, grant un-privileged access for LEDs */ - nspctrl->apbnspppcexp2 |= (1U << CMSDK_FPGA_SCC_PPC_POS) | - (1U << CMSDK_FPGA_IO_PPC_POS); - - /* Configure the response to a security violation as a - * bus error instead of RAZ/WI - */ - spctrl->secrespcfg |= 1U; -} - -void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t pos) -{ - /* Setting NS flag for peripheral to enable NS access */ - struct spctrl_def* spctrl = CMSDK_SPCTRL; - ((uint32_t*)&(spctrl->ahbnsppc0))[bank] |= (1U << pos); -} - -void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t pos) -{ - /* Clear NS flag for peripheral to prevent NS access */ - struct spctrl_def* spctrl = CMSDK_SPCTRL; - ((uint32_t*)&(spctrl->ahbnsppc0))[bank] &= ~(1U << pos); -} - -void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos) -{ - struct spctrl_def* spctrl = CMSDK_SPCTRL; - ((uint32_t*)&(spctrl->ahbspppc0))[bank] |= (1U << pos); -} - -void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos) -{ - struct spctrl_def* spctrl = CMSDK_SPCTRL; - ((uint32_t*)&(spctrl->ahbspppc0))[bank] &= ~(1U << pos); -} - -void ppc_clear_irq(void) -{ - struct spctrl_def* spctrl = CMSDK_SPCTRL; - /* Clear APB PPC EXP2 IRQ */ - spctrl->secppcintclr = CMSDK_APB_PPCEXP2_INT_POS_MASK; -} diff --git a/platform/ext/target/mps2/sse-200_aws/target_cfg.h b/platform/ext/target/mps2/sse-200_aws/target_cfg.h deleted file mode 100644 index 4498728328..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/target_cfg.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2017-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __TARGET_CFG_H__ -#define __TARGET_CFG_H__ - -#include "uart_stdout.h" -#include "tfm_peripherals_def.h" -#include "tfm_plat_defs.h" -#include "uart_cmsdk_drv.h" - -#define TFM_DRIVER_STDIO Driver_USART0 -#define NS_DRIVER_STDIO Driver_USART0 - -/** - * \brief Defines the word offsets of Slave Peripheral Protection Controller - * Registers - */ -enum ppc_bank_e -{ - PPC_SP_DO_NOT_CONFIGURE = -1, - PPC_SP_AHB_PPC0 = 0, - PPC_SP_RES0, - PPC_SP_RES1, - PPC_SP_RES2, - PPC_SP_AHB_PPC_EXP0, - PPC_SP_AHB_PPC_EXP1, - PPC_SP_AHB_PPC_EXP2, - PPC_SP_AHB_PPC_EXP3, - PPC_SP_APB_PPC0, - PPC_SP_APB_PPC1, - PPC_SP_RES3, - PPC_SP_RES4, - PPC_SP_APB_PPC_EXP0, - PPC_SP_APB_PPC_EXP1, - PPC_SP_APB_PPC_EXP2, - PPC_SP_APB_PPC_EXP3, -}; - -/** - * \brief Store the addresses of memory regions - */ -struct memory_region_limits { - uint32_t non_secure_code_start; - uint32_t non_secure_partition_base; - uint32_t non_secure_partition_limit; - uint32_t veneer_base; - uint32_t veneer_limit; -#ifdef BL2 - uint32_t secondary_partition_base; - uint32_t secondary_partition_limit; -#endif /* BL2 */ -}; - -/** - * \brief Holds the data necessary to do isolation for a specific peripheral. - */ -struct platform_data_t -{ - uint32_t periph_start; - uint32_t periph_limit; - enum ppc_bank_e periph_ppc_bank; - int16_t periph_ppc_loc; -}; - -/** - * \brief Configures the Memory Protection Controller. - * - * \return Returns error code. - */ -int32_t mpc_init_cfg(void); - -/** - * \brief Configures the Peripheral Protection Controller. - */ -void ppc_init_cfg(void); - -/** - * \brief Restict access to peripheral to secure - */ -void ppc_configure_to_secure(enum ppc_bank_e bank, uint16_t loc); - -/** - * \brief Allow non-secure access to peripheral - */ -void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t loc); - -/** - * \brief Enable secure unprivileged access to peripheral - */ -void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos); - -/** - * \brief Clear secure unprivileged access to peripheral - */ -void ppc_clr_secure_unpriv(enum ppc_bank_e bank, uint16_t pos); - -/** - * \brief Clears PPC interrupt. - */ -void ppc_clear_irq(void); - -/** - * \brief Configures SAU and IDAU. - */ -void sau_and_idau_cfg(void); - -/** - * \brief Enables the fault handlers and sets priorities. - * - * \return Returns values as specified by the \ref tfm_plat_err_t - */ -enum tfm_plat_err_t enable_fault_handlers(void); - -/** - * \brief Configures the system reset request properties - * - * \return Returns values as specified by the \ref tfm_plat_err_t - */ -enum tfm_plat_err_t system_reset_cfg(void); - -/** - * \brief Configures the system debug properties. - * - * \return Returns values as specified by the \ref tfm_plat_err_t - */ -enum tfm_plat_err_t init_debug(void); - -/** - * \brief Configures all external interrupts to target the - * NS state, apart for the ones associated to secure - * peripherals (plus MPC and PPC) - * - * \return Returns values as specified by the \ref tfm_plat_err_t - */ -enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); - -/** - * \brief This function enable the interrupts associated - * to the secure peripherals (plus the isolation boundary violation - * interrupts) - * - * \return Returns values as specified by the \ref tfm_plat_err_t - */ -enum tfm_plat_err_t nvic_interrupt_enable(void); - -#endif /* __TARGET_CFG_H__ */ diff --git a/platform/ext/target/mps2/sse-200_aws/tfm_hal_isolation.c b/platform/ext/target/mps2/sse-200_aws/tfm_hal_isolation.c deleted file mode 100644 index 6f129c9664..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/tfm_hal_isolation.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "cmsis.h" -#include "Driver_Common.h" -#include "mpu_armv8m_drv.h" -#include "region.h" -#include "target_cfg.h" -#include "tfm_hal_isolation.h" - -#ifdef CONFIG_TFM_ENABLE_MEMORY_PROTECT -#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) - -#define MPU_REGION_VENEERS 0 -#define MPU_REGION_TFM_UNPRIV_CODE 1 -#define MPU_REGION_NS_STACK 2 -#define PARTITION_REGION_RO 3 -#define PARTITION_REGION_RW_STACK 4 -#define PARTITION_REGION_PERIPH 5 -#ifdef TFM_SP_META_PTR_ENABLE -#define MPU_REGION_SP_META_PTR 7 -#endif /* TFM_SP_META_PTR_ENABLE */ - -REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base); -REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit); -REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base); -REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit); -REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); -REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); -REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); -REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base); -REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit); -#ifdef TFM_SP_META_PTR_ENABLE -REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base); -REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit); -#endif /* TFM_SP_META_PTR_ENABLE */ - -const struct mpu_armv8m_region_cfg_t region_cfg[] = { - /* Veneer region */ - { - MPU_REGION_VENEERS, - (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base), - (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit), - MPU_ARMV8M_MAIR_ATTR_CODE_IDX, - MPU_ARMV8M_XN_EXEC_OK, - MPU_ARMV8M_AP_RO_PRIV_UNPRIV, - MPU_ARMV8M_SH_NONE - }, - /* TFM Core unprivileged code region */ - { - MPU_REGION_TFM_UNPRIV_CODE, - (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base), - (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit), - MPU_ARMV8M_MAIR_ATTR_CODE_IDX, - MPU_ARMV8M_XN_EXEC_OK, - MPU_ARMV8M_AP_RO_PRIV_UNPRIV, - MPU_ARMV8M_SH_NONE - }, - /* NSPM PSP */ - { - MPU_REGION_NS_STACK, - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base), - (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit), - MPU_ARMV8M_MAIR_ATTR_DATA_IDX, - MPU_ARMV8M_XN_EXEC_NEVER, - MPU_ARMV8M_AP_RW_PRIV_UNPRIV, - MPU_ARMV8M_SH_NONE - }, - /* RO region */ - { - PARTITION_REGION_RO, - (uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_START, $$Base), - (uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_END, $$Base), - MPU_ARMV8M_MAIR_ATTR_CODE_IDX, - MPU_ARMV8M_XN_EXEC_OK, - MPU_ARMV8M_AP_RO_PRIV_UNPRIV, - MPU_ARMV8M_SH_NONE - }, - /* RW, ZI and stack as one region */ - { - PARTITION_REGION_RW_STACK, - (uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_START, $$Base), - (uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_END, $$Base), - MPU_ARMV8M_MAIR_ATTR_DATA_IDX, - MPU_ARMV8M_XN_EXEC_NEVER, - MPU_ARMV8M_AP_RW_PRIV_UNPRIV, - MPU_ARMV8M_SH_NONE - }, -#ifdef TFM_SP_META_PTR_ENABLE - /* TFM partition metadata pointer region */ - { - MPU_REGION_SP_META_PTR, - (uint32_t)®ION_NAME(Image$$, TFM_SP_META_PTR, $$RW$$Base), - (uint32_t)®ION_NAME(Image$$, TFM_SP_META_PTR, $$RW$$Limit), - MPU_ARMV8M_MAIR_ATTR_DATA_IDX, - MPU_ARMV8M_XN_EXEC_NEVER, - MPU_ARMV8M_AP_RW_PRIV_UNPRIV, - MPU_ARMV8M_SH_NONE - } -#endif -}; -#endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ - -enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void) -{ - /* Set up isolation boundaries between SPE and NSPE */ - sau_and_idau_cfg(); - if (mpc_init_cfg() != ARM_DRIVER_OK) { - return TFM_HAL_ERROR_GENERIC; - } - ppc_init_cfg(); - - /* Set up static isolation boundaries inside SPE */ -#ifdef CONFIG_TFM_ENABLE_MEMORY_PROTECT - int32_t i; - struct mpu_armv8m_dev_t dev_mpu_s = { MPU_BASE }; - - mpu_armv8m_clean(&dev_mpu_s); - - for (i = 0; i < ARRAY_SIZE(region_cfg); i++) { - if (mpu_armv8m_region_enable(&dev_mpu_s, - (struct mpu_armv8m_region_cfg_t *)®ion_cfg[i]) - != MPU_ARMV8M_OK) { - return TFM_HAL_ERROR_GENERIC; - } - } - - mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE, - HARDFAULT_NMI_ENABLE); -#endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ - - return TFM_HAL_SUCCESS; -} diff --git a/platform/ext/target/mps2/sse-200_aws/tfm_peripherals_def.h b/platform/ext/target/mps2/sse-200_aws/tfm_peripherals_def.h deleted file mode 100644 index 332ee90e30..0000000000 --- a/platform/ext/target/mps2/sse-200_aws/tfm_peripherals_def.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. - * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __TFM_PERIPHERALS_DEF_H__ -#define __TFM_PERIPHERALS_DEF_H__ - -#include "platform_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define TFM_TIMER0_IRQ (TIMER0_IRQn) -#define TFM_TIMER1_IRQ (TIMER1_IRQn) - -struct platform_data_t; - -extern struct platform_data_t tfm_peripheral_std_uart; -extern struct platform_data_t tfm_peripheral_fpga_io; -extern struct platform_data_t tfm_peripheral_timer0; - -#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart) -#define TFM_PERIPHERAL_FPGA_IO (&tfm_peripheral_fpga_io) -#define TFM_PERIPHERAL_TIMER0 (&tfm_peripheral_timer0) - -#ifdef __cplusplus -} -#endif - -#endif /* __TFM_PERIPHERALS_DEF_H__ */ |