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author | Mate Toth-Pal <mate.toth-pal@arm.com> | 2018-09-20 12:15:40 +0200 |
---|---|---|
committer | Tamas Ban <tamas.ban@arm.com> | 2018-12-05 16:04:56 +0100 |
commit | bd4c069efcae48c5595a1678f2bcf6f0ed7d99e3 (patch) | |
tree | 927668540966528b9c03bcf2e38ef365e7740b73 | |
parent | 9ff535b5b2b66527c31f2ab84ec4efd00572d8c5 (diff) | |
download | trusted-firmware-m-bd4c069efcae48c5595a1678f2bcf6f0ed7d99e3.tar.gz |
Platform: Add SRAM limit assert to S sct files
The checking of memory limit was missing from ARMCLANG
scatter file. Without this fix linker can easily over allocate
the data memory without noticing it. GCC has this feature in place.
Change-Id: If6923bfe5e78f405b562b652f696330b6f3f971d
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
4 files changed, 46 insertions, 6 deletions
diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct index 6ec703f7a1..4926478dda 100644 --- a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct +++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct @@ -43,7 +43,7 @@ LR_CODE S_CODE_START { ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { } - ER_TFM_DATA +0 S_DATA_SIZE { + ER_TFM_DATA +0 { .ANY (+RW +ZI) } @@ -131,7 +131,7 @@ LR_CODE S_CODE_START { ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { } - ER_TFM_DATA +0 S_DATA_SIZE { + ER_TFM_DATA +0 { .ANY (+RW +ZI) } @@ -214,6 +214,16 @@ LR_CODE S_CODE_START { #endif /* TFM_LVL == 1 */ + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) } LR_VENEER CMSE_VENEER_REGION_START { diff --git a/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct b/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct index 6ec703f7a1..4926478dda 100644 --- a/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct +++ b/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct @@ -43,7 +43,7 @@ LR_CODE S_CODE_START { ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { } - ER_TFM_DATA +0 S_DATA_SIZE { + ER_TFM_DATA +0 { .ANY (+RW +ZI) } @@ -131,7 +131,7 @@ LR_CODE S_CODE_START { ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { } - ER_TFM_DATA +0 S_DATA_SIZE { + ER_TFM_DATA +0 { .ANY (+RW +ZI) } @@ -214,6 +214,16 @@ LR_CODE S_CODE_START { #endif /* TFM_LVL == 1 */ + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) } LR_VENEER CMSE_VENEER_REGION_START { diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct index 2912d34f8d..a1c8ea8d6e 100755 --- a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct +++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct @@ -43,7 +43,7 @@ LR_CODE S_CODE_START { ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { } - ER_TFM_DATA +0 S_DATA_SIZE { + ER_TFM_DATA +0 { .ANY (+RW +ZI) } @@ -131,7 +131,7 @@ LR_CODE S_CODE_START { ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { } - ER_TFM_DATA +0 S_DATA_SIZE { + ER_TFM_DATA +0 { .ANY (+RW +ZI) } @@ -214,6 +214,16 @@ LR_CODE S_CODE_START { #endif /* TFM_LVL == 1 */ + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) } LR_VENEER CMSE_VENEER_REGION_START { diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct b/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct index cccecd211a..d62569a454 100644 --- a/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct +++ b/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct @@ -214,6 +214,16 @@ LR_CODE S_CODE_START { #endif /* TFM_LVL == 1 */ + /* This empty, zero long execution region is here to mark the limit address + * of the last execution region that is allocated in SRAM. + */ + SRAM_WATERMARK +0 EMPTY 0x0 { + } + + /* Make sure that the sections allocated in the SRAM does not exceed the + * size of the SRAM available. + */ + ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) } LR_VENEER CMSE_VENEER_REGION_START { |