plat: Enable Flash driver RWW support (PSoC64)
"Read while write" (RWW) improves flash driver performance
and enables flash driver notifications between two cores.
The latter is required to trigger an interrupt on CM4 side,
which handler is located in RAM, thus preventing the core
accessing flash memory during flash erase/program operations.
- add Cy_SysIpcPipeIsrCm0 interrupt handler to
CM0P interrupt vectors table
- add Cy_SysIpcPipeIsrCm4 and Cy_Flash_ResumeIrqHandler to
CM4 interrupt vectors table
- consider supporting vectors table relocation to RAM in order
to support run-time interrupt handlers registration - TBD
Signed-off-by: Andrei Narkevitch <ainh@cypress.com>
Change-Id: I36ac7a427ca8fb92fed1a765f10bc7a9e3ce29b4
7 files changed