aboutsummaryrefslogtreecommitdiff
path: root/plat/nvidia/tegra/include/t186/tegra_mc_def.h
blob: 398453eb9599707ea66b25549c3ef6632a722664 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
/*
 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef TEGRA_MC_DEF_H
#define TEGRA_MC_DEF_H

/*******************************************************************************
 * Memory Controller's PCFIFO client configuration registers
 ******************************************************************************/
#define MC_PCFIFO_CLIENT_CONFIG0				0xdd0U

#define MC_PCFIFO_CLIENT_CONFIG1				0xdd4U
#define  MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL			0x20000U
#define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED		(0U << 17)
#define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK		(1U << 17)
#define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED		(0U << 21)
#define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK		(1U << 21)
#define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED 	(0U << 29)
#define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK		(1U << 29)

#define MC_PCFIFO_CLIENT_CONFIG2				0xdd8U
#define  MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL			0x20000U
#define  MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED	(0U << 11)
#define  MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK	(1U << 11)
#define  MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED	(0U << 13)
#define  MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK		(1U << 13)

#define MC_PCFIFO_CLIENT_CONFIG3				0xddcU
#define  MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL			0U
#define  MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED	(0U << 7)
#define  MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK		(1U << 7)

#define MC_PCFIFO_CLIENT_CONFIG4				0xde0U
#define  MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL			0U
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED 	(0U << 1)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK		(1U << 1)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED		(0U << 5)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK		(1U << 5)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED 	(0U << 13)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK		(1U << 13)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED 	(0U << 15)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED 		(1U << 15)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK		(1U << 15)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED	(0U << 17)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK		(1U << 17)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED	(0U << 22)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK		(1U << 22)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED	(0U << 26)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK		(1U << 26)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED	(0U << 30)
#define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK		(1U << 30)

#define MC_PCFIFO_CLIENT_CONFIG5				0xbf4U
#define  MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL			0U
#define  MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED	(0U << 0)
#define  MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK		(1U << 0)

/*******************************************************************************
 * Stream ID Override Config registers
 ******************************************************************************/
#define MC_STREAMID_OVERRIDE_CFG_PTCR				0x000U
#define MC_STREAMID_OVERRIDE_CFG_AFIR				0x070U
#define MC_STREAMID_OVERRIDE_CFG_HDAR				0x0A8U
#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR			0x0B0U
#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD			0x0E0U
#define MC_STREAMID_OVERRIDE_CFG_SATAR				0x0F8U
#define MC_STREAMID_OVERRIDE_CFG_MPCORER			0x138U
#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR			0x158U
#define MC_STREAMID_OVERRIDE_CFG_AFIW				0x188U
#define MC_STREAMID_OVERRIDE_CFG_HDAW				0x1A8U
#define MC_STREAMID_OVERRIDE_CFG_MPCOREW			0x1C8U
#define MC_STREAMID_OVERRIDE_CFG_SATAW				0x1E8U
#define MC_STREAMID_OVERRIDE_CFG_ISPRA				0x220U
#define MC_STREAMID_OVERRIDE_CFG_ISPWA				0x230U
#define MC_STREAMID_OVERRIDE_CFG_ISPWB				0x238U
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR			0x250U
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW			0x258U
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR			0x260U
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW			0x268U
#define MC_STREAMID_OVERRIDE_CFG_TSECSRD			0x2A0U
#define MC_STREAMID_OVERRIDE_CFG_TSECSWR			0x2A8U
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD				0x2C0U
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR				0x2C8U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA			0x300U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA			0x308U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCR				0x310U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB			0x318U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA			0x320U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA			0x328U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCW				0x330U
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB			0x338U
#define MC_STREAMID_OVERRIDE_CFG_VICSRD				0x360U
#define MC_STREAMID_OVERRIDE_CFG_VICSWR				0x368U
#define MC_STREAMID_OVERRIDE_CFG_VIW				0x390U
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD			0x3C0U
#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR			0x3C8U
#define MC_STREAMID_OVERRIDE_CFG_APER				0x3D0U
#define MC_STREAMID_OVERRIDE_CFG_APEW				0x3D8U
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD			0x3F0U
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR			0x3F8U
#define MC_STREAMID_OVERRIDE_CFG_SESRD				0x400U
#define MC_STREAMID_OVERRIDE_CFG_SESWR				0x408U
#define MC_STREAMID_OVERRIDE_CFG_ETRR				0x420U
#define MC_STREAMID_OVERRIDE_CFG_ETRW				0x428U
#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB			0x430U
#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB			0x438U
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2			0x440U
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2			0x448U
#define MC_STREAMID_OVERRIDE_CFG_AXISR				0x460U
#define MC_STREAMID_OVERRIDE_CFG_AXISW				0x468U
#define MC_STREAMID_OVERRIDE_CFG_EQOSR				0x470U
#define MC_STREAMID_OVERRIDE_CFG_EQOSW				0x478U
#define MC_STREAMID_OVERRIDE_CFG_UFSHCR				0x480U
#define MC_STREAMID_OVERRIDE_CFG_UFSHCW				0x488U
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR			0x490U
#define MC_STREAMID_OVERRIDE_CFG_BPMPR				0x498U
#define MC_STREAMID_OVERRIDE_CFG_BPMPW				0x4A0U
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR			0x4A8U
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW			0x4B0U
#define MC_STREAMID_OVERRIDE_CFG_AONR				0x4B8U
#define MC_STREAMID_OVERRIDE_CFG_AONW				0x4C0U
#define MC_STREAMID_OVERRIDE_CFG_AONDMAR			0x4C8U
#define MC_STREAMID_OVERRIDE_CFG_AONDMAW			0x4D0U
#define MC_STREAMID_OVERRIDE_CFG_SCER				0x4D8U
#define MC_STREAMID_OVERRIDE_CFG_SCEW				0x4E0U
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR			0x4E8U
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW			0x4F0U
#define MC_STREAMID_OVERRIDE_CFG_APEDMAR			0x4F8U
#define MC_STREAMID_OVERRIDE_CFG_APEDMAW			0x500U
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1			0x508U
#define MC_STREAMID_OVERRIDE_CFG_VICSRD1			0x510U
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1			0x518U

/*******************************************************************************
 * Macro to calculate Security cfg register addr from StreamID Override register
 ******************************************************************************/
#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))

#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV		(0U << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV	(1U << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV		(2U << 4)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV	(3U << 4)

#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL		(0U << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL	(1U << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL		(2U << 8)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL	(3U << 8)

#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO				(0U << 12)
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID		(1U << 12)

/*******************************************************************************
 * Memory Controller transaction override config registers
 ******************************************************************************/
#define MC_TXN_OVERRIDE_CONFIG_HDAR				0x10a8U
#define MC_TXN_OVERRIDE_CONFIG_BPMPW				0x14a0U
#define MC_TXN_OVERRIDE_CONFIG_PTCR				0x1000U
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR			0x1490U
#define MC_TXN_OVERRIDE_CONFIG_EQOSW				0x1478U
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR				0x13f8U
#define MC_TXN_OVERRIDE_CONFIG_ISPRA				0x1220U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA				0x1328U
#define MC_TXN_OVERRIDE_CONFIG_VICSRD				0x1360U
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW				0x11c8U
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD				0x12c0U
#define MC_TXN_OVERRIDE_CONFIG_AXISR				0x1460U
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW				0x14f0U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW				0x1330U
#define MC_TXN_OVERRIDE_CONFIG_EQOSR				0x1470U
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR				0x14f8U
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD				0x10e0U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB				0x1318U
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1				0x1510U
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR				0x14a8U
#define MC_TXN_OVERRIDE_CONFIG_VIW				0x1390U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA				0x1308U
#define MC_TXN_OVERRIDE_CONFIG_AXISW				0x1468U
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR			0x1260U
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR				0x1480U
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR				0x12a8U
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR				0x12c8U
#define MC_TXN_OVERRIDE_CONFIG_SATAR				0x10f8U
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW			0x1258U
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB				0x1438U
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2				0x1440U
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR				0x14e8U
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2				0x1448U
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW				0x14d0U
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW				0x1500U
#define MC_TXN_OVERRIDE_CONFIG_AONW				0x14c0U
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR			0x10b0U
#define MC_TXN_OVERRIDE_CONFIG_ETRR				0x1420U
#define MC_TXN_OVERRIDE_CONFIG_SESWR				0x1408U
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD				0x13f0U
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD				0x13c0U
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB				0x1430U
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW				0x14b0U
#define MC_TXN_OVERRIDE_CONFIG_APER				0x13d0U
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1			0x1518U
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR			0x1250U
#define MC_TXN_OVERRIDE_CONFIG_ISPWA				0x1230U
#define MC_TXN_OVERRIDE_CONFIG_SESRD				0x1400U
#define MC_TXN_OVERRIDE_CONFIG_SCER				0x14d8U
#define MC_TXN_OVERRIDE_CONFIG_AONR				0x14b8U
#define MC_TXN_OVERRIDE_CONFIG_MPCORER				0x1138U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA				0x1320U
#define MC_TXN_OVERRIDE_CONFIG_HDAW				0x11a8U
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR				0x13c8U
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW				0x1488U
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR				0x14c8U
#define MC_TXN_OVERRIDE_CONFIG_SATAW				0x11e8U
#define MC_TXN_OVERRIDE_CONFIG_ETRW				0x1428U
#define MC_TXN_OVERRIDE_CONFIG_VICSWR				0x1368U
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR				0x1158U
#define MC_TXN_OVERRIDE_CONFIG_AFIR				0x1070U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB				0x1338U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA				0x1300U
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1			0x1508U
#define MC_TXN_OVERRIDE_CONFIG_ISPWB				0x1238U
#define MC_TXN_OVERRIDE_CONFIG_BPMPR				0x1498U
#define MC_TXN_OVERRIDE_CONFIG_APEW				0x13d8U
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR				0x1310U
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW			0x1268U
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD				0x12a0U
#define MC_TXN_OVERRIDE_CONFIG_AFIW				0x1188U
#define MC_TXN_OVERRIDE_CONFIG_SCEW				0x14e0U

#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID			(1U << 0)
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV			(2U << 4)
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT	(1U << 12)

/*******************************************************************************
 * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
 * MC_TXN_OVERRIDE_CONFIG_{module} registers
 ******************************************************************************/
#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT			0U
#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID			1U
#define MC_TXN_OVERRIDE_CGID_TAG_ZERO				2U
#define MC_TXN_OVERRIDE_CGID_TAG_ADR				3U
#define MC_TXN_OVERRIDE_CGID_TAG_MASK				3ULL

/*******************************************************************************
 * Memory Controller Reset Control registers
 ******************************************************************************/
#define MC_CLIENT_HOTRESET_CTRL0				0x200U
#define  MC_CLIENT_HOTRESET_CTRL0_RESET_VAL			0U
#define  MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB			(1U << 0)
#define  MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB			(1U << 6)
#define  MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB			(1U << 7)
#define  MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB		(1U << 8)
#define  MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB		(1U << 9)
#define  MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB		(1U << 11)
#define  MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB		(1U << 15)
#define  MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB			(1U << 17)
#define  MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB			(1U << 18)
#define  MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB		(1U << 19)
#define  MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB		(1U << 20)
#define  MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB		(1U << 22)
#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB		(1U << 29)
#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB		(1U << 30)
#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB		(1U << 31)
#define MC_CLIENT_HOTRESET_STATUS0				0x204U
#define MC_CLIENT_HOTRESET_CTRL1				0x970U
#define  MC_CLIENT_HOTRESET_CTRL1_RESET_VAL			0U
#define  MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB		(1U << 0)
#define  MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB			(1U << 2)
#define  MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB		(1U << 5)
#define  MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB			(1U << 6)
#define  MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB			(1U << 7)
#define  MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB		(1U << 8)
#define  MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB			(1U << 12)
#define  MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB		(1U << 13)
#define  MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB		(1U << 18)
#define  MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB		(1U << 19)
#define  MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB		(1U << 20)
#define  MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB		(1U << 21)
#define  MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB		(1U << 22)
#define  MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB			(1U << 23)
#define  MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB			(1U << 24)
#define MC_CLIENT_HOTRESET_STATUS1				0x974U

#ifndef __ASSEMBLY__

/*******************************************************************************
 * Structure to hold the transaction override settings to use to override
 * client inputs
 ******************************************************************************/
typedef struct mc_txn_override_cfg {
	uint32_t offset;
	uint8_t cgid_tag;
} mc_txn_override_cfg_t;

#define mc_make_txn_override_cfg(off, val) \
	{ \
		.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
		.cgid_tag = MC_TXN_OVERRIDE_ ## val \
	}

/*******************************************************************************
 * Structure to hold the Stream ID to use to override client inputs
 ******************************************************************************/
typedef struct mc_streamid_override_cfg {
	uint32_t offset;
	uint8_t stream_id;
} mc_streamid_override_cfg_t;

/*******************************************************************************
 * Structure to hold the Stream ID Security Configuration settings
 ******************************************************************************/
typedef struct mc_streamid_security_cfg {
	char *name;
	uint32_t offset;
	uint32_t override_enable;
	uint32_t override_client_inputs;
	uint32_t override_client_ns_flag;
} mc_streamid_security_cfg_t;

#define OVERRIDE_DISABLE				1U
#define OVERRIDE_ENABLE					0U
#define CLIENT_FLAG_SECURE				0U
#define CLIENT_FLAG_NON_SECURE				1U
#define CLIENT_INPUTS_OVERRIDE				1U
#define CLIENT_INPUTS_NO_OVERRIDE			0U

/*******************************************************************************
 * StreamID to indicate no SMMU translations (requests to be steered on the
 * SMMU bypass path)
 ******************************************************************************/
#define MC_STREAM_ID_MAX			0x7FU

#define mc_make_sec_cfg(off, ns, ovrrd, access) \
	{ \
		.name = # off, \
		.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
				MC_STREAMID_OVERRIDE_CFG_ ## off), \
		.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
		.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
		.override_enable = OVERRIDE_ ## access \
	}

#define mc_make_sid_override_cfg(name) \
	{ \
		.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
		.val = 0x00000000U, \
	}

#define mc_make_sid_security_cfg(name) \
	{ \
		.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
		.val = 0x00000000U, \
	}

#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
	((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
	 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)

#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
	 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED

#define mc_set_tsa_passthrough(client) \
	do { \
		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
			(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
			 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
			(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
	} while (0)

#define mc_set_tsa_w_passthrough(client) \
	do { \
		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
			(TSA_CONFIG_STATIC0_CSW_RESET_W & \
			 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
			(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
	} while (0)

#define mc_set_tsa_r_passthrough(client) \
	{ \
		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
			(TSA_CONFIG_STATIC0_CSR_RESET_R & \
			 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
			(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
	} while (0)

#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
	do { \
		tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
				  MC_TXN_OVERRIDE_##normal_axi_id | \
				  MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
				  MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
				  MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
	} while (0)

#endif /* __ASSEMBLY__ */

#endif /* TEGRA_MC_DEF_H */