aboutsummaryrefslogtreecommitdiff
path: root/plat/mediatek/mt8192/plat_mt_cirq.c
blob: 7fc060799af742fb2f2fb1a5552e33e25361e715 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
/*
 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/arm/gic_common.h>
#include <drivers/console.h>
#include <lib/mmio.h>

#include <mt_gic_v3.h>
#include <mtk_plat_common.h>
#include <plat_mt_cirq.h>
#include <platform_def.h>

static struct cirq_events cirq_all_events = {
	.spi_start = CIRQ_SPI_START
};

static inline void  mt_cirq_write32(uint32_t val, uint32_t addr)
{
	mmio_write_32(addr + SYS_CIRQ_BASE, val);
}

static inline uint32_t mt_cirq_read32(uint32_t addr)
{
	return mmio_read_32(addr + SYS_CIRQ_BASE);
}

/*
 * cirq_clone_flush_check_store:
 * set 1 if we need to enable clone/flush value's check
 */
static int32_t cirq_clone_flush_check_val;

/*
 * cirq_pattern_clone_flush_check_show:  set 1 if we need to do pattern test.
 */
static int32_t cirq_pattern_clone_flush_check_val;

/*
 * cirq_pattern_clone_flush_check_show:  set 1 if we need to do pattern test.
 */
static int32_t cirq_pattern_list;

/*
 * mt_cirq_ack_all: Ack all the interrupt on SYS_CIRQ
 */
void mt_cirq_ack_all(void)
{
	unsigned int i;

	for (i = 0U; i < CIRQ_CTRL_REG_NUM; i++) {
		mt_cirq_write32(0xFFFFFFFF, CIRQ_ACK_BASE + (i * 4U));
	}
	/* make sure all cirq setting take effect before doing other things */
	dmbsy();
}

/*
 * mt_cirq_enable: Enable SYS_CIRQ
 */
void mt_cirq_enable(void)
{
	uint32_t st;

	mt_cirq_ack_all();

	st = mt_cirq_read32(CIRQ_CON);
	st |= (CIRQ_CON_EN << CIRQ_CON_EN_BITS) |
			(CIRQ_CON_EDGE_ONLY << CIRQ_CON_EDGE_ONLY_BITS);

	mt_cirq_write32((st & CIRQ_CON_BITS_MASK), CIRQ_CON);
}

/*
 * mt_cirq_disable: Disable SYS_CIRQ
 */
void mt_cirq_disable(void)
{
	uint32_t st;

	st = mt_cirq_read32(CIRQ_CON);
	st &= ~(CIRQ_CON_EN << CIRQ_CON_EN_BITS);

	mt_cirq_write32((st & CIRQ_CON_BITS_MASK), CIRQ_CON);
}

/*
 * mt_cirq_get_mask: Get the specified SYS_CIRQ mask
 * @cirq_num: the SYS_CIRQ number to get
 * @return:
 *    1: this cirq is masked
 *    0: this cirq is umasked
 *    2: cirq num is out of range
 */
__attribute__((weak)) unsigned int mt_cirq_get_mask(uint32_t cirq_num)
{
	uint32_t st;
	unsigned int val;

	if (cirq_num >= CIRQ_IRQ_NUM) {
		ERROR("[CIRQ] %s: invalid cirq %u\n", __func__, cirq_num);
		return 2;
	}

	st = mt_cirq_read32((cirq_num / 32U) * 4U + CIRQ_MASK_BASE);
	val = (st >> (cirq_num % 32U)) & 1U;
	return val;
}

/*
 * mt_cirq_mask_all: Mask all interrupts on SYS_CIRQ.
 */
void mt_cirq_mask_all(void)
{
	unsigned int i;

	for (i = 0U; i < CIRQ_CTRL_REG_NUM; i++) {
		mt_cirq_write32(0xFFFFFFFF, CIRQ_MASK_SET_BASE + (i * 4U));
	}
	/* make sure all cirq setting take effect before doing other things */
	dmbsy();
}

/*
 * mt_cirq_unmask_all: Unmask all interrupts on SYS_CIRQ.
 */
void mt_cirq_unmask_all(void)
{
	unsigned int i;

	for (i = 0U; i < CIRQ_CTRL_REG_NUM; i++) {
		mt_cirq_write32(0xFFFFFFFF, CIRQ_MASK_CLR_BASE + (i * 4U));
	}
	/* make sure all cirq setting take effect before doing other things */
	dmbsy();
}

/*
 * mt_cirq_mask: Mask the specified SYS_CIRQ.
 * @cirq_num: the SYS_CIRQ number to mask
 * @return:
 *    0: mask success
 *   -1: cirq num is out of range
 */
static int mt_cirq_mask(uint32_t cirq_num)
{
	uint32_t bit = 1U << (cirq_num % 32U);

	if (cirq_num >= CIRQ_IRQ_NUM) {
		ERROR("[CIRQ] %s: invalid cirq %u\n", __func__, cirq_num);
		return -1;
	}

	mt_cirq_write32(bit, (cirq_num / 32U) * 4U + CIRQ_MASK_SET_BASE);
	return 0;
}

/*
 * mt_cirq_unmask: Unmask the specified SYS_CIRQ.
 * @cirq_num: the SYS_CIRQ number to unmask
 * @return:
 *    0: umask success
 *   -1: cirq num is out of range
 */
static int mt_cirq_unmask(uint32_t cirq_num)
{
	uint32_t bit = 1U << (cirq_num % 32U);

	if (cirq_num >= CIRQ_IRQ_NUM) {
		ERROR("[CIRQ] %s: invalid cirq %u\n", __func__, cirq_num);
		return -1;
	}

	mt_cirq_write32(bit, (cirq_num / 32U) * 4U + CIRQ_MASK_CLR_BASE);
	return 0;
}

/*
 * mt_cirq_set_sens: Set the sensitivity for the specified SYS_CIRQ number.
 * @cirq_num: the SYS_CIRQ number to set
 * @sens: sensitivity to set
 * @return:
 *    0: set sens success
 *   -1: cirq num is out of range
 */
static int mt_cirq_set_sens(uint32_t cirq_num, uint32_t sens)
{
	uint32_t base;
	uint32_t bit = 1U << (cirq_num % 32U);

	if (cirq_num >= CIRQ_IRQ_NUM) {
		ERROR("[CIRQ] %s: invalid cirq %u\n", __func__, cirq_num);
		return -1;
	}

	if (sens == MT_CIRQ_EDGE_SENSITIVE) {
		base = (cirq_num / 32U) * 4U + CIRQ_SENS_CLR_BASE;
	} else if (sens == MT_CIRQ_LEVEL_SENSITIVE) {
		base = (cirq_num / 32U) * 4U + CIRQ_SENS_SET_BASE;
	} else {
		ERROR("[CIRQ] set_sens invalid sen value %u\n", sens);
		return -1;
	}

	mt_cirq_write32(bit, base);
	return 0;
}

/*
 * mt_cirq_get_sens: Get the specified SYS_CIRQ sensitivity
 * @cirq_num: the SYS_CIRQ number to get
 * @return:
 *    1: this cirq is MT_LEVEL_SENSITIVE
 *    0: this cirq is MT_EDGE_SENSITIVE
 *    2: cirq num is out of range
 */
__attribute__((weak)) unsigned int mt_cirq_get_sens(uint32_t cirq_num)
{
	uint32_t st;
	unsigned int val;

	if (cirq_num >= CIRQ_IRQ_NUM) {
		ERROR("[CIRQ] %s: invalid cirq %u\n", __func__, cirq_num);
		return 2;
	}

	st = mt_cirq_read32((cirq_num / 32U) * 4U + CIRQ_SENS_BASE);
	val = (st >> (cirq_num % 32U)) & 1U;
	return val;
}

/*
 * mt_cirq_set_pol: Set the polarity for the specified SYS_CIRQ number.
 * @cirq_num: the SYS_CIRQ number to set
 * @pol: polarity to set
 * @return:
 *    0: set pol success
 *   -1: cirq num is out of range
 */
static int mt_cirq_set_pol(uint32_t cirq_num, uint32_t pol)
{
	uint32_t base;
	uint32_t bit = 1U << (cirq_num % 32U);

	if (cirq_num >= CIRQ_IRQ_NUM) {
		ERROR("[CIRQ] %s: invalid cirq %u\n", __func__, cirq_num);
		return -1;
	}

	if (pol == MT_CIRQ_POL_NEG) {
		base = (cirq_num / 32U) * 4U + CIRQ_POL_CLR_BASE;
	} else if (pol == MT_CIRQ_POL_POS) {
		base = (cirq_num / 32U) * 4U + CIRQ_POL_SET_BASE;
	} else {
		ERROR("[CIRQ] set_pol invalid polarity value %u\n", pol);
		return -1;
	}

	mt_cirq_write32(bit, base);
	return 0;
}

/*
 * mt_cirq_get_pol: Get the specified SYS_CIRQ polarity
 * @cirq_num: the SYS_CIRQ number to get
 * @return:
 *    1: this cirq is MT_CIRQ_POL_POS
 *    0: this cirq is MT_CIRQ_POL_NEG
 *    2: cirq num is out of range
 */
__attribute__((weak)) unsigned int mt_cirq_get_pol(uint32_t cirq_num)
{
	uint32_t st;
	unsigned int val;

	if (cirq_num >= CIRQ_IRQ_NUM) {
		ERROR("[CIRQ] %s: invalid cirq %u\n", __func__, cirq_num);
		return 2;
	}

	st = mt_cirq_read32((cirq_num / 32U) * 4U + CIRQ_POL_BASE);
	val = (st >> (cirq_num % 32U)) & 1U;
	return val;
}

/*
 * mt_cirq_get_pending: Get the specified SYS_CIRQ pending
 * @cirq_num: the SYS_CIRQ number to get
 * @return:
 *    1: this cirq is pending
 *    0: this cirq is not pending
 *    2: cirq num is out of range
 */
static unsigned int mt_cirq_get_pending(uint32_t cirq_num)
{
	uint32_t st;
	unsigned int val;

	if (cirq_num >= CIRQ_IRQ_NUM) {
		ERROR("[CIRQ] %s: invalid cirq %u\n", __func__, cirq_num);
		return 2;
	}

	st = mt_cirq_read32((cirq_num / 32U) * 4U + CIRQ_STA_BASE);
	val = (st >> (cirq_num % 32U)) & 1U;
	return val;
}

/*
 * mt_cirq_clone_pol: Copy the polarity setting from GIC to SYS_CIRQ
 */
void mt_cirq_clone_pol(void)
{
	uint32_t cirq_num;

	for (cirq_num = 0U; cirq_num < CIRQ_IRQ_NUM; cirq_num++) {
		mt_cirq_set_pol(cirq_num, MT_CIRQ_POL_POS);
	}
}

/*
 * mt_cirq_clone_sens: Copy the sensitivity setting from GIC to SYS_CIRQ
 */
void mt_cirq_clone_sens(void)
{
	uint32_t cirq_num, irq_num;
	uint32_t st, val;

	for (cirq_num = 0U; cirq_num < CIRQ_IRQ_NUM; cirq_num++) {
		irq_num = CIRQ_TO_IRQ_NUM(cirq_num);

		if ((cirq_num == 0U) || (irq_num % 16U == 0U)) {
			st = mmio_read_32(BASE_GICD_BASE + GICD_ICFGR +
				(irq_num / 16U * 4U));
		}

		val = (st >> ((irq_num % 16U) * 2U)) & 0x2U;

		if (val) {
			mt_cirq_set_sens(cirq_num, MT_CIRQ_EDGE_SENSITIVE);
		} else {
			mt_cirq_set_sens(cirq_num, MT_CIRQ_LEVEL_SENSITIVE);
		}
	}
}

/*
 * mt_cirq_clone_mask: Copy the mask setting from GIC to SYS_CIRQ
 */
void mt_cirq_clone_mask(void)
{
	uint32_t cirq_num, irq_num;
	uint32_t st, val;

	for (cirq_num = 0U; cirq_num < CIRQ_IRQ_NUM; cirq_num++) {
		irq_num = CIRQ_TO_IRQ_NUM(cirq_num);

		if ((cirq_num == 0U) || (irq_num % 32U == 0U)) {
			st = mmio_read_32(BASE_GICD_BASE +
				GICD_ISENABLER + (irq_num / 32U * 4U));
		}

		val = (st >> (irq_num % 32)) & 1U;

		if (val) {
			mt_cirq_unmask(cirq_num);
		} else {
			mt_cirq_mask(cirq_num);
		}
	}
}

/*
 * mt_cirq_clone_gic: Copy the setting from GIC to SYS_CIRQ
 */
void mt_cirq_clone_gic(void)
{
	mt_cirq_clone_sens();
	mt_cirq_clone_mask();
}

/*
 * mt_cirq_disable: Flush interrupt from SYS_CIRQ to GIC
 */
void mt_cirq_flush(void)
{
	unsigned int i;
	unsigned char cirq_p_val = 0U;
	unsigned char irq_p_val = 0U;
	uint32_t irq_p = 0U;
	unsigned char pass = 1U;
	uint32_t first_cirq_found = 0U;
	uint32_t first_flushed_cirq;
	uint32_t first_irq_flushedto;
	uint32_t last_fluashed_cirq;
	uint32_t last_irq_flushedto;

	if (cirq_pattern_clone_flush_check_val == 1U) {
		if (cirq_pattern_list < CIRQ_IRQ_NUM) {
			mt_cirq_unmask(cirq_pattern_list);
			mt_cirq_set_sens(cirq_pattern_list,
				MT_CIRQ_EDGE_SENSITIVE);
			mt_cirq_set_pol(cirq_pattern_list, MT_CIRQ_POL_NEG);
			mt_cirq_set_pol(cirq_pattern_list, MT_CIRQ_POL_POS);
			mt_cirq_set_pol(cirq_pattern_list, MT_CIRQ_POL_NEG);
		} else {
			ERROR("[CIRQ] no pattern to test,");
			ERROR("input pattern first\n");
		}
		ERROR("[CIRQ] cirq_pattern %u, cirq_p %u,",
				cirq_pattern_list,
				mt_cirq_get_pending(cirq_pattern_list));
		ERROR("cirq_s %u, cirq_con 0x%x\n",
				mt_cirq_get_sens(cirq_pattern_list),
				mt_cirq_read32(CIRQ_CON));
	}

	mt_cirq_unmask_all();

	for (i = 0U; i < CIRQ_IRQ_NUM; i++) {
		cirq_p_val = mt_cirq_get_pending(i);
		if (cirq_p_val) {
			mt_irq_set_pending(CIRQ_TO_IRQ_NUM(i));
		}

		if (cirq_clone_flush_check_val == 1U) {
			if (cirq_p_val == 0U) {
				continue;
		}
			irq_p = CIRQ_TO_IRQ_NUM(i);
			irq_p_val = mt_irq_get_pending(irq_p);
			if (cirq_p_val != irq_p_val) {
				ERROR("[CIRQ] CIRQ Flush Failed ");
				ERROR("%u(cirq %d)!= %u(gic %d)\n",
					cirq_p_val, i, irq_p_val,
					CIRQ_TO_IRQ_NUM(i));
				pass = 0;
			} else {
				ERROR("[CIRQ] CIRQ Flush Pass ");
				ERROR("%u(cirq %d) = %u(gic %d)\n",
					cirq_p_val, i, irq_p_val,
					CIRQ_TO_IRQ_NUM(i));
			}
			if (!first_cirq_found) {
				first_flushed_cirq = i;
				first_irq_flushedto = irq_p;
				first_cirq_found = 1U;
			}
			last_fluashed_cirq = i;
			last_irq_flushedto = irq_p;
		}
	}

	if (cirq_clone_flush_check_val == 1U) {
		if (first_cirq_found) {
			ERROR("[CIRQ] The first flush : CIRQ%u to IRQ%u\n",
				first_flushed_cirq, first_irq_flushedto);
			ERROR("[CIRQ] The last flush : CIRQ%u to IRQ%u\n",
				last_fluashed_cirq, last_irq_flushedto);
		} else {
			ERROR("[CIRQ] There are no pending ");
			ERROR("interrupt in CIRQ\n");
			ERROR("[CIRQ] so no flush operation happened\n");
		}
		ERROR("[CIRQ] The Flush Max Range : CIRQ");
		ERROR("%d to IRQ%d ~ CIRQ%d to IRQ%d\n", 0U,
			CIRQ_TO_IRQ_NUM(0U), CIRQ_IRQ_NUM - 1U,
			CIRQ_TO_IRQ_NUM(CIRQ_IRQ_NUM - 1U));
		ERROR("[CIRQ] Flush Check %s, Confirm:SPI_START_OFFSET:%d\n",
			pass == 1 ? "Pass" : "Failed", CIRQ_SPI_START);
	}
	mt_cirq_mask_all();
	mt_cirq_ack_all();
}

void mt_cirq_sw_reset(void)
{
	uint32_t st;

	st = mt_cirq_read32(CIRQ_CON);
	st |= (CIRQ_SW_RESET << CIRQ_CON_SW_RST_BITS);

	mt_cirq_write32(st, CIRQ_CON);
}

void set_wakeup_sources(uint32_t *list, uint32_t num_of_events)
{
	cirq_all_events.num_of_events = num_of_events;
	cirq_all_events.wakeup_events = list;
}