aboutsummaryrefslogtreecommitdiff
path: root/plat/mediatek/mt6795/plat_mt_gic.c
blob: 20cb26d5ee205ca78355d16f1f0dabb0a4dc9a16 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
/*
 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <platform_def.h>

#include <common/interrupt_props.h>
#include <drivers/arm/gicv2.h>
#include <plat/common/platform.h>

static const interrupt_prop_t g0_interrupt_props[] = {
	INTR_PROP_DESC(FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY,
		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};

gicv2_driver_data_t arm_gic_data = {
	.gicd_base = BASE_GICD_BASE,
	.gicc_base = BASE_GICC_BASE,
	.interrupt_props = g0_interrupt_props,
	.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};

void plat_mt_gic_driver_init(void)
{
	gicv2_driver_init(&arm_gic_data);
}

void plat_mt_gic_init(void)
{
	gicv2_distif_init();
	gicv2_pcpu_distif_init();
	gicv2_cpuif_enable();
}

void plat_mt_gic_cpuif_enable(void)
{
	gicv2_cpuif_enable();
}

void plat_mt_gic_cpuif_disable(void)
{
	gicv2_cpuif_disable();
}

void plat_mt_gic_pcpu_init(void)
{
	gicv2_pcpu_distif_init();
}