aboutsummaryrefslogtreecommitdiff
path: root/drivers/st/gpio/stm32_gpio.c
blob: 9591e3738d3d922ce450dbbd50c62e78ee3731b6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
/*
 * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <stdbool.h>

#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/st/stm32_gpio.h>
#include <lib/mmio.h>

static bool check_gpio(uint32_t bank, uint32_t pin)
{
	if (pin > GPIO_PIN_MAX) {
		ERROR("%s: wrong pin number (%d)\n", __func__, pin);
		return false;
	}

	if ((bank > GPIO_BANK_K) && (bank != GPIO_BANK_Z)) {
		ERROR("%s: wrong GPIO bank number (%d)\n", __func__, bank);
		return false;
	}

	return true;
}

void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
	      uint32_t pull, uint32_t alternate)
{
	volatile uint32_t bank_address;

	if (!check_gpio(bank, pin)) {
		return;
	}

	if (bank == GPIO_BANK_Z) {
		bank_address = STM32_GPIOZ_BANK;
	} else {
		bank_address = STM32_GPIOA_BANK +
			(bank * STM32_GPIO_BANK_OFFSET);
	}

	mmio_clrbits_32(bank_address + GPIO_MODE_OFFSET,
			((uint32_t)GPIO_MODE_MASK << (pin << 1)));
	mmio_setbits_32(bank_address + GPIO_MODE_OFFSET,
			(mode & ~GPIO_OPEN_DRAIN) << (pin << 1));

	if ((mode & GPIO_OPEN_DRAIN) != 0U) {
		mmio_setbits_32(bank_address + GPIO_TYPE_OFFSET,
				BIT(pin));
	}

	mmio_clrbits_32(bank_address + GPIO_SPEED_OFFSET,
			((uint32_t)GPIO_SPEED_MASK << (pin << 1)));
	mmio_setbits_32(bank_address + GPIO_SPEED_OFFSET, speed << (pin << 1));

	mmio_clrbits_32(bank_address + GPIO_PUPD_OFFSET,
			((uint32_t)GPIO_PULL_MASK << (pin << 1)));
	mmio_setbits_32(bank_address + GPIO_PUPD_OFFSET, pull << (pin << 1));

	if (pin < GPIO_ALT_LOWER_LIMIT) {
		mmio_clrbits_32(bank_address + GPIO_AFRL_OFFSET,
				((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2)));
		mmio_setbits_32(bank_address + GPIO_AFRL_OFFSET,
				alternate << (pin << 2));
	} else {
		mmio_clrbits_32(bank_address + GPIO_AFRH_OFFSET,
				((uint32_t)GPIO_ALTERNATE_MASK <<
				 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)));
		mmio_setbits_32(bank_address + GPIO_AFRH_OFFSET,
				alternate << ((pin - GPIO_ALT_LOWER_LIMIT) <<
					      2));
	}

	VERBOSE("GPIO %u mode set to 0x%x\n", bank,
		mmio_read_32(bank_address + GPIO_MODE_OFFSET));
	VERBOSE("GPIO %u speed set to 0x%x\n", bank,
		mmio_read_32(bank_address + GPIO_SPEED_OFFSET));
	VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
		mmio_read_32(bank_address + GPIO_PUPD_OFFSET));
	VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank,
		mmio_read_32(bank_address + GPIO_AFRL_OFFSET));
	VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
		mmio_read_32(bank_address + GPIO_AFRH_OFFSET));
}