aboutsummaryrefslogtreecommitdiff
path: root/drivers/marvell/mochi/cp110_setup.c
blob: d7d7373180bcf87bb26615dd41e38b61e41afa01 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
/*
 * Copyright (C) 2018 Marvell International Ltd.
 *
 * SPDX-License-Identifier:     BSD-3-Clause
 * https://spdx.org/licenses
 */

/* CP110 Marvell SoC driver */

#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <drivers/marvell/amb_adec.h>
#include <drivers/marvell/iob.h>
#include <drivers/marvell/mochi/cp110_setup.h>

#include <plat_marvell.h>

/*
 * AXI Configuration.
 */

 /* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */
#define MVEBU_AXI_ATTR_OFFSET			(0x441300)
#define MVEBU_AXI_ATTR_REG(index)		(MVEBU_AXI_ATTR_OFFSET + \
							0x4 * index)

/* AXI Protection bits */
#define MVEBU_AXI_PROT_OFFSET				(0x441200)

/* AXI Protection regs */
#define MVEBU_AXI_PROT_REG(index)		((index <= 4) ? \
						(MVEBU_AXI_PROT_OFFSET + \
							0x4 * index) : \
						(MVEBU_AXI_PROT_OFFSET + 0x18))
#define MVEBU_AXI_PROT_REGS_NUM			(6)

#define MVEBU_SOC_CFGS_OFFSET			(0x441900)
#define MVEBU_SOC_CFG_REG(index)		(MVEBU_SOC_CFGS_OFFSET + \
							0x4 * index)
#define MVEBU_SOC_CFG_REG_NUM			(0)
#define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK	(0xE)

/* SATA3 MBUS to AXI regs */
#define MVEBU_BRIDGE_WIN_DIS_REG		(MVEBU_SOC_CFGS_OFFSET + 0x10)
#define MVEBU_BRIDGE_WIN_DIS_OFF		(0x0)

/* SATA3 MBUS to AXI regs */
#define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG	(0x54ff04)

/* AXI to MBUS bridge registers */
#define MVEBU_AMB_IP_OFFSET			(0x13ff00)
#define MVEBU_AMB_IP_BRIDGE_WIN_REG(win)	(MVEBU_AMB_IP_OFFSET + \
							(win * 0x8))
#define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET	0
#define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK		\
				(0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET	16
#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK	\
				(0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)

#define MVEBU_SAMPLE_AT_RESET_REG	(0x440600)
#define SAR_PCIE1_CLK_CFG_OFFSET	31
#define SAR_PCIE1_CLK_CFG_MASK		(0x1 << SAR_PCIE1_CLK_CFG_OFFSET)
#define SAR_PCIE0_CLK_CFG_OFFSET	30
#define SAR_PCIE0_CLK_CFG_MASK		(0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
#define SAR_I2C_INIT_EN_OFFSET		24
#define SAR_I2C_INIT_EN_MASK		(1 << SAR_I2C_INIT_EN_OFFSET)

/*******************************************************************************
 * PCIE clock buffer control
 ******************************************************************************/
#define MVEBU_PCIE_REF_CLK_BUF_CTRL			(0x4404F0)
#define PCIE1_REFCLK_BUFF_SOURCE			0x800
#define PCIE0_REFCLK_BUFF_SOURCE			0x400

/*******************************************************************************
 * MSS Device Push Set Register
 ******************************************************************************/
#define MVEBU_CP_MSS_DPSHSR_REG				(0x280040)
#define MSS_DPSHSR_REG_PCIE_CLK_SEL			0x8

/*******************************************************************************
 * RTC Configuration
 ******************************************************************************/
#define MVEBU_RTC_BASE					(0x284000)
#define MVEBU_RTC_STATUS_REG				(MVEBU_RTC_BASE + 0x0)
#define MVEBU_RTC_STATUS_ALARM1_MASK			0x1
#define MVEBU_RTC_STATUS_ALARM2_MASK			0x2
#define MVEBU_RTC_IRQ_1_CONFIG_REG			(MVEBU_RTC_BASE + 0x4)
#define MVEBU_RTC_IRQ_2_CONFIG_REG			(MVEBU_RTC_BASE + 0x8)
#define MVEBU_RTC_TIME_REG				(MVEBU_RTC_BASE + 0xC)
#define MVEBU_RTC_ALARM_1_REG				(MVEBU_RTC_BASE + 0x10)
#define MVEBU_RTC_ALARM_2_REG				(MVEBU_RTC_BASE + 0x14)
#define MVEBU_RTC_CCR_REG				(MVEBU_RTC_BASE + 0x18)
#define MVEBU_RTC_NOMINAL_TIMING			0x2000
#define MVEBU_RTC_NOMINAL_TIMING_MASK			0x7FFF
#define MVEBU_RTC_TEST_CONFIG_REG			(MVEBU_RTC_BASE + 0x1C)
#define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG		(MVEBU_RTC_BASE + 0x80)
#define MVEBU_RTC_WRCLK_PERIOD_MASK			0xFFFF
#define MVEBU_RTC_WRCLK_PERIOD_DEFAULT			0x3FF
#define MVEBU_RTC_WRCLK_SETUP_OFFS			16
#define MVEBU_RTC_WRCLK_SETUP_MASK			0xFFFF0000
#define MVEBU_RTC_WRCLK_SETUP_DEFAULT			0x29
#define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG		(MVEBU_RTC_BASE + 0x84)
#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK		0xFFFF
#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT		0x1F

enum axi_attr {
	AXI_ADUNIT_ATTR = 0,
	AXI_COMUNIT_ATTR,
	AXI_EIP197_ATTR,
	AXI_USB3D_ATTR,
	AXI_USB3H0_ATTR,
	AXI_USB3H1_ATTR,
	AXI_SATA0_ATTR,
	AXI_SATA1_ATTR,
	AXI_DAP_ATTR,
	AXI_DFX_ATTR,
	AXI_DBG_TRC_ATTR = 12,
	AXI_SDIO_ATTR,
	AXI_MSS_ATTR,
	AXI_MAX_ATTR,
};

/* Most stream IDS are configured centrally in the CP-110 RFU
 * but some are configured inside the unit registers
 */
#define RFU_STREAM_ID_BASE	(0x450000)
#define USB3H_0_STREAM_ID_REG	(RFU_STREAM_ID_BASE + 0xC)
#define USB3H_1_STREAM_ID_REG	(RFU_STREAM_ID_BASE + 0x10)
#define SATA_0_STREAM_ID_REG	(RFU_STREAM_ID_BASE + 0x14)
#define SATA_1_STREAM_ID_REG	(RFU_STREAM_ID_BASE + 0x18)

#define CP_DMA_0_STREAM_ID_REG  (0x6B0010)
#define CP_DMA_1_STREAM_ID_REG  (0x6D0010)

/* We allocate IDs 128-255 for PCIe */
#define MAX_STREAM_ID		(0x80)

uintptr_t stream_id_reg[] = {
	USB3H_0_STREAM_ID_REG,
	USB3H_1_STREAM_ID_REG,
	CP_DMA_0_STREAM_ID_REG,
	CP_DMA_1_STREAM_ID_REG,
	SATA_0_STREAM_ID_REG,
	SATA_1_STREAM_ID_REG,
	0
};

static void cp110_errata_wa_init(uintptr_t base)
{
	uint32_t data;

	/* ERRATA GL-4076863:
	 * Reset value for global_secure_enable inputs must be changed
	 * from '1' to '0'.
	 * When asserted, only "secured" transactions can enter IHB
	 * configuration space.
	 * However, blocking AXI transactions is performed by IOB.
	 * Performing it also at IHB/HB complicates programming model.
	 *
	 * Enable non-secure access in SOC configuration register
	 */
	data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM));
	data &= ~MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK;
	mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data);
}

static void cp110_pcie_clk_cfg(uintptr_t base)
{
	uint32_t pcie0_clk, pcie1_clk, reg;

	/*
	 * Determine the pcie0/1 clock direction (input/output) from the
	 * sample at reset.
	 */
	reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG);
	pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET;
	pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET;

	/* CP110 revision A2 */
	if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) {
		/*
		 * PCIe Reference Clock Buffer Control register must be
		 * set according to the clock direction (input/output)
		 */
		reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL);
		reg &= ~(PCIE0_REFCLK_BUFF_SOURCE | PCIE1_REFCLK_BUFF_SOURCE);
		if (!pcie0_clk)
			reg |= PCIE0_REFCLK_BUFF_SOURCE;
		if (!pcie1_clk)
			reg |= PCIE1_REFCLK_BUFF_SOURCE;

		mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg);
	}

	/* CP110 revision A1 */
	if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) {
		if (!pcie0_clk || !pcie1_clk) {
			/*
			 * if one of the pcie clocks is set to input,
			 * we need to set mss_push[131] field, otherwise,
			 * the pcie clock might not work.
			 */
			reg = mmio_read_32(base + MVEBU_CP_MSS_DPSHSR_REG);
			reg |= MSS_DPSHSR_REG_PCIE_CLK_SEL;
			mmio_write_32(base + MVEBU_CP_MSS_DPSHSR_REG, reg);
		}
	}
}

/* Set a unique stream id for all DMA capable devices */
static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id)
{
	int i = 0;

	while (stream_id_reg[i]) {
		if (i > MAX_STREAM_ID_PER_CP) {
			NOTICE("Only first %d (maximum) Stream IDs allocated\n",
			       MAX_STREAM_ID_PER_CP);
			return;
		}

		if ((stream_id_reg[i] == CP_DMA_0_STREAM_ID_REG) ||
		    (stream_id_reg[i] == CP_DMA_1_STREAM_ID_REG))
			mmio_write_32(base + stream_id_reg[i],
				      stream_id << 16 |  stream_id);
		else
			mmio_write_32(base + stream_id_reg[i], stream_id);

		/* SATA port 0/1 are in the same SATA unit, and they should use
		 * the same STREAM ID number
		 */
		if (stream_id_reg[i] != SATA_0_STREAM_ID_REG)
			stream_id++;

		i++;
	}
}

static void cp110_axi_attr_init(uintptr_t base)
{
	uint32_t index, data;

	/* Initialize AXI attributes for Armada-7K/8K SoC */

	/* Go over the AXI attributes and set Ax-Cache and Ax-Domain */
	for (index = 0; index < AXI_MAX_ATTR; index++) {
		switch (index) {
		/* DFX and MSS unit works with no coherent only -
		 * there's no option to configure the Ax-Cache and Ax-Domain
		 */
		case AXI_DFX_ATTR:
		case AXI_MSS_ATTR:
			continue;
		default:
			/* Set Ax-Cache as cacheable, no allocate, modifiable,
			 * bufferable
			 * The values are different because Read & Write
			 * definition is different in Ax-Cache
			 */
			data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index));
			data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK;
			data |= (CACHE_ATTR_WRITE_ALLOC |
				 CACHE_ATTR_CACHEABLE   |
				 CACHE_ATTR_BUFFERABLE) <<
				 MVEBU_AXI_ATTR_ARCACHE_OFFSET;
			data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK;
			data |= (CACHE_ATTR_READ_ALLOC |
				 CACHE_ATTR_CACHEABLE  |
				 CACHE_ATTR_BUFFERABLE) <<
				 MVEBU_AXI_ATTR_AWCACHE_OFFSET;
			/* Set Ax-Domain as Outer domain */
			data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK;
			data |= DOMAIN_OUTER_SHAREABLE <<
				MVEBU_AXI_ATTR_ARDOMAIN_OFFSET;
			data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK;
			data |= DOMAIN_OUTER_SHAREABLE <<
				MVEBU_AXI_ATTR_AWDOMAIN_OFFSET;
			mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data);
		}
	}

	/* SATA IOCC supported, cache attributes
	 * for SATA MBUS to AXI configuration.
	 */
	data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG);
	data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK;
	data |= (CACHE_ATTR_WRITE_ALLOC |
		 CACHE_ATTR_CACHEABLE   |
		 CACHE_ATTR_BUFFERABLE) <<
		 MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET;
	data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK;
	data |= (CACHE_ATTR_READ_ALLOC |
		 CACHE_ATTR_CACHEABLE  |
		 CACHE_ATTR_BUFFERABLE) <<
		 MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET;
	mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data);

	/* Set all IO's AXI attribute to non-secure access. */
	for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++)
		mmio_write_32(base + MVEBU_AXI_PROT_REG(index),
			      DOMAIN_SYSTEM_SHAREABLE);
}

static void amb_bridge_init(uintptr_t base)
{
	uint32_t reg;

	/* Open AMB bridge Window to Access COMPHY/MDIO registers */
	reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0));
	reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK |
		 MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK);
	reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) |
	       (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET);
	mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg);
}

static void cp110_rtc_init(uintptr_t base)
{
	/* Update MBus timing parameters before accessing RTC registers */
	mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,
			   MVEBU_RTC_WRCLK_PERIOD_MASK,
			   MVEBU_RTC_WRCLK_PERIOD_DEFAULT);

	mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,
			   MVEBU_RTC_WRCLK_SETUP_MASK,
			   MVEBU_RTC_WRCLK_SETUP_DEFAULT <<
			   MVEBU_RTC_WRCLK_SETUP_OFFS);

	mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG,
			   MVEBU_RTC_READ_OUTPUT_DELAY_MASK,
			   MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT);

	/*
	 * Issue reset to the RTC if Clock Correction register
	 * contents did not sustain the reboot/power-on.
	 */
	if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) &
	    MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) {
		/* Reset Test register */
		mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0);
		mdelay(500);

		/* Reset Status register */
		mmio_write_32(base + MVEBU_RTC_STATUS_REG,
			      (MVEBU_RTC_STATUS_ALARM1_MASK |
			      MVEBU_RTC_STATUS_ALARM2_MASK));
		udelay(62);

		/* Turn off Int1 and Int2 sources & clear the Alarm count */
		mmio_write_32(base + MVEBU_RTC_IRQ_1_CONFIG_REG, 0);
		mmio_write_32(base + MVEBU_RTC_IRQ_2_CONFIG_REG, 0);
		mmio_write_32(base + MVEBU_RTC_ALARM_1_REG, 0);
		mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0);

		/* Setup nominal register access timing */
		mmio_write_32(base + MVEBU_RTC_CCR_REG,
			      MVEBU_RTC_NOMINAL_TIMING);

		/* Reset Status register */
		mmio_write_32(base + MVEBU_RTC_STATUS_REG,
			      (MVEBU_RTC_STATUS_ALARM1_MASK |
			      MVEBU_RTC_STATUS_ALARM2_MASK));
		udelay(50);
	}
}

static void cp110_amb_adec_init(uintptr_t base)
{
	/* enable AXI-MBUS by clearing "Bridge Windows Disable" */
	mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG,
			(1 << MVEBU_BRIDGE_WIN_DIS_OFF));

	/* configure AXI-MBUS windows for CP */
	init_amb_adec(base);
}

void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
{
	INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);

	/* configure IOB windows for CP0*/
	init_iob(cp110_base);

	/* configure AXI-MBUS windows for CP0*/
	cp110_amb_adec_init(cp110_base);

	/* configure axi for CP0*/
	cp110_axi_attr_init(cp110_base);

	/* Execute SW WA for erratas */
	cp110_errata_wa_init(cp110_base);

	/* Confiure pcie clock according to clock direction */
	cp110_pcie_clk_cfg(cp110_base);

	/* configure stream id for CP0 */
	cp110_stream_id_init(cp110_base, stream_id);

	/* Open AMB bridge for comphy for CP0 & CP1*/
	amb_bridge_init(cp110_base);

	/* Reset RTC if needed */
	cp110_rtc_init(cp110_base);
}

/* Do the minimal setup required to configure the CP in BLE */
void cp110_ble_init(uintptr_t cp110_base)
{
#if PCI_EP_SUPPORT
	INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);

	amb_bridge_init(cp110_base);

	/* Configure PCIe clock */
	cp110_pcie_clk_cfg(cp110_base);

	/* Configure PCIe endpoint */
	ble_plat_pcie_ep_setup();
#endif
}