/* * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ motherboard { arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; #interrupt-cells = <1>; ranges; flash@0,00000000 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; bank-width = <4>; }; vram@2,00000000 { compatible = "arm,vexpress-vram"; reg = <2 0x00000000 0x00800000>; }; ethernet@2,02000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; }; v2m_clk24mhz: clk24mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; v2m_refclk1mhz: refclk1mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; v2m_refclk32khz: refclk32khz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "v2m:refclk32khz"; }; iofpga@3,00000000 { compatible = "arm,amba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 3 0 0x200000>; v2m_sysreg: sysreg@10000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; gpio-controller; #gpio-cells = <2>; }; v2m_sysctl: sysctl@20000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; }; aaci@40000 { compatible = "arm,pl041", "arm,primecell"; reg = <0x040000 0x1000>; interrupts = <11>; clocks = <&v2m_clk24mhz>; clock-names = "apb_pclk"; }; mmci@50000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; interrupts = <9 10>; cd-gpios = <&v2m_sysreg 0 0>; wp-gpios = <&v2m_sysreg 1 0>; max-frequency = <12000000>; vmmc-supply = <&v2m_fixed_3v3>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "mclk", "apb_pclk"; }; kmi@60000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x060000 0x1000>; interrupts = <12>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "KMIREFCLK", "apb_pclk"; }; kmi@70000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x070000 0x1000>; interrupts = <13>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "KMIREFCLK", "apb_pclk"; }; v2m_serial0: uart@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial1: uart@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial2: uart@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial3: uart@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; wdt@f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; clock-names = "wdogclk", "apb_pclk"; }; v2m_timer01: timer@110000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x110000 0x1000>; interrupts = <2>; clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; v2m_timer23: timer@120000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x120000 0x1000>; interrupts = <3>; clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; rtc@170000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x170000 0x1000>; interrupts = <4>; clocks = <&v2m_clk24mhz>; clock-names = "apb_pclk"; }; clcd@1f0000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x1f0000 0x1000>; interrupts = <14>; clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; clock-names = "clcdclk", "apb_pclk"; mode = "XVGA"; use_dma = <0>; framebuffer = <0x18000000 0x00180000>; }; virtio_block@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x1000>; interrupts = <0x2a>; }; }; v2m_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; mcc { compatible = "arm,vexpress,config-bus", "simple-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; v2m_oscclk1: osc@1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; freq-range = <23750000 63500000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; /* * Not supported in FVP models * * reset@0 { * compatible = "arm,vexpress-reset"; * arm,vexpress-sysreg,func = <5 0>; * }; */ muxfpga@0 { compatible = "arm,vexpress-muxfpga"; arm,vexpress-sysreg,func = <7 0>; }; /* * Not used - Superseded by PSCI sys_poweroff * * shutdown@0 { * compatible = "arm,vexpress-shutdown"; * arm,vexpress-sysreg,func = <8 0>; * }; */ /* * Not used - Superseded by PSCI sys_reset * * reboot@0 { * compatible = "arm,vexpress-reboot"; * arm,vexpress-sysreg,func = <9 0>; * }; */ dvimode@0 { compatible = "arm,vexpress-dvimode"; arm,vexpress-sysreg,func = <11 0>; }; }; };