aboutsummaryrefslogtreecommitdiff
path: root/plat/nvidia/tegra/soc/t186
AgeCommit message (Collapse)Author
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-12-18Tegra: support for native GICv2 driversVarun Wadekar
This patch converts Tegra platforms to support native GICv2 drivers. This involves removes Tegra's GIC driver port platforms to use interrupt_props Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-11-08Standardise header guards across codebaseAntonio Nino Diaz
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28tegra: Migrate to new interfacesAntonio Nino Diaz
- Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. - Replace zeromem16() by zeromem(). - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I67fbf2206678be80c3a16692024221a131cec42f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-22libc: Fix all includes in codebaseAntonio Nino Diaz
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-04-27types: use int-ll64 for both aarch32 and aarch64Masahiro Yamada
Since commit 031dbb122472 ("AArch32: Add essential Arch helpers"), it is difficult to use consistent format strings for printf() family between aarch32 and aarch64. For example, uint64_t is defined as 'unsigned long long' for aarch32 and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64. A problem typically arises when you use printf() in common code. One solution could be, to cast the arguments to a type long enough for both architectures. For example, if 'val' is uint64_t type, like this: printf("val = %llx\n", (unsigned long long)val); Or, somebody may suggest to use a macro provided by <inttypes.h>, like this: printf("val = %" PRIx64 "\n", val); But, both would make the code ugly. The solution adopted in Linux kernel is to use the same typedefs for all architectures. The fixed integer types in the kernel-space have been unified into int-ll64, like follows: typedef signed char int8_t; typedef unsigned char uint8_t; typedef signed short int16_t; typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; [ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ] This gets along with the codebase shared between 32 bit and 64 bit, with the data model called ILP32, LP64, respectively. The width for primitive types is defined as follows: ILP32 LP64 int 32 32 long 32 64 long long 64 64 pointer 32 64 'long long' is 64 bit for both, so it is used for defining uint64_t. 'long' has the same width as pointer, so for uintptr_t. We still need an ifdef conditional for (s)size_t. All 64 bit architectures use "unsigned long" size_t, and most 32 bit architectures use "unsigned int" size_t. H8/300, S/390 are known as exceptions; they use "unsigned long" size_t despite their architecture is 32 bit. One idea for simplification might be to define size_t as 'unsigned long' across architectures, then forbid the use of "%z" string format. However, this would cause a distortion between size_t and sizeof() operator. We have unknowledge about the native type of sizeof(), so we need a guess of it anyway. I want the following formula to always return 1: __builtin_types_compatible_p(size_t, typeof(sizeof(int))) Fortunately, ARM is probably a majority case. As far as I know, all 32 bit ARM compilers use "unsigned int" size_t. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-08tegra: Use SPDX license identifierAntonio Nino Diaz
Change-Id: I770b2db68c8d115d10067bb557e32b5e269c94a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-02-17tegra: Fix mmap_region_t struct mismatchAndreas Färber
Commit fdb1964c34968921379d3592e7ac6e9a685dbab1 ("xlat: Introduce MAP_REGION2() macro") added a granularity field to mmap_region_t. Tegra platforms were using the v2 xlat_tables implementation in common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c where arrays are being defined. This caused the next physical address to be read as granularity, causing EINVAL error and triggering an assert. Consistently use xlat_tables_v2.h header to avoid this. Fixes ARM-software/tf-issues#548. Signed-off-by: Andreas Färber <afaerber@suse.de>
2017-09-21Fix type of `unsigned long` constantsAntonio Nino Diaz
The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in AArch64. This is inconsistent and that's why we avoid using it as per the Coding Guidelines. This patch changes all `UL` occurrences to `U` or `ULL` depending on the context so that the size of the constant is clear. This problem affected the macro `BIT(nr)`. As long as this macro is used to fill fields of registers, that's not a problem, since all registers are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the macro is used to fill the fields of a 64-bit integer, it won't be able to set the upper 32 bits in AArch32. By changing the type of this macro to `unsigned long long` the behaviour is always the same regardless of the architecture, as this type is 64-bit wide in both cases. Some Tegra platform files have been modified by this patch. Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-08-15Add new alignment parameter to func assembler macroJulius Werner
Assembler programmers are used to being able to define functions with a specific aligment with a pattern like this: .align X myfunction: However, this pattern is subtly broken when instead of a direct label like 'myfunction:', you use the 'func myfunction' macro that's standard in Trusted Firmware. Since the func macro declares a new section for the function, the .align directive written above it actually applies to the *previous* section in the assembly file, and the function it was supposed to apply to is linked with default alignment. An extreme case can be seen in Rockchip's plat_helpers.S which contains this code: [...] endfunc plat_crash_console_putc .align 16 func platform_cpu_warmboot [...] This assembles into the following plat_helpers.o: Sections: Idx Name Size [...] Algn 9 .text.plat_crash_console_putc 00010000 [...] 2**16 10 .text.platform_cpu_warmboot 00000080 [...] 2**3 As can be seen, the *previous* function actually got the alignment constraint, and it is also 64KB big even though it contains only two instructions, because the .align directive at the end of its section forces the assembler to insert a giant sled of NOPs. The function we actually wanted to align has the default constraint. This code only works at all because the linker just happens to put the two functions right behind each other when linking the final image, and since the end of plat_crash_console_putc is aligned the start of platform_cpu_warmboot will also be. But it still wastes almost 64KB of image space unnecessarily, and it will break under certain circumstances (e.g. if the plat_crash_console_putc function becomes unused and its section gets garbage-collected out). There's no real way to fix this with the existing func macro. Code like func myfunc .align X happens to do the right thing, but is still not really correct code (because the function label is inserted before the .align directive, so the assembler is technically allowed to insert padding at the beginning of the function which would then get executed as instructions if the function was called). Therefore, this patch adds a new parameter with a default value to the func macro that allows overriding its alignment. Also fix up all existing instances of this dangerous antipattern. Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10 Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-07-14Fix order of remaining platform #includesIsla Mitchell
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-06-14Tegra186: mce: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] * Added parentheses [Rule 12.1] * Voided non C-library functions whose return types are not used [Rule 17.7] Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: enable 'signed-comparison' compilation warning/errorsVarun Wadekar
This patch enables the 'sign-compare' flag, to enable warning/errors for comparisons between signed/unsigned variables. The warning has been enabled for all the Tegra platforms, to start with. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-01Tegra186: calculate proper power state for cluster/system power downVarun Wadekar
Earlier, we were setting "System Suspend" as the power state for all system states. This caused incorrect system state during a cluster power down. This patch fixes this anomaly and sets the correct power state during a cluster/system power down. Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra186: mce: max retries for ARI requestsSteven Kao
This patch adds max retries for all ARI requests and asserts if the ARI request is still busy. Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-21Merge pull request #912 from vwadekar/tegra-smmu-ctx-save-robustdavidcunado-arm
Tegra: smmu: make the context save sequence robust
2017-04-20Tegra: smmu: make the context save sequence robustVarun Wadekar
This patch sanity checks the SMMU context created by the platform code. The first entry contains the size of the array; which the driver now verifies before moving on with the save. This patch also fixes an error in the calculation of the size of the context that gets copied to TZDRAM. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-17Tegra186: Support AARCH32/64 encoding for MCE callsVarun Wadekar
On Tegra systems, there are multiple software components that require to interact with MCE. The components can either be 32-bit or 64-bit payloads. This patch supports MCE SMC functions ID for AARCH32 and AARCH64 architectures to support such clients. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: fix trivial misra issuesAnthony Zhou
Not having U or ULL as a suffix for these enums causes a lot of unnecessary MISRA issues. This patch adds U or ULL suffix to these common enums to reduce number of MISRA issues. Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra186: mce: Avoid implementation-defined bitfield typesStephen Warren
GCC version 4.8 (and presumably earlier) warn when non-standard types are used for bitfield definitions when -pedantic is enabled. This prevents TF from being built with such toolchains, since -Werror -pedantic options are used. gcc-4.9 removed this warning; -pedantic is intended to cause gcc to emit a warning in all cases required by the standard, but the standard does not require a warning in this case. See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57773 Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-04-13Tegra: smmu: support for multiple devicesPritesh Raithatha
This patch adds flexibility to the code to initialise multiple SMMU devices. The base address macro name has been changed to make it explicit that we support multiple SMMUs. Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: smmu: platform handler for SMMU settingsPritesh Raithatha
This patch empowers the platforms to provide an array with the registers that must be saved/restored across System Suspend. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra: allow platforms to override plat_core_pos_by_mpidr()Varun Wadekar
This patch makes the default implementation of plat_core_pos_by_mpidr() as weakly linked, so that platforms can override it with their own. Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own implementation of plat_core_pos_by_mpidr(). Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra: memctrl_v2: platform handler for MC settingsPritesh Raithatha
This patch empowers the platforms to provide the settings (e.g. stream ID, security setting, transaction overrides) required by the Memory Controller driver. This allows the platforms to program the Memory Controller as per their needs and makes the driver scalable. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: mce: support for TEGRA_ARI_MISC_CCPLEX_EDBGREQRich Wiley
This ARI call enables the EDBGREQ feature in the CCPLEX, which will cause the CPUs to enter debug state instead of vectoring to sw (ie MCA handler) upon receiving an async abort signal. Change-Id: Ifcb0e11446b6ac55179e3350d8f02b60ba32c94d Signed-off-by: Rich Wiley <rwiley@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: update t18x_ari.h to v3.1Varun Wadekar
This patch updates the ARI header file to v3.1. Change-Id: I3e58cf50d27fb6e72062bb9d9782b75296b32025 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: PSCI: support for 64-bit TZDRAM baseSteven Kao
This patch fixes the variable width to store the TZDRAM base address used to resume from System Suspend. Change-Id: Ib67eda64b09f26fb2f427f0d624f057081473132 Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra: memctrl_v2: config to enable SMMU deviceVarun Wadekar
This patch adds a config to the memory controller driver to enable SMMU device init during boot. Tegra186 platforms keeps it enabled by default, but future platforms might not support it. Change-Id: Iebe1c60a25fc1cfb4c97a507e121d6685a49cb83 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: read activity monitor's clock counter valuesVarun Wadekar
This patch adds a new SMC function ID to read the refclk and coreclk clock counter values from the Activity Monitor. The non-secure world requires this information to calculate the CPU's frequency. Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq" The following CPU registers have to be set by the non-secure driver before issuing the SMC: X1 = MPIDR of the target core X2 = MIDR of the target core Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra: memctrl_v2: make AFI device settings configurableVarun Wadekar
This patch adds a new config to enable MC settings for the AFIW and AFIR devices. Platforms must enable this config on their own. Change-Id: I53b450117e4764ea76d9347ee2928f9be178b107 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: move smmu driver to tegra/commonVarun Wadekar
This patch moves the smmu driver introduced by the Tegra186 port to tegra/common so that future chips can (re)use it. Change-Id: Ia44c7f2a62fb2d8869db3a44742a8c6b13c49036 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: split MCE driver into public/private interfacesVarun Wadekar
This patch splits the MCE driver into public and private interfaces to allow usage of common functionality across multiple SoCs. Change-Id: Ib58080e730d72f11ff79507d8e0acffb2ad5c606 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: move platform specific MCE defines to tegra_def.hVarun Wadekar
This patch moves the MCE's configurable parameters to tegra_def.h for the Tegra186 SoC, to allow forward compatiblity. Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: use MSB of wake_timeKrishna Sitaraman
This patch updates wake time of the cpu to use the MSBs and zero out the LSB's. Only 24 out of 32 bits are currently passed through the PSCI interface. Previously all the LSB's were used. Change-Id: Ie2d9d1bf6e3003dd47526a124f64e6ad555d2371 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: Update API for reset vector ARIKrishna Sitaraman
The TEGRA_ARI_COPY_MISCREG_AA64_RST ARI should be called with request_lo/hi set to zero. MTS automatically takes the reset vector from MISCREG_AA64_RST register and does not need it to be passed as parameters. This patch updates the API and the caller function accordingly. Change-Id: Ie3e3402d93951102239d988ca9f0cdf94f290d2f Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: clean CPU wake times from L2 cacheMustafa Yigit Bilgen
When entering C7, ATF disables caches and flushes the L1 cache. However, wake_time[cpu] can still remain in the L2 cache, causing later reads to it to fetch from DRAM. This will read stale values. Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it before disabling caches. Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: update t18x_ari.h to v3.0Krishna Sitaraman
This patch updates the ARI header to version 3.0 Change-Id: I7cfe0c61c80a6b78625232135dd63393602d32fe Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: trampoline: update "System Suspend" exit criteriaVarun Wadekar
The TZRAM memory loses its state during "System Suspend". This patch check if TZRAM base address contains valid data, to decide if the system is exiting from "System Suspend". To enable TZDRAM encryption, the Memory Controller's TZDRAM base/size registers would be populated by the BPMP when the system "wakes up". Change-Id: I5fc8ba1ae3bce12f0ece493f6f9f5f4d92a46344 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: Add smc handler for coresight clock gatingKrishna Sitaraman
This change adds function to invoke for MISC_CCPLEX ARI calls and the corresponding smc handler. This can be used to enable/disable Coresight clock gating. Change-Id: I4bc17aa478a46c29bfe17fd74f839a383ee2b644 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: mce: fix return value for enum features ariKrishna Sitaraman
This patch fixes the incorrect return value that was being passed back for the ENUM_FEATURES ARI call. Change-Id: I3842c6ce27ea24698608830cf4c12cfa7ff64421 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: mce: clear reserved fields for ARI callsKrishna Sitaraman
This patch clears the unused or reserved ARI input registers before issuing the actual ARI command. Change-Id: I454b86566bfe088049a5c63527c1323d7b25248a Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: mce: read MCE's firmware version on "real" platformsVarun Wadekar
This patch runs the MCE firmware's version check only if the underlying platform has the capability to the run the firmware. MCE firmware is not running on simulation platforms, identified by v0.3 or v0.6, read from the Tegra Chip ID value. Change-Id: I3b1788b1ee2a0d4464017bb879ac5792cb7022b8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: use helper functions to get major/minor versionVarun Wadekar
This patch uses helper functions to read the chips's major and minor version values. Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: memmap all UART controllersVarun Wadekar
This patch adds all the UART controllers to the memory map. Change-Id: I035e55ca7bff0a96115102f2295981f9e3a5da6b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: implement plat_get_syscnt_freq2()Varun Wadekar
Commit f3d3b316f82faa88e42f3d09c97cd9e52ac92599 replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all the upstream platforms. This patch modifies the Tegra186 code which is not present usptream, yet. Change-Id: Ieda6168050a7769680a3a94513637fed03463a2d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra: smmu: disable TCU prefetch for all the 64 contextsVarun Wadekar
This patch disables TCU prefetch for all the contexts in order to improve SMMU performance. Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: handlers to get BL31 arguments from previous bootloaderVarun Wadekar
This patch overrides the default handlers to get BL31 arguments from the previous bootloader. The previous bootloader stores the pointer to the arguments in PMC secure scratch register #53. BL31 is the first component running on the CPU, as there isn't a previous bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes that there are no input parameters passed by the previous bootloader. Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: delete 'Video Memory Carveout' handlingVarun Wadekar
This patch removes duplicate code from the platform's SiP handler routine for processing Video Memory Carveout region requests and uses the common SiP handler instead. Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>