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path: root/plat/nvidia/tegra/soc/t186/plat_trampoline.S
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2020-03-18Tegra186: system resume from TZSRAM memoryVarun Wadekar
TZSRAM loses power during System suspend, so the entire contents are copied to TZDRAM before Sysem Suspend entry. The warmboot code verifies and restores the contents to TZSRAM during System Resume. This patch removes the code that sets up CPU vector to point to TZSRAM during System Resume as a result. The trampoline code can also be completely removed as a result. Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-18Tegra186: disable PROGRAMMABLE_RESET_ADDRESSVarun Wadekar
This patch disables the code to program reset vector for secondary CPUs to a different entry point, than cold boot. The cold boot entry point has the ability to differentiate between a cold boot and a warm boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By reusing the same entry point, we can lock the CPU reset vector during cold boot. Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-11Tegra: smmu: remove context save sequencePritesh Raithatha
SMMU and MC registers are saved as part of the System Suspend sequence. The register list includes some NS world SMMU registers that need to be saved by NS world software instead. All that remains as a result are the MC registers. This patch moves code to MC file as a result and renames all the variables and defines to use the MC prefix instead of SMMU. The Tegra186 and Tegra194 platform ports are updated to provide the MC context register list to the parent driver. The memory required for context save is reduced due to removal of the SMMU registers. Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
2019-02-07Tegra186: trampoline: include bl_common.hVarun Wadekar
This patch includes bl_common.h from plat_trampoline.S to link with the __BL31_END__ symbol. Change-Id: Ie66c5009018472607db668583c9a0b3553f0ae73 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-23Tegra186: save system suspend entry marker to TZDRAMVarun Wadekar
This patch adds support to save the system suspend entry and exit markers to TZDRAM to help the trampoline code decide if the current warmboot is actually an exit from System Suspend. The Tegra186 platform handler sets the system suspend entry marker before entering SC7 state and the trampoline flips the state back to system resume, on exiting SC7. Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-23Tegra186: helper functions for CPU rst handler and SMMU ctx offsetVarun Wadekar
This patch adds a helper function to get the SMMU context's offset and uses another helper function to get the CPU trampoline offset. These helper functions are used by the System Suspend entry sequence to save the SMMU context and CPU reset handler to TZDRAM. Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-23Tegra186: secondary: fix MISRA violations for Rules 8.6, 11.1Varun Wadekar
This patch fixes the following MISRA violations: Rule 8.6: Externally-linked object or function has "no" definition(s). Rule 11.1: A cast shall not convert a pointer to a function to any other type. Change-Id: Ic1f6fc14c744e54ff782c6987dab9c9430410f5e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-08-15Add new alignment parameter to func assembler macroJulius Werner
Assembler programmers are used to being able to define functions with a specific aligment with a pattern like this: .align X myfunction: However, this pattern is subtly broken when instead of a direct label like 'myfunction:', you use the 'func myfunction' macro that's standard in Trusted Firmware. Since the func macro declares a new section for the function, the .align directive written above it actually applies to the *previous* section in the assembly file, and the function it was supposed to apply to is linked with default alignment. An extreme case can be seen in Rockchip's plat_helpers.S which contains this code: [...] endfunc plat_crash_console_putc .align 16 func platform_cpu_warmboot [...] This assembles into the following plat_helpers.o: Sections: Idx Name Size [...] Algn 9 .text.plat_crash_console_putc 00010000 [...] 2**16 10 .text.platform_cpu_warmboot 00000080 [...] 2**3 As can be seen, the *previous* function actually got the alignment constraint, and it is also 64KB big even though it contains only two instructions, because the .align directive at the end of its section forces the assembler to insert a giant sled of NOPs. The function we actually wanted to align has the default constraint. This code only works at all because the linker just happens to put the two functions right behind each other when linking the final image, and since the end of plat_crash_console_putc is aligned the start of platform_cpu_warmboot will also be. But it still wastes almost 64KB of image space unnecessarily, and it will break under certain circumstances (e.g. if the plat_crash_console_putc function becomes unused and its section gets garbage-collected out). There's no real way to fix this with the existing func macro. Code like func myfunc .align X happens to do the right thing, but is still not really correct code (because the function label is inserted before the .align directive, so the assembler is technically allowed to insert padding at the beginning of the function which would then get executed as instructions if the function was called). Therefore, this patch adds a new parameter with a default value to the func macro that allows overriding its alignment. Also fix up all existing instances of this dangerous antipattern. Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10 Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-20Tegra: smmu: make the context save sequence robustVarun Wadekar
This patch sanity checks the SMMU context created by the platform code. The first entry contains the size of the array; which the driver now verifies before moving on with the save. This patch also fixes an error in the calculation of the size of the context that gets copied to TZDRAM. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: trampoline: update "System Suspend" exit criteriaVarun Wadekar
The TZRAM memory loses its state during "System Suspend". This patch check if TZRAM base address contains valid data, to decide if the system is exiting from "System Suspend". To enable TZDRAM encryption, the Memory Controller's TZDRAM base/size registers would be populated by the BPMP when the system "wakes up". Change-Id: I5fc8ba1ae3bce12f0ece493f6f9f5f4d92a46344 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-27Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)Varun Wadekar
This patch fixes the "Recursion in included headers" error flagged by Coverity. Fixes coverity errors "31858: Recursion in included headers" and "31857: Recursion in included headers" Change-Id: Icf8838434b1808b396e743e47f59adc452546364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-23Tegra186: save/restore BL31 context to/from TZDRAMVarun Wadekar
This patch adds support to save the BL31 state to the TZDRAM before entering system suspend. The TZRAM loses state during system suspend and so we need to copy the entire BL31 code to TZDRAM before entering the state. In order to restore the state on exiting system suspend, a new CPU reset handler is implemented which gets copied to TZDRAM during boot. TO keep things simple we use this same reset handler for booting secondary CPUs too. Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>