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2023-05-09fix(tree): correct some typosElyes Haouas
found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
2023-02-20build: always prefix section names with `.`Chris Kay
Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-02-10build: clarify linker script generationChris Kay
The following build system variables have been renamed: - `LINKERFILE` -> `DEFAULT_LINKER_SCRIPT` - `BL_LINKERFILE` -> `DEFAULT_LINKER_SCRIPT_SOURCE` - `<IMAGE>_LINKERFILE` -> `<IMAGE>_DEFAULT_LINKER_SCRIPT_SOURCE` These new names better reflect how each variable is used: 1. the default linker script is passed via `-dT` instead of `-T` 2. linker script source files are first preprocessed Additionally, linker scripts are now placed in the build directory relative to where they exist in the source directory. For example, the `bl32/sp_min/sp_min.ld.S` would now preprocess to `sp_min/sp_min.ld` instead of just `bl32.ld` BREAKING-CHANGE: The `LINKERFILE`, `BL_LINKERFILE` and `<IMAGE_LINKERFILE>` build system variables have been renamed. See the commit message for more information. Change-Id: If8cef65dcb8820e8993736702c8741e97a66e6cc Signed-off-by: Chris Kay <chris.kay@arm.com>
2022-11-08fix(ras): restrict RAS support for NS worldManish Pandey
Current RAS framework in TF-A only supports handling errors originating from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all lower Els. To make the current design of RAS explicit, rename this macro to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when switching to NS world. Note: I am unaware of any platform which traps errors originating in Secure world to EL3, if there is any such platform then it need to be explicitly implemented in TF-A Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750
2022-11-08fix(debug): decouple "get_el_str()" from backtraceManish Pandey
get_el_str() was implemented under ENABLE_BACKTRACE macro but being used at generic places too, this causes multiple definition of this function. Remove duplicate definition of this function and move it out of backtrace scope. Also, this patch fixes a small bug where in default case S-EL1 is returned which ideally should be EL1, as there is no notion of security state in EL string. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib186ea03b776e2478eff556065449ebd478c3538
2022-08-30chore: use tabs for indentationJorge Troncoso
This patch changes definitions of bl2_mem_params_descs to follow the TF-A coding style documented at https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html Signed-off-by: Jorge Troncoso <jatron@google.com> Change-Id: I7bd99a50a79499aca0d349e49a3e095e6c5d2f08
2022-08-04fix: make TF-A use provided OpenSSL binarySalome Thirot
Currently Tf-A uses whatever openssl binary is on the system to sign images. However if OPENSSL_DIR is specified in the build flags this can lead to linking issues as the system binary can end up being linked against shared libraries provided in OPENSSL_DIR/lib if both binaries (the system's and the on in OPENSSL_DIR/bin) are the same version. This patch ensures that the binary used is always the one given by OPENSSL_DIR to avoid those link issues. Signed-off-by: Salome Thirot <salome.thirot@arm.com> Change-Id: Ib534e06ebc8482e4391e376d3791a87968de4a99
2022-03-16fix(a3k): change fatal error to warning when CM3 reset is not implementedPali Rohár
This allows TF-A's a3700_system_reset() function to try Warm reset method when CM3 reset method is not implemented by WTMI firmware. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I7303197373e1a8ca5a44ba0b1e90b48855d6c0c3
2022-02-15fix(a3k): fix comment about BootROM address rangePali Rohár
A53 AP BootROM is just 16 kB long and is mapped to address range 0xFFFF0000-0xFFFF4000. RVBAR_EL3 register has value 0xFFFF0000. A53 AP BootROM itself is in the BootROM window which is 1 MB long and mapped to address range 0xFFF00000-0xFFFFFFFF. CM3 BootROM is not accessible from A53 core. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5d4a4c7b1e7550c4738c67a872d341f945d48bbc
2021-12-02feat(plat/marvell/a3k): add north and south bridge reset registersPali Rohár
These registers make it is possible to do external resets of A3700 peripherals. Most peripherals are reset by clearing a particular bit, but some need setting the bit. Reflect this via "_N" suffix in macro names. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iacef5e671746b831b5beea9e4fdcc59d8de84edc
2021-11-08fix: libc: use long for 64-bit types on aarch64Scott Branden
Use long instead of long long on aarch64 for 64_t stdint types. Introduce inttypes.h to properly support printf format specifiers for fixed width types for such change. Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1 Signed-off-by: Scott Branden <scott.branden@broadcom.com>
2021-10-19build(plat/marvell): do not print comments on stdoutPali Rohár
'#' needs to be before TAB, otherwise comment is printed on stdout during build. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I502374ef35d91e194dc35b78d31d6884a466fab2
2021-10-13build(plat/marvell): add descriptions why some checks are requiredPali Rohár
This change adds just comments why some checks are required. They check that ENV variables and external repos are correctly set for TF-A builds. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I2f8af5061411c0c92d3875917f4d97b60dc2cf10
2021-10-11plat/marvell/a8k: add Globalscale Mochabin supportRobert Marko
Add support for Globalscale MOCHAbin board. Its based on Armada 7040 SoC and ships in multiple DRAM options: * 2GB DDR4 (1CS) * 4GB DDR4 (1CS) * 8GB DDR4 (2CS) Since it ships in multiple DRAM configurations, an Armada 3k style DDR_TOPOLOGY variable is added. Currently, this only has effect on the MOCHAbin, but I expect more boards with multiple DRAM sizes to be supported. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Change-Id: I8a1ec9268fed34f6a81c5cbf1e891f638d461305
2021-10-05refactor(makefile): remove BL prefixes in build macrosZelalem Aweke
The current Makefile assumes all TF-A binaries have BL prefixes (BL1, BL2, etc). Now that we have other binary names with FEAT_RME feature, remove this assumption. With this change, we need to pass the full name of a binary when using build macros. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I44e094b2366aa526f807d92dffa709390d14d145
2021-09-08fix(plat/marvell/a3k): enable workaround for erratum 1530924Marek Behún
Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53 revisions from r0p0 to r0p4. Enable the workaround for this erratum. Signed-off-by: Marek Behún <marek.behun@nic.cz> Change-Id: I753225040e49e956788d5617cd7ce76d5e6ea8e8
2021-09-08Merge changes from topic "advk-serror" into integrationMadhukar Pappireddy
* changes: fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default fix(plat/marvell/a3k): update information about PCIe abort hack
2021-08-26feat(plat/marvell): introduce t9130_cex7_evalMarcin Wojtas
This patch adds the necessary files to support the SolidRun CN913X CEx7 Evaluation Board. Because the DRAM connectivity and SerDes settings is shared with the CN913X DB - reuse relevant board-specific files. Change-Id: I75a4554a4373953ca3fdf3b04c4a29c2c4f8ea80 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2021-08-26feat(plat/marvell/a8k): allow overriding default pathsMarcin Wojtas
The common makefile used by every a8k/cn913x platform (a8k_common.mk) assumed default paths in PLAT_INCLUDES, BLE/BL31_PORTING_SOURCES. Allow overriding those variables, in order to avoid code duplication. It can be helpful in case using multiple board variants or sharing common settings between different platforms. Change-Id: Idce603e44ed04d99fb1e3e11a2bb395d552e2bf7 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2021-08-24fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by defaultPali Rohár
It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError accessing PCIe link while it is down") with a workaround for a bug found in U-Boot and Linux kernel driver pci-aardvark.c (PCIe controller driver for Armada 37xx SoC) which results in SError interrupt caused by AXI SLVERR on external access (syndrome 0xbf000002) and immediate kernel panic. Now when proper patches are in both U-Boot and Linux kernel projects, this workaround in TF-A should not have to be enabled by default anymore as it has unwanted side effects like propagating all external aborts, including non-fatal/correctable into EL3 and making them as fatal which cause immediate abort. Add documentation for HANDLE_EA_EL3_FIRST build option into Marvell Armada build section. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ic92b65bf9923505ab682830afb66c2f6cec70491
2021-08-23fix(plat/marvell/a3k): update information about PCIe abort hackPali Rohár
A3700 plat_ea_handler was introduced into TF-A codebase just because of bugs in U-Boot and Linux kernel PCIe controller driver pci-aardvark.c. These bugs were finally fixed in both U-Boot and Linux kernel drivers: https://source.denx.de/u-boot/u-boot/-/commit/eccbd4ad8e4e182638eafbfb87ac139c04f24a01 https://git.kernel.org/stable/c/f18139966d072dab8e4398c95ce955a9742e04f7 Add all these information into comments, including printing error message into a3k plat_ea_handler. Also check that abort is really asynchronous and comes from lower level than EL3. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I46318d221b39773d5e25b3a0221d7738736ffdf1
2021-08-13refactor(plat/ea_handler): Use default ea handler implementation for panicPali Rohár
Put default ea handler implementation into function plat_default_ea_handler() which just print verbose information and panic, so it can be called also from overwritten / weak function plat_ea_handler() implementation. Replace every custom implementation of printing verbose error message of external aborts in custom plat_ea_handler() functions by a common implementation from plat_default_ea_handler() function. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98
2021-07-20Merge changes from topic "marvell-a3k-a8k-updates" into integrationManish Pandey
* changes: fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable fix(plat/marvell/a3k): Fix check for external dependences fix(plat/marvell/a8k): Add missing build dependency for BLE target fix(plat/marvell/a8k): Correctly set include directories for individual targets fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
2021-07-16fix(plat/marvell/a3k): fix printing info messages on outputPali Rohár
INFO() macro for every call prepends "INFO: " string. Therefore current code prints unreadable debug messages: "INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0)INFO: " "INFO: Set IO decode window successfully, base(0xc000)INFO: win_attr(3d) max_dram_win(2) max_remap(0)INFO: win_offset(8)" Fix it by calling exactly one INFO() call for one line. After this change output is: "INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0) remap(0x0)" "INFO: Set IO decode window successfully, base(0xc000) win_attr(3d) max_dram_win(2) max_remap(0) win_offset(8)" Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I6084e64c6f4da6c1929e5300588e4ba2608ca745
2021-07-11fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archivePali Rohár
For UART secure boot it is required also TIMN image, so pack it into uart-images.tgz.bin archive which is created by mrvl_uart target. $(TIMN_IMAGE) and $(TIM_IMAGE) variables are used only for UART images so their content needs to be initialized from $(TIMN_UART_CFG) and $(TIM_UART_CFG) config files. And not from $(TIMN_CFG) and $(TIM_CFG) as it is now because they are not generated during mrvl_uart target. Fix it to allow building mrvl_uart target before mrvl_flash target. To match usage of these variables, rename them to $(TIMN_UART_IMAGE) and $(TIM_UART_IMAGE). To not complicate rule for building uart-images.tgz.bin archive, set list of image files into a new $(UART_IMAGES) variable. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I83b980abb4047a3afb3ce3026842e1d873c490bf
2021-07-11refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variablesPali Rohár
For TIM config file use TIM name instead of DOIMAGE and use underscores to make variable names more readable. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I1282ce11f1431c15458a143ae7bfcee85eed2432
2021-07-10refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBBPali Rohár
Armada 3700 uses external TBB tool for creating images and does not use internal TF-A doimage tool from tools/marvell/doimage/ Therefore set correct name of variable. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I38a94dca78d483de4c79da597c032e1e5d06d92d
2021-07-10refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variablePali Rohár
Armada 3700 uses WTP so use WTP variable directly. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I216b40ffee1f3f8abba4677f050ab376c2224ede
2021-07-10fix(plat/marvell/a3k): Fix check for external dependencesPali Rohár
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with latest TF-A code base. Marvell do not provide these old tarballs on Extranet anymore. Public version on github repository contains all patches and is working fine, so for public TF-A builds use only public external dependencies from git. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
2021-07-10fix(plat/marvell/a8k): Add missing build dependency for BLE targetPali Rohár
BLE source files depend on external Marvell mv-ddr-marvell tree (specified in $(MV_DDR_PATH) variable) and its header files. Add dependency on $(MV_DDR_LIB) target which checks that variable $(MV_DDR_PATH) is correctly set and ensures that make completes compilation of mv-ddr-marvell tree. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I73968b24c45d9af1e3500b8db7a24bb4eb2bfa47
2021-07-10fix(plat/marvell/a8k): Correctly set include directories for individual targetsPali Rohár
Do not set all include directories, including those for external targets in one PLAT_INCLUDES variable. Instead split them into variables: * $(PLAT_INCLUDES) for all TF-A BL images * BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image * $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree Include directory $(CURDIR)/drivers/marvell is required by TF-A BL images, so move it from ble.mk to a8k_common.mk. Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so move it into BLE target specific $(PLAT_INCLUDES) variable. And remaining include directories specified in ble.mk are needed only for building external dependences from Marvell mv-ddr tree, so move them into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB) target. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I331f7de675dca2bc70733d56b768f00d56ae4a67
2021-07-10fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly setPali Rohár
Target mrvl_flash depends on external mv_ddr source code which is not part of TF-A project. Do not expect that it is pre-downloaded at some specific location and require user to specify correct path to mv_ddr source code via MV_DDR_PATH build option. TF-A code for Armada 37x0 platform also depends on mv_ddr source code and already requires passing correct MV_DDR_PATH build option. So for A8K implement same checks for validity of MV_DDR_PATH option as are already used by TF-A code for Armada 37x0 platform. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
2021-06-02fix(plat/marvell/a3720/uart): fix UART parent clock rate determinationPali Rohár
The UART code for the A3K platform assumes that UART parent clock rate is always 25 MHz. This is incorrect, because the xtal clock can also run at 40 MHz (this is board specific). The frequency of the xtal clock is determined by a value on a strapping pin during SOC reset. The code to determine this frequency is already in A3K's comphy driver. Move the get_ref_clk() function from the comphy driver to a separate file and use it for UART parent clock rate determination. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
2021-06-01refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macrosPali Rohár
Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined to same values. De-duplicate them into PLAT_MARVELL_UART* macros. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iae5daf7cad6a971e6f3dbe561df3d0174106ca7f
2021-06-01refactor(plat/marvell/uart): remove unused macrosPali Rohár
Macros PLAT_MARVELL_BL31_RUN_UART* are not used since commit d7c4420cb8a7 ("plat/marvell: Migrate to multi-console API"). Remove them. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ec959ef4de87dcfb332c017ad2599bf8af6ffc3
2021-05-28fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculationPali Rohár
UART parent clock is by default the platform's xtal clock, which is 25 MHz. The value defined in the driver, though, is 25.8048 MHz. This is a hack for the suboptimal divisor calculation Divisor = UART clock / (16 * baudrate) which does not use rounding division, resulting in a suboptimal value for divisor if the correct parent clock rate was used. Change the code for divisor calculation to Divisor = Round(UART clock / (16 * baudrate)) and change the parent clock rate value to 25 MHz. The final UART divisor for default baudrate 115200 is not affected by this change. (Note that the parent clock rate should not be defined via a macro, since the xtal clock can also be 40 MHz. This is outside of the scope of this fix, though.) Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
2021-04-27plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRCPali Rohár
This new compile option is only for Armada 3720 Development Board. When it is set to 1 then TF-A will setup PM wake up src configuration. By default this new option is disabled as it is board specific and no other A37xx board has PM wake up src configuration. Currently neither upstream U-Boot nor upstream Linux kernel has wakeup support for A37xx platforms, so having it disabled does not cause any issue. Prior this commit PM wake up src configuration specific for Armada 3720 Development Board was enabled for every A37xx board. After this change it is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1 Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
2021-04-20plat/marvell: remove subversion from Marvell make filesKonstantin Porotchkin
Subversion is not reflecting the Marvell sources variant anymore. This patch removes version.mk from Marvell plafroms. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
2021-04-20plat/marvell: a8k: move efuse definitions to separate headerKonstantin Porotchkin
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Yi Guo <yi.guo@cavium.com>
2021-04-20plat/marvell/armada: fix TRNG return SMC handlingKonstantin Porotchkin
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single SMC call. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Ib8756cd3c0808b78c359f90c6f6913f7d16ac360 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/33280 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2021-04-20drivers: marvell: comphy: add rx training on 10G portAlex Evraev
This patch forces rx training on 10G ports as part of comphy_smc call from Linux. Signed-off-by: Alex Evraev <alexev@marvell.com> Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2021-04-20plat/marvell/armada: postpone MSS CPU startup to BL31 stageKonstantin Porotchkin
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
2021-04-20plat: marvell: armada: a8k: Fix LD selector maskGuo Yi
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by: Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2021-04-20plat/marvell/armada: allow builds without MSS supportKonstantin Porotchkin
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2021-04-20drivers: marvell: add support for secure read/write of dfx register-setGrzegorz Jaszczyk
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them. This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses. Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25055 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2021-04-20ddr_phy: use smc calls to access ddr phy registersAlex Leibovich
Added smc calls support to access ddr phy registers. Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870 Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20791 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2021-04-20drivers: marvell: thermal: use dedicated function for thermal SiPsGrzegorz Jaszczyk
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name for thermal SiP services. Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25054 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2021-04-20drivers: marvell: add thermal sensor driver and expose it via SIP serviceGrzegorz Jaszczyk
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor. The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c. Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/20581 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2021-04-20fix: plat: marvell: fix MSS loader for A8K familyKonstantin Porotchkin
Wrong brakets caused MSS FW load timeout error: ERROR: MSS DMA failed (timeout) ERROR: MSS FW chunk 0 load failed ERROR: SCP Image load failed This patch fixes the operator precedence in MSS FW load. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: I78c215606bde112f40429926c51f5fa1e4334c13
2021-02-25plat/marvell/armada: cleanup MSS SRAM if used for copyKonstantin Porotchkin
This patch cleans up the MSS SRAM if it was used for MSS image copy (secure boot mode). Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30099 Reviewed-by: Stefan Chulski <stefanc@marvell.com> Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>