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2023-08-24build(bl32): added check for AARCH32_SPJuan Pablo Conde
If AACRH32_SP is not specified, it causes the DEFAULT_LINKER_SCRIPT variable to be empty, and then the linker takes the variable following it as if it was the linker script, which is not one. This patch addresses that issue by requiring the AARCH32_SP variable to be set before continuing. Change-Id: I21db7d5bd86b98faaa1a1cd3f985daa592556a2d Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
2023-08-07Merge changes from topic "mb/mb-signer-id" into integrationLauren Wehrmeister
* changes: feat(qemu): add dummy plat_mboot_measure_key() function docs(rss): update RSS doc for signer-ID feat(imx): add dummy 'plat_mboot_measure_key' function feat(tc): implement platform function to measure and publish Public Key feat(auth): measure and publicise the Public Key feat(fvp): implement platform function to measure and publish Public Key feat(fvp): add public key-OID information in RSS metadata structure feat(auth): add explicit entries for key OIDs feat(rss): set the signer-ID in the RSS metadata feat(auth): create a zero-OID for Subject Public Key docs: add details about plat_mboot_measure_key function feat(measured-boot): introduce platform function to measure and publish Public Key
2023-08-02fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obviousMarco Felsch
Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it more obvious that the detection is based on the runtime autodetection. In addition this moves the evaluation of IMX_BOOT_UART_BASE into the makefile which removes the ugly conditional compilation as well. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Change-Id: I92c13607bf81c6267f4b6aee829d74902b7f72d2
2023-07-28feat(imx): add dummy 'plat_mboot_measure_key' functionManish V Badarkhe
Added dummy implementation of 'plat_mboot_measure_key' function for IMX platform. Change-Id: Ib41fd86a9da330f62561707bda7d16f2825c0a7f Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-25feat(imx8m): detect console base address during runtimeMarco Felsch
Provide a helper to detect the enabled UART device during runtime. This lower the integration effort and make it more straight forward for 'simple' use-cases with a single UART enabled. If multiple UARTs are enabled the first enabled is returned. The auto-detection is enabled by setting IMX_BOOT_UART_BASE=0 to keep the backward compatibility. For more advanced use-cases (multiple UARTs are enabled) the user still has to provide the correct base address. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Change-Id: I300a167e1a10f9aa991c8d1c3efe2c6b23f56c47
2023-06-30feat(imx93): add OPTEE supportClement Faure
Add OPTEE support for imx93 platform. Add support for the device tree overlay. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I99c7819665f8f746b0dd7941fb83dbec9d8651de
2023-06-30feat(imx93): protect OPTEE memory to secure access onlyYe Li
Configure TRDC_NIC MRC0 to protect OPTEE DDR memory to secure access only from A55 cores and other peripherals' masters. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ie5363ecff67e3183fbde998a0bba93df4c099e1f
2023-06-30feat(imx93): add cpuidle and basic suspend supportJacky Bai
Add cpuidle and basic suspend support. For now only core & cluster will be put into low power mode when system suspend. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ife0b6dc48738ae7a2322d6a7f6342ffe15d35342
2023-06-30feat(imx93): add reset & poweroff supportJacky Bai
Add system reset & system power off support on i.MX93. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Id180461541a1b3f73b2dc00c9cad33f484c145e6
2023-06-30feat(imx93): allow SoC masters access to system TCMYangbo Lu
SoC masters should be allowed to access to system TCM. For example, This makes it possible for M core to run ENET/ENET_QOS examples whose DMA accesses system TCM in single boot mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: I4149e047e49a66699015f92c25a7f5334a972835
2023-06-30feat(imx93): update the ocram trdc config for did10Jacky Bai
Update the ocram trdc config for DID10 to make sure NPU can access the OCRAM. Need to fine tune the OCRAM config in the future. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: Iaa8518e0bea2c3939292202c116bd08444e07698
2023-06-30feat(imx93): add the basic supportJacky Bai
Add the basic boot support for i.MX93. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I48bac2fd8bf2145133edf101a315908266c3f50a
2023-05-09fix(tree): correct some typosElyes Haouas
found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
2023-04-17feat(imx8): add support for debug uart on lpuart1Markus Niebel
Needed for TQMa8Xx on MBa8Xx. With this changes it is possible to build: $ make PLAT=imx8qx IMX_DEBUG_UART=1 DEBUG_CONSOLE=1 bl31 Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Change-Id: If380845b254f30fe919ebb33c86130597c4b8ad3
2023-04-04fix(imx8mq): fix compilation with gcc >= 12.xAndre Przywara
Starting with GCC >= 12.x the -Wall option includes -Werror=array-bounds checks. Per default GCC treats all memory accesses below 4096 as NULL, so access to ROMAPI causes the following warning: ------------ In file included from plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:20: In function 'mmio_read_8', inlined from 'imx8mq_soc_info_init' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:70:16, inlined from 'bl31_platform_setup' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:206:2: include/lib/mmio.h:19:16: error: array subscript 0 is outside array bounds of 'volatile uint8_t[0]' {aka 'volatile unsigned char[]'} [-Werror=array-bounds] 19 | return *(volatile uint8_t*)addr; | ^~~~~~~~~~~~~~~~~~~~~~~~ In function 'mmio_read_8', inlined from 'imx8mq_soc_info_init' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:74:16, inlined from 'bl31_platform_setup' at plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c:206:2: include/lib/mmio.h:19:16: error: array subscript 0 is outside array bounds of 'volatile uint8_t[0]' {aka 'volatile unsigned char[]'} [-Werror=array-bounds] 19 | return *(volatile uint8_t*)addr; | ^~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors ------------ This comes arguably from us somewhat abusing pointers to access MMIO memory regions, which is not really covered by the C language. Replace the pointer-dereferencing mmio_read_8() with an implementation that uses inline assembly, to directly generate an 8-bit load instruction. This avoids the compiler thinking that this access is using a pointer it needs to jealously look after. Change-Id: Iab39f6f615d51d3e8a1c54a1262d1e6ec208811d Reported-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-03-15refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
2023-03-09Merge changes from topic "imx8m_misc_changes" into integrationMadhukar Pappireddy
* changes: feat(imx8mq): enable dram dvfs support on imx8mq feat(imx8m): use non-fast wakeup stop mode for system suspend feat(imx8mq): correct the slot ack setting for STOP mode feat(imx8mq): add anamix pll override setting for DSM mode feat(imx8mq): add workaround code for ERR11171 on imx8mq feat(imx8mq): add the dram retention support for imx8mq feat(imx8mq): add version for B2 fix(imx8m): backup mr12/14 value from lpddr4 chip fix(imx8m): add ddr4 dvfs sw workaround for ERR050712 fix(imx8m): fix coverity out of bound access issue fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0 feat(imx8m): add more dram pll setting fix(imx8m): fix the current fsp init fix(imx8m): fix the rank to rank space issue fix(imx8m): fix the dfiphymaster setting after dvfs feat(imx8m): update the ddr4 dvfs flow to include ddr3l support fix(imx8m): correct the rank info get fro mstr feat(imx8m): fix the ddr4 dvfs random hang on imx8m
2023-03-01feat(imx8mq): enable dram dvfs support on imx8mqJacky Bai
Enable DRAM DVFS support on i.MX8MQ. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Id72c5eb9625936052ec51e5a52d9d31175ed1b1b
2023-03-01feat(imx8m): use non-fast wakeup stop mode for system suspendJacky Bai
Use non-fast wakeup stop mode for system suspend support, so the SOC can enter DSM mode by default. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I37828d4e66ee2ebd48e7adca054b93c520cb2c82
2023-03-01feat(imx8mq): correct the slot ack setting for STOP modeJacky Bai
A53 core's power up ack need to be used when system resume from DSM mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I47fb33c0582ae5f483ffaa887f95e27bd47875f7
2023-03-01feat(imx8mq): add anamix pll override setting for DSM modeJacky Bai
Add the anamix PLL override setting for DSM mode support, so that the PLL can be power down in DSM mode to save power. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ibe954bc7c4a7b453ace13f8e4b6a335e6d4856c3
2023-03-01feat(imx8mq): add workaround code for ERR11171 on imx8mqJacky Bai
This new workaround takes advantage of the per core IMR registers in GPC in order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register (which now remains always set), so it can only wake up one core at the time.Also, this entire workaround has now been moved here in TF-A, allowing the kernel side to be minimal. Another advantage this workaround brings is the removal of the 50us delay (which was necessary before in gic_raise_softirq in kernel) by allowing the core that is waking up to mask his own IRQ0 in the suspend finish callback. One important change here is the way the cores are woken up in dram_dvfs_handler. Since the wake up mechanism has changed from asserting the 12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then masking/unmasking the IMR1 1st bit for each independent core, we need to use the imx_gpc_core_wake to wake up the cores. Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel(gic_raise_softirq), since the new cpuidle workaround does not need it in order to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed in order to delay the affinity info OFF for the dying core. This is something that needs further investigation. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I9f17ff6fc3452b8225a50b232964712aafeab78a
2023-03-01feat(imx8mq): add the dram retention support for imx8mqJacky Bai
Add the dram retention support for i.MX8MQ. As there is no enough ocram space available before entering TF-A, so the timing info need to be copied from dram into ocram. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Id8264c342fd62e297b1969cba5ed505450c78a25
2023-03-01feat(imx8mq): add version for B2Ye Li
iMX8MQ B2 chip uses same OCOTP magic value with B1. So read the ROM version to distinguish it with B1. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I3e6865922deeb66816a0dddb49d986405e802b6f
2023-03-01fix(imx8m): backup mr12/14 value from lpddr4 chipJacky Bai
Backup the mr12/14 value as the actual value used is not the one we configured in the ddrc config timing. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: If04733b34a3b4c080828bb7c82e83f0badbeaafd
2023-02-28fix(imx8m): add ddr4 dvfs sw workaround for ERR050712Jacky Bai
APB Write data corruption following MRCTRL0.mr_wr=1 while hardware-driven MR access is occurring When performing a software driven MR access, the following sequence must be done automatically before performing other APB register accesses: 1. Set MRCTRL0.mr_wr=1 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time), if not, go to step (2). Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: Ie26e08bcc83d3ed4844ed04a853162308dcdccd0
2023-02-28fix(imx8m): fix coverity out of bound access issueJacky Bai
Fix the out of bound access to the rank setting array. Fix Coverity issue: CID 6474575: Out-of-bounds access (OVERRUN) CID 11014855: Unused value (UNUSED_VALUE) Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: I5d9ef90f1479e5d46d1b6c8693a27e3abd614766
2023-02-28fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0Jacky Bai
It seems the DRAM APB clock root slice can NOT work normally if the PLLs is power down in DSM mode. So update this clock slice's setting explicitly to make it work. This piece of code is there for a long while on previous release, so just add it back to align with previous flow. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Change-Id: I113069494074194e116fdb1229052d2956bf90ea
2023-02-28feat(imx8m): add more dram pll settingJacky Bai
Add DRAM PLL frequency setting for 3200mts & 4000mts. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Change-Id: I4b0609f9e7c0f35d75a26ec9ccebec77b3dbe68f
2023-02-28fix(imx8m): fix the current fsp initJacky Bai
The dfimisc reg value should be shift right 8 bit to get the current fsp. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Change-Id: I4c8c166bc3ad4cc1376961cbf47631c68b5900cc
2023-02-28fix(imx8m): fix the rank to rank space issueJacky Bai
update umctl2's setting based on phy training CDD value to workaround the rank-to-rank space issue. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Change-Id: I0fab18cdc378fda760daa0f89c4dd84eb46f7e11
2023-02-27fix(imx8m): fix the dfiphymaster setting after dvfsJacky Bai
the dfi phy master setting need to be save/restore to make sure it aligned with the initial config. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Change-Id: I4f572b9aff9cc47a6c28524ce0fe03cdc66b88a1
2023-02-27feat(imx8m): update the ddr4 dvfs flow to include ddr3l supportJacky Bai
the DDR3L & DDR4 can share same piece of code for DDR frequency scaling. So update the ddr4 dvfs flow to support DDR3L too. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Change-Id: Ifc6981f05ed8a4e399adad97690197a9680f554d
2023-02-27fix(imx8m): correct the rank info get fro mstrJacky Bai
the bitfield of active_ranks in MSTR is defined as below. Correct the rank num get in dram_info. 0x01: one rank; 0x11: two rank; Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Change-Id: Idcadb39f492a8fe81c973ac4136d9a1eaa32f54b
2023-02-27feat(imx8m): fix the ddr4 dvfs random hang on imx8mJacky Bai
Remove the while loop waiting in step12 to align with what we did before, just use a 'if' condition check for debug purpose. Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Id2685c5f628270a24944470d675a5c8706f39f13
2023-02-16fix: remove useless "return" at void functionsElyes Haouas
void functions() returns nothing. So remove useless "return". found using checkpatch.pl[1] [1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl Change-Id: I3daab2abec225a657af48f7d8c215cc554713074 Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-27perf(imx): speed-up console/uart TX using FIFOLoic Poulain
The current putc version test for TXEMPTY bit set (#6) instead of waiting for TXFULL bit clear (#4), that slows the global boot time as we are not taking benefit of the 32-byte FIFO. We then need to implement the flush function to be sure the transmit is complete (FIFO and shift register empty). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Change-Id: I54873a5203e2afdc230e44ce73284e7a80985b4f
2023-01-10Merge changes from topic "bk/warnings" into integrationManish Pandey
* changes: docs: describe the new warning levels build: add -Wunused-const-variable=2 to W=2 build: include -Wextra in generic builds docs(porting-guide): update a reference fix(st-usb): replace redundant checks with asserts fix(brcm): add braces around bodies of conditionals fix(renesas): align incompatible function pointers fix(zynqmp): remove redundant api_version check fix: remove old-style declarations fix: unify fallthrough annotations
2022-12-13feat(imx8mq): add BL31 PIE supportLucas Stach
Enable PIE support so the BL31 firmware can be loaded from anywhere within the OCRAM (SRAM). For the PIE support we only need to replace the BL31_BASE define by the BL31_START symbol which is a relocatable and we need to enable it by setting ENABLE_PIE := 1. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Change-Id: Ie6a13e4ae0fdc6627a94798d7a86df7d5b310896
2022-12-13refactor(imx8mq): introduce BL31_SIZELucas Stach
No functional change. Introduce BL31_SIZE define and calculate the limits based on the BL31_BASE and the BL31_SIZE define. Also make use of SZ_64K to make it easier to read. This is required for later BL31 PIE support since it drops the calculation based on the BL31_LIMIT and BL31_BASE. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Change-Id: I517074b866b5bf11841b51777f87c926b304488d
2022-12-13refactor(imx8mq): make use of setup_page_tables()Lucas Stach
Improve code readability and align with other i.MX8M* platforms. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Change-Id: Ifd29b74872e3a567288d208de4827403078164e9
2022-12-13feat(imx8mq): always set up consoleLucas Stach
This aligns the i.MX8MQ platform behaviour with the other i.MX8M* platforms by always setting up the console UART. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Change-Id: I1279d9cb4feb6e789422b9844cab711b8daae74e
2022-12-13feat(imx8mq): remove empty bl31_plat_runtime_setupLucas Stach
Having this empty definition is actively harmful, as it prevents the default weak function to be used, which does a switch of the console state. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Change-Id: I3b78e0c524c4907714036dba573a44d8f9c48b09
2022-12-13feat(imx8mq): make IMX_BOOT_UART_BASE configurable via build parameterLucas Stach
This aligns the i.MX8MQ build with the other i.MX8M platforms by allowing to override the default IMX_BOOT_UART_BASE value via a make parameter. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Change-Id: Iad9b844517209fc7d051c61767f71ac9fa2b55c7
2022-12-01fix: remove old-style declarationsBoyan Karatotev
TF-A wants to eventually enable -Wold-style-definition globally. Convert the rare few instances where this is still the case. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I9c450fc875cf097e6de2ed577ea3b085821c9f5e
2022-11-22refactor(imx8m): pass platform metadata as a function's argumentManish V Badarkhe
Based on the prototype modification of the event_log_measure_and_record function in the previous patch, platform metadata was passed as an argument. Change-Id: I4b98b6a035abb28c000344f2dbeb3996c69eee61 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-11-01Merge "feat(imx8mm): add BL31 PIE support" into integrationMadhukar Pappireddy
2022-11-01Merge "refactor(imx8mm): introduce BL2_SIZE and BL31_SIZE" into integrationMadhukar Pappireddy
2022-11-01Merge "refactor(imx8mm): make use of setup_page_tables()" into integrationMadhukar Pappireddy
2022-11-01Merge "refactor(imx8mm): cleanup the mmap region settings" into integrationMadhukar Pappireddy