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2021-01-11plat/arm: rename rddanielxlr to rdv1mcAditya Angadi
Reference Design platform RD-Daniel-ConfigXLR has been renamed to RD-V1-MC. Correspondingly, remove all uses of 'rddanielxlr' and replace it with 'rdv1mc' where appropriate. Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Change-Id: I5d91c69738397b19ced43949b4080c74678e604c
2021-01-11plat/arm: rename rddaniel to rdv1Aditya Angadi
Reference Design platform RD-Daniel has been renamed to RD-V1. Correspondingly, remove all uses of 'rddaniel' and replace it with 'rdv1' where appropriate. Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Change-Id: I1702bab39c501f8c0a09df131cb2394d54c83bcf
2020-12-21Merge changes from topic "tc0_optee_sp" into integrationMadhukar Pappireddy
* changes: fdts: tc0: Add reserved-memory node for OP-TEE plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2 docs: arm: Add OPTEE_SP_FW_CONFIG plat: tc0: enable opteed support plat: arm: Increase SP max size
2020-12-16plat/arm/rdn2: update gic redistributor base addressVijayenthiran Subramaniam
RD-N2 platform has been updated to use six GIC ITS blocks. This results in change in base address of the GIC Redistributor to accomodate two new GIC ITS blocks. Update the base address of GICR to reflect the same. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I740a547328fb9a9f25d7a09c08e61bdbc8bf781c
2020-12-14plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2Arunachalam Ganapathy
This patch adds support to enable OP-TEE as S-EL1 SP with SPMC at S-EL2 - create SPMC manifest file with OP-TEE as SP - add support for ARM_SPMC_MANIFEST_DTS build option - add optee entry with ffa as method in tc0.dts Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Ia9b5c22c6f605d3886914bbac8ac45e8365671cb
2020-12-14plat: tc0: enable opteed supportArunachalam Ganapathy
Enable SPD=opteed support for tc0 platform. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Ieb038d645c68fbe6b5a211c7279569e21b476fc3
2020-12-11Merge changes from topic "rdevans" into integrationMadhukar Pappireddy
* changes: doc: Update list of supported FVP platforms board/rdn2: add board support for rdn2 platform plat/arm/sgi: adapt to changes in memory map plat/arm/sgi: add platform id value for rdn2 platform plat/arm/sgi: platform definitions for upcoming platforms plat/arm/sgi: refactor header file inclusions plat/arm/sgi: refactor the inclusion of memory mapping
2020-12-09board/rdn2: add board support for rdn2 platformAditya Angadi
Add the initial board support for RD-N2 platform. Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09plat/arm/sgi: adapt to changes in memory mapAditya Angadi
Upcoming RD platforms will have an updated memory map for the various pheripherals on the system. So, for the newer platforms, handle the memory mapping and other platform specific functionality separately from the existing platforms. Change-Id: Iab1355a4c8ea1f6db4f79fcdd6eed907903b6a18 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09plat/arm/sgi: add platform id value for rdn2 platformAditya Angadi
In preparation for adding the board support for RD-N2 platform, add macros to define the platform id and the corresponding SCMI platform info for the RD-N2 platform. Change-Id: Ie764ae618732b39e316f7ed080421f5d79adab21 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09plat/arm/sgi: platform definitions for upcoming platformsAditya Angadi
Upcoming RD platforms have changes in the SOC address map from that of the existing platforms. As a prepartory step to add support for the upcoming platforms, create platform definitions for those platforms. Change-Id: Ic5df9fed02c44e65ec260bbb5efc1b8dbd919a56 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09plat/arm/sgi: refactor header file inclusionsAditya Angadi
Upcoming RD platforms have deviations in various definitions of platform macros from that of the exisiting platforms. In preparation for adding support for those upcoming RD platforms, refactor the header file inclusion to allow newer platforms to use a different set of platform macros. Change-Id: Ic80283ddadafaa7f766f300652cb0d4e507efdb6 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-09plat/arm/sgi: refactor the inclusion of memory mappingAditya Angadi
Upcoming RD platforms have a different memory map from those of the existing platforms. So make the build of the existing mmap entries to be usable only for existing platforms and let upcoming platforms define a different set of mmap entries. Change-Id: Id1ef0293efe8749c78a99237e78d32573c7233aa Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-12-08spm: provide number of vCPUs and VM size for first SPOlivier Deprez
The primary VM concept is removed from the SPMC. Update the SPMC manifests with number of Execution Contexts and SP workspace size for the first Secure Partition (as it is done for NWd secondary VMs and other SPs). Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3b9c52666f7dfe74ab1f7d2148ad0070ee44b54e
2020-12-08spm: remove chosen node from SPMC manifestsOlivier Deprez
The chosen node is no longer required as the SPMC implements a specific boot flow which no longer requires this node. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ib566b602a7f83003a1b2d0ba5f6ebf4d8b7a9156
2020-12-08spm: move OP-TEE SP manifest DTS to FVP platformOlivier Deprez
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I0981c43e2ef8172138f65d95eac7b20f8969394e
2020-12-08spm: remove device-memory node from SPMC manifestsOlivier Deprez
The PVM concept is removed from the SPMC so the device-memory node which is specifying the device memory range for the PVM is no longer applicable. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: If0cb956e0197028b24ecb78952c66ec454904516
2020-11-30Add support for Neoverse-N2 CPUs.Javier Almansa Sobrino
Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-10-29Merge "Use constant stack size with RECLAIM_INIT_CODE" into integrationv2.4-rc0Alexei Fedorov
2020-10-28Use constant stack size with RECLAIM_INIT_CODEDavid Horstmann
Currently, when RECLAIM_INIT_CODE is set, the stacks are scaled to ensure that the entirety of the init section can be reclaimed as stack. This causes an issue in lib/psci/aarch64/psci_helpers.S, where the stack size is used for cache operations in psci_do_pwrdown_cache_maintenance(). If the stacks are scaled, then the PSCI code may fail to invalidate some of the stack memory before power down. Resizing stacks is also not good for stability in general, since code that works with a small number of cores may overflow the stack when the number of cores is increased. Change to make every stack be PLATFORM_STACK_SIZE big, and allow the total stack to be smaller than the init section. Any pages of the init section not reclaimed as stack will be set to read-only and execute-never, for security. Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8 Signed-off-by: David Horstmann <david.horstmann@arm.com>
2020-10-26Merge "SPMC: adjust device region for first secure partition" into integrationOlivier Deprez
2020-10-22SPMC: adjust device region for first secure partitionOlivier Deprez
For the first partition, mark first 2GB as device memory excluding the Trusted DRAM region reserved for the SPMC. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3ff110b3facf5b6d41ac2519ff6ca5e30a0a502b
2020-10-20plat: tc0: Configure TZC with secure world regionsUsama Arif
This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20plat: tc0: Enable SPMC execution at S-EL2Arunachalam Ganapathy
This patch enables SPMC execution at S-EL2 by adding below changes - Map TC0_MAP_TZC_DRAM1 for loading SPMC - Add details of cactus test secure partitions - Adds tc0 spmc manifest file with details on secure partitions - Inlcude TOS_FW_CONFIG when SPM is spmd - Increases bl2 image size SPMC at S-EL2 is only enabled when build with SPD=spmd. Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20plat: tc0: Add TZC DRAM1 region for SPMC and trusted OSArunachalam Ganapathy
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1 - Add TC0_NS_DRAM1 base and mapping - Reserve memory region in tc0.dts Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabledArunachalam Ganapathy
To support platforms without Trusted DRAM this patch defines PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or DRAM region behind TZC. Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20plat: tc0: Disable SPEArunachalam Ganapathy
Statistical Profiling Extension is not supported by Matterhorn core Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-18Merge "Increase type widths to satisfy width requirements" into integrationJoanna Farley
2020-10-12Increase type widths to satisfy width requirementsJimmy Brisson
Usually, C has no problem up-converting types to larger bit sizes. MISRA rule 10.7 requires that you not do this, or be very explicit about this. This resolves the following required rule: bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None> The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U | 0x3c0U" (32 bits) is less that the right hand operand "18446744073709547519ULL" (64 bits). This also resolves MISRA defects such as: bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)] In the expression "3U << 20", shifting more than 7 bits, the number of bits in the essential type of the left expression, "3U", is not allowed. Further, MISRA requires that all shifts don't overflow. The definition of PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues. This fixes the violation by changing the definition to 1UL << 12. Since this uses 32bits, it should not create any issues for aarch32. This patch also contains a fix for a build failure in the sun50i_a64 platform. Specifically, these misra fixes removed a single and instruction, 92407e73 and x19, x19, #0xffffffff from the cm_setup_context function caused a relocation in psci_cpus_on_start to require a linker-generated stub. This increased the size of the .text section and caused an alignment later on to go over a page boundary and round up to the end of RAM before placing the .data section. This sectionn is of non-zero size and therefore causes a link error. The fix included in this reorders the functions during link time without changing their ording with respect to alignment. Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-09Don't return error information from console_flushJimmy Brisson
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-06Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into ↵Madhukar Pappireddy
integration * changes: Rename Neoverse Zeus to Neoverse V1 Rename Cortex Hercules AE to Cortex 78 AE
2020-10-06plat/arm: common: add guard for arm_get_rotpk_info_regsUsama Arif
Only define arm_get_rotpk_info_regs if ROTPK is in registers, i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will allow platform build without definition of TZ_PUB_KEY_HASH_BASE if dedicated registers for ROTPK are not available on the platform. Change-Id: I74ee2d5007f5d876a031a1efca20ebee2dede0c7 Signed-off-by: Usama Arif <usama.arif@arm.com>
2020-10-05Rename Neoverse Zeus to Neoverse V1Jimmy Brisson
Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-05Rename Cortex Hercules AE to Cortex 78 AEJimmy Brisson
Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-02morello: Add changes to fix build of Morello PlatformChandni Cherukuri
This patch makes changes required to get the morello platform working with the tip of TF-A. Change-Id: I095006615c9959bba49fcc75b52e1de7d7486309 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2020-09-30Merge changes from topic "fpga_generic" into integrationAndré Przywara
* changes: arm_fpga: Add platform documentation arm_fpga: Add post-build linker script arm_fpga: Add ROM trampoline arm_fpga: Add devicetree file arm_fpga: Remove SPE PMU DT node if SPE is not available arm_fpga: Adjust GICR size in DT to match number of cores fdt: Add function to adjust GICv3 redistributor size drivers: arm: gicv3: Allow detecting number of cores
2020-09-29arm_fpga: Add post-build linker scriptAndre Przywara
For the Arm Ltd. FPGAs to run, we need to load several payloads into the FPGA's memory: - Some trampoline code at address 0x0, to jump to BL31's entry point. - The actual BL31 binary at the beginning of DRAM. - The (generic) DTB image to describe the hardware. - The actual non-secure payloads (kernel, ramdisks, ...) The latter is application specific, but the first three blobs are rather generic. Since the uploader tool supports ELF binaries, it seems helpful to combine these three images into one .axf file, as this also simplifies the command line. Add a post-build linker script, that combines those three bits into one ELF file, together with their specific load addresses. Include a call to "ld" with this linker script in the platform Makefile, so it will be build automatically. The result will be called "bl31.axf". Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-29arm_fpga: Add ROM trampolineAndre Przywara
The application cores of the FPGAs used in Arm Ltd. start execution at address 0x0. This is the location of some (emulated) ROM area (which can be written to by the uploading tool). Since the arm_fpga port is configured to run from DRAM, we load BL31 to the beginning of DRAM (mapped at 2GB). This requires some small trampoline code in the "ROM" to jump to the BL31 entry point. To avoid some extra magic binary, add a tiny assembly file with that trivial jump instruction to the tree, so this binary can be created alongside BL31. Change-Id: I9e4439fc0f093fa24dd49a8377c9edb030fbb477 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-29arm_fpga: Add devicetree fileAndre Przywara
The FPGA images used in Arm Ltd. focus on CPU cores, so they share a common platform, with a minimal set of peripherals (interconnect, GIC, UART). This allows to support most platforms with a single devicetree file. The topology and number of CPU cores differ, but those will added at runtime, in BL31. Other adjustments (GICR size, SPE node, command line) are also done at this point. Add the common devicetree file to TF-A's build system, so it can be build together with BL31. At runtime, the resulting .dtb file should be uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time. Change-Id: I3206d6131059502ec96896e95329865452c9d83e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-29arm_fpga: Remove SPE PMU DT node if SPE is not availableAndre Przywara
The Statistical Profiling Extension (SPE) is an architectural feature we can safely detect at runtime. However it still relies on one piece of platform-specific information: the interrupt line it is connected to. This requires SPE to be described in a devicetree node. Since SPE support varies with the CPU cores found on an FPGA image, we should detect the presence of SPE at runtime, and remove a potentially existing SPE PMU node from the DT. This allows to always have the SPE node in a generic devicetree file, without risking exposing it on a CPU without this feature. Change-Id: I73d83ea8509b03fe7bba20b9cce8d1335035fa31 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-29arm_fpga: Adjust GICR size in DT to match number of coresAndre Przywara
The size of a GICv3 redistributor region depends on the number of cores in the system. For the ARM FPGA port, we detect the topology at runtime, and adjust the CPU DT nodes accordingly. Now the size of the GICR region must also be adjusted, or Linux will fail to initialise the GICv3. Use the newly introduced function to overwrite the GICR size entry in the GICv3 reg property. We count the number of existing cores by iterating over the GICR frames until we find the LAST bit set in TYPER. Change-Id: Ib69565600859de9b1b15ceb8495172cd26d16fce Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-29Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integrationManish Pandey
* changes: plat/arm: Add platform support for Morello fdts: add device tree sources for morello platform lib/cpus: add support for Morello Rainier CPUs
2020-09-28Merge "arm_fpga: Add support for unknown MPIDs" into integrationAndré Przywara
2020-09-28plat/arm: Add platform support for MorelloChandni Cherukuri
This patch adds support for Morello platform. It is an initial port which includes only BL31 support as the System Control Processor (SCP) is expected to take the role of primary bootloader. Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Anurag Koul <anurag.koul@arm.com>
2020-09-25arm_fpga: Add support for unknown MPIDsJavier Almansa Sobrino
This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones. This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform). This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
2020-09-25Merge changes from topic "tc0_architecture_change" into integrationOlivier Deprez
* changes: plat: tc0: enable TZC fdts: tc0: update MHUv2 interrupt number
2020-09-24Merge "plat/arm/css/sgi: Map flash used for mem_protect" into integrationManish Pandey
2020-09-24Merge "plat/arm: Introduce and use libc_asm.mk makefile" into integrationOlivier Deprez
2020-09-24plat/arm/css/sgi: Map flash used for mem_protectSami Mujawar
The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which indicates that the platform has mitigation for cold reboot attacks. However, the flash memory used for the mem_protect region was not mapped. This results in a crash when an OS calls PSCI MEM_PROTECT. To fix this map the flash region used for mem_protect. Change-Id: Ia494f924ecfe2ce835c045689ba8f942bf0941f4 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2020-09-24plat: tc0: enable TZCUsama Arif
Change-Id: Ic2bb8482f0b602f6b7850d4fa553448bc4931edc Signed-off-by: Usama Arif <usama.arif@arm.com>