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2018-01-18bl2-el3: Add BL2_EL3 imageRoberto Vargas
This patch enables BL2 to execute at the highest exception level without any dependancy on TF BL1. This enables platforms which already have a non-TF Boot ROM to directly load and execute BL2 and subsequent BL stages without need for BL1. This is not currently possible because BL2 executes at S-EL1 and cannot jump straight to EL3. Change-Id: Ief1efca4598560b1b8c8e61fbe26d1f44e929d69 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2017-12-14Merge pull request #1104 from nmenon/dtb_build-v2davidcunado-arm
Makefile: Add ability to build dtb (v2)
2017-12-11Merge pull request #1178 from davidcunado-arm/dc/enable_svedavidcunado-arm
Enable SVE for Non-secure world
2017-12-04Merge pull request #1168 from matt2048/masterdavidcunado-arm
Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS
2017-11-30Enable SVE for Non-secure worldDavid Cunado
This patch adds a new build option, ENABLE_SVE_FOR_NS, which when set to one EL3 will check to see if the Scalable Vector Extension (SVE) is implemented when entering and exiting the Non-secure world. If SVE is implemented, EL3 will do the following: - Entry to Non-secure world: SIMD, FP and SVE functionality is enabled. - Exit from Non-secure world: SIMD, FP and SVE functionality is disabled. As SIMD and FP registers are part of the SVE Z-registers then any use of SIMD / FP functionality would corrupt the SVE registers. The build option default is 1. The SVE functionality is only supported on AArch64 and so the build option is set to zero when the target archiecture is AArch32. This build option is not compatible with the CTX_INCLUDE_FPREGS - an assert will be raised on platforms where SVE is implemented and both ENABLE_SVE_FOR_NS and CTX_INCLUDE_FPREGS are set to 1. Also note this change prevents secure world use of FP&SIMD registers on SVE-enabled platforms. Existing Secure-EL1 Payloads will not work on such platforms unless ENABLE_SVE_FOR_NS is set to 0. Additionally, on the first entry into the Non-secure world the SVE functionality is enabled and the SVE Z-register length is set to the maximum size allowed by the architecture. This includes the use case where EL2 is implemented but not used. Change-Id: Ie2d733ddaba0b9bef1d7c9765503155188fe7dae Signed-off-by: David Cunado <david.cunado@arm.com>
2017-11-29ARM platforms: Fixup AArch32 buildsSoby Mathew
This patch fixes a couple of issues for AArch32 builds on ARM reference platforms : 1. The arm_def.h previously defined the same BL32_BASE value for AArch64 and AArch32 build. Since BL31 is not present in AArch32 mode, this meant that the BL31 memory is empty when built for AArch32. Hence this patch allocates BL32 to the memory region occupied by BL31 for AArch32 builds. As a side-effect of this change, the ARM_TSP_RAM_LOCATION macro cannot be used to control the load address of BL32 in AArch32 mode which was never the intention of the macro anyway. 2. A static assert is added to sp_min linker script to check that the progbits are within the bounds expected when overlaid with other images. 3. Fix specifying `SPD` when building Juno for AArch32 mode. Due to the quirks involved when building Juno for AArch32 mode, the build option SPD needed to specifed. This patch corrects this and also updates the documentation in the user-guide. 4. Exclude BL31 from the build and FIP when building Juno for AArch32 mode. As a result the previous assumption that BL31 must be always present is removed and the certificates for BL31 is only generated if `NEED_BL31` is defined. Change-Id: I1c39bbc0abd2be8fbe9f2dea2e9cb4e3e3e436a8 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-11-29Implement support for the Activity Monitor Unit on Cortex A75Dimitris Papastamos
The Cortex A75 has 5 AMU counters. The first three counters are fixed and the remaining two are programmable. A new build option is introduced, `ENABLE_AMU`. When set, the fixed counters will be enabled for use by lower ELs. The programmable counters are currently disabled. Change-Id: I4bd5208799bb9ed7d2596e8b0bfc87abbbe18740 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-11-23Merge pull request #1145 from etienne-lms/rfc-armv7-2davidcunado-arm
Support ARMv7 architectures
2017-11-23Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONSMatt Ma
This patch replaces the macro ASM_ASSERTION with the macro ENABLE_ASSERTIONS in ARM Cortex-A53/57/72 MPCore Processor related files. There is build error when ASM_ASSERTION is set to 1 and ENABLE_ASSERTIONS is set to 0 because function asm_assert in common/aarch32/debug.S is defined in the macro ENABLE_ASSERTIONS but is called with the macro ASM_ASSERTION. There is also the indication to use ENABLE_ASSERTIONS but not ASM_ASSERTION in the Makefile. Signed-off-by: Matt Ma <matt.ma@spreadtrum.com>
2017-11-22Merge pull request #1165 from geesun/qx/support-sha512davidcunado-arm
Add support sha512 for hash algorithm
2017-11-21tbbr: Add build flag HASH_ALG to let the user to select the SHAQixiang Xu
The flag support the following values: - sha256 (default) - sha384 - sha512 Change-Id: I7a49d858c361e993949cf6ada0a86575c3291066 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
2017-11-20Change Statistical Profiling Extensions build option handlingDimitris Papastamos
It is not possible to detect at compile-time whether support for an optional extension such as SPE should be enabled based on the ARM_ARCH_MINOR build option value. Therefore SPE is now enabled by default. Change-Id: I670db164366aa78a7095de70a0962f7c0328ab7c Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-11-13BL31: Add SDEI dispatcherJeenu Viswambharan
The implementation currently supports only interrupt-based SDEI events, and supports all interfaces as defined by SDEI specification version 1.0 [1]. Introduce the build option SDEI_SUPPORT to include SDEI dispatcher in BL31. Update user guide and porting guide. SDEI documentation to follow. [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf Change-Id: I758b733084e4ea3b27ac77d0259705565842241a Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-11-13BL31: Introduce Exception Handling FrameworkJeenu Viswambharan
EHF is a framework that allows dispatching of EL3 interrupts to their respective handlers in EL3. This framework facilitates the firmware-first error handling policy in which asynchronous exceptions may be routed to EL3. Such exceptions may be handed over to respective exception handlers. Individual handlers might further delegate exception handling to lower ELs. The framework associates the delegated execution to lower ELs with a priority value. For interrupts, this corresponds to the priorities programmed in GIC; for other types of exceptions, viz. SErrors or Synchronous External Aborts, individual dispatchers shall explicitly associate delegation to a secure priority. In order to prevent lower priority interrupts from preempting higher priority execution, the framework provides helpers to control preemption by virtue of programming Priority Mask register in the interrupt controller. This commit allows for handling interrupts targeted at EL3. Exception handlers own interrupts by assigning them a range of secure priorities, and registering handlers for each priority range it owns. Support for exception handling in BL31 image is enabled by setting the build option EL3_EXCEPTION_HANDLING=1. Documentation to follow. NOTE: The framework assumes the priority scheme supported by platform interrupt controller is compliant with that of ARM GIC architecture (v2 or later). Change-Id: I7224337e4cea47c6ca7d7a4ca22a3716939f7e42 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-11-09Merge pull request #1148 from antonio-nino-diaz-arm/an/spmdavidcunado-arm
Introduce Secure Partition Manager
2017-11-08SPM: Introduce Secure Partition ManagerAntonio Nino Diaz
A Secure Partition is a software execution environment instantiated in S-EL0 that can be used to implement simple management and security services. Since S-EL0 is an unprivileged exception level, a Secure Partition relies on privileged firmware e.g. ARM Trusted Firmware to be granted access to system and processor resources. Essentially, it is a software sandbox that runs under the control of privileged software in the Secure World and accesses the following system resources: - Memory and device regions in the system address map. - PE system registers. - A range of asynchronous exceptions e.g. interrupts. - A range of synchronous exceptions e.g. SMC function identifiers. A Secure Partition enables privileged firmware to implement only the absolutely essential secure services in EL3 and instantiate the rest in a partition. Since the partition executes in S-EL0, its implementation cannot be overly complex. The component in ARM Trusted Firmware responsible for managing a Secure Partition is called the Secure Partition Manager (SPM). The SPM is responsible for the following: - Validating and allocating resources requested by a Secure Partition. - Implementing a well defined interface that is used for initialising a Secure Partition. - Implementing a well defined interface that is used by the normal world and other secure services for accessing the services exported by a Secure Partition. - Implementing a well defined interface that is used by a Secure Partition to fulfil service requests. - Instantiating the software execution environment required by a Secure Partition to fulfil a service request. Change-Id: I6f7862d6bba8732db5b73f54e789d717a35e802f Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Achin Gupta <achin.gupta@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-11-08ARMv7 may not support Generic Timer ExtensionEtienne Carriere
If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_GENERIC_TIMER to enable generic timer support. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-08ARMv7 may not support Virtualization ExtensionsEtienne Carriere
ARMv7-A Virtualization extensions brings new instructions and resources that were supported by later architectures. Reference ARM ARM Issue C.c [DDI0406C_C]. ERET and extended MSR/MRS instructions, as specified in [DDI0406C_C] in ID_PFR1 description of bits[15:12] (Virtualization Extensions): A value of 0b0001 implies implementation of the HVC, ERET, MRS (Banked register), and MSR (Banked register) instructions. The ID_ISARs do not identify whether these instructions are implemented. UDIV/SDIV were introduced with the Virtualization extensions, even if not strictly related to the virtualization extensions. If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_VIRTUALIZATION to enable virtualization extension related resources. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-08ARMv7 may not support large page addressingEtienne Carriere
ARCH_SUPPORTS_LARGE_PAGE_ADDRESSING allows build environment to handle specific case when target ARMv7 core only supports 32bit MMU descriptor mode. If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING to enable large page addressing support. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-08ARMv7 target is driven by ARM_ARCH_MAJOR==7Etienne Carriere
External build environment shall sets directive ARM_ARCH_MAJOR to 7 to specify a target ARMv7-A core. As ARM-TF expects AARCH to be set, ARM_ARCH_MAJOR==7 mandates AARCH=aarch32. The toolchain target architecture/cpu is delegated after the platform configuration is parsed. Platform shall define target core through ARM_CORTEX_A<x>=yes, <x> being 5, 7, 9, 12, 15 and/or 17. Platform can bypass ARM_CORTEX_A<x>=yes directive and provide straight the toolchain target directive through MARCH32_DIRECTIVE. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-11-07Build: introduce ${BUILD_PLAT} target to create the top build directoryMasahiro Yamada
Some platforms (for ex. UniPhier) want to create files in the very top of the build directory. Add ${BUILD_PLAT} so such files can depend on it. Make existing directory targets depend on ${BUILD_PLAT} because they are sub-directories of ${BUILD_PLAT}. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16GIC: Add APIs to set interrupt type and query supportJeenu Viswambharan
The back end GIC driver converts and assigns the interrupt type to suitable group. For GICv2, a build option GICV2_G0_FOR_EL3 is introduced, which determines to which type Group 0 interrupts maps to. - When the build option is set 0 (the default), Group 0 interrupts are meant for Secure EL1. This is presently the case. - Otherwise, Group 0 interrupts are meant for EL3. This means the SPD will have to synchronously hand over the interrupt to Secure EL1. The query API allows the platform to query whether the platform supports interrupts of a given type. API documentation updated. Change-Id: I60fdb4053ffe0bd006b3b20914914ebd311fc858 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-09-19Makefile: Add ability to build dtbNishanth Menon
This is a revamp of the original approach in: https://github.com/ARM-software/arm-trusted-firmware/pull/747 Current build system has no means to automatically generate dtbs from dts, instead, stores the dtbs in the fdts/ folder. While this makes perfect sense for many reference platforms, this becomes a minor breakage in development flow for newer platforms. However, this can be solved by providing a rule for the dtbs while building the ATF binaries by purely describing which dts sources we need. For example, with this change, we will now be able to describe the dtbs we need for the platform in the corresponding platform.mk file: FDT_SOURCES += fdts/abc.dts This should be able to generate the abc.dtb appropriately. Since device trees are specification of hardware, we don't tie the rule to any specific BL, instead a generic rule is introduced. Further, this approach allows us to generate appropriate dtbs which may be need to be regenerated when a common dtsi gets updated, by just restricting changes to the dtsi alone, instead of synchronizing all the dtbs as well. If dtc is not available in default paths, but is available in an alternate location, it can be chosen by overriding the DTC variable such as 'make DTC=~/dtc/dtc ....` NOTE: dtbs are built only with the explicit make dtbs command. The rule is only available if the platform defines a FDT_SOURCES variable. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2017-08-31Export KEY_ALG as a user build optionSoby Mathew
The `KEY_ALG` variable is used to select the algorithm for key generation by `cert_create` tool for signing the certificates. This variable was previously undocumented and did not have a global default value. This patch corrects this and also adds changes to derive the value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the platform. The corresponding assignment of these variables are also now removed from the `arm_common.mk` makefile. Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4
2017-08-14Merge pull request #1040 from sliai/support-opteed-headerdanh-arm
Support opteed header
2017-08-09Support Trusted OS firmware extra images in TF toolsSummer Qin
Since Trusted OS firmware may have extra images, need to assign new uuid and image id for them. The TBBR chain of trust has been extended to add support for the new images within the existing Trusted OS firmware content certificate. Change-Id: I678dac7ba1137e85c5779b05e0c4331134c10e06 Signed-off-by: Summer Qin <summer.qin@arm.com>
2017-08-01CCI: Adapt for specific product at run timeJeenu Viswambharan
The current build system and driver requires the CCI product to be specified at build time. The device constraints can be determined at run time from its ID registers, obviating the need for specifying them ahead. This patch adds changes to identify and validate CCI at run time. Some global variables are renamed to be in line with the rest of the code base. The build option ARM_CCI_PRODUCT_ID is now removed, and user guide is updated. Change-Id: Ibb765e349d3bc95ff3eb9a64bde1207ab710a93d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-06-28Add support to link an external lib with ARM TFSoby Mathew
This patch defines the variable `LDLIBS` which allows external libraries to be specified to 'ld' to enable it to link the libraries. Change-Id: I02a490eca1074063d00153ccb0ee974ef8859a0e Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Introduce TF_LDFLAGSDouglas Raillard
Use TF_LDFLAGS from the Makefiles, and still append LDFLAGS as well to the compiler's invocation. This allows passing extra options from the make command line using LDFLAGS. Document new LDFLAGS Makefile option. Change-Id: I88c5ac26ca12ac2b2d60a6f150ae027639991f27 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-22aarch64: Enable Statistical Profiling Extensions for lower ELsdp-arm
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-06-01Remove `DISABLE_PEDANTIC` build optionAntonio Nino Diaz
It doesn't make sense to use the `-pedantic` flag when building the Trusted Firmware as we use GNU extensions and so our code is not fully ISO C compliant. This flag only makes sense if the code intends to be ISO C compliant. Change-Id: I6273564112759ff57f03b273f5349733a5f38aef Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-24Merge pull request #938 from masahir0y/tools_sharedanh-arm
Collect headers shared between TF and host-tools into include/tools_share
2017-05-24cert: move platform_oid.h to include/tools_share for all platformsMasahiro Yamada
Platforms aligned with TBBR are supposed to use their own OIDs, but defining the same macros with different OIDs does not provide any value (at least technically). For easier use of TBBR, this commit allows platforms to reuse the OIDs obtained by ARM Ltd. This will be useful for non-ARM vendors that do not need their own extension fields in their certificate files. The OIDs of ARM Ltd. have been moved to include/tools_share/tbbr_oid.h Platforms can include <tbbr_oid.h> instead of <platform_oid.h> by defining USE_TBBR_DEFS as 1. USE_TBBR_DEFS is 0 by default to keep the backward compatibility. For clarification, I inserted a blank line between headers from the include/ directory (#include <...>) and ones from a local directory (#include "..." ). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-23Build: fix assert_boolean implementationMasahiro Yamada
The current assert_boolean does not work with variables assigned with '=' flavor instead of ':='. For example, FOO = $(BAR) BAR := 1 Here, $(value FOO) is evaluated to $(BAR), not 1. This is not what we expect. While I am here, I simplified the implementation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-15AArch32: Add `TRUSTED_BOARD_BOOT` supportdp-arm
This patch adds `TRUSTED_BOARD_BOOT` support for AArch32 mode. To build this patch the "mbedtls/include/mbedtls/bignum.h" needs to be modified to remove `#define MBEDTLS_HAVE_UDBL` when `MBEDTLS_HAVE_INT32` is defined. This is a workaround for "https://github.com/ARMmbed/mbedtls/issues/708" NOTE: TBBR support on Juno AArch32 is not currently supported. Change-Id: I86d80e30b9139adc4d9663f112801ece42deafcf Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
2017-05-08Merge pull request #926 from EvanLloyd/win_make_4davidcunado-arm
Minor makefile fixes
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-02Build: Correct Unix specific echo commandsEvan Lloyd
Some recent changes have added direct use of the echo command without parameters. This fails on a Windows shell, because echo without parameters reports the mode ("ECHO is on"). This is corrected using the ECHO_BLANK_LINE macro already provided for that purpose. Change-Id: I5fd7192861b4496f6f46b4f096e80a752cd135d6 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
2017-05-02Build: Fix parallel buildEvan Lloyd
2 problems were found, but are in one change to avoid submitting a patch that might fail to build. The problems were: 1. The macro MAKE_PREREQ_DIR has a minor bug, in that it is capable of generating recursive dependencies. 2. The inclusion of BUILD_DIR in TEMP_OBJ_DIRS left no explicit dependency, BUILD_DIR might not exist when subdirectories are created by a thread on another CPU. This fix corrects these with the following changes: 1. MAKE_PREREQ_DIR does nothing for a direct self dependency. 2. BUILD_DIR is built using MAKE_PREREQ_DIR. 3. BUILD_DIR is an explicit prerequisite of all OBJ_DIRS. Change-Id: I938cddea4a006df225c02a47b9cf759212f27fb7 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
2017-04-19PSCI: Build option to enable D-Caches early in warmbootSoby Mathew
This patch introduces a build option to enable D-cache early on the CPU after warm boot. This is applicable for platforms which do not require interconnect programming to enable cache coherency (eg: single cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. Fixes ARM-Software/tf-issues#456 Change-Id: I44c8787d116d7217837ced3bcf0b1d3441c8d80e Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-03-31Add support for GCC stack protectionDouglas Raillard
Introduce new build option ENABLE_STACK_PROTECTOR. It enables compilation of all BL images with one of the GCC -fstack-protector-* options. A new platform function plat_get_stack_protector_canary() is introduced. It returns a value that is used to initialize the canary for stack corruption detection. Returning a random value will prevent an attacker from predicting the value and greatly increase the effectiveness of the protection. A message is printed at the ERROR level when a stack corruption is detected. To be effective, the global data must be stored at an address lower than the base of the stacks. Failure to do so would allow an attacker to overwrite the canary as part of an attack which would void the protection. FVP implementation of plat_get_stack_protector_canary is weak as there is no real source of entropy on the FVP. It therefore relies on a timer's value, which could be predictable. Change-Id: Icaaee96392733b721fa7c86a81d03660d3c1bc06 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-03-02build: Define build option for hardware-assisted coherencyJeenu Viswambharan
The boolean build option HW_ASSISTED_COHERENCY is introduced to enable various optimizations in ARM Trusted Software, when built for such systems. It's set to 0 by default. Change-Id: I638390da6e1718fe024dcf5b402e07084f1eb014 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-02-14Introduce locking primitives using CAS instructionJeenu Viswambharan
The ARMv8v.1 architecture extension has introduced support for far atomics, which includes compare-and-swap. Compare and Swap instruction is only available for AArch64. Introduce build options to choose the architecture versions to target ARM Trusted Firmware: - ARM_ARCH_MAJOR: selects the major version of target ARM Architecture. Default value is 8. - ARM_ARCH_MINOR: selects the minor version of target ARM Architecture. Default value is 0. When: (ARM_ARCH_MAJOR > 8) || ((ARM_ARCH_MAJOR == 8) && (ARM_ARCH_MINOR >= 1)), for AArch64, Compare and Swap instruction is used to implement spin locks. Otherwise, the implementation falls back to using load-/store-exclusive instructions. Update user guide, and introduce a section in Firmware Design guide to summarize support for features introduced in ARMv8 Architecture Extensions. Change-Id: I73096a0039502f7aef9ec6ab3ae36680da033f16 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-01-28fiptool: support --align option to add desired alignment to image offsetMasahiro Yamada
The current fiptool packs all the images without any padding between them. So, the offset to each image has no alignment. This is not efficient, for example, when the FIP is read from a block-oriented device. For example, (e)MMC is accessed by block-addressing. The block size is 512 byte. So, the best case is each image is aligned by 512 byte since the DMA engine can transfer the whole of the image to its load address directly. The worst case is the offset does not have even DMA-capable alignment (this is where we stand now). In this case, we need to transfer every block to a bounce buffer, then do memcpy() from the bounce buffer to our final destination. At least, this should work with the abstraction by the block I/O layer, but the CPU-intervention for the whole data transfer makes it really slow. This commit adds a new option --align to the fiptool. This option, if given, requests the tool to align each component in the FIP file by the specified byte. Also, add a new Make option FIP_ALIGN for easier access to this feature; users can give something like FIP_ALIGN=512 from the command line, or add "FIP_ALIGN := 512" to their platform.mk file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-19Build: strip trailing slashes from directory paths more simplyMasahiro Yamada
Append . then strip /. seems clumsy. Just use $(patsubst %/,%, ). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-19Build: Fix parallel buildingMasahiro Yamada
Soren reports build fails if -j option is given: $ make -j16 CROSS_COMPILE=aarch64-linux-gnu- Building fvp make: *** No rule to make target 'build/fvp/release/bl1/', needed by 'build/fvp/release/bl1/bl1.ld'. Stop. make: *** Waiting for unfinished jobs.... The cause of the failure is that $(dir ) leaves a trailing / on the directory names. It must be ripped off to let Make create the directory. There are some ways to fix the issue. Here, I chose to make MAKE_LD look like MAKE_C and MAKE_S because bl*_dirs seems the central place of making directories. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2017-01-05Build: add -MP option to add dummy rules to *.d filesMasahiro Yamada
This adds a phony target for each dependency other than the main file, causing each to depend on nothing. Without this, the incremental build will fail when a header file is removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-05Build: generate .d file at the same time as object is createdMasahiro Yamada
Currently, .d files are generated before any objects are built. So, IS_ANYTHING_TO_BUILD flag is needed to avoid such processing for non-build targets. There is a cleverer way; just create a .d file simultaneously when the corresponding object is created. No need to have separate rules for .d files. This commit will also fix a bug; -D$(IMAGE) is defined for $(OBJ), but not for $(PREREQUISITES). So, .d files are generated with different macro sets from those for .o files, then wrong .d files are generated. For example, in lib/cpus/aarch64/cpu_helpers.S #if IMAGE_BL31 #include <cpu_data.h> #endif <cpu_data.h> is parsed for the object when built for BL31, but the .d file does not pick up that dependency. With this commit, the compiler will generate .o and .d at the same time, guaranteeing they are generated under the same circumstances. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-05Build: use CPP just for pre-processingMasahiro Yamada
Using AS for pre-processing looks a bit weird, and some assembly specific options are given for nothing. Rather, use CPP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-05Build: exclude -c flag from TF_CFLAGSMasahiro Yamada
The -c flag should not be included in the global variable TF_CFLAGS; it should be specified in the build rule only when its target is a *.o file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>