aboutsummaryrefslogtreecommitdiff
path: root/lib
AgeCommit message (Collapse)Author
2019-05-24Add support for Branch Target IdentificationAlexei Fedorov
This patch adds the functionality needed for platforms to provide Branch Target Identification (BTI) extension, introduced to AArch64 in Armv8.5-A by adding BTI instruction used to mark valid targets for indirect branches. The patch sets new GP bit [50] to the stage 1 Translation Table Block and Page entries to denote guarded EL3 code pages which will cause processor to trap instructions in protected pages trying to perform an indirect branch to any instruction other than BTI. BTI feature is selected by BRANCH_PROTECTION option which supersedes the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication and is disabled by default. Enabling BTI requires compiler support and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0. The assembly macros and helpers are modified to accommodate the BTI instruction. This is an experimental feature. Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3 is now made as an internal flag and BRANCH_PROTECTION flag should be used instead to enable Pointer Authentication. Note. USE_LIBROM=1 option is currently not supported. Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-05-21romlib: Improve compilation flags definitionLouis Mayencourt
* Optimization flags were only provided for debug build. * Set optimisation level to -O1 * Remove CFLAGS which is never used for romlib * Remove the ignored -g flag from LDFLAGS Change-Id: Id4b69026d8a322ed4cb0acf06c350f13d31571ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-05-16Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integrationSoby Mathew
* changes: N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN N1SDP: Fix DRAM2 start address Add option for defining platform DRAM2 base Disable speculative loads only if SSBS is supported
2019-05-14Disable speculative loads only if SSBS is supportedSami Mujawar
Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative loads (SSBS) is implemented, before disabling speculative loads. Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-13Remove .arch directives from spinlock.SAlexei Fedorov
This patch removes .arch "arm8.1-a" and "armv8-a" directives which overwrite ASFLAGS_aarch64 option based on ARM_ARCH_MINOR passed to Makefile and cause translation errors like "selected processor does not support `bti jc'" for armv8.5-a targets when BTI support is enabled. Change-Id: Idca5b66ed1e5d86e2188b0c0f16c3819990957c4 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-05-07Merge changes from topic "sm/fix_a76_errata" into integrationSoby Mathew
* changes: Workaround for cortex-A76 errata 1286807 Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
2019-05-07Workaround for cortex-A76 errata 1286807Soby Mathew
The workaround for Cortex-A76 errata #1286807 is implemented in this patch. Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-05-07Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112Soby Mathew
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are added to the Cortex-A76 cpu specific file. The workarounds are disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I70474927374cb67725f829d159ddde9ac4edc343 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-05-03Add compile-time errors for HW_ASSISTED_COHERENCY flagJohn Tsichritzis
This patch fixes this issue: https://github.com/ARM-software/tf-issues/issues/660 The introduced changes are the following: 1) Some cores implement cache coherency maintenance operation on the hardware level. For those cores, such as - but not only - the DynamIQ cores, it is mandatory that TF-A is compiled with the HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is unpredictable. To prevent this, compile time checks have been added and compilation errors are generated, if needed. 2) To enable this change for FVP, a logical separation has been done for the core libraries. A system cannot contain cores of both groups, i.e. cores that manage coherency on hardware and cores that don't do it. As such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the libraries only of the relevant cores. 3) The neoverse_e1.S file has been added to the FVP sources. Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-04-30Merge changes from topic "lm/stack_protector" into integrationSoby Mathew
* changes: juno: Add security sources for tsp-juno Add support for default stack-protector flag
2019-04-30Add support for default stack-protector flagLouis Mayencourt
The current stack-protector support is for none, "strong" or "all". The default use of the flag enables the stack-protection to all functions that declare a character array of eight bytes or more in length on their stack. This option can be tuned with the --param=ssp-buffer-size=N option. Change-Id: I11ad9568187d58de1b962b8ae04edd1dc8578fb0 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-25Cortex-A53: Fix reporting of missing errata when not neededAndrew F. Davis
Errata 819472, 824069, and 827319 are currently reported in a warning as missing during boot for platforms that do not need them. Only warn when the errata is needed for a given revision but not compiled in like other errata workarounds. Fixes: bd393704d2b1 ("Cortex-A53: Workarounds for 819472, 824069 and 827319") Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ifd757b3d0e73a9bd465b98dc20648b6c13397d8d
2019-04-18Neoverse N1: Forces cacheable atomic to nearLouis Mayencourt
This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17DSU: Implement workaround for errata 798953Louis Mayencourt
Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17DSU: Small fix and reformat on errata frameworkLouis Mayencourt
Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-17Cortex-A35: Implement workaround for errata 855472Louis Mayencourt
Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-12Cortex A9:errata 794073 workaroundJoel Hutton
On Cortex A9 an errata can cause the processor to violate the rules for speculative fetches when the MMU is off but branch prediction has not been disabled. The workaround for this is to execute an Invalidate Entire Branch Prediction Array (BPIALL) followed by a DSB. see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf for more details. Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93 Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
2019-04-10cache_helpers.s:fix mixed tabs and spacesJoel Hutton
Change-Id: I8b7c7888d09200410e1a1c11a070c94dd8013ea7 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-10Add note about erratum 814220 for A7Joel Hutton
On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruction before changing cache. The cache cleaning code happens to already be doing this, so only a comment was added. Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-04-08Add support for Cortex-A76AE CPUAlexei Fedorov
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-04-03Remove deprecated interfacesAmbroise Vincent
Change-Id: I14fcabbdfd53153d1d5f187f6f8b23a045794408 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-03SPM: Move shim layer to TTBR1_EL1Antonio Nino Diaz
This gives each Secure Partition complete freedom on its address space. Previously, the memory used by the exception vectors was reserved and couldn't be used. Also, it always had to be mapped, forcing SPM to generate translation tables that included the exception vectors as well as the Partition memory regions. With this change, partitions can reduce their address space size easily. Change-Id: I67fb5e9bdf2870b73347f23bff702fab0a8f8711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-04-01Remove several warnings reported with W=2Ambroise Vincent
Improved support for W=2 compilation flag by solving some nested-extern and sign-compare warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed. Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-01Remove several warnings reported with W=1Ambroise Vincent
Improved support for W=1 compilation flag by solving missing-prototypes and old-style-definition warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed without heavy structural changes. Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-21Merge pull request #1902 from jts-arm/romlibDimitris Papastamos
ROMLIB bug fixes
2019-03-21ROMLIB bug fixesJohn Tsichritzis
Fixed the below bugs: 1) Bug related to build flag V=1: if the flag was V=0, building with ROMLIB would fail. 2) Due to a syntax bug in genwrappers.sh, index file entries marked as "patch" or "reserved" were ignored. 3) Added a prepending hash to constants that genwrappers is generating. 4) Due to broken dependencies, currently the inclusion functionality is intentionally not utilised. This is why the contents of romlib/jmptbl.i have been copied to platform specific jmptbl.i files. As a result of the broken dependencies, when changing the index files, e.g. patching functions, a clean build is always required. This is a known issue that will be fixed in the future. Change-Id: I9d92aa9724e86d8f90fcd3e9f66a27aa3cab7aaa Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-20Merge pull request #1887 from ambroise-arm/av/a76-cveDimitris Papastamos
Cortex-A76: Optimize CVE_2018_3639 workaround
2019-03-19Merge pull request #1900 from soby-mathew/sm/revert_xlat_changesv2.1-rc0Soby Mathew
xlat_tables_v2: Revert recent changes to remove recursion
2019-03-19xlat_tables_v2: Revert recent changes to remove recursionAntonio Nino Diaz
This commit reverts the following commits: - c54c7fc35842 ("xlat_tables_v2: print xlat tables without recursion") - db8cac2d986a ("xlat_tables_v2: unmap region without recursion.") - 0ffe269215bd ("xlat_tables_v2: map region without recursion.") This was part of PR#1843. A problem has been detected in one of our test run configurations involving dynamic mapping of regions and it is blocking the next release. Until the problem can be solved, it is safer to revert the changes. Change-Id: I3d5456e4dbebf291c8b74939c6fb02a912e0903b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-03-18Merge pull request #1892 from sandrine-bailleux-arm/sb/pauthSoby Mathew
Pointer authentication fixes
2019-03-15Merge pull request #1888 from jts-arm/zeusDimitris Papastamos
Introduce preliminary support for Neoverse Zeus
2019-03-14Fix restoring APIBKey registersSandrine Bailleux
Instruction key A was incorrectly restored in the instruction key B registers. Change-Id: I4cb81ac72180442c077898509cb696c9d992eda3 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-03-14Introduce preliminary support for Neoverse ZeusJohn Tsichritzis
Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-14Apply variant 4 mitigation for Neoverse N1John Tsichritzis
This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-14Cortex-A76: Optimize CVE_2018_3639 workaroundAmbroise Vincent
Switched from a static check to a runtime assert to make sure a workaround is implemented for CVE_2018_3639. This allows platforms that know they have the SSBS hardware workaround in the CPU to compile out code under DYNAMIC_WORKAROUND_CVE_2018_3639. The gain in memory size without the dynamic workaround is 4KB in bl31. Change-Id: I61bb7d87c59964b0c7faac5d6bc7fc5c4651cbf3 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-14Cortex-A76: fix spellingAmbroise Vincent
Change-Id: I6adf7c14e8a974a7d40d51615b5e69eab1a7436f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13Cortex-A17: Implement workaround for errata 852423Ambroise Vincent
Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13Cortex-A17: Implement workaround for errata 852421Ambroise Vincent
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13Merge pull request #1882 from ambroise-arm/av/a15-errataSoby Mathew
Apply workarounds for errata of Cortex-A15
2019-03-13Merge pull request #1880 from lmayencourt/lm/pieSoby Mathew
PIE: fix linking with pie and binutils > 2.27
2019-03-13Merge pull request #1843 from DavidPu/xlat_tables_v2_non_recursionSoby Mathew
Remove recursion from xlat_tables_v2 library
2019-03-13Cortex-A15: Implement workaround for errata 827671Ambroise Vincent
This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13Cortex-A15: Implement workaround for errata 816470Ambroise Vincent
Change-Id: I9755252725be25bfd0147839d7df56888424ff84 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-12PIE: Correct minor typographical errorsLouis Mayencourt
Change-Id: Ie7832b2ebffe15d53ffe3584e4d23a449d4f81ac Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-03-08Fixup register handling in aarch32 reset_handlerHeiko Stuebner
The BL handover interface stores the bootloader arguments in registers r9-r12, so when the reset_handler stores the lr pointer in r10 it clobers one of the arguments. Adapt to use r8 and adapt the comment about registers allowed to clober. I've checked aarch32 reset_handlers and none seem to use higher registers as far as I can tell. Fixes: a6f340fe58b9 ("Introduce the new BL handover interface") Cc: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-03-05xlat_tables_v2: print xlat tables without recursionDavid Pu
This patch uses an array on stack to save parent xlat table information when traversing the xlat tables. It keeps exactly same xlat table traversal order compared to recursive version. fixes arm-software/tf-issues#664 Signed-off-by: David Pu <dpu@nvidia.com>
2019-03-05xlat_tables_v2: unmap region without recursion.David Pu
This patch uses an array on stack to save parent xlat table information when traversing the xlat tables. It keeps exactly same xlat table traversal order compared to recursive version. fixes arm-software/tf-issues#664 Signed-off-by: David Pu <dpu@nvidia.com>
2019-03-05xlat_tables_v2: map region without recursion.David Pu
This patch uses an array on stack to save parent xlat table information when traversing the xlat tables. It keeps exactly same xlat table traversal order compared to recursive version. fixes arm-software/tf-issues#664 Signed-off-by: David Pu <dpu@nvidia.com>
2019-03-01Merge pull request #1842 from DavidPu/reduce_cyclomatic_complexity_metricAntonio Niño Díaz
Reduce cyclomatic complexity metric
2019-03-01Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz
Tegra scatter file support