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2021-05-28Merge "fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs" into integrationMadhukar Pappireddy
2021-05-28fix: rename Matterhorn, Matterhorn ELP, and Klein CPUsjohpow01
This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to Cortex A710, Cortex X2, and Cortex A510 respectively. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I056d3114210db71c2840a24562b51caf2546e195
2021-05-25SMCCC/PCI: Add initial PCI conduit definitionsJeremy Linton
Add constants, structures and build definition for the new standard SMCCC PCI conduit. These are documented in DEN0115A. https://developer.arm.com/documentation/den0115/latest Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Change-Id: If667800a26b9ae88626e8d895674c9c2e8c09658
2021-05-24Merge "feat(hw_crc): add support for HW computed CRC" into integrationMark Dykes
2021-05-19feat(hw_crc): add support for HW computed CRCManish V Badarkhe
Added support for HW computed CRC using Arm ACLE intrinsics. These are built-in intrinsics available for ARMv8.1-A, and onwards. These intrinsics are enabled via '-march=armv8-a+crc' compile switch for ARMv8-A (supports CRC instructions optionally). HW CRC support is enabled unconditionally in BL2 for all Arm platforms. HW CRC calculation is verified offline to ensure a similar result as its respective ZLib utility function. HW CRC calculation support will be used in the upcoming firmware update patches. Change-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-05-17refactor(juno): disable non-invasive debug of secure stateZelalem
Disable non-invasive debug of secure state for Juno in release builds. This makes sure that PMU counts only Non-secure events. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I0d1c3f96f3b4e48360a7211ae55851d65d291025
2021-04-29Merge changes from topic "fw-update" into integrationOlivier Deprez
* changes: docs: add build options for GPT support enablement feat(plat/arm): add GPT parser support
2021-04-29Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integrationManish Pandey
* changes: stm32mp1: enable PIE for BL32 stm32mp1: set BL sizes regardless of flags Add PIE support for AARCH32 Avoid the use of linker *_SIZE__ macros
2021-04-29feat(plat/arm): add GPT parser supportManish V Badarkhe
Added GPT parser support in BL2 for Arm platforms to get the entry address and length of the FIP in the GPT image. Also, increased BL2 maximum size for FVP platform to successfully compile ROM-enabled build with this change. Verified this change using a patch: https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/9654 Change-Id: Ie8026db054966653b739a82d9ba106d283f534d0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-04-28Merge "refactor(plat/arm): replace FIP base and size macro with a generic ↵Mark Dykes
name" into integration
2021-04-28Merge "refactor(plat/arm): store UUID as a string, rather than ints" into ↵Mark Dykes
integration
2021-04-28Merge "feat(fdt): introduce wrapper function to read DT UUIDs" into integrationMark Dykes
2021-04-28Merge changes from topic "mit-license" into integrationOlivier Deprez
* changes: fix(dt-bindings): fix static checks docs(license): rectify `arm-gic.h` license
2021-04-28refactor(plat/arm): store UUID as a string, rather than intsDavid Horstmann
NOTE: Breaking change to the way UUIDs are stored in the DT Currently, UUIDs are stored in the device tree as sequences of 4 integers. There is a mismatch in endianness between the way UUIDs are represented in memory and the way they are parsed from the device tree. As a result, we must either store the UUIDs in little-endian format in the DT (which means that they do not match up with their string representations) or perform endianness conversion after parsing them. Currently, TF-A chooses the second option, with unwieldy endianness-conversion taking place after reading a UUID. To fix this problem, and to make it convenient to copy and paste UUIDs from other tools, change to store UUIDs in string format, using a new wrapper function to parse them from the device tree. Change-Id: I38bd63c907be14e412f03ef0aab9dcabfba0eaa0 Signed-off-by: David Horstmann <david.horstmann@arm.com>
2021-04-28feat(fdt): introduce wrapper function to read DT UUIDsDavid Horstmann
TF-A does not have the capability to read UUIDs in string form from the device tree. This capability is useful for readability, so add a wrapper function, fdtw_read_uuid() to parse UUIDs from the DT. This function should parse a string of the form: "aabbccdd-eeff-4099-8877-665544332211" to the byte sequence in memory: [aa bb cc dd ee ff 40 99 88 77 66 55 44 33 22 11] Change-Id: I99a92fbeb40f4f4713f3458b36cb3863354d2bdf Signed-off-by: David Horstmann <david.horstmann@arm.com>
2021-04-28refactor(plat/arm): replace FIP base and size macro with a generic nameManish V Badarkhe
Replaced PLAT_ARM_FIP_BASE and PLAT_ARM_FIP_MAX_SIZE macro with a generic name PLAT_ARM_FLASH_IMAGE_BASE and PLAT_ARM_FLASH_IMAGE_MAX_SIZE so that these macros can be reused in the subsequent GPT based support changes. Change-Id: I88fdbd53e1966578af4f1e8e9d5fef42c27b1173 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-04-27fix(dt-bindings): fix static checksAlexei Fedorov
This patch fixes static checks errors reported for missing copyright in `include/dt-bindings/interrupt-controller/arm-gic.h` and the include order of header files in `.dts` and `.dtsi` files. Change-Id: I2baaf2719fd2c84cbcc08a8f0c4440a17a9f24f6 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-04-27Merge changes I36e45c0a,I69c21293 into integrationManish Pandey
* changes: plat/qemu: add "max" cpu support Add support for QEMU "max" CPU
2021-04-26docs(license): rectify `arm-gic.h` licenseChris Kay
The `arm-gic.h` file distributed by the Linux kernel is disjunctively dual-licensed under the GPL-2.0 or MIT licenses, but the BSD-3-Clause license has been applied in violation of the requirements of both licenses. This change ensures the file is correctly licensed under the terms of the MIT license, and that we comply with it by distributing a copy of the license text. Change-Id: Ie90066753a5eb8c0e2fc95ba43e3f5bcbe2fa459 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-04-22Merge "Plat FVP: Fix Generic Timer interrupt types" into integrationManish Pandey
2021-04-21Merge "Add "_arm" suffix to Makalu ELP CPU lib" into integrationbipin.ravi
2021-04-21Add PIE support for AARCH32Yann Gautier
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*. Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-04-21Avoid the use of linker *_SIZE__ macrosYann Gautier
The use of end addresses is preferred over the size of sections. This was done for some AARCH64 files for PIE with commit [1], and some extra explanations can be found in its commit message. Align the missing AARCH64 files. For AARCH32 files, this is required to prepare PIE support introduction. [1] f1722b693d36 ("PIE: Use PC relative adrp/adr for symbol reference") Change-Id: I8f1c06580182b10c680310850f72904e58a54d7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-04-21Plat FVP: Fix Generic Timer interrupt typesAlexei Fedorov
The Arm Generic Timer specification mandates that the interrupt associated with each timer is low level triggered, see: Arm Cortex-A76 Core: "Each timer provides an active-LOW interrupt output to the SoC." Arm Cortex-A53 MPCore Processor: "It generates timer events as active-LOW interrupt outputs and event streams." The following files in fdts\ fvp-base-gicv3-psci-common.dtsi fvp-base-gicv3-psci-aarch32-common.dtsi fvp-base-gicv2-psci-aarch32.dts fvp-base-gicv2-psci.dts fvp-foundation-gicv2-psci.dts fvp-foundation-gicv3-psci.dts describe interrupt types as edge rising IRQ_TYPE_EDGE_RISING = 0x01: interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; , see include\dt-bindings\interrupt-controller\arm-gic.h: which causes Linux to generate the warnings below: arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low arch_timer: WARNING: Please fix your firmware This patch adds GIC_CPU_MASK_RAW macro definition to include\dt-bindings\interrupt-controller\arm-gic.h, modifies interrupt type to IRQ_TYPE_LEVEL_LOW and makes use of type definitions in arm-gic.h. Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2021-04-20Add "_arm" suffix to Makalu ELP CPU libjohpow01
ELP processors can sometimes have different MIDR values or features so we are adding the "_arm" suffix to differentiate the reference implementation from other future versions. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
2021-04-20Add SiP service to configure Arm Ethos-N NPUMikael Olsson
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode the non-secure world cannot access the registers needed to use the NPU. To still allow the non-secure world to use the NPU, a SiP service has been added that can delegate non-secure access to the registers needed to use it. Only the HW_CONFIG for the Arm Juno platform has been updated to include the device tree for the NPU and the platform currently only loads the HW_CONFIG in AArch64 builds. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
2021-04-20plat/marvell: a8k: move efuse definitions to separate headerKonstantin Porotchkin
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Yi Guo <yi.guo@cavium.com>
2021-04-15Merge changes from topic "scmi_v2_0" into integrationMadhukar Pappireddy
* changes: drivers/arm/css/scmi: Update power domain protocol version to 2.0 tc0: update GICR base address
2021-04-14drivers/arm/css/scmi: Update power domain protocol version to 2.0Nicola Mazzucato
The SCMI power domain protocol in firmware has been updated to v2.0, thus update the corresponding version in TF-A too. Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com> Change-Id: If3920ff71136dce94b2780e29a47f24aa09876c0
2021-04-13Merge changes from topic "dcc_console" into integrationMadhukar Pappireddy
* changes: plat:xilinx:versal: Add JTAG DCC support plat:xilinx:zynqmp: Add JTAG DCC support drivers: dcc: Support JTAG DCC console
2021-04-13Add support for QEMU "max" CPULeif Lindholm
Enable basic support for QEMU "max" CPU. The "max" CPU does not attampt to emulate any specific CPU, but rather just enables all the functions emulated by QEMU. Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2 Signed-off-by: Leif Lindholm <leif@nuviainc.com>
2021-04-12Merge "driver: brcm: add USB driver" into integrationMadhukar Pappireddy
2021-04-12Merge "driver: brcm: add mdio driver" into integrationMadhukar Pappireddy
2021-04-12Merge "arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms" into ↵Olivier Deprez
integration
2021-04-07Merge "Fix: Remove save/restore of EL2 timer registers" into integrationOlivier Deprez
2021-04-07Fix: Remove save/restore of EL2 timer registersMax Shvetsov
Since there is a secure and non-secure version of the timer registers there is no need to preserve their context in EL3. With that, following registers were removed from EL3 save/restore routine: cnthps_ctl_el2 cnthps_tval_el2 cnthps_cval_el2 cnthvs_ctl_el2 cnthvs_tval_el2 cnthvs_cval_el2 cnthp_ctl_el2 cnthp_cval_el2 cnthp_tval_el2 cnthv_ctl_el2 cnthv_cval_el2 cnthv_tval_el2 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
2021-03-31drivers: dcc: Support JTAG DCC consoleVenkatesh Yadav Abbarapu
The legacy console is gone. Re-add DCC console support based on the multi-console framework. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e
2021-03-31Add Cortex_A78C CPU libBipin Ravi
Add basic support for Cortex_A78C CPU. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56
2021-03-29Merge "Add Makalu ELP CPU lib" into integrationbipin.ravi
2021-03-29Merge changes from topic "tzc400_stm32mp" into integrationSandrine Bailleux
* changes: stm32mp1: add TZC400 interrupt management stm32mp1: use TZC400 macro to describe filters tzc400: add support for interrupts
2021-03-26driver: brcm: add i2c driverBharat Gooty
Broadcom I2C controller driver. Follwoing API's are supported:- - i2c_init() Intialize ethe I2C controller - i2c_probe() - i2c_set_bus_speed() Set the I2C bus speed - i2c_get_bus_speed() Get the current bus speed - i2c_recv_byte() Receive one byte of data. - i2c_send_byte() Send one byteof data - i2c_read_byte() Read single byte of data - i2c_read() Read multiple bytes of data - i2c_write_byte Write single byte of data - i2c_write() Write multiple bytes of data This driver is verified by reading the DDR SPD data. Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
2021-03-24Add Makalu ELP CPU libjohpow01
Add basic support for Makalu ELP processor core. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93
2021-03-24nxp: adding the smmu driverPankaj Gupta
NXP SMMU driver API for NXP SoC. - Currently it supports by-passing SMMU, called only when NXP CAAM is enabled. - (TBD) AMQ based SMMU access control: Access Management Qualifiers (AMQ) advertised by a bus master for a given transaction. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I23a12928ddedb1a2cf4b396606e35c67e016e331
2021-03-24nxp: add flexspi driver supportKuldeep Singh
Flexspi driver now introduces read/write/erase APIs for complete flash size, FAST-READ are by default used and IP bus is used for erase, read and write using flexspi APIs. Framework layer is currently embedded in driver itself using flash_info defines. Test cases are also added to confirm flash functionality currently under DEBUG flag. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
2021-03-24NXP: Timer API added to enable ARM generic timerPankaj Gupta
NXP Timer Apis are based on: - drivers/delay_timer Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
2021-03-24tools: add mechanism to allow platform specific image UUIDPankaj Gupta
Generic framework is added to include platform defined UUID. This framework is added for the following: - All NXP SoC based platforms needed additional fip-fuse.bin - NXP SoC lx2160a based platforms requires additional fip-ddr.bin Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ibe05d9c596256e34077287a490dfcd5b731ef2cf
2021-03-24tbbr-cot: conditional definition for the macroPankaj Gupta
Conditional definition for the macro MAX_NUMBER_IDS. This will allow to update this definition by the platform specific implementation. Since, NXP SoC lx2160a based platforms requires additional FIP DDR to be loaded before initializing the DDR. It requires addition of defines for DDR image IDs. A dedicated header plat_tbbr_img_def.h is added to the platform folder - plat/nxp/common/include/default/ Inclusion of this header file will depend on the compile time flag PLAT_TBBR_IMG_DEF. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I4faba74dce578e2a34acbc8915ff75d7b8368cee
2021-03-24tbbr-cot: fix the issue of compiling time definePankaj Gupta
Incorrect value is picked for TF_MBEDTLS_USE_RSA defination, even if the TF_MBEDTLS_RSA is enabled. Due to which PK_DER_LEN is defined incorrectly. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I2ca4ca121e0287b88ea689c885ddcd45a34a3e91
2021-03-24cert_create: updated tool for platform defined certs, keys & extensionsPankaj Gupta
Changes to 'tools/cert_create' folder, to include platform defined certificates, keys, and extensions. NXP SoC lx2160a : based platforms requires additional FIP DDR to be loaded before initializing the DDR. To enable chain of trust on these platforms, FIP DDR image needs to be authenticated, additionally. Platform specific folder 'tools/nxp/cert_create_helper' is added to support platform specific macros and definitions. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I4752a30a9ff3aa1d403e9babe3a07ba0e6b2bf8f
2021-03-23tzc400: add support for interruptsYann Gautier
A new function tzc400_it_handler() is created to manage TZC400 interrupts. The required helpers to read and clear interrupts are added as well. In case DEBUG is enabled, more information about the faulty access (address, NSAID, type of access) is displayed. Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a Signed-off-by: Yann Gautier <yann.gautier@st.com>