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2020-09-24nand: raw_nand: fix timeout issue in nand_wait_readyLionel Debieve
nand_wait_ready is called with a millisecond delay but the timeout used a micro second. Fixing the conversion in the timeout call. The prototype of the function is also changed to use an unsigned int parameter. Change-Id: Ia3281be7980477dfbfdb842308d35ecd8b926fb8 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-09-23Merge "libc: Import strtok_r from FreeBSD project" into integrationLauren Wehrmeister
2020-09-22Merge "plat: marvell: ap807: implement workaround for errata-id 3033912" ↵Manish Pandey
into integration
2020-09-18libc: Import strtok_r from FreeBSD projectMadhukar Pappireddy
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b Made small changes to fit into TF-A project Change-Id: I991f653a7ace04f9c84bcda78ad8d7114ea18e93 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-09-18Merge changes from topic "ehf_common" into integrationManish Pandey
* changes: plat: tegra: Use generic ehf defines ehf: use common priority level enumuration
2020-09-15lib: fconf: Implement a parser to populate CoTManish V Badarkhe
Implemented a parser which populates the properties of the CoT descriptors as per the binding document [1]. 'COT_DESC_IN_DTB' build option is disabled by default and can be enabled in future for all Arm platforms by making necessary changes in the memory map. Currently, this parser is tested only for FVP platform. [1]: https://trustedfirmware-a.readthedocs.io/en/latest/components/cot-binding.html Change-Id: I2f911206087a1a2942aa728de151d2ac269d27cc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-09-11Merge "libc: Import strlcat from FreeBSD project" into integrationMark Dykes
2020-09-11Merge "libc: Add support for vsnprintf()" into integrationMark Dykes
2020-09-11libc: Add support for vsnprintf()Madhukar Pappireddy
It uses the existing implementation of snprintf() function Change-Id: Ie59418564c2e415222e819cf322c34e9a4d1f336 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-09-09libc: Import strlcat from FreeBSD projectMadhukar Pappireddy
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b Made small changes to fit into TF-A project Change-Id: I07fd7fe1037857f6b299c35367c104fb51fa5cfa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-09-03Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" ↵Manish Pandey
into integration
2020-09-03psci: utility api to invoke stop for other coresSandeep Tripathy
The API can be used to invoke a 'stop_func' callback for all other cores from any initiating core. Optionally it can also wait for other cores to power down. There may be various use of such API by platform. Ex: Platform may use this to power down all other cores from a crashed core. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: I4f9dc8a38d419f299c021535d5f1bcc6883106f9
2020-09-02lib: cpu: Check SCU presence in DSU before accessing DSU registersPramod Kumar
The DSU contains system control registers in the SCU and L3 logic to control the functionality of the cluster. If "DIRECT CONNECT" L3 memory system variant is used, there won't be any L3 cache, snoop filter, and SCU logic present hence no system control register will be present. Hence check SCU presence before accessing DSU register for DSU_936184 errata. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63
2020-09-02Merge "plat/arm: Get the base address of nv-counters from device tree" into ↵Alexei Fedorov
integration
2020-09-02Merge "dtsi: Update the nv-counter node in the device tree" into integrationAlexei Fedorov
2020-09-01Add support to export a /cpus node to the device tree.Javier Almansa Sobrino
This patch creates and populates the /cpus node in a device tree based on the existing topology. It uses the minimum required nodes and properties to satisfy the binding as specified in https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I03bf4e9a6427da0a3b8ed013f93d7bc43b5c4df0
2020-08-31lib: cpus: denver: add MIDR PN9 variantHemant Nigam
This patch introduces support for PN9 variant for some Denver based platforms. Original change by: Hemant Nigam <hnigam@nvidia.com> Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3
2020-08-28plat/arm: Get the base address of nv-counters from device treeManish V Badarkhe
Using the Fconf, register base address of the various nv-counters (currently, trusted, non-trusted nv-counters) are moved to the device tree and retrieved during run-time. This feature is enabled using the build option COT_DESC_IN_DTB. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I236f532e63cea63b179f60892cb406fc05cd5830
2020-08-28dtsi: Update the nv-counter node in the device treeManish V Badarkhe
Created a header file defining the id of the various nv-counters used in the system. Also, updated the device tree to add 'id' property for the trusted and non-trusted nv-counters. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ia41a557f7e56ad4ed536aee11c7a59e078ae07c0
2020-08-26ehf: use common priority level enumurationSandeep Tripathy
'EHF' is used by RAS, SDEI, SPM_MM common frameworks. If platform needs to plug-in specific handlers then 'PLAT_EHF_DESC' can be used to populate platform specific priority levels. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: I37af7e0e48111f87b6982604bf5c15db3e05755d
2020-08-20SPMC: manifest changes to support multicore bootOlivier Deprez
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Icf90c2ccce75257908ba3d4703926041d64b1dd3
2020-08-20SPMD: introduce SPMC to SPMD messagesOlivier Deprez
FF-A interface to handle SPMC to SPMD direct messages requests. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Ia707a308c55561a31dcfa86e554ea1c9e23f862a
2020-08-18Add wrapper for AT instructionManish V Badarkhe
In case of AT speculative workaround applied, page table walk is disabled for lower ELs (EL1 and EL0) in EL3. Hence added a wrapper function which temporarily enables page table walk to execute AT instruction for lower ELs and then disables page table walk. Execute AT instructions directly for lower ELs (EL1 and EL0) assuming page table walk is enabled always when AT speculative workaround is not applied. Change-Id: I4ad4c0bcbb761448af257e9f72ae979473c0dde8 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-08-18runtime_exceptions: Update AT speculative workaroundManish V Badarkhe
As per latest mailing communication [1], we decided to update AT speculative workaround implementation in order to disable page table walk for lower ELs(EL1 or EL0) immediately after context switching to EL3 from lower ELs. Previous implementation of AT speculative workaround is available here: 45aecff00 AT speculative workaround is updated as below: 1. Avoid saving and restoring of SCTLR and TCR registers for EL1 in context save and restore routine respectively. 2. On EL3 entry, save SCTLR and TCR registers for EL1. 3. On EL3 entry, update EL1 system registers to disable stage 1 page table walk for lower ELs (EL1 and EL0) and enable EL1 MMU. 4. On EL3 exit, restore SCTLR and TCR registers for EL1 which are saved in step 2. [1]: https://lists.trustedfirmware.org/pipermail/tf-a/2020-July/000586.html Change-Id: Iee8de16f81dc970a8f492726f2ddd57e7bd9ffb5 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-08-18el3_runtime: Rearrange context offset of EL1 sys registersManish V Badarkhe
SCTLR and TCR registers of EL1 plays role in enabling/disabling of page table walk for lower ELs (EL0 and EL1). Hence re-arranged EL1 context offsets to have SCTLR and TCR registers values one after another in the stack so that these registers values can be saved and restored using stp and ldp instruction respectively. Change-Id: Iaa28fd9eba82a60932b6b6d85ec8857a9acd5f8b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-08-14Merge "lib: cpus: denver: add some MIDR values" into integrationVarun Wadekar
2020-08-14Merge changes from topic "sp_dual_signing" into integrationManish Pandey
* changes: SPM: Add owner field to cactus secure partitions SPM: Alter sp_gen.mk entry depending on owner of partition plat/arm: enable support for Plat owned SPs
2020-08-14plat/arm: enable support for Plat owned SPsManish Pandey
For Arm platforms SPs are loaded by parsing tb_fw_config.dts and adding them to SP structure sequentially, which in-turn is appended to loadable image list. With recently introduced dualroot CoT for SPs where they are owned either by SiP or by Platform. SiP owned SPs index starts at SP_PKG1_ID and Plat owned SPs index starts at SP_PKG5_ID. As the start index of SP depends on the owner, there should be a mechanism to parse owner of a SP and put it at the correct index in SP structure. This patch adds support for parsing a new optional field "owner" and based on it put SP details(UUID & Load-address) at the correct index in SP structure. Change-Id: Ibd255b60d5c45023cc7fdb10971bef6626cb560b Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2020-08-14Merge changes from topic "sp_dual_signing" into integrationSandrine Bailleux
* changes: dualroot: add chain of trust for Platform owned SPs cert_create: add Platform owned secure partitions support
2020-08-14Specify signed-ness of constantsJimmy Brisson
We relyed on the default signed-ness of constants, which is usually signed. This can create MISRA violations, such as: bl1/bl1_main.c:257:[MISRA C-2012 10.8 (required)] Cast of composite expression off essential type signed to essential type unsigned These constants were only used as unsigned, so this patch makes them explicitly unsigned. Change-Id: I5f1310c881e936077035fbb1d5ffb449b45de3ad Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-14Prevent colliding identifiersJimmy Brisson
There was a collision between the name of the typedef in the CASSERT and something else, so we make the name of the typedef unique to the invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into the macro. This eliminates the following MISRA violation: bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier "invalid_svc_uuid" is already used to represent a typedef. This also resolves MISRA rule 5.9. These renamings are as follows: * tzram -> secram. This matches the function call name as it has sec_mem in it's name * fw_config_base -> config_base. This file does not mess with hw_conig, so there's little chance of confusion Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-12dualroot: add chain of trust for Platform owned SPsManish Pandey
For dualroot CoT there are two sets of SP certificates, one owned by Silicon Provider(SiP) and other owned by Platform. Each certificate can have a maximum of 4 SPs. This patch reduces the number of SiP owned SPs from 8 to 4 and adds the remaining 4 to Plat owned SP. Plat owned SP certificate is signed using Platform RoT key and protected against anti-rollback using the Non-trusted Non-volatile counter. Change-Id: Idc3ddd87d6d85a5506a7435f45a6ec17c4c50425 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2020-08-12cert_create: add Platform owned secure partitions supportManish Pandey
Add support to generate a certificate named "plat-sp-cert" for Secure Partitions(SP) owned by Platform. Earlier a single certificate file "sip-sp-cert" was generated which contained hash of all 8 SPs, with this change SPs are divided into two categories viz "SiP owned" and "Plat owned" containing 4 SPs each. Platform RoT key pair is used for signing. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I5bd493cfce4cf3fc14b87c8ed1045f633d0c92b6
2020-08-11Merge "TF-A AMU extension: fix detection of group 1 counters." into integrationMark Dykes
2020-08-11Merge "plat/arm: Reduce size of BL31 binary" into integrationManish Pandey
2020-08-11plat: marvell: ap807: implement workaround for errata-id 3033912Stefan Chulski
ERRATA ID: RES-3033912 - Internal Address Space Init state causes a hang upon accesses to [0xf070_0000, 0xf07f_ffff] Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and [0x80_0000, 0xff_ffff] that cause accesses to the segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. Reuse common work-around code for both AP806 and AP807. Change-Id: Ia91a4802d02917d1682faa0c81571093d1687d97 Signed-off-by: Stefan Chulski <stefanc@marvell.com>
2020-08-10Merge changes from topic "release/14.0" into integrationManish Pandey
* changes: docs: marvell: update PHY porting layer description docs: marvell: update path in marvell documentation docs: marvell: update build instructions with CN913x plat: marvell: octeontx: add support for t9130 plat: marvell: t9130: add SVC support plat: marvell: t9130: update AVS settings plat: marvell: t9130: pass actual CP count for load_image plat: marvell: armada: a7k: add support to SVC validation mode plat: marvell: armada: add support for twin-die combined memory device
2020-08-10TF-A AMU extension: fix detection of group 1 counters.Alexei Fedorov
This patch fixes the bug when AMUv1 group1 counters was always assumed being implemented without checking for its presence which was causing exception otherwise. The AMU extension code was also modified as listed below: - Added detection of AMUv1 for ARMv8.6 - 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now calculated based on 'AMU_GROUP1_COUNTERS_MASK' value - Added bit fields definitions and access functions for AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers - Unification of amu.c Aarch64 and Aarch32 source files - Bug fixes and TF-A coding style compliant changes. Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-08-10plat/arm: Reduce size of BL31 binaryAlexei Fedorov
BL31 binary size is aligned to 4KB because of the code in include\plat\arm\common\arm_reclaim_init.ld.S: __INIT_CODE_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); __INIT_CODE_END__ = .; with all the zero data after the last instruction of BL31 code to the end of the page. This causes increase in size of BL31 binary stored in FIP and its loading time by BL2. This patch reduces the size of BL31 image by moving page alignment from __INIT_CODE_END__ to __STACKS_END__ which also increases the stack size for secondary CPUs. Change-Id: Ie2ec503fc774c22c12ec506d74fd3ef2b0b183a9 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-08-08lib: cpus: denver: add some MIDR valuesAlex Van Brunt
This patch adds support for additional Denver MIDRs to cover all the current SKUs. Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28 Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-08-04Merge "SPM: build OP-TEE as an S-EL1 Secure Partition" into integrationManish Pandey
2020-07-31tbbr/dualroot: rename SP package certificate fileManish Pandey
Currently only single signing domain is supported for SP packages but there is plan to support dual signing domains if CoT is dualroot. SP_CONTENT_CERT_ID is the certificate file which is currently generated and signed with trusted world key which in-turn is derived from Silicon provider RoT key. To allow dual signing domain for SP packages, other certificate file will be derived from Platform owned RoT key. This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and does other related changes. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
2020-07-30SPM: build OP-TEE as an S-EL1 Secure PartitionOlivier Deprez
Provide manifest and build options to boot OP-TEE as a guest S-EL1 Secure Partition on top of Hafnium in S-EL2. Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb
2020-07-30plat: marvell: t9130: pass actual CP count for load_imageBen Peled
Add CN913x case to bl2_plat_get_cp_count. Fix loading of cp1/2 image. This is a preparation patch for adding CN913x SoC family support. Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9 Signed-off-by: Ben Peled <bpeled@marvell.com>
2020-07-29GIC-600: Fix MISRA-2012 defectsAlexei Fedorov
This patch fixes violation of Rules 10.1, 10.4, 11.9 and 13.2 reported by MISRA-2012 scan. Change-Id: Ibe9190cb0f26ae85d9a31db8e92fbd32f1740e25 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-28Merge "SMCCC: Introduce function to check SMCCC function availability" into ↵Madhukar Pappireddy
integration
2020-07-27TZ DMC620 driver: Fix MISRA-2012 defectsAlexei Fedorov
This patch fixes defects 10.3, 10.4, 10.7, 20.7 reported by MISRA-2012 scan and adds braces for conditional statements according to the TF-A coding style. Change-Id: If84ed31cdd55bc8e7cdd2a5f48c0dacc25792112 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-26SMCCC: Introduce function to check SMCCC function availabilityManish V Badarkhe
Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to be not correct for the platform which doesn't implement soc-id functionality i.e. functions to retrieve both soc-version and soc-revision. Hence introduced a platform function which will check whether SMCCC feature is available for the platform. Also, updated porting guide for the newly added platform function. Change-Id: I389f0ef6b0837bb24c712aa995b7176117bc7961 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-23Merge "Revert workaround for Neoverse N1 erratum 1800710" into integrationLauren Wehrmeister
2020-07-23Revert workaround for Neoverse N1 erratum 1800710johpow01
This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97