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2019-02-27Merge pull request #1829 from antonio-nino-diaz-arm/an/pauthAntonio Niño Díaz
Add Pointer Authentication (ARMv8.3-PAuth) support to the TF
2019-02-27Merge pull request #1840 from grandpaul/rpi3-sdhost-improve1Antonio Niño Díaz
RaspberryPi3 sdhost driver improvement.
2019-02-27TSP: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.4% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +352 | +0 | +16 | +0 | | | 3.1% | | 15.8% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I6cc1fe0b2345c547dcef66f98758c4eb55fe5ee4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27BL31: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +192 | +1536 | +0 | +0 | | | 0.3% | 3.1% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +1848 | +1536 | +16 | +0 | | | 3.3% | 3.1% | 3.1% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I43db7e509a4f39da6599ec2faa690d197573ec1b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27BL2_AT_EL3: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +44 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +712 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ The results are valid for the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ BL2_AT_EL3=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I1c0616e7dea30962a92b4fd113428bc30a018320 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27BL2: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +664 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 The changes for BL2_AT_EL3 aren't done in this commit. Change-Id: I8c803b40c7160525a06173bc6cdca21c4505837d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27BL1: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +108 | +192 | +0 | +0 | | | 0.5% | 0.8% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +748 | +192 | +16 | +0 | | | 3.7% | 0.8% | 7.0% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I3a7d02feb6a6d212be32a01432b0c7c1a261f567 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27Add support for pointer authenticationAntonio Nino Diaz
The previous commit added the infrastructure to load and save ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but didn't actually enable pointer authentication in the firmware. This patch adds the functionality needed for platforms to provide authentication keys for the firmware, and a new option (ENABLE_PAUTH) to enable pointer authentication in the firmware itself. This option is disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be enabled. Change-Id: I35127ec271e1198d43209044de39fa712ef202a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27Add ARMv8.3-PAuth registers to CPU contextAntonio Nino Diaz
ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27Cleanup context handling libraryAntonio Nino Diaz
Minor style cleanup. Change-Id: Ief19dece41a989e2e8157859a265701549f6c585 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27Merge pull request #1831 from antonio-nino-diaz-arm/an/sccdAntonio Niño Díaz
Disable processor Cycle Counting in Secure state
2019-02-27rpi3: sdhost: SDHost driver improvementYing-Chun Liu (PaulLiu)
This commit improves the SDHost driver for RPi3 as following: * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on block reading. * In some low probability that SEND_OP_COND might results CRC7 error. We can consider that the command runs correctly. We don't need to retry this command so removing the code for retry. * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability. * Increase the clock to 50Mhz in data mode to speed up the io. * Change the pull resistors configuration to gain more stability. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
2019-02-22Merge pull request #1836 from Yann-lms/docs_and_m4Antonio Niño Díaz
Update documentation for STM32MP1 and add Cortex-M4 support
2019-02-22Merge pull request #1835 from jts-arm/renameAntonio Niño Díaz
Apply official names to new Arm Neoverse cores
2019-02-21Merge pull request #1828 from uarif1/masterAntonio Niño Díaz
Introduce Versatile Express FVP platform to arm-trusted-firmware.
2019-02-20stm32mp1: add minimal support for co-processor Cortex-M4Yann Gautier
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-02-19plat/arm: Support for Cortex A5 in FVP Versatile Express platformUsama Arif
Cortex A5 doesnt support VFP, Large Page addressing and generic timer which are addressed in this patch. The device tree for Cortex a5 is also included. Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678 Signed-off-by: Usama Arif <usama.arif@arm.com>
2019-02-19Division functionality for cores that dont have divide hardware.Usama Arif
Cortex a5 doesnt support hardware division such as sdiv and udiv commands. This commit adds a software division function in assembly as well as include appropriate files for software divison. The software division algorithm is a modified version obtained from: http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm Change-Id: Ib405a330da5f1cea1e68e07e7b520edeef9e2652 Signed-off-by: Usama Arif <usama.arif@arm.com>
2019-02-19ARMv7: support non-LPAE mapping (not xlat_v2)Etienne Carriere
Support 32bit descriptor MMU table. This is required by ARMv7 architectures that do not support the Large Page Address Extensions. nonlpae_tables.c source file is dumped from the OP-TEE project: core_mmu_armv7.c and related header files. Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Usama Arif <usama.arif@arm.com>
2019-02-19Rename Cortex-Helios to Neoverse E1John Tsichritzis
Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19Rename Cortex-Helios filenames to Neoverse E1John Tsichritzis
Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19Rename Cortex-Ares to Neoverse N1John Tsichritzis
Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19Rename Cortex-Ares filenames to Neoverse N1John Tsichritzis
Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19Merge pull request #1825 from antonio-nino-diaz-arm/an/csv2Antonio Niño Díaz
Update macro to check need for CVE-2017-5715 mitigation
2019-02-18Disable processor Cycle Counting in Secure stateAntonio Nino Diaz
In a system with ARMv8.5-PMU implemented: - If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting in Secure state in PMCCNTR. - If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in Secure state in PMCCNTR_EL0. So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64) or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure as any EL can change that value. Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-18Rename PLAT_ARM_BL31_RUN_UART* variableUsama Arif
The variable is renamed to PLAT_ARM_RUN_UART as the UART is used outside BL31 as well. Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a Signed-off-by: Usama Arif <usama.arif@arm.com>
2019-02-14Update macro to check need for CVE-2017-5715 mitigationAntonio Nino Diaz
Armv8.5 introduces the field CSV2 to register ID_AA64PFR0_EL1. It can have the following 3 values: - 0: Branch targets trained in one hardware described context may affect speculative execution in a different hardware described context. In some CPUs it may be needed to apply mitigations. - 1: Branch targets trained in one hardware described context can only affect speculative execution in a different hardware described context in a hard-to-determine way. No mitigation required. - 2: Same as 1, but the device is also aware of SCXTNUM_ELx register contexts. The TF doesn't use the registers, so there is no difference with 1. The field CSV2 was originally introduced in the TRM of the Cortex-A76 before the release of the Armv8.5 architecture. That TRM only mentions the meaning of values 0 and 1. Because of this, the code only checks if the field has value 1 to know whether to enable or disable the mitigations. This patch makes it aware of value 2 as well. Both values 1 and 2 disable the mitigation, and 0 enables it. Change-Id: I5af33de25a0197c98173f52c6c8c77b51a51429f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-14stm32mp1: update clock driverYann Gautier
Remove useless private structure in function prototypes. Add a reference counter on clocks. Prepare for future secured/shared/non-secured clocks. Change-Id: I3dbed81721da5ceff5e10b2c4155b1e340c036ee Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
2019-02-14stm32mp1: add timeout detection in reset driverYann Gautier
This change makes the platform to panic in case of peripheral reset resource malfunction. Change-Id: I17eb9cb045b78a4e5142a8c33b744e84992d732a Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
2019-02-14stm32mp1: split clkfunc codeYann Gautier
Create a new file stm32mp_clkfunc.c to put functions that could be common between several platforms. Change-Id: Ica915c796b162b2345056b33328acc05035a242c Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-02-14stm32mp1: update I2C and PMIC driversYann Gautier
Regulator configuration at boot takes more information from DT. I2C configuration from DT is done in I2C driver. I2C driver manages more transfer modes. The min voltage of buck1 should also be increased to 1.2V, else the platform does not boot. Heavily modifies stm32_i2c.c since many functions move inside the source file to remove redundant declarations. Change-Id: I0bee5d776cf3ff15e687427cd6abc06ab237d025 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
2019-02-14stm32mp1: use new functions to manage timeoutsYann Gautier
Remove the previously use function: get_timer, and use new functions timeout_init_us and timeout_elapsed. Change-Id: I4e95b123648bff7ca91e40462a2a3ae24cfe1697 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
2019-02-14stm32mp1: make functions and macros more commonYann Gautier
Mainly remove suffix 1 from prefix stm32mp1 in several macros and functions that can be used in drivers shared by different platforms. Change-Id: I2295c44f5b1edac7e80a93c0e8dfd671b36e88e7 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2019-02-11cpus: Add casts to all definitions in CPU headersAntonio Nino Diaz
There are some incorrect casts and some missing casts in the headers. This patch fixes the ones that were 64-bit or 32-bit wide wrongly and adds casts where they were missing. Note that none of the changes of the patch actually changes the values of the definitions. This patch is just for correctness. Change-Id: Iad6458021bad521922ce4f91bafff38b116b49eb Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-11cpus: Fix some incorrect definitions in CPU headersAntonio Nino Diaz
There are some values that should be 64-bit immediates but that resolve to 0 because the type of the value is 32-bit wide. This patch casts the expressions to 64-bit before the shift so that the definition has the correct value. The definitions are only used in assembly so far, so the code is not actually affected by this bug. The assembler treats all values as 64-bit values, so there are no overflows. Change-Id: I965e4be631c1d28787c0913661d224c82a6b9155 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-08libc: Move setjmp to libc folderAntonio Nino Diaz
Now that setjmp() and longjmp() are compliant with the standard they can be moved with the other libc files. Change-Id: Iea3b91c34eb353ace5e171e72f331602d57774d5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-08Make setjmp.h prototypes comply with the C standardAntonio Nino Diaz
Instead of having a custom implementation of setjmp() and longjmp() it is better to follow the C standard. The comments in setjmp.h are no longer needed as there are no deviations from the expected one, so they have been removed. All SDEI code that relied on them has been fixed to use the new function prototypes and structs. Change-Id: I6cd2e21cb5a5bcf81ba12283f2e4c067bd5172ca Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-06Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19Antonio Niño Díaz
Tf2.0 tegra downstream rebase 1.25.19
2019-02-06drivers: generic_delay_timer: Assert presence of Generic TimerAntonio Nino Diaz
The Generic Timer is an optional extension to an ARMv7-A implementation. The generic delay timer can be used from any architecture supported by the Trusted Firmware. In ARMv7 it is needed to check that this feature is present. In ARMv8 it is always present. Change-Id: Ib7e8ec13ffbb2f64445d4ee48ed00f26e34b79b7 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-05Merge pull request #1804 from antonio-nino-diaz-arm/an/cleanupAntonio Niño Díaz
Minor cleanup
2019-02-04Merge pull request #1803 from sandrine-bailleux-arm/sb/arm-bl33-fixesAntonio Niño Díaz
Fixes related to BL33 image on Arm platforms
2019-02-04Merge pull request #1796 from grandpaul/rpi3-sdhost-driverAntonio Niño Díaz
RPi3 SDHost driver
2019-02-01Remove duplicated definitions of linker symbolsAntonio Nino Diaz
Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-01Arm platforms: Rename PLAT_ARM_NS_IMAGE_OFFSETSandrine Bailleux
PLAT_ARM_NS_IMAGE_OFFSET is in fact not an offset relative to some base address, it is an absolute address. Rename it to avoid any confusion. Change-Id: I1f7f5e8553cb267786afe7e5f3cd4d665b610d3f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-02-01rpi3: Add SDHost driverYing-Chun Liu (PaulLiu)
This commit adds SDHost driver for RaspberryPi3. SDHost driver uses the GPIO driver to connect the SDCard and SDHost. By using this driver it is able to read/write raw blocks on SDCard. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
2019-01-31tlkd: support new TLK SMCsMihir Joshi
This patch adds support to handle following TLK SMCs: {TLK_SS_REGISTER_HANDLER, TLK_REGISTER_NS_DRAM_RANGES, TLK_SET_ROOT_OF_TRUST} These SMCs need to be supported in ATF in order to forward them to TLK. Otherwise, these functionalities won't work. Brief: TLK_SS_REGISTER_HANDLER: This SMC is issued by TLK Linux Driver to set up secure storage buffers. TLK_REGISTER_NS_DRAM_RANGES: Cboot performs this SMC during boot to pass NS memory ranges to TLK. TLK_SET_ROOT_OF_TRUST: Cboot performs this SMC during boot to pass Verified Boot parameters to TLK. Change-Id: I18af35f6dd6f510dfc22c1d1d1d07f643c7b82bc Reviewed-on: https://git-master.nvidia.com/r/1643851 Signed-off-by: Mihir Joshi <mihirj@nvidia.com>
2019-01-31Remove dead code related to LOAD_IMAGE_V2=0Sandrine Bailleux
Commit ed51b51f7a9163a ("Remove build option LOAD_IMAGE_V2") intended to remove all code related to LOAD_IMAGE_V2=0 but missed a few things. Change-Id: I16aaf52779dd4af1e134e682731328c5f1e5d622 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-31Merge pull request #1797 from antonio-nino-diaz-arm/an/remove-smccc-v2Antonio Niño Díaz
Remove support for the SMC Calling Convention 2.0
2019-01-31Merge pull request #1792 from satheesbalya-arm/sb1/sb1_2159_v84_xlatAntonio Niño Díaz
lib/xlat_tables: Add support for ARMv8.4-TTST
2019-01-30Remove support for the SMC Calling Convention 2.0Antonio Nino Diaz
This reverts commit 2f370465241c ("Add support for the SMC Calling Convention 2.0"). SMCCC v2.0 is no longer required for SPM, and won't be needed in the future. Removing it makes the SMC handling code less complicated. The SPM implementation based on SPCI and SPRT was using it, but it has been adapted to SMCCC v1.0. Change-Id: I36795b91857b2b9c00437cfbfed04b3c1627f578 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>