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2014-07-31Optimize EL3 register state stored in cpu_context structureSoby Mathew
This patch further optimizes the EL3 register state stored in cpu_context. The 2 registers which are removed from cpu_context are: * cntfrq_el0 is the system timer register which is writable only in EL3 and it can be programmed during cold/warm boot. Hence it need not be saved to cpu_context. * cptr_el3 controls access to Trace, Floating-point, and Advanced SIMD functionality and it is programmed every time during cold and warm boot. The current BL3-1 implementation does not need to modify the access controls during normal execution and hence they are expected to remain static. Fixes ARM-software/tf-issues#197 Change-Id: I599ceee3b73a7dcfd37069fd41b60e3d397a7b18
2014-07-28Merge pull request #177 from jcastillo-arm/jc/tf-issues/096danh-arm
Rework incorrect use of assert() and panic() in codebase
2014-07-28Merge pull request #172 from soby-mathew/sm/asm_assertdanh-arm
Introduce asm assert and optimize crash reporting
2014-07-28Merge pull request #170 from achingupta/ag/tf-issues#226danh-arm
Simplify management of SCTLR_EL3 and SCTLR_EL1
2014-07-28Merge pull request #169 from achingupta/ag/tf-issues#198danh-arm
Ag/tf issues#198
2014-07-28Rework incorrect use of assert() and panic() in codebaseJuan Castillo
Assert a valid security state using the macro sec_state_is_valid(). Replace assert() with panic() in those cases that might arise because of runtime errors and not programming errors. Replace panic() with assert() in those cases that might arise because of programming errors. Fixes ARM-software/tf-issues#96 Change-Id: I51e9ef0439fd5ff5e0edfef49050b69804bf14d5
2014-07-28Add CPUECTLR_EL1 and Snoop Control register to crash reportingSoby Mathew
This patch adds the CPUECTLR_EL1 register and the CCI Snoop Control register to the list of registers being reported when an unhandled exception occurs. Change-Id: I2d997f2d6ef3d7fa1fad5efe3364dc9058f9f22c
2014-07-28Rework the crash reporting in BL3-1 to use less stackSoby Mathew
This patch reworks the crash reporting mechanism to further optimise the stack and code size. The reporting makes use of assembly console functions to avoid calling C Runtime to report the CPU state. The crash buffer requirement is reduced to 64 bytes with this implementation. The crash buffer is now part of per-cpu data which makes retrieving the crash buffer trivial. Also now panic() will use crash reporting if invoked from BL3-1. Fixes ARM-software/tf-issues#199 Change-Id: I79d27a4524583d723483165dc40801f45e627da5
2014-07-28Implement an assert() callable from assembly codeSoby Mathew
The patch implements a macro ASM_ASSERT() which can be invoked from assembly code. When assertion happens, file name and line number of the check is written to the crash console. Fixes ARM-software/tf-issues#95 Change-Id: I6f905a068e1c0fa4f746d723f18df60daaa00a86
2014-07-28Introduce crash console APIs for crash reportingSoby Mathew
This patch introduces platform APIs to initialise and print a character on a designated crash console. For the FVP platform, PL011_UART0 is the designated crash console. The platform porting guide is also updated to document the new APIs. Change-Id: I5e97d8762082e0c88c8c9bbb479353eac8f11a66
2014-07-28Parametrize baudrate and UART clock during console_init()Soby Mathew
This patch adds baud rate and UART clock frequency as parameters to the pl011 driver api console_init(). This allows each platform to specify UART clock and baud rate according to their specific hardware implementation. Fixes ARM-software/tf-issues#215 Change-Id: Id13eef70a1c530e709b34dd1e6eb84db0797ced2
2014-07-28Introduce asm console functions in TFSoby Mathew
This patch replaces the pl011 console family of functions with their equivalents defined in assembly. The baud rate is defined by the PL011_BAUDRATE macro and IBRD and FBRD values for pl011 are computed statically. This patch will enable us to invoke the console functions without the C Runtime Stack. Change-Id: Ic3f7b7370ded38bf9020bf746b362081b76642c7
2014-07-28Simplify management of SCTLR_EL3 and SCTLR_EL1Achin Gupta
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They do not have to be saved and restored either. The M, WXN and optionally the C bit are set in the enable_mmu_elX() function. This is done during both the warm and cold boot paths. Fixes ARM-software/tf-issues#226 Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
2014-07-25Add support for printing version at runtimeJuan Castillo
Print out Trusted Firmware version at runtime at each BL stage. Message consists of TF version as defined statically in the Makefile (e.g. v0.4), build mode (debug|release) and a customizable build string: 1. By defining BUILD_STRING in command line when building TF 2. Default string is git commit ID 3. Empty if git meta-data is not available Fixes ARM-software/tf-issues#203 Change-Id: I5c5ba438f66ab68810427d76b49c5b9177a957d6
2014-07-25Implement a leaner printf for Trusted FirmwareSoby Mathew
This patch implements a "tf_printf" which supports only the commonly used format specifiers in Trusted Firmware, which uses a lot less stack space than the stdlib printf function. Fixes ARM-software/tf-issues#116 Change-Id: I7dfa1944f4c1e634b3e2d571f49afe02d109a351
2014-07-19Remove coherent stack usage from the warm boot pathAchin Gupta
This patch uses stacks allocated in normal memory to enable the MMU early in the warm boot path thus removing the dependency on stacks allocated in coherent memory. Necessary cache and stack maintenance is performed when a cpu is being powered down and up. This avoids any coherency issues that can arise from reading speculatively fetched stale stack memory from another CPUs cache. These changes affect the warm boot path in both BL3-1 and BL3-2. The EL3 system registers responsible for preserving the MMU state are not saved and restored any longer. Static values are used to program these system registers when a cpu is powered on or resumed from suspend. Change-Id: I8357e2eb5eb6c5f448492c5094b82b8927603784
2014-07-19Make enablement of the MMU more flexibleAchin Gupta
This patch adds a 'flags' parameter to each exception level specific function responsible for enabling the MMU. At present only a single flag which indicates whether the data cache should also be enabled is implemented. Subsequent patches will use this flag when enabling the MMU in the warm boot paths. Change-Id: I0eafae1e678c9ecc604e680851093f1680e9cefa
2014-07-11Merge pull request #162 from jcastillo-arm/jc/tf-issues/194danh-arm
Allow FP register context to be optional at build time
2014-07-11Merge pull request #164 from sandrine-bailleux/sb/bl30-support-v2danh-arm
Add support for BL3-0 image (v2)
2014-07-10Add support for BL3-0 imageSandrine Bailleux
- Add support for loading a BL3-0 image in BL2. Information about memory extents is populated by platform-specific code. Subsequent handling of BL3-0 is also platform specific. The BL2 main function has been broken down to improve readability. The BL3-2 image is now loaded before the BL3-3 image to align with the boot flow. - Build system: Add support for specifying a BL3-0 image that will be included into the FIP image. - IO FIP driver: Add support for identifying a BL3-0 image inside a FIP image. - Update the documentation to reflect the above changes. Change-Id: I067c184afd52ccaa86569f13664757570c86fc48
2014-07-10Merge pull request #157 from sandrine-bailleux/sb/tf-issue-109danh-arm
TF issue 109
2014-07-10Merge pull request #146 from danh-arm/dh/refactor-fvp-gicdanh-arm
Refactor fvp config and gic code
2014-07-10Allow FP register context to be optional at build timeJuan Castillo
CTX_INCLUDE_FPREGS make variable allows us to include or exclude FP registers from context structure, in case FP is not used by TSPD. Fixes ARM-software/tf-issues#194 Change-Id: Iee41af382d691340c7ae21830ad1bbf95dad1f4b
2014-07-09Refactor fvp gic code to be a generic driverDan Handley
Refactor the FVP gic code in plat/fvp/fvp_gic.c to be a generic ARM GIC driver in drivers/arm/gic/arm_gic.c. Provide the platform specific inputs in the arm_gic_setup() function so that the driver has no explicit dependency on platform code. Provide weak implementations of the platform interrupt controller API in a new file, plat/common/plat_gic.c. These simply call through to the ARM GIC driver. Move the only remaining FVP GIC function, fvp_gic_init() to plat/fvp/aarch64/fvp_common.c and remove plat/fvp/fvp_gic.c Fixes ARM-software/tf-issues#182 Change-Id: Iea82fe095fad62dd33ba9efbddd48c57717edd21
2014-07-09Refactor fvp_config into common platform headerDan Handley
Changed the fvp_config array in fvp_common.c into a struct and moved into a new optional common platform header, include/plat/common/plat_config.h. Removed the config definitions in fvp_def.h and updated all references to the platform config. This makes the interface to the platform config cleaner and uses a little less RAM. Fixes ARM-software/tf-issues#180 Change-Id: I58dd7b3c150f24f7ee230a26fd57c827853ba803
2014-07-09Calculate TCR bits based on VA and PALin Ma
Currently the TCR bits are hardcoded in xlat_tables.c. In order to map higher physical address into low virtual address, the TCR bits need to be configured accordingly. This patch is to save the max VA and PA and calculate the TCR.PS/IPS and t0sz bits in init_xlat_tables function. Change-Id: Ia7a58e5372b20200153057d457f4be5ddbb7dae4
2014-07-01Remove concept of top/bottom image loadingSandrine Bailleux
This concept is no longer required since we now support loading of images at fixed addresses only. The image loader now automatically detects the position of the image inside the current memory layout and updates the layout such that memory fragmentation is minimised. The 'attr' field of the meminfo data structure, which used to hold the bottom/top loading information, has been removed. Also the 'next' field has been removed as it wasn't used anywhere. The 'init_bl2_mem_layout()' function has been moved out of common code and put in BL1-specific code. It has also been renamed into 'bl1_init_bl2_mem_layout'. Fixes ARM-software/tf-issues#109 Change-Id: I3f54642ce7b763d5ee3b047ad0ab59eabbcf916d
2014-06-26Merge pull request #154 from athoelke/at/inline-mmioAndrew Thoelke
Inline the mmio accessor functions
2014-06-24Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2danh-arm
Remove all checkpatch errors from codebase
2014-06-24Merge pull request #147 from athoelke/at/remove-bakery-mpidrdanh-arm
Remove calling CPU mpidr from bakery lock API
2014-06-24Inline the mmio accessor functionsAndrew Thoelke
Making the simple mmio_read_*() and mmio_write_*() functions inline saves 360 bytes of code in FVP release build. Fixes ARM-software/tf-issues#210 Change-Id: I65134f9069f3b2d8821d882daaa5fdfe16355e2f
2014-06-24Remove all checkpatch errors from codebaseJuan Castillo
Exclude stdlib files because they do not follow kernel code style. Fixes ARM-software/tf-issues#73 Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab
2014-06-23Remove calling CPU mpidr from bakery lock APIAndrew Thoelke
The bakery lock code currently expects the calling code to pass the MPIDR_EL1 of the current CPU. This is not always done correctly. Also the change to provide inline access to system registers makes it more efficient for the bakery lock code to obtain the MPIDR_EL1 directly. This change removes the mpidr parameter from the bakery lock interface, and results in a code reduction of 160 bytes for the ARM FVP port. Fixes ARM-software/tf-issues#213 Change-Id: I7ec7bd117bcc9794a0d948990fcf3336a367d543
2014-06-23Correctly dimension the PSCI aff_map_node arrayAndrew Thoelke
The array of affinity nodes is currently allocated for 32 entries with the PSCI_NUM_AFFS value defined in psci.h. This is not enough for large systems, and will substantially over allocate the array for small systems. This patch introduces an optional platform definition PLATFORM_NUM_AFFS to platform_def.h. If defined this value is used for PSCI_NUM_AFFS, otherwise a value of two times the number of CPU cores is used. The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves nearly 1.5KB of memory. Fixes ARM-software/tf-issues#192 Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445
2014-06-23Initialise CPU contexts from entry_point_infoAndrew Thoelke
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI and SPDs into two functions: * The first uses entry_point_info to initialize the relevant cpu_context for first entry into a lower exception level on a CPU * The second populates the EL1 and EL2 system registers as needed from the cpu_context to ensure correct entry into the lower EL This patch alters the way that BL3-1 determines which exception level is used when first entering EL1 or EL2 during cold boot - this is now fully determined by the SPSR value in the entry_point_info for BL3-3, as set up by the platform code in BL2 (or otherwise provided to BL3-1). In the situation that EL1 (or svc mode) is selected for a processor that supports EL2, the context management code will now configure all essential EL2 register state to ensure correct execution of EL1. This allows the platform code to run non-secure EL1 payloads directly without requiring a small EL2 stub or OS loader. Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
2014-06-23Merge pull request #138 from athoelke/at/cpu-contextdanh-arm
Move CPU context pointers into cpu_data
2014-06-17Remove early_exceptions from BL3-1Andrew Thoelke
The crash reporting support and early initialisation of the cpu_data allow the runtime_exception vectors to be used from the start in BL3-1, removing the need for the additional early_exception vectors and 2KB of code from BL3-1. Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871
2014-06-16Move CPU context pointers into cpu_dataAndrew Thoelke
Moving the context pointers for each CPU into the per-cpu data allows for much more efficient access to the contexts for the current CPU. Change-Id: Id784e210d63cbdcddb44ac1591617ce668dbc29f
2014-06-16Per-cpu data cache restructuringAndrew Thoelke
This patch prepares the per-cpu pointer cache for wider use by: * renaming the structure to cpu_data and placing in new header * providing accessors for this CPU, or other CPUs * splitting the initialization of the TPIDR pointer from the initialization of the cpu_data content * moving the crash stack initialization to a crash stack function * setting the TPIDR pointer very early during boot Change-Id: Icef9004ff88f8eb241d48c14be3158087d7e49a3
2014-06-16Merge pull request #131 from athoelke/at/cm_get_contextdanh-arm
Provide cm_get/set_context() for current CPU
2014-06-16Merge pull request #130 from athoelke/at/inline-asm-sysreg-v2danh-arm
Make system register functions inline assembly v2
2014-06-11Provide cm_get/set_context() for current CPUAndrew Thoelke
All callers of cm_get_context() pass the calling CPU MPIDR to the function. Providing a specialised version for the current CPU results in a reduction in code size and better readability. The current function has been renamed to cm_get_context_by_mpidr() and the existing name is now used for the current-CPU version. The same treatment has been done to cm_set_context(), although only both forms are used at present in the PSCI and TSPD code. Change-Id: I91cb0c2f7bfcb950a045dbd9ff7595751c0c0ffb
2014-06-10Make system register functions inline assemblyAndrew Thoelke
Replace the current out-of-line assembler implementations of the system register and system instruction operations with inline assembler. This enables better compiler optimisation and code generation when accessing system registers. Fixes ARM-software/tf-issues#91 Change-Id: I149af3a94e1e5e5140a3e44b9abfc37ba2324476
2014-06-02Enable mapping higher physical addressLin Ma
Current ATF uses a direct physical-to-virtual mapping, that is, a physical address is mapped to the same address in the virtual space. For example, physical address 0x8000_0000 is mapped to 0x8000_0000 virtual. This approach works fine for FVP as all its physical addresses fall into 0 to 4GB range. But for other platform where all I/O addresses are 48-bit long, If we follow the same direct mapping, we would need virtual address range from 0 to 0x8fff_ffff_ffff, which is about 144TB. This requires a significant amount of memory for MMU tables and it is not necessary to use that much virtual space in ATF. The patch is to enable mapping a physical address range to an arbitrary virtual address range (instead of flat mapping) Changed "base" to "base_va" and added "base_pa" in mmap_region_t and modified functions such as mmap_add_region and init_xlation_table etc. Fixes ARM-software/tf-issues#158
2014-05-27Further renames of platform porting functionsDan Handley
Rename the ic_* platform porting functions to plat_ic_* to be consistent with the other functions in platform.h. Also rename bl31_get_next_image_info() to bl31_plat_get_next_image_ep_info() and remove the duplicate declaration in bl31.h. Change-Id: I4851842069d3cff14c0a468daacc0a891a7ede84
2014-05-27Remove FVP specific comments in platform.hDan Handley
Remove the FVP specific comments in platform.h since this file is re-usable across all platforms. Change-Id: Ifd4a4f72562adb3ecf8b9078b0150f170ef22dba
2014-05-23Add enable mmu platform porting interfacesfor-v0.4-rc0Dan Handley
Previously, the enable_mmu_elX() functions were implicitly part of the platform porting layer since they were included by generic code. These functions have been placed behind 2 new platform functions, bl31_plat_enable_mmu() and bl32_plat_enable_mmu(). These are weakly defined so that they can be optionally overridden by platform ports. Also, the enable_mmu_elX() functions have been moved to lib/aarch64/xlat_tables.c for optional re-use by platform ports. These functions are tightly coupled with the translation table initialization code. Fixes ARM-software/tf-issues#152 Change-Id: I0a2251ce76acfa3c27541f832a9efaa49135cc1c
2014-05-23Move BL porting functions into platform.hDan Handley
Some platform porting functions were in BL specific header files. These have been moved to platform.h so that all porting functions are in the same place. The functions are now grouped by BL. Obsolete BL headers files have been removed. Also, the weak declaration of the init_bl2_mem_layout() function has been moved out the header file and into the source file (bl_common.c) using the more succinct #pragma syntax. This mitigates the risk of 2 weak definitions being created and the wrong one being picked up by the compiler. Change-Id: Ib19934939fd755f3e5a5a5bceec88da684308a83
2014-05-23Split platform.h into separate headersDan Handley
Previously, platform.h contained many declarations and definitions used for different purposes. This file has been split so that: * Platform definitions used by common code that must be defined by the platform are now in platform_def.h. The exact include path is exported through $PLAT_INCLUDES in the platform makefile. * Platform definitions specific to the FVP platform are now in /plat/fvp/fvp_def.h. * Platform API declarations specific to the FVP platform are now in /plat/fvp/fvp_private.h. * The remaining platform API declarations that must be ported by each platform are still in platform.h but this file has been moved to /include/plat/common since this can be shared by all platforms. Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a
2014-05-23Remove unused data declarationsDan Handley
Some data variables were declared but not used. These have been removed. Change-Id: I038632af3c32d88984cd25b886c43ff763269bf9