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13 daysfeat(drivers/st): manage boot part in io_mmcVyacheslav Yurkov
Use dedicated read function for boot partition Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com> Change-Id: If75df7691fce0797205365736fc6e4e3429efdca
13 daysfeat(drivers/mmc): boot partition read supportVyacheslav Yurkov
Added a public function to read blocks from a current boot partition. switch between partitions has to respect eMMC partition switch timing. Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com> Change-Id: I55b0c910314253e5647486609583fd290dadd30a
2021-04-20Add SiP service to configure Arm Ethos-N NPUMikael Olsson
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode the non-secure world cannot access the registers needed to use the NPU. To still allow the non-secure world to use the NPU, a SiP service has been added that can delegate non-secure access to the registers needed to use it. Only the HW_CONFIG for the Arm Juno platform has been updated to include the device tree for the NPU and the platform currently only loads the HW_CONFIG in AArch64 builds. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
2021-04-15Merge changes from topic "scmi_v2_0" into integrationMadhukar Pappireddy
* changes: drivers/arm/css/scmi: Update power domain protocol version to 2.0 tc0: update GICR base address
2021-04-14drivers/arm/css/scmi: Update power domain protocol version to 2.0Nicola Mazzucato
The SCMI power domain protocol in firmware has been updated to v2.0, thus update the corresponding version in TF-A too. Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com> Change-Id: If3920ff71136dce94b2780e29a47f24aa09876c0
2021-04-13Merge changes from topic "dcc_console" into integrationMadhukar Pappireddy
* changes: plat:xilinx:versal: Add JTAG DCC support plat:xilinx:zynqmp: Add JTAG DCC support drivers: dcc: Support JTAG DCC console
2021-04-12Merge "driver: brcm: add USB driver" into integrationMadhukar Pappireddy
2021-04-12Merge "driver: brcm: add mdio driver" into integrationMadhukar Pappireddy
2021-03-31drivers: dcc: Support JTAG DCC consoleVenkatesh Yadav Abbarapu
The legacy console is gone. Re-add DCC console support based on the multi-console framework. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e
2021-03-29Merge changes from topic "tzc400_stm32mp" into integrationSandrine Bailleux
* changes: stm32mp1: add TZC400 interrupt management stm32mp1: use TZC400 macro to describe filters tzc400: add support for interrupts
2021-03-26driver: brcm: add i2c driverBharat Gooty
Broadcom I2C controller driver. Follwoing API's are supported:- - i2c_init() Intialize ethe I2C controller - i2c_probe() - i2c_set_bus_speed() Set the I2C bus speed - i2c_get_bus_speed() Get the current bus speed - i2c_recv_byte() Receive one byte of data. - i2c_send_byte() Send one byteof data - i2c_read_byte() Read single byte of data - i2c_read() Read multiple bytes of data - i2c_write_byte Write single byte of data - i2c_write() Write multiple bytes of data This driver is verified by reading the DDR SPD data. Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
2021-03-24nxp: adding the smmu driverPankaj Gupta
NXP SMMU driver API for NXP SoC. - Currently it supports by-passing SMMU, called only when NXP CAAM is enabled. - (TBD) AMQ based SMMU access control: Access Management Qualifiers (AMQ) advertised by a bus master for a given transaction. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I23a12928ddedb1a2cf4b396606e35c67e016e331
2021-03-24nxp: add flexspi driver supportKuldeep Singh
Flexspi driver now introduces read/write/erase APIs for complete flash size, FAST-READ are by default used and IP bus is used for erase, read and write using flexspi APIs. Framework layer is currently embedded in driver itself using flash_info defines. Test cases are also added to confirm flash functionality currently under DEBUG flag. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
2021-03-23tzc400: add support for interruptsYann Gautier
A new function tzc400_it_handler() is created to manage TZC400 interrupts. The required helpers to read and clear interrupts are added as well. In case DEBUG is enabled, more information about the faulty access (address, NSAID, type of access) is displayed. Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-03-10driver: brcm: add USB driverBharat Gooty
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Change-Id: I456aa7a641fffa8ea4e833615af3effec42a31b2
2021-03-08tzc400: correct FAIL_CONTROL Privileged bitYann Gautier
When bit 20 of TZC400 Fail control register [1] is set to 1, it means Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this. [1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-02-25Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into ↵Manish Pandey
integration * changes: plat/marvell/armada: cleanup MSS SRAM if used for copy plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage plat/marvell/armada/common/mss: use MSS SRAM in secure mode include/drivers/marvell/mochi: add detection of secure mode plat/marvell: fix SPD handling in dram port marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1 drivers/marvell/mochi: add support for cn913x in PCIe EP mode drivers/marvell/mochi: add missing stream IDs configurations plat/marvell/armada/a8k: support HW RNG by SMC drivers/rambus: add TRNG-IP-76 driver
2021-02-24driver: brcm: add mdio driverBharat Gooty
Change-Id: Id873670f68a4c584e3b7b586cab28565bb5a1c27 Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
2021-02-22Merge changes Ie5c48303,I5d363c46 into integrationMadhukar Pappireddy
* changes: tzc400: adjust filter flag if it is set to FILTER_BIT_ALL tzc400: fix logical error in FILTER_BIT definitions
2021-02-11include/drivers/marvell/mochi: add detection of secure modeKonstantin Porotchkin
Change-Id: I99afc312617df86ae68eb30302203a03877ca748 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/22541 Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com> Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
2021-02-11drivers/rambus: add TRNG-IP-76 driverKonstantin Porotchkin
Add Rambus (InsideSecure) TRNG-IP-76 HW RNG driver. This IP is part of Marvell Armada CP110/CP115 die integrated to Armada 7k/8K/CN913x SoCs Change-Id: I9c5f510ad6728c7ed168da43d85b19d5852cd873 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com>
2021-02-09tzc400: fix logical error in FILTER_BIT definitionsHeyi Guo
The filters parameter passed to tzc400_configure_region() is supposed to be filter bit flag without bit shift, so the macros TZC_400_REGION_ATTR_FILTER_BIT and TZC_400_REGION_ATTR_FILTER_BIT_ALL should always construct the value without any shift. It is not a functional issue for TZC_REGION_ATTR_F_EN_SHIFT is lucky to be 0. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I5d363c462b8517256523f637e670eefa56722afd
2021-02-04ddr: stm32mp1_ddr: correct SELFREF_TO_X32 maskYann Gautier
In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is wrong. This field is from bit 16 to 23. Change-Id: Id336fb08c88f0a153df186dd819e41af72febb88 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-01-27Merge changes from topic "scmi-msg" into integrationMadhukar Pappireddy
* changes: doc: maintainers: add scmi server drivers: move scmi-msg out of st
2021-01-20drivers: move scmi-msg out of stPeng Fan
Make the scmi-msg driver reused by others. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124
2021-01-18marvell: uart: a3720: Fix macro name for 6th bit of Status RegisterPali Rohár
This patch does not change code, it only updates comments and macro name for 6th bit of Status Register. So TF-A binary stay same. 6th bit of the Status Register is named TX EMPTY and is set to 1 when both Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are empty. It is when all characters were already transmitted. There is also TX FIFO EMPTY bit in the Status Register which is set to 1 only when THR is empty. In both console_a3700_core_init() and console_a3700_core_flush() functions we should wait until both THR and TSR are empty therefore we should check 6th bit of the Status Register. So current code is correct, just had misleading macro names and comments. This change fixes this "documentation" issue, fixes macro name for 6th bit of the Status Register and also updates comments. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3
2021-01-18marvell: uart: a3720: Implement console_a3700_core_getcPali Rohár
Implementation is simple, just check if there is a pending character in RX FIFO via RXRDY bit of Status Register and if yes, read it from UART_RX_REG register. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I226b6e336f44f5d0ca8dcb68e49a68e8f2f49708
2021-01-11cadence: Change logic in uart driverMichal Simek
Write char if fifo is empty. If this is done like this all chars are printed. Because origin code just put that chars to fifo and in case of reset messages were missing. Before this change chars are put to fifo and only check before adding if fifo is full. The patch is changing this logic that it is adding char only when fifo is empty to make sure that in case of reset (by another SW for example) all chars are printed. Maybe one char can be missed but for IP itself it is much easier to send just one char compare to full fifo. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f
2020-12-13allwinner: Return the PMIC to I2C mode after useSamuel Holland
This gives the rich OS the flexibility to choose between I2C and RSB communication. Since a runtime address can only be assigned once after entering RSB mode, it also lets the rich OS choose any runtime address. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id49c124c5e925985fc31c0ba38c7fb6c941aafa8
2020-10-14Merge "Don't return error information from console_flush" into integrationMark Dykes
2020-10-13stm32mp1: get peripheral base address from a defineYann Gautier
Retrieve peripheral base address from a define instead of parsing the device tree. The goal is to improve execution time. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b
2020-10-12Remove deprecated macro from TF-A codeManish V Badarkhe
Removed '__ASSEMBLY__' deprecated macro from TF-A code Change-Id: I9082a568b695acb5b903f509db11c8672b62d9d0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-10-09Don't return error information from console_flushJimmy Brisson
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-01Crypto library: Migrate support to MbedTLS v2.24.0Alexei Fedorov
This patch migrates the mbedcrypto dependency for TF-A to mbedTLS repo v2.24.0 which is the latest release tag. The relevant documentation is updated to reflect the use of new version. Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-09-29drivers: arm: gicv3: Allow detecting number of coresAndre Przywara
A GICv3 interrupt controller will be instantiated for a certain number of cores. This will result in the respective number of GICR frames. The last frame will have the "Last" bit set in its GICR_TYPER register. For platforms with a topology unknown at build time (the Arm FPGAs, for instance), we need to learn the number of used cores at runtime, to size the GICR region in the devicetree accordingly. Add a generic function that iterates over all GICR frames until it encounters one with the "Last" bit set. It returns the number of cores the GICv3 has been configured for. Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-25Merge changes from topic "stm32_drivers_update" into integrationManish Pandey
* changes: clk: stm32mp1: fix rcc mckprot status drivers: st: add missing includes in ETZPC header mmc: st: clear some flags before sending a command mmc: st: correct retries management nand: raw_nand: fix timeout issue in nand_wait_ready mtd: spi_nor: change message level on macronix detection gpio: stm32_gpio: check GPIO node status after checking DT crypto: stm32_hash: fix issue when restarting computation
2020-09-24drivers: st: add missing includes in ETZPC headerYann Gautier
Depending on compiler, the issue about bool or uint*_t not defined can appear. Correct this by adding stdbool.h and stdint.h includes in etzpc.h. Change-Id: If1419dc511efbe682459fa4a776481fa52a38aa3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-09-24nand: raw_nand: fix timeout issue in nand_wait_readyLionel Debieve
nand_wait_ready is called with a millisecond delay but the timeout used a micro second. Fixing the conversion in the timeout call. The prototype of the function is also changed to use an unsigned int parameter. Change-Id: Ia3281be7980477dfbfdb842308d35ecd8b926fb8 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-09-22Select the Log Level for the Event Log Dump on Measured Boot at build time.Javier Almansa Sobrino
Builds in Debug mode with Measured Boot enabled might run out of trusted SRAM. This patch allows to change the Log Level at which the Measured Boot driver will dump the event log, so the latter can be accessed even on Release builds if necessary, saving space on RAM. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I133689e313776cb3f231b774c26cbca4760fa120
2020-09-22Merge "plat: marvell: ap807: implement workaround for errata-id 3033912" ↵Manish Pandey
into integration
2020-09-15lib: fconf: Implement a parser to populate CoTManish V Badarkhe
Implemented a parser which populates the properties of the CoT descriptors as per the binding document [1]. 'COT_DESC_IN_DTB' build option is disabled by default and can be enabled in future for all Arm platforms by making necessary changes in the memory map. Currently, this parser is tested only for FVP platform. [1]: https://trustedfirmware-a.readthedocs.io/en/latest/components/cot-binding.html Change-Id: I2f911206087a1a2942aa728de151d2ac269d27cc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-08-12dualroot: add chain of trust for Platform owned SPsManish Pandey
For dualroot CoT there are two sets of SP certificates, one owned by Silicon Provider(SiP) and other owned by Platform. Each certificate can have a maximum of 4 SPs. This patch reduces the number of SiP owned SPs from 8 to 4 and adds the remaining 4 to Plat owned SP. Plat owned SP certificate is signed using Platform RoT key and protected against anti-rollback using the Non-trusted Non-volatile counter. Change-Id: Idc3ddd87d6d85a5506a7435f45a6ec17c4c50425 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2020-08-11plat: marvell: ap807: implement workaround for errata-id 3033912Stefan Chulski
ERRATA ID: RES-3033912 - Internal Address Space Init state causes a hang upon accesses to [0xf070_0000, 0xf07f_ffff] Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and [0x80_0000, 0xff_ffff] that cause accesses to the segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. Reuse common work-around code for both AP806 and AP807. Change-Id: Ia91a4802d02917d1682faa0c81571093d1687d97 Signed-off-by: Stefan Chulski <stefanc@marvell.com>
2020-08-10Merge changes from topic "release/14.0" into integrationManish Pandey
* changes: docs: marvell: update PHY porting layer description docs: marvell: update path in marvell documentation docs: marvell: update build instructions with CN913x plat: marvell: octeontx: add support for t9130 plat: marvell: t9130: add SVC support plat: marvell: t9130: update AVS settings plat: marvell: t9130: pass actual CP count for load_image plat: marvell: armada: a7k: add support to SVC validation mode plat: marvell: armada: add support for twin-die combined memory device
2020-07-31tbbr/dualroot: rename SP package certificate fileManish Pandey
Currently only single signing domain is supported for SP packages but there is plan to support dual signing domains if CoT is dualroot. SP_CONTENT_CERT_ID is the certificate file which is currently generated and signed with trusted world key which in-turn is derived from Silicon provider RoT key. To allow dual signing domain for SP packages, other certificate file will be derived from Platform owned RoT key. This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and does other related changes. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
2020-07-30plat: marvell: t9130: pass actual CP count for load_imageBen Peled
Add CN913x case to bl2_plat_get_cp_count. Fix loading of cp1/2 image. This is a preparation patch for adding CN913x SoC family support. Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9 Signed-off-by: Ben Peled <bpeled@marvell.com>
2020-07-29GIC-600: Fix MISRA-2012 defectsAlexei Fedorov
This patch fixes violation of Rules 10.1, 10.4, 11.9 and 13.2 reported by MISRA-2012 scan. Change-Id: Ibe9190cb0f26ae85d9a31db8e92fbd32f1740e25 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-27TZ DMC620 driver: Fix MISRA-2012 defectsAlexei Fedorov
This patch fixes defects 10.3, 10.4, 10.7, 20.7 reported by MISRA-2012 scan and adds braces for conditional statements according to the TF-A coding style. Change-Id: If84ed31cdd55bc8e7cdd2a5f48c0dacc25792112 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-21TF-A: Add Event Log for Measured BootAlexei Fedorov
This patch adds support for Event Log generation required for Measured Boot functionality. Change-Id: I34f05a33565e6659e78499d62cc6fb00b7d6c2dc Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-16Merge "drivers: st: clock: register parent of secure clocks" into integrationMadhukar Pappireddy