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2022-04-06feat(gic600ae_fmu): introduce support for RAS error handlingVarun Wadekar
The GIC-600AE uses a range of RAS features for all RAMs, which include SECDED, ECC, and Scrub, software and bus error reporting. The GIC makes all necessary information available to software through Armv8.2 RAS architecture compliant register space. This patch introduces support to probe the FMU_ERRGSR register to find the right error record. Once the correct record is identified, the "handler" function queries the FMU_ERR<m>STATUS register to further identify the block ID, safety mechanism and the architecturally defined primary error code. The description of the error is displayed on the console to simplify debug. Change-Id: I7e543664b74457afee2da250549f4c3d9beb1a03 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2022-03-27feat(nxp-gic): add some macros definition for gicv3Biwen Li
Add macros as follows, - GICD_ISENABLER_1 - GICD_ISENABLER_3 - GICD_ICENABLER_1 - GICD_ICENABLER_3 Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ia522ab4bc496d9a47613a49829b65db96e2b1279
2022-03-27feat(nxp-crypto): add chassis 3 supportJiafei Pan
Add Chassis 3 support for CAAM driver. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ied26dd3881489a03017a45966888a61a0813492c
2022-03-27feat(nxp-dcfg): add Chassis 3 supportBiwen Li
Add support for Chassis 3. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I85cf68d4f1db81bf344e34dce13799ae173aa23a
2022-03-22feat(st-pmic): add pmic_voltages_init() functionYann Gautier
This new function pmic_voltages_init() is used to set the minimum value for STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved from device tree. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Ibbe237cb5dccc1fddf92e07ffd3955048ff82075
2022-03-22feat(st-clock): add clock driver for STM32MP13Gabriel Fernandez
Add new clock driver for STM32MP13. Split the include file to manage either STM32MP13 or STM32MP15. Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e985 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2022-02-28Merge "fix(measured-boot): add RMM entry to event_log_metadata" into integrationSandrine Bailleux
2022-02-23fix(measured-boot): add RMM entry to event_log_metadataTamas Ban
Platforms which support Realm world cannot boot up properly if measured boot is enabled at build time. An assertions occurs due to the missing RMM entry in the event_log_metadata array. Signed-off-by: Tamas Ban <tamas.ban@arm.com> Change-Id: I172f10a440797f7c9e1bc79dc72242b40c2521ea
2022-02-18fix(nxp-crypto): refine code to avoid hang issue for some of toolchainJiafei Pan
bitfield structure maybe has strict-aliasing issue for some compiler, for example the old code has hang issue for yocto 3.4 toolchain, so refine the code to avoid to use bitfield structure. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I6b6d7597311240dd6d6b8ca4ce508c69332f9c68
2022-02-04Merge "feat(st): update the security based on new compatible" into integrationMadhukar Pappireddy
2022-02-03feat(gic): allow overriding GICD_PIDR2_GICV2 addressStephan Gerhold
Older Qualcomm SoCs seem to have a custom Qualcomm implementation of the GICv2 specification. It's mostly compliant but unfortunately it looks like a mistake was made with the GICD_PIDR registers. PIDR2 is defined to be at offset 0xFE8, but the Qualcomm implementation has it at 0xFD8. It looks like the entire PIDR0-3/4-7 block is swapped compared to the ARM implementation: PIDR0 starts at 0xFD0 (instead of 0xFE0) and PIDR4 starts at 0xFE0 (instead of 0xFD0). Actually this only breaks a single assert in gicv2_main.c that checks the GIC version: assert((gic_version == ARCH_REV_GICV2) ... In release mode everything seems to work correctly. To keep the code generic, allow affected platforms to override the GICD_PIDR2_GICV2 register address in platform_def.h. Since this header is typically included very early (e.g. from assert.h), add an #ifndef so the definitions from platform_def.h takes priority. Change-Id: I2929a8c1726f8d751bc28796567eb30b81eca2fe Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2022-02-03feat(st): update the security based on new compatibleLionel Debieve
From the new binding, the RCC become secured based on the new compatible. This must be done only from the secure OS initialisation. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I7f0a62f22bfcca638ddaefc9563df00f89f01653
2022-02-01feat(st-gpio): allow to set a gpio in output modeFabien Dessenne
Allow to set a gpio in output mode from the device tree. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Change-Id: Ic483324bc5fe916a60df05f74706bd1da4d08aa5
2022-02-01refactor(st-gpio): code improvementsFabien Dessenne
No functional, change, but some improvements: - Declare set_gpio() as static (only called locally) - Handle the type ('open-drain') property independently from the mode one. - Replace mmio_clrbits_32() + mmio_setbits_32() with mmio_clrsetbits_32(). - Add a missing log - Add missing U() in macro definitions Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Change-Id: I1a79609609ac8e8001127ebefdb81def573f76fa
2022-01-28refactor(st-drivers): improve BSEC driverNicolas Le Bayon
Rename driver file to BSEC2. Split header file in IP and feature parts. Add functions to access BSEC scratch register. Several corrections and improvements. Probe the driver earlier, especially to check debug features. Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-27refactor(st-clock): update STGEN managementLionel Debieve
Rework STGEN config function, and move it to stm32mp_clkfunc.c file. Change-Id: I7784a79c486d1b8811f6f8d123e49ea34899e9b6 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-27refactor(st-clock): use refcnt instead of secure statusYann Gautier
Rework the internal functions __stm32mp1_clk_enable/disable to check for reference count instead of secure status for a clock. Some functions now unused can be removed. Change-Id: Ie4359110d7144229f85c961dcd5a019222c3fd25 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-27feat(fwu): add a function to pass metadata structure to platformsSughosh Ganu
Add a helper function to pass the metadata structure to the platforms. Platforms can then read the metadata structure and pass the boot index value, i.e. the bank(partition) from which the firmware images were booted, to the Update Agent. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Change-Id: I571179b9baa0fbc4d0f08d7a6e3b50c0c7165c5c
2022-01-27feat(partition): add a function to identify a partition by GUIDSughosh Ganu
With the GPT partition scheme, a partition can be identified using it's UniquePartitionGUID, instead of it's name. Add a function to identify the partition based on this GUID value. This functionality is useful in identification of a partition whose UniquePartitionGUID value is known. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Change-Id: I543f794e1f7773f969968a6bce85ecca6f6a1659
2022-01-27feat(partition): make provision to store partition GUID valueSughosh Ganu
The FWU multi bank feature supports multiple partitions or banks of firmware components, where a platform can support having an active and a backup partition(bank) of firmware images to boot from. This feature identifies the images in a given bank using image GUID's -- this GUID value corresponds to the UniquePartitionGUID value used to uniquely identify a GPT partition. To support identification of images, add a member to the partition_entry structure to store the UniquePartitionGUID value of the GPT partition entry. This value is subsequently used to select the firmware image to boot in a multi partition setup. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Change-Id: I2d235467ce7a7f20ebc1cef4db09924a5282e714
2022-01-27feat(partition): cleanup partition and gpt headersSughosh Ganu
The EFI_NAMELEN macro has been moved to efi.h header. Get the macro from efi.h. Use the struct efi_guid structure for declaring GUID members in gpt.h Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Change-Id: I1c3a2605b9f857b9cf2dcfdaed4dc9d0a2cbf0f0
2022-01-27feat(fwu): add basic definitions for GUID handlingSughosh Ganu
The FWU metadata structure uses GUID's to identify the updatable firmware images. Add some basic helper functions and macros that would be used for working with the GUID datatype. With the FWU feature enabled, these would then be used for image identification and booting of images from a particular bank(partition). Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Change-Id: Ia54c0402d72b503d6abd1d94bc751cc14602cd39
2022-01-25Merge changes from topic "decouple-tb-mb" into integrationSandrine Bailleux
* changes: refactor(renesas): disable CRYPTO_SUPPORT option refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot build: introduce CRYPTO_SUPPORT build option
2022-01-20Merge changes from topic "new_ls1043a" into integrationManish Pandey
* changes: docs(maintainers): update nxp layerscape maintainers docs(plat/nxp/layerscape): add ls1043a soc and board support feat(plat/nxp/ls1043ardb): add ls1043ardb board support feat(plat/nxp/ls1043a): add ls1043a soc support refactor(plat/ls1043): remove old implementation for platform ls1043 feat(nxp/driver/dcfg): add some macro definition fix(nxp/common/setup): increase soc name maximum length feat(nxp/common/errata): add SoC erratum a008850 feat(nxp/driver/tzc380): add tzc380 platform driver support feat(tzc380): add sub-region register definition feat(nxp/common/io): add ifc nor and nand as io devices feat(nxp/driver/ifc_nand): add IFC NAND flash driver feat(nxp/driver/ifc_nor): add IFC nor flash driver feat(nxp/driver/csu): add bypass bit mask definition feat(nxp/driver/dcfg): add gic address align register definition feat(nxp/common/rcpm): add RCPM2 registers definition fix(nxp/common/setup): fix total dram size checking feat(nxp/common): add CORTEX A53 helper functions
2022-01-20feat(nxp/driver/dcfg): add some macro definitionJiafei Pan
Added offset for register DEVDISR2 and DEVDISR3, added bit definiton for PORSR1_RCW, and some macro for SVR. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ie49392b89280c6c2c3510fcb4c85d827a1efdac0
2022-01-20feat(nxp/driver/tzc380): add tzc380 platform driver supportJiafei Pan
Added TZC380 platform driver support. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Id0aa6cb64fa7af79dd44e0dbb0e62cb2fd4cb824
2022-01-20feat(tzc380): add sub-region register definitionJiafei Pan
Added sub-region register definition. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Iab8130b56089d804c51ab967b184ddfc192e2858
2022-01-20feat(nxp/driver/ifc_nand): add IFC NAND flash driverJiafei Pan
Support IFC NAND flash as boot device. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I1aba7035ff70b179915e181c04e7b00be2066abe
2022-01-20feat(nxp/driver/ifc_nor): add IFC nor flash driverJiafei Pan
Add IFC Nor flash driver. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I3275664b8848d0fe3c15ed92d95fb19adbf57f84
2022-01-19feat(nxp/driver/csu): add bypass bit mask definitionJiafei Pan
Add TZASC_BYPASS_MUX_DISABLE definition. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ife4d819e2af6deb5e027491d30f6b7c5f79764e7
2022-01-19feat(nxp/driver/dcfg): add gic address align register definitionJiafei Pan
Add some register fields definition. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I9fd78c318b34a2becd82d502fa6d18c8298eb40a
2022-01-18refactor(st-clock): directly use oscillator nameGabriel Fernandez
Instead of transmitting an 'enum stm32mp_osc_id', just send directly the clock name with a 'const char *' Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7b1d35fc932 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2022-01-11refactor(measured-boot): avoid Measured-Boot dependency on Trusted-BootManish V Badarkhe
Measured-Boot and Trusted-Boot are orthogonal to each other and hence removed dependency of Trusted-Boot on Measured-Boot by making below changes - 1. BL1 and BL2 main functions are used for initializing Crypto module instead of the authentication module 2. Updated Crypto module registration macro for MEASURED_BOOT with only necessary callbacks for calculating image hashes 3. The 'load_auth_image' function is now used for the image measurement during Trusted or Non-Trusted Boot flow Change-Id: I3570e80bae8ce8f5b58d84bd955aa43e925d9fff Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-01-05refactor(st-ddr): move basic tests in a dedicated fileNicolas Le Bayon
These basic tests are generic and should be used independently of the driver, depending on the plaftorm characteristics. Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
2022-01-05refactor(st-ddr): reorganize generic and specific elementsNicolas Le Bayon
stm32mp_ddrctl structure contains DDRCTRL registers definitions. stm32mp_ddr_info contains general DDR information extracted from DT. stm32mp_ddr_size moves to the generic side. stm32mp1_ddr_priv contains platform private data. stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to retrieve data from DT. They are located in new generic c/h files in which stm32mp_ddr_param structure is declared. Platform makefile is updated. Adapt driver with this new classification. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I4187376c9fff1a30e7a94407d188391547107997
2022-01-05feat(stm32mp1): allow configuration of DDR AXI ports numberYann Gautier
A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default. It will allow choosing single or dual AXI ports for DDR. Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-01-05feat(st-ddr): add read valid training supportNicolas Le Bayon
Add the read data eye training = training for optimal read valid placement (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
2022-01-05refactor(stm32mp1): remove the support of calibration resultPatrick Delaunay
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by CubeMX. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional "st,phy-cal" After this patch the built-in calibration is always executed. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
2022-01-04refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplicationJona Stubbe
Refactor the GPIO code to use a small lookup table instead of redundant or repetitive code. Signed-off-by: Jona Stubbe <tf-a@jona-stubbe.de> Change-Id: Icf60385095efc1f506e4215d497b60f90e16edfd Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2022-01-01Merge "feat(allwinner): allow to skip PMIC regulator setup" into integrationAndré Przywara
2021-12-27feat(allwinner): allow to skip PMIC regulator setupAndre Przywara
For somewhat historical reasons we are doing some initial PMIC regulator setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked fine so far, but there is at least one board (OrangePi 3) that gets upset, because the Ethernet PHY needs some *coordinated* bringup of *two* regulators. To avoid custom hacks, let's introduce a build option to keep doing the regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break support for some devices on some boards in U-Boot (Ethernet and HDMI), but will allow to bring up the OrangePi 3 in Linux correctly. We keep the default at 1 to not change the behaviour for all other boards. After U-Boot gained proper PMIC support at some point in the future, we will probably change the default to 0, to get rid of the less optimal PMIC code in TF-A. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7
2021-12-24Merge changes from topic "st_regulator" into integrationMadhukar Pappireddy
* changes: feat(st-sdmmc2): manage cards power cycle feat(stm32mp1): register fixed regulator feat(st-drivers): introduce fixed regulator driver refactor(st): update CPU and VDD voltage get refactor(stm32mp1-fdts): update regulator description refactor(st-pmic): use regulator framework for DDR init feat(st-pmic): register the PMIC to regulator framework refactor(st-pmic): split initialize_pmic() feat(stm32mp1): add regulator framework compilation feat(regulator): add a regulator framework feat(stpmic1): add new services feat(stpmic1): add USB OTG regulators refactor(st-pmic): improve driver usage refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean refactor(stm32mp1): re-order drivers init
2021-12-22feat(st-sdmmc2): manage cards power cycleYann Gautier
To correctly initialize the MMC devices, a power cycle is required. For this we need to: - disable vmmc-supply regulator - make the power cycle required for SDMMC2 peripheral - enable regulators Change-Id: I2be6d9082d1cc4c864a82cf2c31ff8522e2d31a2 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-22feat(st-drivers): introduce fixed regulator driverPascal Paillet
Fixed regulator is mainly used when no pmic is available Change-Id: Ib6a998684bcb055ba95a093bee563372d9051474 Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22feat(st-pmic): register the PMIC to regulator frameworkYann Gautier
Register the PMIC to the regulator framework. Change-Id: Ic825a8ef08505316db3dbd5944d62ea907f73c4a Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22refactor(st-pmic): split initialize_pmic()Nicolas Le Bayon
print_pmic_info_and_debug() prints the PMIC version ID and displays regulator information if debug is enabled. It is under DEBUG flag and called after initialize_pmic() in BL2. Change-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2021-12-22feat(regulator): add a regulator frameworkPascal Paillet
Add a regulator framework to: - provide an interface to consumers and drivers, - connect consumers with drivers, - handle most of devicetree-parsing, - handle always-on and boot-on regulators, - handle min/max voltages, Change-Id: I23c939fdef2c71a416c44c9de332f70db0d2aa53 Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22feat(stpmic1): add new servicesPascal Paillet
Add support for ICC, sink mode, bypass mode, active discharge and list voltages. Handle LDO3 sink source mode in a different way to avoid setting voltage while in sink source mode. Change-Id: Ib1b909fd8a153f542917f650e43e24317a570534 Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22feat(stpmic1): add USB OTG regulatorsEtienne Carriere
Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are needed since manipulated during the suspend/resume power sequence as per FDT description for stm32mp15x-xxx boards from STMicroelectronics. Change-Id: I6217de707e49882bd5a9100db43e0d354908800d Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2021-12-22refactor(stpmic1): set stpmic1_is_regulator_enabled() as booleanNicolas Le Bayon
Improve use and readability. Change-Id: Ia99fc38287f36c9dd12bfe51352afa5da68c0e47 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>