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2020-07-31tbbr/dualroot: rename SP package certificate fileManish Pandey
Currently only single signing domain is supported for SP packages but there is plan to support dual signing domains if CoT is dualroot. SP_CONTENT_CERT_ID is the certificate file which is currently generated and signed with trusted world key which in-turn is derived from Silicon provider RoT key. To allow dual signing domain for SP packages, other certificate file will be derived from Platform owned RoT key. This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and does other related changes. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
2020-07-30fdts: n1sdp: DTS file for single-chip and multi-chip environment.Andre Przywara
N1SDP supports both single-chip and multi-chip environment. Added DTS file for both type of environment. Enabled DTS files compilation for N1SDP platform. Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0 Co-authored-by: Robin Murphy <Robin.Murphy@arm.com> Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com> Co-authored-by: Anurag Koul <anurag.koul@arm.com> Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
2020-07-10dts: Add CoT descriptor nodes and properties in device treeManish V Badarkhe
Added CoT descriptor nodes and properties in device tree. Currently, CoT descriptors which are used by BL2 are added as part of device tree. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0
2020-07-06corstone700: splitting the platform support into FVP and FPGAAbdellatif El Khlifi
This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-06-09plat/fvp: Add support for dynamic description of secure interruptsMadhukar Pappireddy
Using the fconf framework, the Group 0 and Group 1 secure interrupt descriptors are moved to device tree and retrieved in runtime. This feature is enabled by the build flag SEC_INT_DESC_IN_FCONF. Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-06-03dts: stm32mp157c: fix etzpc node location in DTSI fileEtienne Carriere
Fix etzpc node location in stm32mp157c DTSI file as requested during the patch review. The comment was addressed then fixup change discarded while rebasing. Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d Fixes: 627298d4b655 ("dts: stm32mp157c: add etzpc node") Reported-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2020-06-03dts: stm32mp157c: add etzpc nodeEtienne Carriere
Add a node for the ETZPC device so that driver initializes during stm32mp15* boot sequence. Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2020-05-27plat/arm: Introduce TC0 platformUsama Arif
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
2020-05-19FVP: Add support for passing platform's topology to DTSAlexei Fedorov
This patch adds support for passing FVP platform's topology configuration to DTS files for compilation, which allows to build DTBs with correct number of clusters and CPUs. This removes non-existing clusters/CPUs from the compiled device tree blob and fixes reported Linux errors when trying to power on absent CPUs/PEs. If DTS file is passed using FVP_HW_CONFIG_DTS build option from the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will use the default values from the corresponding DTS file. Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-05-15plat/arm/fvp: Support performing SDEI platform setup in runtimeBalint Dobszay
This patch introduces dynamic configuration for SDEI setup and is supported when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays and processing the configuration at compile time, the config is moved to dts files. It will be retrieved at runtime during SDEI init, using the fconf layer. Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-04-17fdts: a5ds: Fix for the system timer issue.lakshmi Kailasanathan
A5DS FPGA system timer clock frequency is 7.5Mhz. The dt is file updated inline with the hardware clock frequency. Change-Id: I3f6c2e0d4a7b293175a42cf398a8730448504af9 Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>
2020-03-24corstone700: updating the kernel arguments to support initramfsAbdellatif El Khlifi
In the context of enabling initramfs this change makes the kernel arguments compatible with the initramfs requirements Change-Id: Ifa955a5790ae1398fd8ad9ca1c8272f019c121a6 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-03-11fconf: Extract topology node properties from HW_CONFIG dtbMadhukar Pappireddy
Create, register( and implicitly invoke) fconf_populate_topology() function which extracts the topology related properties from dtb into the newly created fconf based configuration structure 'soc_topology'. Appropriate libfdt APIs are added to jmptbl.i file for use with USE_ROMLIB build feature. A new property which describes the power domain levels is added to the HW_CONFIG device tree source files. This patch also fixes a minor bug in the common device tree file fvp-base-gicv3-psci-dynamiq-common.dtsi As this file includes fvp-base-gicv3-psci-common.dtsi, it is necessary to delete all previous cluster node definitons because DynamIQ based models have upto 8 CPUs in each cluster. If not deleted, the final dts would have an inaccurate description of SoC topology, i.e., cluster0 with 8 or more core nodes and cluster1 with 4 core nodes. Change-Id: I9eb406da3ba4732008a66c01afec7c9fa8ef59bf Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-03-04fdts: a5ds: add ethernet node in devicetreeVishnu Banavath
This change is to add ethernet and voltage regulator nodes into a5ds devicetree. Change-Id: If9ed67040d54e76af1813c9f99835f51f617e9df Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
2020-02-26Modify multithreaded dts file of DynamIQ FVPsImre Kis
The dts file now contains a CPU map that precisely describes the topology including thread nodes. The map was also extended to have 16 PEs to be able to test multithreaded FVPs with 8 cores in the same cluster. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: If39559b05d20bfd68d0ecf830ddcbc5233b288a0
2020-02-18corstone700: fdts: using DDR memory and XIP rootfsRui Silva
This patch allows to use DDR address in memory node because on FPGA we typically use DDR instead of shared RAM. This patch also modifies the kernel arguments to allow the rootfs to be mounted from a direct mapping of the QSPI NOR flash using the physmap driver in the kernel. This allows to support CRAMFS XIP. Change-Id: I4e2bc6a1f48449c7f60e00f5f1a698df8cb2ba89 Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-02-17corstone700: set UART clocks to 32MHzVishnu Banavath
Adding support for 32MHz UART clock and selecting it as the default UART clock Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2020-02-13Fix topology description of cpus for DynamIQ based FVPMadhukar Pappireddy
DynamIQ based designs have upto 8 CPUs in each cluster. This patch fixes the device tree node which describes the topology of the CPU for DynamIQ FVP Model. Change-Id: I7146bc79029ce38314026d4853e5b6406863725c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-21Merge "Replace dts includes with C preprocessor syntax" into integrationManish Pandey
2020-01-20fdts: stm32mp1: remove second QSPI flash instanceLionel Debieve
Remove second flash node as only one must be used by QSPI NOR driver. Change-Id: I48189f2fdf4e0455aabe7d4cd9b2f3d36bb9cfb5 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2020-01-20fdts: stm32mp1: update for FMC2 pin muxingLionel Debieve
Include the required FMC2 pinmux definition for the NAND management. Change-Id: I80333deacdf3444b2f21f17f2fb5919e569a3591 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2020-01-14Replace dts includes with C preprocessor syntaxBalint Dobszay
Using the /include/ syntax, the include was evaluated by dtc, only after running the preprocessor, therefore the .dtsi files were not preprocessed. This patch adds the #include syntax instead. Evaluating this and preprocessing the files now happens in a single step, done by the C preprocessor. Change-Id: I6d0104b6274316fc736e84973502a4d6c2c9d6e0 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2020-01-07A5DS: Correct system freq, Cache Writeback GranuleAvinash Mehta
Correct the system, timer and uart frequencies to successfully run the stack on FPGA Correct Cortex-A5MPcore to 8 word granularity for Cache writeback Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
2019-12-18fdts: a5ds: cleanup enable-method in devicetreeVishnu Banavath
Same enable method is used by all the four cores. So, make it globally for all the cores instead of adding it to individual level. Change-Id: I9b5728b0e0545c9e27160ea586009d929eb78cad Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
2019-12-18fdts: a5ds: add L2 cache node in devicetreeVishnu Banavath
This change is to add L2 cache node into a5ds device tree. Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947 Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
2019-11-13Add multithreaded DynamIQ dts fileImre Kis
The new dts file overrides the MPIDR values of the processing elements which were defined in the common dtsi file. The new dts file defines four cores in a single cluster, each core having two threads. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: I0f8d8d250289077aee11eede4508871bb61dbc88
2019-10-03fdts: stm32mp1: move FDCAN to PLL4_RAntonio Borneo
LTDC modifies the clock frequency to adapt it to the display. Such frequency change is not detected by the FDCAN driver that instead caches the value at probe and pretends to use it later. This change fixes the issue by moving the FDCAN to PLL4_R, leaving the LTDC alone on PLL4_Q. Signed-off-by: Antonio Borneo <antonio.borneo@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58
2019-09-27Merge changes from topic "ld/stm32-authentication" into integrationSoby Mathew
* changes: stm32mp1: add authentication support for stm32image bsec: move bsec_mode_is_closed_device() service to platform crypto: stm32_hash: Add HASH driver
2019-09-23a5ds: add multicore supportUsama Arif
Enable cores 1-3 using psci. On receiving the smc call from kernel, core 0 will bring the secondary cores out pen and signal an event for the cores. Currently on switching the cores is enabled i.e. it is not possible to suspend, switch cores off, etc. Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f Signed-off-by: Usama Arif <usama.arif@arm.com>
2019-09-23stm32mp1: add authentication support for stm32imageLionel Debieve
This commit adds authentication binary support for STM32MP1. It prints the bootrom authentication result if signed image is used and authenticates the next loaded STM32 images. It also enables the dynamic translation table support (PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
2019-09-08Add Linux DTS files for 32 bit threaded FVPsImre Kis
RevC models have the MT bit set and the affinities shifted in the MPIDR register. To make the Linux able to boot all CPUs it needs a modified DTS file containing the shifted affinity values. Beside these values the DTS files should be the same so the common part was moved into a new file which is included in the DTS files with shifted and non-shifted affinities. The same setup already exists for 64 bit systems. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: I90f7b9c8d8a24c9b3f97232441dbe0a29aa8976d
2019-08-20plat/arm: Introduce corstone700 platform.Manish Pandey
This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2019-07-16plat/arm: Introduce A5 DesignStart platform.Usama Arif
This patch adds support for Cortex-A5 FVP for the DesignStart program. DesignStart aims at providing low cost and fast access to Arm IP. Currently with this patch only the primary CPU is booted and the rest of them wait for an interrupt. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
2019-06-17fdts: stm32mp1: realign device tree files with internal devsYann Gautier
Update DDR parameters to version 1.45. Remove useless sdmmc1_dir_pins_b node. Add USART3 and UART7 nodes. Correct a PMIC value for USB regulator. Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes. Update DTSI file for SDMMC compatible, but overwrite it with the former name. Move BSEC board_id node to boards DTS files, as this OTP is specific to STMicroelectronics boards. Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-06-17stm32mp1: add general SYSCFG managementYann Gautier
The system configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. The SYSCFG driver is in charge of configuring masters on the interconnect, IO compensation, low voltage boards, or pull-ups for boot pins. All other configurations should be handled in Linux drivers requiring it. Device tree files are also updated to manage vdd-supply regulator. Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-04-26fdts: Fix DTC warnings for STM32MP1 platformManivannan Sadhasivam
DTC issues below warnings for STM32MP1 platform for using upper case in unit address: fdts/stm32mp15-ddr.dtsi:8.20-151.5: Warning (simple_bus_reg): /soc/ddr@5A003000: simple-bus unit address format error, expected "5a003000" fdts/stm32mp157c-security.dtsi:9.25-13.5: Warning (simple_bus_reg): /soc/stgen@5C008000: simple-bus unit address format error, expected "5c008000" Fix this by using the lower case unit address for concerned nodes. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Change-Id: Id3d19ac3b47ec6bcea2bd3382225e2e923dc4a70
2019-04-26stm32mp1: Add Avenger96 board supportManivannan Sadhasivam
Add board support for Avenger96 board from Arrow Electronics. This board is based on STM32MP157A SoC and is one of the 96Boards Consumer Edition platform. More information about this board can be found in 96Boards website: https://www.96boards.org/product/avenger96/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Change-Id: Ic905f26c38d03883c6e4ea221b4b275a4b534857
2019-03-11fdts: stm32mp1: add bsec nodeYann Gautier
This node is added in a new file stm32mp157c-security.dtsi. This node includes OTPs that should be shadowed and made readable to non secure world. Explicitly add status and secure-status, as these OTPs are accessible by secure and non-secure world. The stgen node is also moved to this file. Change-Id: I3c89a01588d2e411fecfc44997e1c5df2fc37cad Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-02-22Merge pull request #1836 from Yann-lms/docs_and_m4Antonio Niño Díaz
Update documentation for STM32MP1 and add Cortex-M4 support
2019-02-20stm32mp1: add minimal support for co-processor Cortex-M4Yann Gautier
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-02-19plat/arm: Support for Cortex A5 in FVP Versatile Express platformUsama Arif
Cortex A5 doesnt support VFP, Large Page addressing and generic timer which are addressed in this patch. The device tree for Cortex a5 is also included. Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678 Signed-off-by: Usama Arif <usama.arif@arm.com>
2019-02-19plat/arm: Introduce FVP Versatile Express platform.Usama Arif
This patch adds support for Versatile express FVP (Fast models). Versatile express is a family of platforms that are based on ARM v7. Currently this port has only been tested on Cortex A7, although it should work with other ARM V7 cores that support LPAE, generic timers, VFP and hardware divide. Future patches will support other cores like Cortex A5 that dont support features like LPAE and hardware divide. This platform is tested on and only expected to work on single core models. Change-Id: I10893af65b8bb64da7b3bd851cab8231718e61dd Signed-off-by: Usama Arif <usama.arif@arm.com>
2019-02-14stm32mp1: introduce STM32MP1 discovery boardsYann Gautier
Add the device tree files to support the 2 discovery boards: DK1 & DK2. Change-Id: I90b4797dc69bd0aab1b643a72c932ead48a03c1f Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-02-14stm32mp1: update I2C and PMIC driversYann Gautier
Regulator configuration at boot takes more information from DT. I2C configuration from DT is done in I2C driver. I2C driver manages more transfer modes. The min voltage of buck1 should also be increased to 1.2V, else the platform does not boot. Heavily modifies stm32_i2c.c since many functions move inside the source file to remove redundant declarations. Change-Id: I0bee5d776cf3ff15e687427cd6abc06ab237d025 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
2019-01-18stm32mp1: update device tree filesYann Gautier
The drivers are also updated to reflect the changes. Set RCC as non-secure. Change-Id: I568fa1f418355830ad1d4d1cdcdb910fb362231b Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-01-18stm32mp1: rename stpmu1 to stpmic1Yann Gautier
This is the correct name of the IP. Rename stm32mp1_pmic files to stm32mp_pmic. Change-Id: I238a7d1f9a1d099daf7788dc9ebbd3146ba2f15f Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-07-24stm32mp1: Add device tree filesYann Gautier
Those device tree files are taken from STM32MP1 U-Boot and Linux. And they are updated to fit TF-A needs. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-05-21Dynamic_config: remove the FVP dtb filesSoby Mathew
Since FVP enables dynamic configuration by default, the DT blobs are compiled from source and included in FIP during build. Hence this patch removes the dtb files from the `fdts` folder. Change-Id: Ic155ecd257384a33eb2aa38c9b4430e47b09cd31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-04-24Remove dtc warningsRoberto Vargas
DTC generates warnings when unit names begin with 0, or when a node containing a reg or range property doesn't have a unit name in the node name. This patch fixes those cases. Change-Id: If24ec68ef3034fb3fcefb96c5625c47a0bbd8474 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-28fdts: Add DTS for DynamIQ platformsJeenu Viswambharan
DynamIQ platforms host all CPUs in a single cluster. This patch adds a DTS and DTB for DynamicQ platforms hosting up to 8 CPUs. Change-Id: I2d97bc740ac3062818767e7251020644f5bb9100 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>