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6 daysMerge "fix(gicv3): add dsb in both disable and enable function of ↵Manish Pandey
gicv3_cpuif" into integration
11 daysfix(gicv3): add dsb in both disable and enable function of gicv3_cpuifMing Huang
A RAS error may be triggered while offline core in OS. Error: Uncorrected software error in the Distributor, with IERR=9,SERR=f. Core put to sleep before its Group enables were cleared. gicv3_cpuif_disable() will be called in offline core flow. According to GIC architecture version 3 and version 4: Architectural execution of a DSB instruction guarantees that the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1, ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed by the associated Redistributor. An ISB or other context synchronization operation must precede the DSB to ensure visibility of System register writes. Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d
12 daysfix(drivers/scmi-msg): entry: add weak functionsPeng Fan
One platform may not implement all the protocols, to avoid build break when we not include all the protocols, add weak functions. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I1485baa2e8f381cb0eede1a7b93ed10e49934971
12 daysfeat(drivers/scmi-msg): add power domain protocolPeng Fan
Add SCMI power domain protocol, with POWER_STATE_NOTIFY and POWER_STATE_CHANGE_REQUESTED_NOTIFY not implemented. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ia7c4db57c4c702667f8eaa630c924016e4a8bde0
2021-07-15fix(drivers/scmi-msg): smt: fix build for aarch64Peng Fan
For AARCH64, BIT() will make the number as ULL type, let use BIT_32() here. And use %zu for size_t print format. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I1dc18d374cd2c6eb83b40b66ed6189dcc6a21728
2021-07-05refactor(measured boot): revisit error handling (3/3)Sandrine Bailleux
- In tpm_record_measurement(): The platform layer is responsible for providing an exhaustive list of images to measure. If it doesn't then this should be treated as a programming error, as documented in [1]. Thus, turn the error test into an assertion. [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#using-assert-to-check-for-programming-errors Change-Id: I002309c2ebdf2d348a7d12a8f7f9e82465046b8e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-05refactor(measured boot): revisit error handling (2/3)Sandrine Bailleux
- In add_event2(): Turn the first error condition checking whether there is room for an extra event2 data structure into an assertion. The platform layer is responsible for choosing an appropriate event log buffer size based on the number of measurements it expects. If this assertion fires, the platform macro EVENT_LOG_SIZE should be adjusted and the firmware recompiled. Call this assumption out in the function documentation. Also remove the second error condition check, which is a subset of the first one and thus is redundant. As a result of these changes, add_event2() can no longer fail. Thus, change its return type from int to void. Also, the 'size_of_event' local variable is now unused in release builds so remove it and move its value into the assertion. Change-Id: I113fc141de59708b20435a0c7126255561ab7786 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-05refactor(measured boot): revisit error handling (1/3)Sandrine Bailleux
- In event_log_init(): Throughout the function, we are incrementing a pointer by some fixed amounts of bytes (corresponding to the size of some data structure or to some constant number of bytes), there is no variable-size increments in the picture. Thus it seems pointless to verify that the pointer has indeed been incremented by this fixed amount of bytes afterwards. For this reason, remove these checks altogether. As a result, the start_ptr local variable is now unused so remove it as well. Change-Id: I612e2278cd3a63d1417427e45d81e285503f5efe Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-05style(measured boot): fix incorrect indentationSandrine Bailleux
Change-Id: I5b84a28ed254a7c7bb95c18fa999592a4e3f6d90 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-01Merge changes from topic "st_fixes" into integrationMark Dykes
* changes: fix(plat/st): correct IO compensation disabling fix(plat/st): correct BSEC error code management fix(drivers/st/pmic): missing error check fix(drivers/st/pmic): initialize i2c_state fix(drivers/st/clk): use correct return value
2021-07-01Merge "fix(drivers/mtd): macronix quad enable bit issue" into integrationMark Dykes
2021-07-01refactor(measured boot): remove weak definition of plat_get_measured_boot_data()Sandrine Bailleux
Weak definitions are confusing and should be avoided if possible. Thus, turn plat_get_measured_boot_data() into a strong definition that platforms must provide (if they need measured boot). We could have moved the old weak implementation under plat/common as a sane, default implementation that platforms may pull in if it suits them. However, this implementation right now simply measures BL2, which is not enough to get a complete measured boot flow, so this patch just removes it. This change only affects the Arm FVP platform, as no other upstream platform implements measured boot at the moment. Change-Id: If8680a39ae0ef1044ee981315439d5e0c8461229 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-06-28Merge "fix(drivers/mtd): fix MISRA issues and logic improvement" into ↵Mark Dykes
integration
2021-06-28Merge "style(scmi_common): add \n to warning messages" into integrationMark Dykes
2021-06-22fix(drivers/mtd): macronix quad enable bit issueLionel Debieve
Invert test logic on the status register control to fix issue when the bit SR_QUAD_EN_MX is not set. Change-Id: I8b2f140219f124336bf96462abf9d9445d0308bc Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22fix(drivers/mtd): fix MISRA issues and logic improvementLionel Debieve
Fix MISRA issues and invert the spi_nor_ready status to improve readability. Remove an unneeded variable initialization. Change-Id: I25a97fbd6c4389156b4f077b986019fa7c30a457 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22fix(drivers/st/pmic): missing error checkNicolas Le Bayon
In pmic_operate(), "regulators" node value must be checked before entering in the fdt_for_each_subnode loop. Change-Id: I1460cd24ec56ec47ab644f396b71b92973e75fb4 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22fix(drivers/st/pmic): initialize i2c_stateBenjamin Gaignard
Make sure that i2c->i2c_state is correctly initialized with I2C_STATE_RESET value this avoid hi2c->lock to not be set to 0 when calling stm32_i2c_init during platform suspend/resume operations. Change-Id: I3b4c1f9115589325eb256789a1764c322741db7d Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22fix(drivers/st/clk): use correct return valueYann Gautier
The function stm32mp1_clk_init() returns an int. Return a negative error value if the device tree is not found. Change-Id: I422d5fea46c4d63d55a5b62e1db154c1f53f41b7 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-18Merge changes from topic "io_stm32image" into integrationMadhukar Pappireddy
* changes: fix(io_stm32image): invalidate cache on local buf refactor(io_stm32image): add header size variable fix(io_stm32image): uninitialized variable warning
2021-06-16refactor(gicv3): use helper functions to get SPI/ESPI INTID limitHeyi Guo
Use helper functions to get SPI and ESPI INTID limit, to remove several pieces of similar code in gicv3 driver. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: Iaf441fe5e333c4260e7f6d98df6fdd931591976d
2021-06-16refactor(gicv3): add helper function to get the limit of ESPI INTIDHeyi Guo
Add helper function gicv3_get_espi_limit() to get the value of (maximum extended SPI INTID + 1), so that some duplicated code can be removed later. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I0355ca2647f872e8189add259f6c47d415494cce
2021-06-08style(scmi_common): add \n to warning messagesHeyi Guo
Add newline(\n) to make the message clearer when the warnings are really triggered. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I5e2574a52c9065db32ecb4d453b9b02445f69a82
2021-06-08refactor(gicv3): add helper function to get the limit of SPI INTIDHeyi Guo
Add helper function gicv3_get_spi_limit() to get the value of (maximum SPI INTID + 1), so that some duplicated code can be removed later. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I160c8a88fbb71d22790b8999a84afbfba766f5e7
2021-06-07Merge changes I85a87dc9,If75df769,I55b0c910 into integrationMadhukar Pappireddy
* changes: feat(plat/st): add STM32MP_EMMC_BOOT option feat(drivers/st): manage boot part in io_mmc feat(drivers/mmc): boot partition read support
2021-06-07Merge "fix(plat/marvell/armada): select correct pcie reference clock source" ↵Manish Pandey
into integration
2021-06-04fix(io_stm32image): invalidate cache on local bufYann Gautier
When retrieving data from stm32 image file, the header is removed with a memcpy that shifts the data to overwrite the useless header for next binary. STM32 binary from boot device: |-------------------------------------| | header | payload | |-------------------------------------| After the memcpy: |-------------------------------------| | payload | remain | |-------------------------------------| But the remaining data after the shifted payload is still in the cache. As it is of no use for anyone, just invalidate the cache at this address. This is required if the DDR is mapped secure in BL2, and the secure access is forbidden in BL33, or else TZC-400 issues an error. Change-Id: Ice2af3b1ca49eccb79bfc62db60437e259d344ca Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-04refactor(io_stm32image): add header size variableYann Gautier
A variable hdr_sz is created in stm32image_partition_read() function. It just represents the size of the stm32 image header but it really improves the readability of the function. Change-Id: I95ec62a78a4b6c6a75b0d8c8aa0faef8bee424da Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-04fix(io_stm32image): uninitialized variable warningNicolas Le Bayon
Fixes implementation against build warning reported by GCC: drivers/st/io/io_stm32image.c: In function ‘stm32image_partition_read’: drivers/st/io/io_stm32image.c:249:6: error: ‘result’ may be used uninitialized in this function [-Werror=maybe-uninitialized] int result; ^~~~~~ Actually, by construction the current implementation of function stm32image_partition_read() does not mandate result to be initialized since it always reaches the exit point with a valid value in 'result'. Yet, this change prevents compiler from complaining and is more robust against future changes in the implementation. Change-Id: I383575edb605b7535398952a5fdfc266c0068c71 Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-04feat(drivers/st): manage boot part in io_mmcVyacheslav Yurkov
Use dedicated read function for boot partition Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com> Change-Id: If75df7691fce0797205365736fc6e4e3429efdca
2021-06-04feat(drivers/mmc): boot partition read supportVyacheslav Yurkov
Added a public function to read blocks from a current boot partition. switch between partitions has to respect eMMC partition switch timing. Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com> Change-Id: I55b0c910314253e5647486609583fd290dadd30a
2021-06-02fix(plat/marvell/a3720/uart): fix UART parent clock rate determinationPali Rohár
The UART code for the A3K platform assumes that UART parent clock rate is always 25 MHz. This is incorrect, because the xtal clock can also run at 40 MHz (this is board specific). The frequency of the xtal clock is determined by a value on a strapping pin during SOC reset. The code to determine this frequency is already in A3K's comphy driver. Move the get_ref_clk() function from the comphy driver to a separate file and use it for UART parent clock rate determination. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
2021-06-01fix(plat/marvell/armada): select correct pcie reference clock sourceGuo Yi
when comphy is in pcie mode, correct reference clock need be selected according to SAR register that reflect the CPx_MPP boot strapping pins. Either from external or from internal Signed-off-by: Guo Yi <yguo@cavium.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Change-Id: I99ed64a141e85174cc0f8e9dab5886ab2506efa1
2021-06-01fix(plat/marvell/a3720/uart): fix configuring UART clockPali Rohár
When configuring the UART_BAUD_REG register, the function console_a3700_core_init() currently only changes the baud divisor field, leaving other fields to their previous value. This is incorrect, because the baud divisor is computed with the assumption that the parent clock rate is 25 MHz, and since the other fields in this register configure the parent clock, which could have been changed by U-Boot or Linux. Fix this function to also configure the other fields so that the UART parent clock is selected to be the xtal clock. For example without this change TF-A prints only ERROR: a3700_system_off needs to be implemented followed by garbage after plat_crash_console_init() is called. After applying this change instead of garbage it also print crash info: PANIC at PC : 0x0000000004023800 Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81
2021-05-28fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculationPali Rohár
UART parent clock is by default the platform's xtal clock, which is 25 MHz. The value defined in the driver, though, is 25.8048 MHz. This is a hack for the suboptimal divisor calculation Divisor = UART clock / (16 * baudrate) which does not use rounding division, resulting in a suboptimal value for divisor if the correct parent clock rate was used. Change the code for divisor calculation to Divisor = Round(UART clock / (16 * baudrate)) and change the parent clock rate value to 25 MHz. The final UART divisor for default baudrate 115200 is not affected by this change. (Note that the parent clock rate should not be defined via a macro, since the xtal clock can also be 40 MHz. This is outside of the scope of this fix, though.) Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
2021-04-27fix(driver/auth): avoid NV counter upgrade without certificate validationManish V Badarkhe
Platform NV counter get updated (if cert NV counter > plat NV counter) before authenticating the certificate if the platform specifies NV counter method before signature authentication in its CoT, and this provides an opportunity for a tempered certificate to upgrade the platform NV counter. This is theoretical issue, as in practice none of the standard CoT (TBBR, dualroot) or upstream platforms ones (NXP) exercised this issue. To fix this issue, modified the auth_nvctr method to do only NV counter check, and flags if the NV counter upgrade is needed or not. Then ensured that the platform NV counter gets upgraded with the NV counter value from the certificate only after that certificate gets authenticated. This change is verified manually by modifying the CoT that specifies certificate with: 1. NV counter authentication before signature authentication method 2. NV counter authentication method only Change-Id: I1ad17f1a911fb1035a1a60976cc26b2965b05166 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-04-21Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into ↵Manish Pandey
integration * changes: renesas: rzg: Add support to identify EK874 RZ/G2E board drivers: renesas: common: watchdog: Add support for RZ/G2E drivers: renesas: rzg: Add QoS support for RZ/G2E drivers: renesas: rzg: Add PFC support for RZ/G2E drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC drivers: renesas: rzg: Add QoS support for RZ/G2N drivers: renesas: rzg: Add PFC support for RZ/G2N drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC drivers: renesas: rzg: Add QoS support for RZ/G2H drivers: renesas: rzg: Add PFC support for RZ/G2H drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC drivers: renesas: rzg: Switch using common ddr code drivers: renesas: ddr: Move to common
2021-04-20renesas: rzg: Add support to identify EK874 RZ/G2E boardLad Prabhakar
Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
2021-04-20drivers: renesas: common: watchdog: Add support for RZ/G2ELad Prabhakar
Add watchdog support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ia813e051f6605028d0bb83967893ebd107fc8551
2021-04-20drivers: renesas: rzg: Add QoS support for RZ/G2ELad Prabhakar
Add QoS support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I2c4373807ab8c550d86d6abc97f5b01f2fb78fb3
2021-04-20drivers: renesas: rzg: Add PFC support for RZ/G2ELad Prabhakar
Add pin control support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I736724cc0dd32f2169018ed7f2f48319b039b61f
2021-04-20drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoCLad Prabhakar
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the same. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df
2021-04-20renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N boardLad Prabhakar
Add support to identify HopeRun HiHope RZ/G2N board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce
2021-04-20drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoCLad Prabhakar
Select MMC_CH1 for eMMC on RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee
2021-04-20drivers: renesas: rzg: Add QoS support for RZ/G2NLad Prabhakar
Add QoS support for RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I663b50d9fb41b9b20a6b54795278659b2b184bc4
2021-04-20drivers: renesas: rzg: Add PFC support for RZ/G2NLad Prabhakar
Add pin control support for RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib5eb4f3b1b75e158ec13c4eefdbe9688344206a3
2021-04-20drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoCLad Prabhakar
Add support for initializing DRAM on RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0
2021-04-20renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H boardLad Prabhakar
Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970
2021-04-20drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoCLad Prabhakar
Select MMC_CH1 for eMMC on RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I1bdfa462fd98b144042c014701b342b87e1efc9d
2021-04-20drivers: renesas: rzg: Add QoS support for RZ/G2HLad Prabhakar
Add QoS support for RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: If7d8940148fc31887568fd501c6cab609e715ba4