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2018-10-12pl011: cnds: cbmem: 16550: Fix commentsAntonio Nino Diaz
The comments with the prototypes of the register functions of the console drivers are incorrect. The arguments are wrong. This patch fixes them. Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-04Merge pull request #1583 from danielboulby-arm/db/AArch32_Multi_ConsoleDimitris Papastamos
Enable Multi Console API in AArch32
2018-10-03Mark GICV3, CCI and CCN boot time code as initDaniel Boulby
Mark the GICv3, CCI and CCN code only used in Bl31 initialization with __init to be reclaimed once no longer needed. Change-Id: I3d77f36758450d9d1d87ecc60bc1c63fe4082667 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-09-28console: Remove deprecated filesAntonio Nino Diaz
Change-Id: Ib9eebbdff6f7868e1d1b8c41761cacc7501a25bd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28cci400: Remove deprecated driverAntonio Nino Diaz
This driver is deprecated. Change-Id: Ic6e154a5756e779743b17a329eed4570ccc61389 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28tzc400: Remove deprecated interfacesAntonio Nino Diaz
Change-Id: I9874883ec33dbf293f607f9779d7c56f23cb8023 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28gic: Remove deprecated driver and interfacesAntonio Nino Diaz
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473 Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-21pl011: Add support in AArch32 for MULTI_CONSOLE_APIDaniel Boulby
Allow AArch32 to use the multi console driver by adding the required functions Change-Id: I9e69f18965f320074cf75442d6b0de891aef7936 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-09-04Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09Soby Mathew
Marvell updates 18.09
2018-09-03gicv2: enable configuring IRQ trigger typeMarcin Wojtas
This patch introduces new helper routines that allow configuring the individual IRQs to be edge/level-triggered via GICD_ICFGR registers. This is helpful to modify the default configuration of the non-secure GIC SPI's, which are all set during initialization to be level-sensitive. Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-08-30GIC: Fix build errorAndrew F. Davis
Pointers should be comparied to NULL. Fixes: 3fea9c8b8e8e ("gic: Fix types") Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-08-30Merge pull request #1542 from antonio-nino-diaz-arm/an/bl31-misraDimitris Papastamos
Some MISRA fixes in BL31, cci and smmu
2018-08-30drivers: cci: Fix MISRA defectsAntonio Nino Diaz
Change-Id: Ifdb0ceec19d267b14d796b5d31f08f7342190484 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30drivers: smmu: Fix MISRA defectsAntonio Nino Diaz
Change-Id: I2954a99d5b72069bcb7bac9d6926c6209d6ba881 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30gic v3: Fix width of types of helper functionsAntonio Nino Diaz
Change-Id: I08447b44fffb6e54f9fab957eee369ccbda4247a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30gic: Fix typesAntonio Nino Diaz
Change-Id: I6a2adef87c20f9279446a54b7e69618fba3d2a25 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30gic: Fix definitionsAntonio Nino Diaz
Change-Id: I945029ca26ea2e63f0d92c5f33019b882f23bd72 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30gic v3: Turn macros into static inline functionsAntonio Nino Diaz
Change-Id: Ib587f12f36810fc7d4f4b8f575195554299b8ed4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-13cci: Use dsb to wait before reading status registerRoberto Vargas
The CCI500 TRM explicitily requires completion of the write operation before the read operation, and it is not guaranteed by dmb but it is dsb. Change-Id: Ieeaa0d1a4b8fcb87108dea9b6de03d9c8a150829 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-08-06Merge pull request #1501 from robertovargas-arm/cciDimitris Papastamos
cci: Wait before reading status register
2018-07-30Merge pull request #1498 from glneo/cache-early-fixesDimitris Papastamos
Early cache enable and coherency fixes
2018-07-30Fix MISRA defects in SP805 driverAntonio Nino Diaz
Fix violations of MISRA C-2012 Rules 10.1, 10.3 and 10.4. Change-Id: I13c6acda798c1666892f630f097a23e68748f9e4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-26GIC: Do not flush cache when unneededAndrew F. Davis
When a platform enables its caches before it initializes the GICC/GICR interface then explicit cache maintenance is not needed. Remove these here. Signed-off-by: Andrew F. Davis <afd@ti.com>
2018-07-19cci: Wait before reading status registerRoberto Vargas
The functions cci_enable_snoop_dvm_reqs and cci_disable_snoop_dvm_reqs write in the SNOOP_CTRL_REGISTER of the slave interface and it polls the status register to be sure that the operation is finished before leaving the functions. If the write in SNOOP_CTRL_REGISTER is reordered after the first read in the status register then these functions can finish before enabling/disabling snoops and DVM messages. The CCI500 TRM specifies: Wait for the completion of the write to the Snoop Control Register before testing the change_pending bit. Change-Id: Idc7685963f412be1c16bcd3c6e3cca826e2fdf38 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-06-12Fix MISRA Rule 5.3 Part 2Daniel Boulby
Use a _ prefix for Macro arguments to prevent that argument from hiding variables of the same name in the outer scope Rule 5.3: An identifier declared in an inner scope shall not hide an identifier declared in an outer scope Fixed For: make LOG_LEVEL=50 PLAT=fvp Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12Fix MISRA Rule 5.1Daniel Boulby
Rule 5.1: External identifiers shall be distinct Some of the identifier names in the GICv3 driver were so long that the first 31 characters were identical. This patch shortens these names to make sure they are different. Fixed for: LOG_LEVEL=50 PLAT=fvp Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-05-17Merge pull request #1340 from Andre-ARM/sec-irqs-fixesDimitris Papastamos
Fix support for systems without secure interrupts
2018-04-27Fix pointer type mismatch of handlersMasahiro Yamada
Commit 4c0d03907652 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the type mismatch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-09DMC500: Add platform support to set system interface countAmit Daniel Kachhap
Some low end platforms using DMC500 memory controller do not have CCI(Cache Coherent Interconnect) interface and only have non-coherent system interface support. Hence this patch makes the system interface count configurable from the platforms. Change-Id: I6d54c90eb72fd18026c6470c1f7fd26c59dc4b9a Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
2018-04-03gicv3: Fix support for systems without secure interruptsAndre Przywara
Accessing the interrupt_props array only happens inside a loop over interrupt_props_num, so the GICv3 driver can cope with no secure interrupts. This allows us to relax the asserts that insists on a non-NULL interrupt_props pointer and at least one secure interrupt. This enables GICv3 platforms which have no need for a secure interrupt. This only covers the non-deprecated code paths. Change-Id: I49db291906512f56af065772f69acb281dfbdcfb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-04-03gicv2: Fix support for systems without secure interruptsSamuel Holland
Accessing the interrupt_props array only happens inside a loop over interrupt_props_num, so the GICv2 driver can cope with no secure interrupts. As in fact we have already some asserts in place that respect that, lets change the final place where we insist on a non-NULL pointer to relax that. This enables GICv2 platforms which have no need for a secure interrupt. This only covers the non-deprecated code paths. Also we remove a now redundant assert(). Change-Id: Id100ea978643d8558335ad28649d55743fe9bd4c Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-03-29Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statementsDimitris Papastamos
Fix switch statements to comply with MISRA rules
2018-03-26drivers: fix switch statements to comply with MISRA rulesJonathan Wright
Ensure (where possible) that switch statements in drivers comply with MISRA rules 16.1 - 16.7. Change-Id: I7a91e04b02af80fbc4673a52293386c0f81a0f7a Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
2018-03-26GIC: Fix setting interrupt configurationJeenu Viswambharan
- Interrupt configuration is a 2-bit field, so the field shift has to be double that of the bit number. - Interrupt configuration (level- or edge-trigger) is specified in the MSB of the field, not LSB. Fixes applied to both GICv2 and GICv3 drivers. Fixes ARM-software/tf-issues#570 Change-Id: Ia6ae6ed9ba9fb0e3eb0f921a833af48e365ba359 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-03-05[PATCH 1/2] qemu: Support MULTI_CONSOLE_APIMichalis Pappas
Include missing plat_helpers.S into pl011_console.S, to build successfully when MULTI_CONSOLE_API is enabled. Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
2018-03-01Emit warnings when using deprecated GIC initDan Handley
Emit runtime warnings when intializing the GIC drivers using the deprecated method of defining integer interrupt arrays in the GIC driver data structures; interrupt_prop_t arrays should be used instead. This helps platforms detect that they have migration work to do. Previously, no warning was emitted in this case. This affects both the GICv2 and GICv3 drivers. Also use the __deprecated attribute to emit a build time warning if these deprecated fields are used. These warnings are suppressed in the GIC driver compatibility functions but will be visible if platforms use them. Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a Signed-off-by: Dan Handley <dan.handley@arm.com>
2018-02-28Fix MISRA rule 8.4 Part 1Roberto Vargas
Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-28Fix MISRA rule 8.4 in common codeRoberto Vargas
Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined. Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-21Resolve TZC400 build issue when DEBUG=1 and ENABLE_ASSERTIONS=0Soby Mathew
Previously the definition of `_tzc_read_peripheral_id()` was wrapped in ENABLE_ASSERTIONS build flag. This causes build issue for TZC400 driver when DEBUG=1 and ENABLE_ASSERTIONS=0. This patch fixes the same by moving the definitions outside the ENABLE_ASSERTIONS build flag. Change-Id: Ic1cad69f02ce65ac34aefd39eaa96d5781043152 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-02-14Remove URLs from commentsAntonio Nino Diaz
This fixes all defects according to MISRA Rule 3.1: "The character sequences /* and // shall not be used within a comment". This affects all URLs in comments, so they have been removed: - The link in `sdei_state.c` can also be found in the documentation file `docs/sdei.rst`. - The bug that the file `io_fip.c` talks about doesn't affect the currently supported version of GCC, so it doesn't make sense to keep the comment. Note that the version of GCC officially supported is the one that comes with Linaro Release 17.10, which is GCC 6.2. - The link in `tzc400.c` was broken, and it didn't correctly direct to the Technical Reference Manual it should. The link has been replaced by the title of the document, which is more convenient when looking for the document. Change-Id: I89f60c25f635fd4c008a5d3a14028f814c147bbe Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-02-01Merge pull request #1236 from dbasehore/gic-save-restoredavidcunado-arm
RK3399 GIC save/restore
2018-01-23GICv3: Fix Dist restore for when the GIC is resetDerek Basehore
If the GIC loses power during suspend, which the restore code was written for, exit early in the post restore power sequence. This prevents an assert from tripping, and the power sequence isn't needed in this case anyways. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2018-01-19drivers: arm: pl011: Update PL011 driver to support MULTI_CONSOLE_APIJulius Werner
This patch updates the ARM PL011 console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: Ic34e4158addbb0c5fae500c9cff899c05a4f4206 Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-11-23Merge pull request #1145 from etienne-lms/rfc-armv7-2davidcunado-arm
Support ARMv7 architectures
2017-11-13GIC: Fix Group 0 enablingJeenu Viswambharan
At present, the GIC drivers enable Group 0 interrupts only if there are Secure SPIs listed in the interrupt properties/list. This means that, even if there are Group 0 SGIs/PPIs configured, the group remained disabled in the absence of a Group 0 SPI. Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when corresponding SGIs/PPIs are present. Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-11-13GICv2: Fix populating PE target dataJeenu Viswambharan
This patch brings in the following fixes: - The per-PE target data initialized during power up needs to be flushed so as to be visible to other PEs. - Setup per-PE target data for the primary PE as well. At present, this was only setup for secondary PEs when they were powered on. Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-11-08ARMv7: GICv2 driver can manage GICv1 with security extensionEtienne Carriere
Some SoCs integrate a GIC in version 1 that is currently not supported by the trusted firmware. This change hijacks GICv2 driver to handle the GICv1 as GICv1 is compatible enough with GICv2 as far as the platform does not attempt to play with virtualization support or some GICv2 specific power features. Note that current trusted firmware does not use these GICv2 features that are not available in GICv1 Security Extension. Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-10-16GIC: Allow specifying interrupt propertiesJeenu Viswambharan
The GIC driver initialization currently allows an array of interrupts to be configured as secure. Future use cases would require more interrupt configuration other than just security, such as priority. This patch introduces a new interrupt property array as part of both GICv2 and GICv3 driver data. The platform can populate the array with interrupt numbers and respective properties. The corresponding driver initialization iterates through the array, and applies interrupt configuration as required. This capability, and the current way of supplying array (or arrays, in case of GICv3) of secure interrupts, are however mutually exclusive. Henceforth, the platform should supply either: - A list of interrupts to be mapped as secure (the current way). Platforms that do this will continue working as they were. With this patch, this scheme is deprecated. - A list of interrupt properties (properties include interrupt group). Individual interrupt properties are specified via. descriptors of type 'interrupt_prop_desc_t', which can be populated with the macro INTR_PROP_DESC(). A run time assert checks that the platform doesn't specify both. Henceforth the old scheme of providing list of secure interrupts is deprecated. When built with ERROR_DEPRECATED=1, GIC drivers will require that the interrupt properties are supplied instead of an array of secure interrupts. Add a section to firmware design about configuring secure interrupts. Fixes ARM-software/tf-issues#262 Change-Id: I8eec29e72eb69dbb6bce77879febf32c95376942 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add helpers to set interrupt configurationJeenu Viswambharan
The helpers perform read-modify-write on GIC*_ICFGR registers, but don't serialise callers. Any serialisation must be taken care of by the callers. Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add API to set priority maskJeenu Viswambharan
API documentation updated. Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>