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5 daysMerge "refactor(plat/marvell): move doc platform build options into own ↵HEADmasterManish Pandey
subsections" into integration
6 daysrefactor(plat/marvell): move doc platform build options into own subsectionsPali Rohár
Update documentation and group platform specific build options into their own subsections. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I05927d8abf9f811493c49b856f06329220e7d8bb
8 daysMerge "docs(maintainers): update imx8 entry" into integrationJoanna Farley
9 daysdocs(maintainers): update imx8 entryPeng Fan
Add myself as i.MX8 maintainer. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ib037c24a75d42febd79f2eb1ab3b985356dbfb58
11 daysfeat: adding the diphda platformAbdellatif El Khlifi
This commit enables trusted-firmware-a with Trusted Board Boot support for the Diphda 64-bit platform. Diphda uses a FIP image located in the flash. The FIP contains the following components: - BL2 - BL31 - BL32 - BL32 SPMC manifest - BL33 - The TBB certificates The board boot relies on CoT (chain of trust). The trusted-firmware-a BL2 is extracted from the FIP and verified by the Secure Enclave processor. BL2 verification relies on the signature area at the beginning of the BL2 image. This area is needed by the SecureEnclave bootloader. Then, the application processor is released from reset and starts by executing BL2. BL2 performs the actions described in the trusted-firmware-a TBB design document. Signed-off-by: Rui Miguel Silva <rui.silva@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d
13 daysMerge changes from topic "marvell-a3k-a8k-updates" into integrationManish Pandey
* changes: fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable fix(plat/marvell/a3k): Fix check for external dependences fix(plat/marvell/a8k): Add missing build dependency for BLE target fix(plat/marvell/a8k): Correctly set include directories for individual targets fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
2021-07-20Merge "errata: workaround for Neoverse V1 errata 1940577" into integrationbipin.ravi
2021-07-19errata: workaround for Neoverse V1 errata 1940577johpow01
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some revisions of the V1 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r1p1 but this workaround only applies to revisions r1p0 - r1p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa
2021-07-19Merge changes I2b3aa9bd,I3237199b into integrationMadhukar Pappireddy
* changes: docs: add mt6795 to deprecated list feat(plat/mediatek/mt8195): add DCM driver
2021-07-19Merge "errata: workaround for Neoverse V1 errata 1791573" into integrationbipin.ravi
2021-07-17docs: add mt6795 to deprecated listRex-BC Chen
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2b3aa9bd0c23c360ecee673c68e1b2c92bc6d2be
2021-07-16errata: workaround for Neoverse V1 errata 1791573johpow01
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and r1p0 of the V1 processor core. It is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
2021-07-16Merge "docs(maintainers): add Julius Werner as Rockchip platform code owner" ↵Madhukar Pappireddy
into integration
2021-07-12docs: update supported FVP models as per release 11.15.14Manish V Badarkhe
Change-Id: I65da6ead356e3f4ee47c5a6bf391f65309bafcdd Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-07-12docs(maintainers): add Julius Werner as Rockchip platform code ownerJulius Werner
The two existing plat/rockchip code owners seem to be no longer active in the project and are not responding to reviews. There have been a couple of small fixup patches[1][2][3] pending for months that couldn't be checked in for lack of Code-Owner-Review+1 flag. Add myself to the code owner list to unblock this bottleneck (I have been deeply involved in the rk3399 port, at least, so I know most of the code reasonably well). [1] https://review.trustedfirmware.org/9616 [2] https://review.trustedfirmware.org/9990 [2] https://review.trustedfirmware.org/10415 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic7b2bb73c35a9bea91ff46ee445a22819d2045d9
2021-07-10fix(plat/marvell/a3k): Fix check for external dependencesPali Rohár
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with latest TF-A code base. Marvell do not provide these old tarballs on Extranet anymore. Public version on github repository contains all patches and is working fine, so for public TF-A builds use only public external dependencies from git. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
2021-07-10fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly setPali Rohár
Target mrvl_flash depends on external mv_ddr source code which is not part of TF-A project. Do not expect that it is pre-downloaded at some specific location and require user to specify correct path to mv_ddr source code via MV_DDR_PATH build option. TF-A code for Armada 37x0 platform also depends on mv_ddr source code and already requires passing correct MV_DDR_PATH build option. So for A8K implement same checks for validity of MV_DDR_PATH option as are already used by TF-A code for Armada 37x0 platform. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
2021-07-05Merge changes from topic "sb/measured-boot" into integrationSandrine Bailleux
* changes: refactor(plat/fvp): tidy up list of images to measure docs: explain Measured Boot dependency on Trusted Boot
2021-07-01Merge "docs: update maintainer entry for nxp platform code" into integrationManish Pandey
2021-06-30docs: update maintainer entry for nxp platform codePankaj Gupta
Add maintainer entry for NXP platform code Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Idd5407b8a9c1aa50ba812b2b1a7ce45e8fac5027
2021-06-30Merge "feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1" into integrationManish Pandey
2021-06-30Merge "feat(sve): enable SVE for the secure world" into integrationOlivier Deprez
2021-06-29Merge "errata: workaround for Cortex A77 errata 1791578" into integrationManish Pandey
2021-06-29docs: explain Measured Boot dependency on Trusted BootSandrine Bailleux
Change-Id: I04d9439d5967e93896dfdb0f3d7b0aec96c743f9 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-06-29feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1Manish Pandey
For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode. The underlying changes for enabling PIE in aarch32 is submitted in commit 4324a14bf Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469
2021-06-28feat(sve): enable SVE for the secure worldMax Shvetsov
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD. ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the platform. SVE is configured during initial setup and then uses EL3 context save/restore routine to switch between SVE configurations for different contexts. Reset value of CPTR_EL3 changed to be most restrictive by default. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
2021-06-24errata: workaround for Cortex A78 errata 1821534johpow01
Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and r1p0 of the A78 processor core, it is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/603e3733492bde1625aa8780 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c
2021-06-23errata: workaround for Cortex A77 errata 1791578johpow01
Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0, and r1p1 of the A77 processor core, it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ib4b963144f880002de308def12744b982d3df868
2021-06-22Merge "refactor(dt-bindings): align irq bindings with kernel" into integrationMark Dykes
2021-06-15Merge "docs: change Linaro release version to 20.01" into integrationMark Dykes
2021-06-14refactor(dt-bindings): align irq bindings with kernelYann Gautier
The arm-gic.h was a concatenation of arm-gic.h and irq.h from Linux. Just copy the 2 files here. They both have MIT license which is accepted in TF-A. With this alignment, a new macro is added (GIC_CPU_MASK_SIMPLE). Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ib45174f35f1796ebb7f34af861b59810cfb808b0
2021-06-11Merge "docs: change owner for MediaTek platforms" into integrationMadhukar Pappireddy
2021-06-08docs(imx8m): update build support for imx8mqJacky Bai
Due to the small OCRAM space used for TF-A, we will meet imx8mq build failure caused by too small RAM size. We CANNOT support it in TF-A CI. It does NOT mean that imx8mq will be dropped by NXP. NXP will still actively maintain it in NXP official release. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Iad726ffbc4eedc5f6770612bb9750986b9324ae9
2021-06-06Merge "docs: add threat model code owners" into integrationJoanna Farley
2021-06-01docs: change Linaro release version to 20.01Zelalem
We currently use Linaro release software stack version 20.01 in the CI. Reflect that change in the docs. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I0fa9f0163afb0bf399ec503abe9af4f17231f173
2021-05-31Merge "feat(tc0): add support for trusted services" into integrationOlivier Deprez
2021-05-27Merge changes from topic "Arm_PCI_Config_Space_Interface" into integrationManish Pandey
* changes: TF-A: Document SMC_PCI_SUPPORT option SMCCC/PCI: Handle std svc boilerplate SMCCC/PCI: Add initial PCI conduit definitions SMCCC: Hoist SMC_32 sanitization
2021-05-25fix(docs): fix typos in v2.5 release documentationMadhukar Pappireddy
Two issues in documentation were identified after the release. This patch fixes these typos. 1. Matternhorn ELP CPU was made available through v2.5 release, not Matternhorn CPU 2. We had upgraded TF-A to use GCC 10.2 toolchain family and used this toolchain for release testing Change-Id: I33e59bb5a6d13f4d40dbb3352004d5b133431d65 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-05-25TF-A: Document SMC_PCI_SUPPORT optionJeremy Linton
Add some basic documentation and pointers for the SMCCC PCI build options. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Change-Id: Ia35f31d15066ea74135367cde2dce2f26e6ab31e
2021-05-25docs: change owner for MediaTek platformsRex-BC Chen
Change owner for MediaTek platforms. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I60848a2c1b236cef61c2c22d8278197ad257b1c2
2021-05-17Merge changes I10b5cc17,I382d599f into integrationv2.5Madhukar Pappireddy
* changes: docs(prerequisites): add `--no-save` to `npm install` fix(hooks): downgrade `package-lock.json` version
2021-05-17docs(prerequisites): add `--no-save` to `npm install`Chris Kay
To avoid the mistake fixed by the previous commit, ensure users install the Node.js dependencies without polluting the lock file by passing `--no-save` to the `npm install` line. Change-Id: I10b5cc17b9001fc2e26deee02bf99ce033a949c1 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-05-14Merge "docs(juno): update TF-A build instructions" into integrationbipin.ravi
2021-05-14Merge "docs: spm design document refresh" into integrationOlivier Deprez
2021-05-13Merge "docs(release): add change log for v2.5 release" into integrationMadhukar Pappireddy
2021-05-12docs(juno): update TF-A build instructionsZelalem
Clean up instructions for building/running TF-A on the Juno platform and add correct link to SCP binaries. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b
2021-05-12docs: spm design document refreshOlivier Deprez
General refresh of the SPM document. Change-Id: I2f8e37c3f34bc8511b115f00b9a53b6a6ff41bea Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
2021-05-10feat(tc0): add support for trusted servicesDavidson K
This patch adds support for the crypto and secure storage secure partitions for the Total Compute platform. These secure partitions have to be managed by Hafnium executing at S-EL2 Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
2021-05-07docs(release): add change log for v2.5 releaseMadhukar Pappireddy
Change log for trusted-firmware-a v2.5 release Change-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-05-05docs: add threat model code ownersZelalem
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I97b2c5c5cfbf4ddb055d0f7a5ab04386460db060