aboutsummaryrefslogtreecommitdiff
path: root/bl32
AgeCommit message (Collapse)Author
3 daysrefactor(mte): remove mte, mte_permGovindraj Raja
Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling of any feature bits in EL3. So remove both FEAT handling. All mte regs that are currently context saved/restored are needed only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and remove FEAT_MTE usage. BREAKING CHANGE: Any platform or downstream code trying to use SCR_EL3.ATA bit(26) will see failures as this is now moved to be used only with FEAT_MTE2 with commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2 Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-02-20Merge "build: use toolchain identifiers in conditions" into integrationMark Dykes
2024-02-20Merge "build: use new toolchain variables for tools" into integrationMark Dykes
2024-02-12feat(mte): add mte2 featGovindraj Raja
Add support for feat mte2. tfsr_el2 is available only with mte2, however currently its context_save/restore is done with mte rather than mte2, so introduce 'is_feat_mte2_supported' to check mte2. Change-Id: I108d9989a8f5b4d1d2f3b9865a914056fa566cf2 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-02-06build: use toolchain identifiers in conditionsChris Kay
The toolchain refactor change introduces the `${toolchain}-${tool}-id` variables, which provide identifiers for all of the toolchain tools used by the build system. This change replaces the various conditions that are in use to identify these tools based on the path with a standard set of comparisons against these new identifier variables. Change-Id: Ib60e592359fa6e415c19a012e68d660f87436ca7 Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-02-06build: use new toolchain variables for toolsChris Kay
This change migrates the values of `CC`, `CPP`, `AS` and other toolchain variables to the new `$(toolchain)-$(tool)` variables, which were introduced by the toolchain refactor patch. These variables should be equivalent to the values that they're replacing. Change-Id: I644fe4ce82ef1894bed129ddb4b6ab94fb04985d Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-01-23refactor(mte): deprecate CTX_INCLUDE_MTE_REGSGovindraj Raja
Currently CTX_INCLUDE_MTE_REGS is used for dual purpose, to enable allocation tags register and to context save and restore them and also to check if mte feature is available. To make it more meaningful, remove CTX_INCLUDE_MTE_REGS and introduce FEAT_MTE. This would enable allocation tags register when FEAT_MTE is enabled and also supported from platform. Also arch features can be conditionally enabled disabled based on arch version from `make_helpers/arch_features.mk` Change-Id: Ibdd2d43874634ad7ddff93c7edad6044ae1631ed Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-11-06feat(build): check that .text section starts at page boundaryAndrey Skvortsov
Linker may decide to put new unspecified sections before .text section. That will cause non-working image, because entry point isn't at __BLXX_START__. Device just not booted with such image. This happened for example with .note.gnu.build-id section generated for LTO build in some cases. Now linker will report this situation as an error. ``` /usr/lib/gcc-cross/aarch64-linux-gnu/13/../../../../aarch64-linux-gnu/bin/ld: .text is not aligned on a page boundary. collect2: error: ld returned 1 exit status ``` Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Change-Id: I5ae46ddd1e6e431e1df1715d1d301f6dd7181cc7
2023-08-04feat(bl32): print entry point before exiting SP_MINStephan Gerhold
BL31 prints information about the entry point in the normal world before exiting, but for some reason SP_MIN does not do that. Add the missing call to print_entry_point_info() for more consistency. Change-Id: I2f4961fec57fcc9955cd15652d4ceba3bbb32375 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-08-04fix(bl32): avoid clearing argument registers in RESET_TO_SP_MIN caseStephan Gerhold
RESET_TO_SP_MIN is also used by platforms with a non TF-A bootloader, in which case there might be platform-specific arguments passed in the CPU registers. At the moment these are cleared and cannot be used by the platform layer. For BL31 this was recently changed in "fix(bl31): avoid clearing of argument registers in RESET_TO_BL31 case", but on AArch32 SP_MIN still has the old behavior. Make this consistent by preserving the registers in SP_MIN as well and use the chance to clarify the existing comments a bit. Change-Id: I0039c72477249eed76c3da23cb4f10ac59b310d0 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-08-04fix(bl32): always include arm_arch_svc in SP_MINStephan Gerhold
The PSCI_FEATURES call implementation in TF-A always indicates support for SMCCC_VERSION, but only BL31 ensures that the corresponding Arm Architecture Service (arm_arch_svc) is really included in the build. For SP_MIN only stm32mp1 currently includes it in the platform-specific make file. This means that it is easily possible to build configurations that violate the PSCI/SMCCC specification. On Linux this leads to incorrect detection of the SMC Calling Convention when using SP_MIN: [ 0.000000] psci: SMC Calling Convention v65535.65535 Fix this by always including the Arm Architecture Service in SP_MIN builds. This allows Linux to detect the convention correctly: [ 0.000000] psci: SMC Calling Convention v1.4 Change-Id: Iaa3076c162b7a55633ec1e27eb5c44d22f8eb2a1 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-06-29refactor(pmu): convert FEAT_MTPMU to C and move to persistent register initBoyan Karatotev
The FEAT_MTPMU feature disable runs very early after reset. This means, it needs to be written in assembly, since the C runtime has not been initialised yet. However, there is no need for it to be initialised so soon. The PMU state is only relevant after TF-A has relinquished control. The code to do this is also very verbose and difficult to read. Delaying the initialisation allows for it to happen with the rest of the PMU. Align with FEAT_STATE in the process. BREAKING CHANGE: This patch explicitly breaks the EL2 entry path. It is currently unsupported. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I2aa659d026fbdb75152469f6d19812ece3488c6f
2023-06-21fix(tsp): fix destination ID in direct requestMarc Bonnici
Ensure the TSP ID is set as the source ID in a direct request. Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Change-Id: Ia082fe5a1da6f2994072ec70c6ba818212a52f20
2023-06-12chore(bl): add UNALIGNED symbols for TEXT/RODATAMichal Simek
Add symbols to mark end of TEXT/RODATA before page alignment. Similar change was done by commit 8d69a03f6a7d ("Various improvements/cleanups on the linker scripts") for RO_END/COHERENT_RAM. These symbols help to know how much free space is in the final binary because of page alignment. Also show all *UNALIGNED__ symbols via poetry. For example: poetry run memory -p zynqmp -b debug Change-Id: I322beba37dad76be9f4e88ca7e5b3eff2df7d96e Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-01Merge changes from topic "hm/memmap-feat" into integrationSandrine Bailleux
* changes: build(bl32): add symbols for memory layout build(bl31): add symbols for memory layout build(bl2): add symbols for memory layout build(bl1): add symbols for memory layout refactor: improve readability of symbol table
2023-05-22fix(tsp): flush uart consoleGovindraj Raja
tsp uses uart2 and is printing some init messages in main, but in certain situations we may exit tsp and may not have flushed uart data, this could later land in uart fifo overflow or random corruption. Time to time we have seen a character corruption on uart2 arising out of logs from tsp main. So flush console messages from tsp_main before leaving the function. This is inline with our uart usage strategy across TF-A as most entry _main function ensures uart console is flushed before exit. The console flush is harmless and should fix the potential character corruption if it was due to tsp_main negligence. But we cannot also rule out that it could be a potential FVP-UART problem, but that's quite unlikely and further CI daily's will give us a idea if this fixes the character corruption seen or we may need stress test FVP-UART which maybe corrupting character in certain circumstances. Signed-off-by: Govindraj Raja <govindraj.raja@arm.com> Change-Id: I300c6b71c00fa92b8b97b3e77ea936b393d0f7b5
2023-05-12build(bl32): add symbols for memory layoutHarrison Mutai
Add symbols for mapping the physical memory layout of BL32. There are symbols that partially satisfy this requirement, however, the naming of these is inconsistent. Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> Change-Id: I106187f93b227d604bda650892f9e919047b3fc7
2023-05-05feat(errata_abi): errata management firmware interfaceSona Mathew
This patch adds the errata management firmware interface for lower ELs to discover details about CPU erratum. Based on the CPU erratum identifier the interface enables the OS to find the mitigation of an erratum in EL3. The ABI can only be present in a system that is compliant with SMCCCv1.1 or higher. This implements v1.0 of the errata ABI spec. For details on all possible return values, refer the design documentation below: ABI design documentation: https://developer.arm.com/documentation/den0100/1-0?lang=en Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> Change-Id: I70f0e2569cf92e6e02ad82e3e77874546232b89a
2023-04-26Merge changes from topic "align-sections" into integrationJoanna Farley
* changes: build(trp): sort sections by alignment by default build(tsp): sort sections by alignment by default build(sp-min): sort sections by alignment by default build(bl31): sort sections by alignment by default build(bl2u): sort sections by alignment by default build(bl2): sort sections by alignment by default
2023-04-25refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKEDAndre Przywara
At the moment we only support FEAT_DIT to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_DIT=2), by splitting is_armv8_4_dit_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed). We use ENABLE_DIT in two occassions in assembly code, where we just set the DIT bit in the DIT system register. Protect those two cases by reading the CPU ID register when ENABLE_DIT is set to 2. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-17build(tsp): sort sections by alignment by defaultChris Kay
This change forces LD to sort all input sections by alignment when allocating them within an output section. This is done in some places explicitly in the linker scripts today, but this makes sure we don't miss any easy targets. Change-Id: Id702a2a572f2b43c77d53634ddc64b0220d2560b Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-04-17build(sp-min): sort sections by alignment by defaultChris Kay
This change forces LD to sort all input sections by alignment when allocating them within an output section. This is done in some places explicitly in the linker scripts today, but this makes sure we don't miss any easy targets. Change-Id: I33d5044e4d34a9d1187d0935ffc03d1f1177e340 Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-03-27refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1Andre Przywara
So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-03-22refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKEDAndre Przywara
At the moment we only support access to the trace unit by system registers (SYS_REG_TRACE) to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_SYS_REG_TRACE_FOR_NS=2), by adding is_feat_sys_reg_trace_supported(). That function considers both build time settings and runtime information (if needed), and is used before we access SYS_REG_TRACE related registers. The FVP platform decided to compile in support unconditionally (=1), even though this is an optional feature, so it is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I450a574a4f6bd9fc269887037049c94c906f54b2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-02-27refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKEDAndre Przywara
At the moment we only support FEAT_TRF to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_TRF_FOR_NS=2), by splitting is_feat_trf_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access TRF related registers. Also move the context saving code from assembly to C, and use the new is_feat_trf_supported() function to guard its execution. The FVP platform decided to compile in support unconditionally (=1), even though FEAT_TRF is an ARMv8.4 feature, so is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: Ia97b01adbe24970a4d837afd463dc5506b7295a3 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-02-20build: always prefix section names with `.`Chris Kay
Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-02-10build: clarify linker script generationChris Kay
The following build system variables have been renamed: - `LINKERFILE` -> `DEFAULT_LINKER_SCRIPT` - `BL_LINKERFILE` -> `DEFAULT_LINKER_SCRIPT_SOURCE` - `<IMAGE>_LINKERFILE` -> `<IMAGE>_DEFAULT_LINKER_SCRIPT_SOURCE` These new names better reflect how each variable is used: 1. the default linker script is passed via `-dT` instead of `-T` 2. linker script source files are first preprocessed Additionally, linker scripts are now placed in the build directory relative to where they exist in the source directory. For example, the `bl32/sp_min/sp_min.ld.S` would now preprocess to `sp_min/sp_min.ld` instead of just `bl32.ld` BREAKING-CHANGE: The `LINKERFILE`, `BL_LINKERFILE` and `<IMAGE_LINKERFILE>` build system variables have been renamed. See the commit message for more information. Change-Id: If8cef65dcb8820e8993736702c8741e97a66e6cc Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-02-10style: normalize linker script code styleChris Kay
There are a variety of code styles used by the various linker scripts around the code-base. This change brings them in line with one another and attempts to make the scripts more friendly for skim-readers. Change-Id: Ibee2afad0d543129c9ba5a8a22e3ec17d77e36ea Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-02-10fix(tsp): loop / crash if mmap of region failsThomas Viehweger
In test_memory_send the variable i is of unsigned type, so it is never negative. If i is 0, the result of i-- is 4294967295. Don't know what happens if trying to access composite->address_range_array[4294967295]. Made i a signed integer. Signed-off-by: Thomas Viehweger <Thomas.Viehweger@rohde-schwarz.com> Change-Id: I8b4e532749b5e86e4b5acd238e72c3f88e309ff2
2022-12-08fix(tsp): use verbose for power logsShruti Gupta
TSP use verbose for cpu suspend resume logs Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: Ic1d3706feec6361946dd5c0d2bea90a2dd7a2d02
2022-12-08fix(el3-spmc): fix coverity scan warningsShruti Gupta
Validate emad descriptor integrity before accessing. Check for NULL pointer access. Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: Id4ff3e5d88be95ca8d067378e344947880ec984b
2022-10-03feat(debug): add helpers for aborts on AARCH32Yann Gautier
New helper functions are created to handle data & prefetch aborts in AARCH32. They call platform functions, just like what report_exception is doing. As extended MSR/MRS instructions (to access lr_abt in monitor mode) are only available if CPU (Armv7) has virtualization extension, the functions branch to original report_exception handlers if this is not the case. Those new helpers are created mainly to distinguish data and prefetch aborts, as they both share the same mode. This adds 40 bytes of code. Change-Id: I5dd31930344ad4e3a658f8a9d366a87a300aeb67 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-08-25feat(tsp): enable test cases for EL3 SPMCMarc Bonnici
Introduce initial test cases to the TSP which are designed to be exercised by the FF-A Test Driver in the Normal World. These have been designed to test basic functionality of the EL3 SPMC. These tests currently ensure the following functionality: - Partition discovery. - Direct messaging. - Communication with a Logical SP. - Memory Sharing and Lending ABIs - Sharing of contiguous and non-contiguous memory regions. - Memory region descriptors spread of over multiple invocations. Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: Iaee4180aa18d6b7ac7b53685c6589f0ab306e876
2022-08-25feat(tsp): add ffa_helpers to enable more FF-A functionalityMarc Bonnici
Include ffa_helpers originally taken from the TF-A Tests repo to provide support for additional FF-A functionality. Change-Id: Iacc3ee270d5e3903f86f8078ed915d1e791c1298 Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
2022-08-24feat(tsp): add FF-A support to the TSPAchin Gupta
This patch adds the FF-A programming model in the test secure payload to ensure that it can be used to test the following spec features. 1. SP initialisation on the primary and secondary cpus. 2. An event loop to receive direct requests and respond with direct responses. 3. Ability to receive messages that indicate power on and off of a cpu. 4. Ability to handle a secure interrupt. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Signed-off-by: Shruti <shruti.gupta@arm.com> Change-Id: I81cf744904d5cdc0b27862b5e4bc6f2cfe58a13a
2022-04-28fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960John Powell
Cortex-A15 does not support FEAT_CSV2 so the existing workaround for Spectre V2 is sufficient to mitigate against Spectre BHB attacks, however the code needed to be updated to work with the new build flag. Also, some code was refactored several years ago and not updated in the Cortex-A15 library file so this patch fixes that as well. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I768c88a38c561c91019b038ac6c22b291955f18e
2022-02-03test(el3-runtime): dit is retained on world switchDaniel Boulby
Add tsp service to check the value of the PSTATE DIT bit is as expected and toggle it's value. This is used to ensure that the DIT bit is maintained during a switch from the Normal to Secure worlds and back. Change-Id: I4e8bdfa6530e5e75925c0079d4fa2795133c5105 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2021-11-12fix: use correct printf format for uint64_tManish Pandey
sha 4ce3e99a3 introduced printf format specifiers for fixed width types, which uses PRI*64 instead of "ll" for 64 bit values. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic6811cc1788c698adde0807e5f8ab5290a900a26
2021-11-08fix: libc: use long for 64-bit types on aarch64Scott Branden
Use long instead of long long on aarch64 for 64_t stdint types. Introduce inttypes.h to properly support printf format specifiers for fixed width types for such change. Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1 Signed-off-by: Scott Branden <scott.branden@broadcom.com>
2021-10-26build(amu): introduce `amu.mk`Chris Kay
This change introduces the `amu.mk` Makefile, used to remove the need to manually include AMU sources into the various build images. Makefiles requiring the list of AMU sources are expected to include this file and use `${AMU_SOURCES}` to retrieve them. Change-Id: I3d174033ecdce6439a110d776f0c064c67abcfe0 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-19fix(pie): invalidate data cache in the entire image range if PIE is enabledZelalem Aweke
Currently on image entry, the data cache in the RW address range is invalidated before MMU is enabled to safeguard against potential stale data from previous firmware stage. If PIE is enabled however, RO sections including the GOT may be also modified during pie fixup. Therefore, to be on the safe side, invalidate the entire image region if PIE is enabled. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I7ee2a324fe4377b026e32f9ab842617ad4e09d89
2021-08-26feat(trf): enable trace filter control register access from lower NS ELManish V Badarkhe
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is implemented but unused). Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26feat(sys_reg_trace): enable trace system registers access from lower NS ELsManish V Badarkhe
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is implemented but unused). Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-04-21Add PIE support for AARCH32Yann Gautier
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*. Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-04-21Avoid the use of linker *_SIZE__ macrosYann Gautier
The use of end addresses is preferred over the size of sections. This was done for some AARCH64 files for PIE with commit [1], and some extra explanations can be found in its commit message. Align the missing AARCH64 files. For AARCH32 files, this is required to prepare PIE support introduction. [1] f1722b693d36 ("PIE: Use PC relative adrp/adr for symbol reference") Change-Id: I8f1c06580182b10c680310850f72904e58a54d7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-02-11bl32: Enable TRNG service buildAndre Przywara
The Trusted Random Number Generator service is using the standard SMC service dispatcher, running in BL31. For that reason we list the files implementing the service in bl31.mk. However when building for a 32-bit TF-A runtime, sp_min.mk is the Makefile snippet used, so we have to add the files into there as well. This fixes 32-bit builds of platforms that provide the TRNG service. Change-Id: I8be61522300d36477a9ee0a9ce159a140390b254 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-12-11Add support for FEAT_MTPMU for Armv8.6Javier Almansa Sobrino
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads. If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it. This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
2020-11-13TSP: Fix GCC 11.0.0 compilation error.Alexei Fedorov
This patch fixes the following compilation error reported by aarch64-none-elf-gcc 11.0.0: bl32/tsp/tsp_main.c: In function 'tsp_smc_handler': bl32/tsp/tsp_main.c:393:9: error: 'tsp_get_magic' accessing 32 bytes in a region of size 16 [-Werror=stringop-overflow=] 393 | tsp_get_magic(service_args); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ bl32/tsp/tsp_main.c:393:9: note: referencing argument 1 of type 'uint64_t *' {aka 'long long unsigned int *'} In file included from bl32/tsp/tsp_main.c:19: bl32/tsp/tsp_private.h:64:6: note: in a call to function 'tsp_get_magic' 64 | void tsp_get_magic(uint64_t args[4]); | ^~~~~~~~~~~~~ by changing declaration of tsp_get_magic function from void tsp_get_magic(uint64_t args[4]); to uint128_t tsp_get_magic(void); which returns arguments directly in x0 and x1 registers. In bl32\tsp\tsp_main.c the current tsp_smc_handler() implementation calls tsp_get_magic(service_args); , where service_args array is declared as uint64_t service_args[2]; and tsp_get_magic() in bl32\tsp\aarch64\tsp_request.S copies only 2 registers in output buffer: /* Store returned arguments to the array */ stp x0, x1, [x4, #0] Change-Id: Ib34759fc5d7bb803e6c734540d91ea278270b330 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-10-18Merge "Increase type widths to satisfy width requirements" into integrationJoanna Farley
2020-10-12Increase type widths to satisfy width requirementsJimmy Brisson
Usually, C has no problem up-converting types to larger bit sizes. MISRA rule 10.7 requires that you not do this, or be very explicit about this. This resolves the following required rule: bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None> The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U | 0x3c0U" (32 bits) is less that the right hand operand "18446744073709547519ULL" (64 bits). This also resolves MISRA defects such as: bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)] In the expression "3U << 20", shifting more than 7 bits, the number of bits in the essential type of the left expression, "3U", is not allowed. Further, MISRA requires that all shifts don't overflow. The definition of PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues. This fixes the violation by changing the definition to 1UL << 12. Since this uses 32bits, it should not create any issues for aarch32. This patch also contains a fix for a build failure in the sun50i_a64 platform. Specifically, these misra fixes removed a single and instruction, 92407e73 and x19, x19, #0xffffffff from the cm_setup_context function caused a relocation in psci_cpus_on_start to require a linker-generated stub. This increased the size of the .text section and caused an alignment later on to go over a page boundary and round up to the end of RAM before placing the .data section. This sectionn is of non-zero size and therefore causes a link error. The fix included in this reorders the functions during link time without changing their ording with respect to alignment. Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>