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path: root/bl31/aarch64/bl31_entrypoint.S
AgeCommit message (Expand)Author
2020-01-27Changes necessary to support SEPARATE_NOBITS_REGION featureMadhukar Pappireddy
2020-01-22Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"Mark Dykes
2020-01-21Changes necessary to support SEPARATE_NOBITS_REGION featureMadhukar Pappireddy
2019-12-17pmf: Make the runtime instrumentation work on AArch32Bence Szépkúti
2019-12-12PIE: make call to GDT relocation fixup generalizedManish Pandey
2019-09-13Refactor ARMv8.3 Pointer Authentication support codeAlexei Fedorov
2019-05-24Add support for Branch Target IdentificationAlexei Fedorov
2019-03-25PIE: Fix reloc at the beginning of bl31 entrypointLouis Mayencourt
2019-03-07BL31: Enable pointer authentication support in warm boot pathAlexei Fedorov
2019-02-27BL31: Enable pointer authentication supportAntonio Nino Diaz
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
2018-10-29PIE: Position Independant Executable support for BL31Soby Mathew
2018-10-04Remove some MISRA defects in common codeAntonio Nino Diaz
2018-06-27DynamIQ: Enable MMU without using stackJeenu Viswambharan
2018-02-28Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatchdavidcunado-arm
2018-02-27Add comments about mismatched TCR_ELx and xlat tablesAntonio Nino Diaz
2018-02-26Introduce the new BL handover interfaceSoby Mathew
2017-06-21Fully initialise essential control registersDavid Cunado
2017-05-03Use SPDX license identifiersdp-arm
2017-04-19PSCI: Build option to enable D-Caches early in warmbootSoby Mathew
2017-03-17Merge pull request #860 from jeenu-arm/hw-asstd-cohdavidcunado-arm
2017-03-08Simplify translation tables headers dependenciesAntonio Nino Diaz
2017-03-02Enable data caches early with hardware-assisted coherencyJeenu Viswambharan
2016-10-12Add PMF instrumentation points in TFdp-arm
2016-07-19Introduce PSCI Library InterfaceSoby Mathew
2015-12-14Remove dashes from image names: 'BL3-x' --> 'BL3x'Juan Castillo
2015-11-26Introduce COLD_BOOT_SINGLE_CPU build optionSandrine Bailleux
2015-09-14Make generic code work in presence of system cachesAchin Gupta
2015-06-04Introduce PROGRAMMABLE_RESET_ADDRESS build optionSandrine Bailleux
2015-06-04Rationalize reset handling codeSandrine Bailleux
2015-04-08Add support to indicate size and end of assembly functionsKévin Petit
2015-03-13Initialise cpu ops after enabling data cacheVikram Kanigiri
2015-01-26Call reset handlers upon BL3-1 entry.Yatharth Kochar
2015-01-22Remove coherent memory from the BL memory mapsSoby Mathew
2014-08-27Miscellaneous documentation fixesSandrine Bailleux
2014-08-20Add CPU specific power management operationsSoby Mathew
2014-08-20Introduce framework for CPU specific operationsSoby Mathew
2014-08-15Unmask SError interrupt and clear SCR_EL3.EA bitAchin Gupta
2014-08-01Call platform_is_primary_cpu() only from reset handlerJuan Castillo
2014-07-28Merge pull request #172 from soby-mathew/sm/asm_assertdanh-arm
2014-07-28Rework the crash reporting in BL3-1 to use less stackSoby Mathew
2014-07-28Simplify management of SCTLR_EL3 and SCTLR_EL1Achin Gupta
2014-07-19Remove coherent stack usage from the cold boot pathAchin Gupta
2014-06-27Merge pull request #151 from vikramkanigiri/vk/t133-code-readabilityAndrew Thoelke
2014-06-24Simplify entry point information generation code on FVPVikram Kanigiri
2014-06-17Remove early_exceptions from BL3-1Andrew Thoelke
2014-06-16Per-cpu data cache restructuringAndrew Thoelke
2014-05-22Introduce interrupt handling framework in BL3-1Achin Gupta
2014-05-22Add support for BL3-1 as a reset vectorVikram Kanigiri
2014-05-22Populate BL31 input parameters as per new specVikram Kanigiri