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32 hoursMerge "refactor: moved drivers hdr files to include/drivers/nxp" into ↵HEADmasterintegrationManish Pandey
integration
34 hoursrefactor: moved drivers hdr files to include/drivers/nxpPankaj Gupta
NXP drivers header files are moved: - from: drivers/nxp/<xx>/*.h - to : include/drivers/nxp/<xx>/*.h To accommodate these changes each drivers makefiles drivers/nxp/<xx>/xx.mk, are updated. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21
47 hoursMerge changes from topic "fw-update-2" into integrationMadhukar Pappireddy
* changes: feat(sw_crc32): add software CRC32 support refactor(hw_crc32): renamed hw_crc32 to tf_crc32 feat(fwu): avoid booting with an alternate boot source docs(fwu): add firmware update documentation feat(fwu): avoid NV counter upgrade in trial run state feat(plat/arm): add FWU support in Arm platforms feat(fwu): initialize FWU driver in BL2 feat(fwu): add FWU driver feat(fwu): introduce FWU platform-specific functions declarations docs(fwu_metadata): add FWU metadata build options feat(fwu_metadata): add FWU metadata header and build options
2 daysfeat(sw_crc32): add software CRC32 supportManish V Badarkhe
Added software CRC32 support in case platform doesn't support hardware CRC32. Platform must include necessary Zlib source files for compilation to use software CRC32 implementation. Change-Id: Iecb649b2edf951944b1a7e4c250c40fe7a3bde25 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysrefactor(hw_crc32): renamed hw_crc32 to tf_crc32Manish V Badarkhe
Renamed hw_crc32 to tf_crc32 to make the file and function name more generic so that the same name can be used in upcoming software CRC32 implementation. Change-Id: Idff8f70c50ca700a4328a27b49d5e1f14d2095eb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysfeat(fwu): avoid booting with an alternate boot sourceManish V Badarkhe
All firmware banks should be part of the same non-volatile storage as per PSA FWU specification, hence avoid checking for any alternate boot source when PSA FWU is enabled. Change-Id: I5b016e59e87f1cbfc73f4cd29fce6017c24f88b3 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysdocs(fwu): add firmware update documentationManish V Badarkhe
Added firmware update documentation for: 1. PSA firmware update build flag 2. Porting guidelines to set the addresses of FWU metadata image and updated components in I/O policy Change-Id: Iad3eb68b4be01a0b5850b69a067c60fcb464f54b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysfeat(fwu): avoid NV counter upgrade in trial run stateManish V Badarkhe
Avoided NV counter update when the system is running in trial run state. Change-Id: I5da6a6760f8a9faff777f2ff879156e9c3c76726 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysfeat(plat/arm): add FWU support in Arm platformsManish V Badarkhe
Added firmware update support in Arm platforms by using FWU platform hooks and compiling FWU driver in BL2 component. Change-Id: I71af06c09d95c2c58e3fd766c4a61c5652637151 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysfeat(fwu): initialize FWU driver in BL2Manish V Badarkhe
Initialized FWU driver module in BL2 component under build flag PSA_FWU_SUPPORT. Change-Id: I08b191599835925c355981d695667828561b9a21 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysfeat(fwu): add FWU driverManish V Badarkhe
Implemented FWU metadata load and verification APIs. Also, exported below APIs to the platform: 1. fwu_init - Load FWU metadata in a structure. Also, set the addresses of updated components in I/O policy 2. fwu_is_trial_run_state - To detect trial run or regular run state Change-Id: I67eeabb52d9275ac83be635306997b7c353727cd Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysfeat(fwu): introduce FWU platform-specific functions declarationsManish V Badarkhe
Added FWU platform specific functions declarations in common platform header. Change-Id: I637e61753ea3dc7f7e7f3159ae1b43ab6780aef2 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysMerge "feat(ff-a): change manifest messaging method" into integrationOlivier Deprez
2 daysdocs(fwu_metadata): add FWU metadata build optionsManish V Badarkhe
Added the build options used in defining the firmware update metadata structure. Change-Id: Idd40ea629e643e775083f283b75c80f6c026b127 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2 daysfeat(fwu_metadata): add FWU metadata header and build optionsManish V Badarkhe
Added a firmware update metadata structure as per section 4.1 in the specification document[1]. Also, added the build options used in defining the firmware update metadata structure. [1]: https://developer.arm.com/documentation/den0118/a/ Change-Id: I8f43264a46fde777ceae7fd2a5bb0326f1711928 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
5 daysMerge changes Ic7579b60,I05414ca1 into integrationMadhukar Pappireddy
* changes: fix(plat/ea_handler): print newline before fatal abort error message feat(common/debug): add new macro ERROR_NL() to print just a newline
6 daysfix(plat/ea_handler): print newline before fatal abort error messagePali Rohár
External Abort may happen also during printing of some messages by U-Boot or kernel. So print newline before fatal abort error message. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ic7579b605e695c2e4cb9a4f5cdc2d0b3e5083e49
6 daysMerge "refactor(plat/marvell): move doc platform build options into own ↵Manish Pandey
subsections" into integration
7 daysMerge "services: Fix pmr_el1 rewrote issue in sdei_disaptch_event()" into ↵Joanna Farley
integration
7 daysMerge "fix(plat/fvp): provide boot files via semihosting" into integrationManish Pandey
7 daysfix(plat/fvp): provide boot files via semihostingStas Sergeev
These files are needed during boot, but they were missing for semihosting. With this patch, the list of files is complete enough to boot on ATF platform via semihosting. Change-Id: I2f0ca25983a6e18096f040780776f19f8040ea79 Signed-off-by: stsp@users.sourceforge.net
7 daysMerge "rpi4: enable RPi4 PCI SMC conduit" into integrationManish Pandey
7 daysMerge "fix(gicv3): add dsb in both disable and enable function of ↵Manish Pandey
gicv3_cpuif" into integration
7 daysMerge "rpi4: SMCCC PCI implementation" into integrationJoanna Farley
7 daysservices: Fix pmr_el1 rewrote issue in sdei_disaptch_event()Ming Huang
Consider a RAS scenario: Enter EL3 by sync exception, then call spm_mm_sp_call() enter EL0s to handle this error, then call sdei_dispatch_event() to inform OS. Finally, return back to OS from sync exception flow. Similar flow is sgi_ras_intr_handler() in sgi_ras.c. The icc_pmr_el1 register will be change in above flow: 1 cm_el1_sysregs_context_save(NON_SECURE); -> ehf_exited_normal_world(); ##icc_pmr_el1: 0xf8 => 0x80 2 spm_mm_sp_call(); 3 sdei_dispatch_event(); 4 ehf_activate_priority(sdei_event_priority(map)); ##icc_pmr_el1: 0x80 => 0x60 5 restore_and_resume_ns_context(); -> ehf_exited_normal_world(); ##return due to has_valid_pri_activations(pe_data) == 1 6 ehf_deactivate_priority(sdei_event_priority(map)); ##icc_pmr_el1: 0x60 => 0x80 The icc_pmr_el1 was rewrote from 0xf8 to 0x80. This issue will result in OS hang when eret to OS from RAS flow. Move ehf_activate_priority(sdei_event_priority(map)) after restore_and_resume_ns_context() can fix this issue. Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Change-Id: If01ec55cf0aabf1594dece1ad50d3ec3406cdabc
8 daysrpi4: SMCCC PCI implementationJeremy Linton
The rpi4 has a single nonstandard ECAM. It is broken into two pieces, the root port registers, and a window to a single device's config space which can be moved between devices. Now that we have widened the page tables/MMIO window, we can create a read/write acces functions that are called by the SMCCC/PCI API. As an example platform, the rpi4 single device ECAM region quirk is pretty straightforward. The assumption here is that a lower level (uefi) has configured and initialized the PCI root to match the values we are using here. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Change-Id: Ie1ffa8fe9aa1d3c62e6aa84746a949c1009162e0
8 daysrpi4: enable RPi4 PCI SMC conduitJeremy Linton
Now that we have adjusted the address map, added the SMC conduit code, and the RPi4 PCI callbacks, lets add the flags to enable everything in the build. By default this service is disabled because the expectation is that its only useful in a UEFI+ACPI environment. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Change-Id: I2a3cac6d63ba8119d3b711db121185816b89f8a2
8 daysMerge "plat/sgi: tag dmc620 MM communicate messages with a guid" into ↵Madhukar Pappireddy
integration
8 daysrefactor(plat/marvell): move doc platform build options into own subsectionsPali Rohár
Update documentation and group platform specific build options into their own subsections. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I05927d8abf9f811493c49b856f06329220e7d8bb
8 daysMerge "fix(rk3399/suspend): correct LPDDR4 resume sequence" into integrationMadhukar Pappireddy
8 daysMerge "fix(fdt): fix OOB write in uuid parsing function" into integrationOlivier Deprez
9 daysfix(fdt): fix OOB write in uuid parsing functionDavid Horstmann
The function read_uuid() zeroes the UUID destination buffer on error. However, it mistakenly uses the dest pointer that has been incremented many times during the parsing, leading to an out-of-bounds write. To fix this, retain a pointer to the start of the buffer, and use this when clearing it instead. Signed-off-by: David Horstmann <david.horstmann@arm.com> Change-Id: Iee8857be5d3f383ca2eab86cde99a43bf606f306
9 daysMerge "fix(plat/imx): do not keep mmc_device_info in stack" into integrationMadhukar Pappireddy
9 daysMerge changes from topic "allwinner_mmap" into integrationAndré Przywara
* changes: refactor(plat/allwinner): clean up platform definitions refactor(plat/allwinner): do not map BL32 DRAM at EL3 refactor(plat/allwinner): map SRAM as device memory by default refactor(plat/allwinner): rename static mmap region constant feat(bl_common): import BL_NOBITS_{BASE,END} when defined
9 daysMerge "fix(sdei): set SPSR for SDEI based on TakeException" into integrationManish Pandey
9 daysMerge changes from topic "sve+amu" into integrationManish Pandey
* changes: fix(plat/tc0): enable AMU extension fix(el3_runtime): fix SVE and AMU extension enablement flags
10 daysMerge "docs(maintainers): update imx8 entry" into integrationJoanna Farley
11 daysMerge "refactor(aarch64): remove `FEAT_BTI` architecture check" into integrationJoanna Farley
11 daysdocs(maintainers): update imx8 entryPeng Fan
Add myself as i.MX8 maintainer. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ib037c24a75d42febd79f2eb1ab3b985356dbfb58
12 daysMerge changes from topic "diphda" into integrationMadhukar Pappireddy
* changes: feat: disabling non volatile counters in diphda feat: adding the diphda platform
12 daysfix(sdei): set SPSR for SDEI based on TakeExceptionDaniel Boulby
The SDEI specification now says that during an SDEI event handler dispatch the SPSR should be set according to the TakeException() pseudocode function defined in the Arm Architecture Reference Manual. This patch sets the SPSR according to the function given in ARM DDI 0487F.c page J1-7635 Change-Id: Id2f8f2464fd69c701d81626162827e5c4449b658 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
12 daysfix(plat/tc0): enable AMU extensionArunachalam Ganapathy
Recent changes to enable SVE for the secure world have disabled AMU extension by default in the reset value of CPTR_EL3 register. So the platform has to enable this extension explicitly. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I7d930d96ec22d7c3db961411370564bece0ce272
12 daysfix(el3_runtime): fix SVE and AMU extension enablement flagsArunachalam Ganapathy
If SVE are enabled for both Non-secure and Secure world along with AMU extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit from bl31. This restricts access to the AMU register set in normal world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT by saving and restoring CPTR_EL3 register from EL3 context. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
13 daysfix(gicv3): add dsb in both disable and enable function of gicv3_cpuifMing Huang
A RAS error may be triggered while offline core in OS. Error: Uncorrected software error in the Distributor, with IERR=9,SERR=f. Core put to sleep before its Group enables were cleared. gicv3_cpuif_disable() will be called in offline core flow. According to GIC architecture version 3 and version 4: Architectural execution of a DSB instruction guarantees that the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1, ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed by the associated Redistributor. An ISB or other context synchronization operation must precede the DSB to ensure visibility of System register writes. Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d
13 daysrefactor(plat/allwinner): clean up platform definitionsSamuel Holland
Group the SCP base/size definitions in a more logical location. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id43f9b468d7d855a2413173d674a5ee666527808
13 daysrefactor(plat/allwinner): do not map BL32 DRAM at EL3Samuel Holland
BL31 does not appear to ever access the DRAM allocated to BL32, so there is no need to map it at EL3. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ie8727b793e53ea14517894942266f6da0333eb74
13 daysrefactor(plat/allwinner): map SRAM as device memory by defaultSamuel Holland
The SRAM on Allwinner platforms is shared between BL31 and coprocessor firmware. Previously, SRAM was mapped as normal memory by default. This scheme requires carveouts and cache maintenance code for proper synchronization with the coprocessor. A better scheme is to only map pages owned by BL31 as normal memory, and leave everything else as device memory. This removes the need for cache maintenance, and it makes the mapping for BL31 RW data explicit instead of magic. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348
13 daysrefactor(plat/allwinner): rename static mmap region constantSamuel Holland
This constant specifically refers to the number of static mmap regions. Rename it to make that clear. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I475c037777ce2a10db2631ec0e7446bb73590a36
13 daysfeat(bl_common): import BL_NOBITS_{BASE,END} when definedSamuel Holland
If SEPARATE_NOBITS_REGION is enabled, the platform may need to map memory specifically for that region. Import the symbols from the linker script to allow the platform to do so. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Iaec4dee94a6735b22f58f7b61f18d53e7bc6ca8d
13 daysfeat: disabling non volatile counters in diphdaAbdellatif El Khlifi
At this stage of development Non Volatile counters are not implemented in the Diphda platform. This commit disables their use during the Trusted Board Boot by overriding the NV counters get/set functions. Change-Id: I8dcbebe0281cc4d0837c283ff637e20b850988ef Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>