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2020-04-20Merge "Incrementing the minor version to reflect upcoming v2.3 release" into ↵v2.3Mark Dykes
integration
2020-04-20Incrementing the minor version to reflect upcoming v2.3 releaseMadhukar Pappireddy
Change-Id: I27f7d92988fc16f68041c2ddaa8dd3a60362ddd1 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-04-17Merge "juno/sgm: Align SCP_BL2 to page boundary" into integrationv2.3-rc2Mark Dykes
2020-04-17Merge "doc: Fixup some SMCCC links" into integrationMark Dykes
2020-04-17juno/sgm: Align SCP_BL2 to page boundaryChris Kay
This commit fixes an assertion that was triggering in certain contexts: ERROR: mmap_add_region_check() failed. error -22 ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:790 Change-Id: Ia55b3fb4f496c8cd791ea6093d122edae0a7e92a Signed-off-by: Chris Kay <chris.kay@arm.com> Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-04-17doc: Fixup some SMCCC linksSandrine Bailleux
This is a fixup for patch 3ba55a3c5fa260c9218be1adff8f39fc2a568d68 ("docs: Update SMCCC doc, other changes for release"), where some links names got changed but their references didn't. Change-Id: I980d04dde338f3539a2ec1ae2e807440587b1cf5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-04-17Merge "doc: Set fconf as experimental feature" into integrationSandrine Bailleux
2020-04-16Merge "docs: Update SMCCC doc, other changes for release" into integrationMark Dykes
2020-04-16Merge "docs: Updating Change log for v2.3 Release" into integrationMark Dykes
2020-04-16doc: Set fconf as experimental featureLouis Mayencourt
Following the messages on the mailing list regarding the possible issue around reading DTB's information, we decided to flag the fconf feature as experimental. A uniform approach should be used to handle properties miss and DTB validation. Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: Ib3c86e81fb2e89452c593f68d825d3d8f505e1fb
2020-04-16docs: Updating Change log for v2.3 Releaselaurenw-arm
Updating the change log for the v2.3 release and the upcoming change log template for v2.4 release. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ice875d3c93227069738a429d4b945512af8470e9
2020-04-16docs: Update SMCCC doc, other changes for releaselaurenw-arm
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ie842d6a9919776de151a4e9304f870aede07c47a
2020-04-16Merge "docs: Fixes and updates for the v2.3 release" into integrationSandrine Bailleux
2020-04-16Merge "docs: Updating Release information for v2.4" into integrationjoanna.farley
2020-04-15docs: Fixes and updates for the v2.3 releaselaurenw-arm
A small set of misc changes to ensure correctness before the v2.3 release. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I5b4e35b3b46616df0453cecff61f5a414951cd62
2020-04-15docs: Updating Release information for v2.4laurenw-arm
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I5a7ae778999295f3453b7ab0bfc26351e545fb8f
2020-04-15Merge "plat/arm/sgi: update mmap and xlat count" into integrationv2.3-rc1Manish Pandey
2020-04-15Merge "Fix Broadcom Stingray platform documentation" into integrationSandrine Bailleux
2020-04-15Fix Broadcom Stingray platform documentationSandrine Bailleux
- Include the platform documentation in the table of contents. - Add a title for the document. Without this, the platform documentation was listed under a 'Description' title on page https://trustedfirmware-a.readthedocs.io/en/latest/plat/index.html - Change TF-A git repository URL to point to tf.org (rather than the deprecated read-only mirror on Github). - Fix the restructuredText syntax for the FIP command line. It was not displayed at all on the rendered version. Change-Id: I7a0f062bcf8e0dfc65e8f8bdd6775c497a47e619 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-04-14plat/arm/sgi: update mmap and xlat countAditya Angadi
A single chip platform requires five mmap entries and a corresponding number of translation tables. For every additional chip in the system, three additional mmap entries are required to map the shared SRAM and the IO regions. A corresponding number of additional translation tables are required as well. Change-Id: I1332a1305f2af62181387cf36954f6fb0e6f11ed Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
2020-04-14Merge "stingray: fix coverity reported issues on brcm platform" into integrationSandrine Bailleux
2020-04-13stingray: fix coverity reported issues on brcm platformSheetal Tigadoli
fix coverity reported issues 1. uninitialized var, 2. check for negative val on unsigned variable Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> Change-Id: I28b7517135ba6c1ba0df04f0c73189cf84ba89e6
2020-04-09Merge "arm_fpga: Remove bogus timer initialisation" into integrationSandrine Bailleux
2020-04-09arm_fpga: Remove bogus timer initialisationAndre Przywara
The arm_fpga platform code contains an dubious line to initialise some timer. On closer inspection this turn out to be bogus, as this was only needed on some special (older) FPGA board, and is actually not needed on the current model. Also the base address was wrong anyways. Remove the code entirely. Change-Id: I02e71aea645051b5addb42d972d7a79f04b81106 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-04-07Merge "TF-A GICv3 driver: Change API for GICR_IPRIORITYR accessors" into ↵v2.3-rc0joanna.farley
integration
2020-04-07TF-A GICv3 driver: Change API for GICR_IPRIORITYR accessorsAlexei Fedorov
To support compatibility with previous GICv3 driver version this patch: - restores original API for gicr_read_ipriority() and gicr_wrtite_ipriority() functions; - adds accessor functions for GICR_XXX0,1 registers, e.g. GICR_IGROUPR0, GICR_ICFGR0, GICR_ICFGR1, etc. Change-Id: I796a312a61665ff384e3d9de2f4b3c60f700b43b Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-04-07Merge "plat/arm/rddaniel: enabled GICv4 extension" into integrationAlexei Fedorov
2020-04-07Merge "gic multichip: add support for clayton" into integrationAlexei Fedorov
2020-04-07plat/arm/rddaniel: enabled GICv4 extensionVijayenthiran Subramaniam
RD-Daniel uses GIC-Clayton as its interrupt controller which is an implementation of GICv4.1 architecture. Hence for RD-Daniel, enable GICv4 extension support. Change-Id: I45ae8c82376f8fe8fc0666306822ae2db74e71b8 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2020-04-07gic multichip: add support for claytonVijayenthiran Subramaniam
GIC-Clayton supports multichip operation mode which allows it to connect upto 16 other GIC-Clayton instances. GIC-Clayton's multichip programming and operation remains same as GIC-600 with a minor change in the SPI_BLOCKS and SPI_BLOCK_MIN shifts to accommodate additional SPI ranges. So identify if the GIC v4 extension is enabled by the platform makefile and appropriately select the SPI_BLOCKS and SPI_BLOCK_MIN shifts. Change-Id: I95fd80ef16af6c7ca09e2335539187b133052d41 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2020-04-07Merge changes from topics "af/fvp_gicv4", "af/gicv4", "af/gic_extended" into ↵Olivier Deprez
integration * changes: FVP: Add support for GICv4 extension TF-A: Add GICv4 extension for GIC driver TF-A GICv3 driver: Add extended PPI and SPI range
2020-04-07FVP: Add support for GICv4 extensionAlexei Fedorov
This patch adds support for GICv4 extension for FVP platform. Change-Id: Ia389b61266af669b1ca9b999a8b76476cab214f4 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-04-07TF-A: Add GICv4 extension for GIC driverAlexei Fedorov
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when set to 1. This option defaults to 0. Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-04-07Merge "coreboot: Add memory range parsing" into integrationSandrine Bailleux
2020-04-07coreboot: Add memory range parsingJulius Werner
This patch adds code to parse memory range information passed by coreboot, and a simple helper to test whether a specific address belongs to a range. This may be useful for coreboot-using platforms that need to know information about the system's memory layout (e.g. to check whether an address passed in via SMC targets valid DRAM). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3bea326c426db27d1a8b7d6e17418e4850e884b4
2020-04-07Increase maximum size of BL2 imageManish V Badarkhe
Increased the maximum size of BL2 image in order to accommodate the BL2 image when TF-A build with no compiler optimization for ARM platform. Note: As of now, "no compiler optimization" build works only when TRUSTED_BOOT_BOARD option is set to 0. This change is verified using below CI configuration: 1. juno-no-optimize-default:juno-linux.uboot 2. fvp-no-optimize-default,fvp-default:fvp-tftf-fip.tftf-aemv8a-debug Change-Id: I5932621237f8acd1b510682388f3ba78eae90ea4 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-04-07locks: bakery: use is_dcache_enabled() helperMasahiro Yamada
bakery_lock_normal.c uses the raw register accessor, read_sctlr(_el3) to check whether the dcache is enabled. Using is_dcache_enabled() is cleaner, and a good abstraction for the library code like this. A problem is is_dcache_enabled() is declared in the local header, lib/xlat_tables_v2/xlat_tables_private.h I searched for a good place to declare this helper. Moving it to arch_helpers.h, closed to cache operation helpers, looks good enough to me. I also changed the type of 'is_cached' to bool for consistency, and to avoid MISRA warnings. Change-Id: I9b016f67bc8eade25c316aa9c0db0fa4cd375b79 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-04-06Merge "stingray: Fix board configuration typo."Mark Dykes
2020-04-06TF-A GICv3 driver: Add extended PPI and SPI rangeAlexei Fedorov
This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to gicv3.mk makefile. This option defaults to 0 with no extended range support. Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-04-06stingray: Fix board configuration typo.Max Shvetsov
Default board configuration was set to bcm958742k which is not present in current codebase. This causes a default platform build to fail. Changing to bcm958742t. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Ie24f94ef0ef316ff56fe142df5de45d70ba93c28
2020-04-04Merge "Fix MISRA C issues in BL1/BL2/BL31" into integrationMark Dykes
2020-04-03Merge "xlat_tables_v2: use get_current_el_maybe_constant() in ↵Mark Dykes
is_dcache_enabled()" into integration
2020-04-03Fix MISRA C issues in BL1/BL2/BL31John Powell
Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code. Mainly issues like not using boolean expressions in conditionals, conflicting variable names, ignoring return values without (void), adding explicit casts, etc. Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a Signed-off-by: John Powell <john.powell@arm.com>
2020-04-03Merge "arm_fpga: adapt to new way of including gicv3 files" into integrationAlexei Fedorov
2020-04-03arm_fpga: adapt to new way of including gicv3 filesManish Pandey
with commit a6ea06f5, the way platform includes gicv3 files has been modified, this patch adapts to new method of including gicv3 files for arm_fpga platform. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic5ccae842b39b7db06d4f23c5738b174c42edf63
2020-04-03Merge "xlat lib v2: Add support to pass shareability attribute for normal ↵Manish Pandey
memory region" into integration
2020-04-03Merge changes from topic "brcm_initial_support" into integrationManish Pandey
* changes: doc: brcm: Add documentation file for brcm stingray platform drivers: Add SPI Nor flash support drivers: Add iproc spi driver drivers: Add emmc driver for Broadcom platforms Add BL31 support for Broadcom stingray platform Add BL2 support for Broadcom stingray platform Add bl31 support common across Broadcom platforms Add bl2 setup code common across Broadcom platforms drivers: Add support to retrieve plat_toc_flags
2020-04-03xlat lib v2: Add support to pass shareability attribute for normal memory regionPramod Kumar
Present framework restricts platform to pass desired shareability attribute for normal memory region mapped in MMU. it defaults to inner shareability. There are platforms where memories (like SRAM) are not placed at snoopable region in advaned interconnect like CCN/CMN hence snoopable transaction is not possible to these memory. Though These memories could be mapped in MMU as MT_NON_CACHEABLE, data caches benefits won't be available. If these memories are mapped as cacheable with non-shareable attribute, when only one core is running like at boot time, MMU data cached could be used for faster execution. Hence adding support to pass the shareability attribute for memory regions. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754
2020-04-03doc: brcm: Add documentation file for brcm stingray platformSheetal Tigadoli
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> Change-Id: I5e2c1220e9694d6ba771cc90daa0e70e967eebe6
2020-04-03drivers: Add SPI Nor flash supportSheetal Tigadoli
Add SPI Nor flash support Change-Id: I0cde3fdb4dcad5bcaf445b3bb48e279332bd28af Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>