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2020-11-16[wip] docs: Update changelog for v2.4 releasetopics/v2.4-changelogChris Kay
Change-Id: I67c9db2fc6d4b83fec2d001745b9305102d4a2ae Signed-off-by: Chris Kay <chris.kay@arm.com>
2020-10-26Merge "SPMC: adjust device region for first secure partition" into integrationOlivier Deprez
2020-10-24Merge "docs: marvell: update ddr3 build instructions" into integrationVarun Wadekar
2020-10-24Merge changes I5ae9d08b,I5cbbd7eb,Idb389223 into integrationVarun Wadekar
* changes: plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k plat: marvell: armada: Fix including plat/marvell/marvell.mk file plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it
2020-10-22Merge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integrationManish Pandey
2020-10-22SPMC: adjust device region for first secure partitionOlivier Deprez
For the first partition, mark first 2GB as device memory excluding the Trusted DRAM region reserved for the SPMC. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3ff110b3facf5b6d41ac2519ff6ca5e30a0a502b
2020-10-21Merge changes from topic "tc0_sel2_spmc" into integrationManish Pandey
* changes: plat: tc0: Configure TZC with secure world regions plat: tc0: Enable SPMC execution at S-EL2 plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled plat: tc0: Disable SPE
2020-10-21Merge changes from topic "tc0_sel2_spmc" into integrationManish Pandey
* changes: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context lib: el3_runtime: Conditionally save/restore EL2 NEVE registers lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context
2020-10-21plat/qemu_sbsa: Remove cortex_a53 and aem_genericTomas Pilar
The qemu_sbsa platform uses 42bit address size but the cortex-a53 only supports 40bit addressing, the cpu is incompatible with the platform. The aem_generic is also not used with qemu_sbsa, in fact, the platform currently only properly supports the cortex-a57 cpu. Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14 Signed-off-by: Tomas Pilar <tomas@nuviateam.com>
2020-10-21plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8kPali Rohár
Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6
2020-10-20Merge "docs: code review guidelines" into integrationManish Pandey
2020-10-20plat: tc0: Configure TZC with secure world regionsUsama Arif
This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20plat: tc0: Enable SPMC execution at S-EL2Arunachalam Ganapathy
This patch enables SPMC execution at S-EL2 by adding below changes - Map TC0_MAP_TZC_DRAM1 for loading SPMC - Add details of cactus test secure partitions - Adds tc0 spmc manifest file with details on secure partitions - Inlcude TOS_FW_CONFIG when SPM is spmd - Increases bl2 image size SPMC at S-EL2 is only enabled when build with SPD=spmd. Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20plat: tc0: Add TZC DRAM1 region for SPMC and trusted OSArunachalam Ganapathy
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1 - Add TC0_NS_DRAM1 base and mapping - Reserve memory region in tc0.dts Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabledArunachalam Ganapathy
To support platforms without Trusted DRAM this patch defines PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or DRAM region behind TZC. Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20plat: tc0: Disable SPEArunachalam Ganapathy
Statistical Profiling Extension is not supported by Matterhorn core Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20lib: el3_runtime: Fix SPE system registers in el2_sysregs_contextArunachalam Ganapathy
Include EL2 registers related to SPE in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20lib: el3_runtime: Conditionally save/restore EL2 NEVE registersArunachalam Ganapathy
Include EL2 registers related to Nested Virtualization in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_contextArunachalam Ganapathy
AArch64-only platforms do not implement AArch32 at EL1 and higher ELs. In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0. So don't save/restore aarch32 system registers in el2_sysregs_context save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0. Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-19plat: marvell: armada: Fix including plat/marvell/marvell.mk filePali Rohár
Include file plat/marvell/marvell.mk for platform A3700 was included two times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and second time from common file plat/marvell/armada/common/marvell_common.mk. It caused following warning every time was make called: plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean' plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean' Change in this commit removes inclusion of plat/marvell/marvell.mk file in common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform needs this include file, add it also into a80x0 platform specific include file lat/marvell/armada/a8k/common/a8k_common.mk. Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL are already defined, but it defines MARVELL_SECURE_BOOT variable which is needed by plat/marvell/armada/a3k/common/a3700_common.mk. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa
2020-10-19Merge "fdts: add missing hash node in STM32MP157C-ED1 board DT" into integrationAlexei Fedorov
2020-10-18Merge "Increase type widths to satisfy width requirements" into integrationJoanna Farley
2020-10-16Merge changes Iba51bff1,I3f563cff into integrationMadhukar Pappireddy
* changes: plat:qti Mandate SMC implementaion and bug fix Update in coreboot_get_memory_type API to include size as well
2020-10-16Merge "docs: Remove deprecated information" into integrationMark Dykes
2020-10-16Merge "docs: Update Release information for v2.5" into integrationMark Dykes
2020-10-16Merge "docs: Update code freeze and release target date for v2.4" into ↵Mark Dykes
integration
2020-10-16docs: Remove deprecated informationManish V Badarkhe
There are no references to AARCH32, AARCH64 and __ASSEMBLY__ macros in the TF-A code hence removed the deprecated information mentioning about these macros in the document. Change-Id: I472ab985ca2e4173bae23ff7b4465a9b60bc82eb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-10-16docs: Update Release information for v2.5Manish V Badarkhe
Updated tentative code freeze and release target date for v2.5 release. Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-10-16docs: Update code freeze and release target date for v2.4Manish V Badarkhe
Updated code freeze and release information date for v2.4 release. Change-Id: I76d5d04d0ee062a350f6a693eb04c29017d8b2e0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-10-15Merge changes I0005959b,I2ea59edb into integrationManish Pandey
* changes: bl32: add an assert on BL32_SIZE in sp_min.ld.S bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S
2020-10-16plat:qti Mandate SMC implementaion and bug fixSaurabh Gorecha
implementation of SMC call SMCCC_ARCH_SOC_ID adding debugging logs in mem assign call. Checking range of param in mem_assign call is from CB_MEM_RAM or CB_MEM_RESERVED. Change-Id: Iba51bff154df01e02dcb7715582ffaff7beba26e Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
2020-10-16Update in coreboot_get_memory_type API to include size as wellSaurabh Gorecha
Change-Id: I3f563cffd58b0591b433c85c0ff6b71e486eb2c8 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
2020-10-15plat: marvell: armada: a3k: When WTP is empty do not define variables and ↵Pali Rohár
targets which depends on it Some of targets (e.g. mrvl_flash) depends on WTP build option. Other targets (e.g. fip) can be build also without WTP build option as they do not depend on it. This change put all A3720 variables and targets which depends on WTP into conditional if-endif section, so they are not defined when user has not supplied WTP build option. Target mrvl_flash is defined also when WTP was not specified and in this case it just print error message to help user. Variables which do not depend on WTP are moved to the top of a3700_common.mk file. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Idb3892233586a0afca3e0e6564279641d2e4b960
2020-10-14Merge "Don't return error information from console_flush" into integrationMark Dykes
2020-10-14Merge "stm32mp1: use %u in NOTICE message for board info" into integrationAlexei Fedorov
2020-10-13fdts: add missing hash node in STM32MP157C-ED1 board DTYann Gautier
Without this node, the board fails to boot and panics in the function stm32mp_init_auth(). Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87e2 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-10-13stm32mp1: use %u in NOTICE message for board infoYann Gautier
The board information values, read in an OTP are never negative, %u is then used instead of %d. Change-Id: I3bc22401fb4d54666ddf56411f75b79aca738492 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-10-13Merge changes from topic "stm32mp1_plat_updates" into integrationMadhukar Pappireddy
* changes: docs: update STM32MP1 with versions details stm32mp1: get peripheral base address from a define stm32mp1: add finished good variant in board identifier
2020-10-13Merge "stm32mp1: add asserts in get_cpu_package() and get_part_number()" ↵Alexei Fedorov
into integration
2020-10-13Merge "stm32mp1: add support for new SoC profiles" into integrationAlexei Fedorov
2020-10-13Merge "stm32mp1: support of STM32MP15x Rev.Z" into integrationAlexei Fedorov
2020-10-13Merge changes from topic "st/fmc2" into integrationManish Pandey
* changes: drivers: stm32_fmc2_nand: fix boundary check for chip select drivers: stm32_fmc2_nand: move to new bindings
2020-10-13docs: update STM32MP1 with versions detailsYann Gautier
After introducing the new STM32MP1 SoC versions in patch [1], the document describing STM32MP1 platform is updated with the information given in the patch commit message. [1]: stm32mp1: add support for new SoC profiles Change-Id: I6d7ce1a3c29678ddac78a6685f5d5daf28c3c3a1 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-10-13stm32mp1: add asserts in get_cpu_package() and get_part_number()Nicolas Le Bayon
Change-Id: I2b702698d6be93da5ac86da1cbc98b3838315a5a Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-10-13stm32mp1: add support for new SoC profilesLionel Debieve
Update to support new part numbers. Add new STM32 MPUs Part = STM32MP151F, STM32MP153F, STM32MP157F, STM32MP151D, STM32MP153D, STM32MP157D The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz Each line comes with a security option (cryptography & secure boot) & a Cortex-A frequency option : - A Basic + Cortex-A7 @ 650 MHz - C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - D Basic + Cortex-A7 @ 800 MHz - F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz Remove useless variable in stm32mp_is_single_core(). Change-Id: Id30c836af986c6340c91efa8a7ae9480a2827089 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-10-13stm32mp1: support of STM32MP15x Rev.ZLionel Debieve
Add a new revision of STM32MP15x CPU (Rev.Z). Change-Id: I227dd6d9b3fcc43270015cfb21f60aeb0a8ab658 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-10-13stm32mp1: get peripheral base address from a defineYann Gautier
Retrieve peripheral base address from a define instead of parsing the device tree. The goal is to improve execution time. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b
2020-10-13stm32mp1: add finished good variant in board identifierPatrick Delaunay
Update the board info with the new coding including the finished good variant: Board: MBxxxx Var<CPN>.<FG> Rev.<Rev>-<BOM> The OTP 59 coding is: bit [31:16] (hex) => MBxxxx bit [15:12] (dec) => Variant CPN (1....15) bit [11:8] (dec) => Revision board (index with A = 1, Z = 26) bit [7:4] (dec) => Variant FG : finished good (NEW) bit [3:0] (dec) => BOM (01, .... 255) Change-Id: I4fbc0c84596419d1bc30d166311444ece1d9123f Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-10-12Merge "Fix casting bug in gicv2_main.c" into integrationMadhukar Pappireddy
2020-10-12Increase type widths to satisfy width requirementsJimmy Brisson
Usually, C has no problem up-converting types to larger bit sizes. MISRA rule 10.7 requires that you not do this, or be very explicit about this. This resolves the following required rule: bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None> The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U | 0x3c0U" (32 bits) is less that the right hand operand "18446744073709547519ULL" (64 bits). This also resolves MISRA defects such as: bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)] In the expression "3U << 20", shifting more than 7 bits, the number of bits in the essential type of the left expression, "3U", is not allowed. Further, MISRA requires that all shifts don't overflow. The definition of PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues. This fixes the violation by changing the definition to 1UL << 12. Since this uses 32bits, it should not create any issues for aarch32. This patch also contains a fix for a build failure in the sun50i_a64 platform. Specifically, these misra fixes removed a single and instruction, 92407e73 and x19, x19, #0xffffffff from the cm_setup_context function caused a relocation in psci_cpus_on_start to require a linker-generated stub. This increased the size of the .text section and caused an alignment later on to go over a page boundary and round up to the end of RAM before placing the .data section. This sectionn is of non-zero size and therefore causes a link error. The fix included in this reorders the functions during link time without changing their ording with respect to alignment. Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>