aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2 daysMerge "fix(drivers/tzc400): never disable filter 0" into integrationintegrationJoanna Farley
3 daysMerge changes from topic "TrcDbgExt" into integrationManish Pandey
* changes: feat(plat/fvp): enable trace extension features by default feat(trf): enable trace filter control register access from lower NS EL feat(trf): initialize trap settings of trace filter control registers access feat(sys_reg_trace): enable trace system registers access from lower NS ELs feat(sys_reg_trace): initialize trap settings of trace system registers access feat(trbe): enable access to trace buffer control registers from lower NS EL feat(trbe): initialize trap settings of trace buffer control registers access
5 daysMerge changes Iedc19d8f,Ic5fc78c9 into integrationHEADmasterMadhukar Pappireddy
* changes: feat(plat/mediatek/mt8195): add EMI MPU basic drivers feat(plat/mediatek/mt8195): add vcore-dvfs support
5 daysMerge "refactor(tc): use internal trusted storage" into integrationOlivier Deprez
5 daysrefactor(tc): use internal trusted storageDavidson K
Trusted Services had removed secure storage and added two new trusted services - Protected Storage and Internal Trusted Storage. Hence we are removing secure storage and adding support for the internal trusted storage. And enable external SP images in BL2 config for TC, so that we do not have to modify this file whenever the list of SPs changes. It is already implemented for fvp in the below commit. commit 33993a3737737a03ee5a9d386d0a027bdc947c9c Author: Balint Dobszay <balint.dobszay@arm.com> Date: Fri Mar 26 15:19:11 2021 +0100 feat(fvp): enable external SP images in BL2 config Change-Id: I3e0a0973df3644413ca5c3a32f36d44c8efd49c7 Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
5 daysfix(drivers/tzc400): never disable filter 0Stas Sergeev
Disabling filter 0 causes inability to access DRAM. An attempt leads to an abort. ARM manual disallows to disable filter 0, but if we do that from SRAM, nothing bad happens. This patch prevents disabling of a filter 0, allowing to reconfigure other filters from DRAM. Note: this patch doesn't change the logic after reset. It is only needed in case someone wants to reconfigure the previously configured TZASC. Change-Id: I196a0cb110a89afbde97f64a94df3101f28708a4 Signed-off-by: stsp@users.sourceforge.net
5 daysMerge "docs(ff-a): fix specification naming" into integrationManish Pandey
5 daysMerge "docs(ff-a): managed exit parameter separation" into integrationManish Pandey
6 daysfeat(plat/mediatek/mt8195): add EMI MPU basic driversPenny Jan
EMI MPU stands for external memory interface memory protect unit. MT8195 supports 32 regions and 16 domains. We add basic drivers currently, and will add more setting for EMI MPU in next patch. Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd Signed-off-by: Penny Jan <penny.jan@mediatek.com>
6 daysMerge "fix(plat/synquacer): update scmi power domain off handling" into ↵Madhukar Pappireddy
integration
7 daysfix(plat/synquacer): update scmi power domain off handlingMasahisa Kojima
In the SCMI power domain off handling, configure GIC to prevent interrupt toward to the core to be turned off, and configure CCN to disable coherency when the cluster is turned off. The same operation is done in SCPI power domain off processing. This commit adds the missing operation in SCMI power domain off handling. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781
7 daysfeat(plat/mediatek/mt8195): add vcore-dvfs supportDawei Chien
Add DVFSRC init flow. Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358 Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
7 daysMerge "fix(plat/qti/sc7180): qti smc addition" into integrationJulius Werner
10 daysMerge changes from topic "gic-700-auto" into integrationAndré Przywara
* changes: feat(arm_fpga): support GICv4 images feat(gicv3): detect GICv4 feature at runtime feat(gicv3): multichip: detect GIC-700 at runtime refactor(gic): move GIC IIDR numbers refactor(gicv3): rename GIC Clayton to GIC-700
11 daysMerge "fix(plat/marvell/a3k): enable workaround for erratum 1530924" into ↵Madhukar Pappireddy
integration
11 daysMerge "fix(docs-contributing.rst): fix formatting for code snippet" into ↵Madhukar Pappireddy
integration
11 daysMerge "docs(stm32mp1): update doc for FIP/FCONF" into integrationMark Dykes
11 daysMerge "feat(plat/st): add a new DDR firewall management" into integrationMark Dykes
11 daysMerge "feat(tzc400): update filters by region" into integrationMark Dykes
11 daysMerge "feat(fdts): add firewall regions into STM32MP1 DT" into integrationMark Dykes
11 daysMerge changes from topic "st_fip_fconf" into integrationMark Dykes
* changes: refactor(plat/st): use TZC400 bindings feat(dt-bindings): add STM32MP1 TZC400 bindings
11 daysMerge changes from topic "st_fip_fconf" into integrationMark Dykes
* changes: feat(plat/st): manage io_policies with FCONF feat(fdts): add IO policies for STM32MP1
11 daysMerge changes from topic "st_fip_fconf" into integrationMark Dykes
* changes: feat(plat/st): use FCONF to configure platform feat(fdts): add STM32MP1 fw-config DT files
11 daysMerge "feat(plat/st): improve FIP image loading from MMC" into integrationMark Dykes
11 daysMerge changes from topic "st_fip_fconf" into integrationMark Dykes
* changes: feat(plat/st): use FIP to load images refactor(plat/st): updates for OP-TEE feat(lib/optee): introduce optee_header_is_valid()
11 daysfix(docs-contributing.rst): fix formatting for code snippetJayanth Dodderi Chidanand
This patch will fix the formatting errors concerning code snippet, lines 245 and 256 respectively. The code snippet is updated to 'shell' to lex it appropriately. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I53aefd81da350b6511e7a97b5fee7b0d6f9dde2d
12 daysMerge "fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode" into ↵Madhukar Pappireddy
integration
12 daysfix(plat/marvell/a3k): enable workaround for erratum 1530924Marek Behún
Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53 revisions from r0p0 to r0p4. Enable the workaround for this erratum. Signed-off-by: Marek Behún <marek.behun@nic.cz> Change-Id: I753225040e49e956788d5617cd7ce76d5e6ea8e8
12 daysdocs(stm32mp1): update doc for FIP/FCONFYann Gautier
Describe the boot using FIP, and how to compile it. The STM32IMAGE boot chain is still available but it is not recommended. Update the build command lines, for FIP. The memory mapping is also updated. Change-Id: I2b1e0df5500b6213d33dc558b0e0da38340a4d79 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
12 daysfeat(plat/st): add a new DDR firewall managementLionel Debieve
Based on FCONF framework, define DDR firewall regions from firmware config file instead of static defines. Change-Id: I471e15410ca286d9079a86e3dc3474f66d37b5ab Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
12 daysfeat(tzc400): update filters by regionLionel Debieve
Add a new function that allows to enable or disabled filters on configured regions dynamically. This will avoid the need to reconfigure the entire attribute and just manage to enable/disable filters. Change-Id: If0937ca755bec6c45d3649718147108459682fff Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysMerge "docs(contribution-guidelines): add coverity build configuration ↵Madhukar Pappireddy
section" into integration
13 daysMerge changes from topic "advk-serror" into integrationMadhukar Pappireddy
* changes: fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default fix(plat/marvell/a3k): update information about PCIe abort hack
13 daysdocs(contribution-guidelines): add coverity build configuration sectionJayanth Dodderi Chidanand
Added a sub-section in the "Processes and Policies" chapter under Contributor's guide on how to add new build configurations when new source files are added to the TF-A repository. This will help the patch contributor to update their files to get analysed by Coverity Scan. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I71f410a061028f89bd0e984e48e61e5935616d71
13 daysfix(plat/qti/sc7180): qti smc additionSaurabh Gorecha
Adding QTI SIP SMC CALL to detect qti platform supporting ARM 64 SMC calls or not. Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Change-Id: I3231325a6ffe5aa69856dd25ac2c0a2004484e4b
13 daysMerge changes I0ae8a6ea,I0b4fc83e into integrationOlivier Deprez
* changes: feat(tc): Enable SVE for both secure and non-secure world feat(tc): populate HW_CONFIG in BL31
13 daysfeat(tc): Enable SVE for both secure and non-secure worldUsama Arif
Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I0ae8a6ea3245373a17af76c9b7dc3f38f3711091
13 daysfeat(tc): populate HW_CONFIG in BL31Usama Arif
BL2 passes FW_CONFIG to BL31 which contains information about different DTBs present. BL31 then uses FW_CONFIG to get the base address of HW_CONFIG and populate fconf. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616
13 daysMerge "docs: nxp soc-lx2160a based platforms" into integrationMadhukar Pappireddy
13 daysfeat(fdts): add firewall regions into STM32MP1 DTYann Gautier
Add the corresponding firewall memory regions into fw-config device tree. Change-Id: Ie39b0339f3c42b3dd756354138a872500c64f84c Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysrefactor(plat/st): use TZC400 bindingsYann Gautier
This avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR. And remove the previous TZC400 definitions from stm32mp1_def.h. Change-Id: I6c72c2a18731f69d855fbce8ce822a21da9364fa Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysfeat(plat/st): manage io_policies with FCONFYann Gautier
Introduced IO policies management through the trusted boot firmware config device tree for UUID references. Change-Id: Ibeeabede51b0514ebba26dbbdae587363b2aa0a7 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysfeat(plat/st): use FCONF to configure platformYann Gautier
Add required code to support FCONF on STM32MP1 platform. The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2. It will be used to configure the addresses where to load other binaries. BL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min), so optee_utils.c is always compiled, and some OP-TEE flags are removed. Change-Id: Id957b49b0117864136250bfc416664f815043ada Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysfeat(plat/st): improve FIP image loading from MMCYann Gautier
Instead of using a scratch buffer of 512 bytes, we can directly use the image address and max size. The mmc_block_dev_spec struct info is then overwritten for each image with this info, except FW_CONFIG and GPT table which will still use the scratch buffer. This allows using multiple blocks read on MMC, and so improves the boot time. A cache invalidate is required for the remaining data not used from the first and last blocks read. It is not required for FW_CONFIG_ID, as it is in scratch buffer in SYSRAM, and also because bl_mem_params struct is overwritten in this case. This should also not be done if the image is not found (OP-TEE extra binaries when using SP_min). Change-Id: If3ecfdfe35bb9db66284036ca49c4bd1be4fd121 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysfeat(plat/st): use FIP to load imagesYann Gautier
BL2 still uses the STM32 header binary format to be loaded from ROM code. BL32 and BL33 and their respective device tree files are now put together in a FIP file. One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are in charge of removing useless nodes for a given BL. This is done because BL2 and BL32 share the same device tree files base. The previous way of booting is still available, the compilation flag STM32MP_USE_STM32IMAGE has to be set to 1 in the make command. Some files are duplicated and their names modified with _stm32_ to avoid too much switches in the code. Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysfeat(dt-bindings): add STM32MP1 TZC400 bindingsLionel Debieve
Add bindings that will be used to define DDR regions and their access rights. Change-Id: I745a7e580ef2b9e251d53db12c5a0a86dfe34463 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysfeat(fdts): add IO policies for STM32MP1Lionel Debieve
Add the UUID into the io policies node that are retrieved by BL2 using stm32mp_fconf_io.c populate function. Change-Id: I595d5a41a1e0a27fcc02ea2ab5495d9dbf0e6773 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
13 daysfeat(fdts): add STM32MP1 fw-config DT filesYann Gautier
Create all boards fw-config DT files. They all include a generic stm32mp15-fw-config.dtsi. Change-Id: Ib9ac8a59e93e01365001b0d11fee41f7c507c08e Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
14 daysMerge "feat(gic600ae): introduce support for Fault Management Unit" into ↵Joanna Farley
integration
2021-09-06docs(ff-a): fix specification namingOlivier Deprez
Rename the FF-A specification to: Arm Firmware Framework for Arm A-profile Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I4f9d29409d048e7a49832b95d39d2583c1fb5792