diff options
Diffstat (limited to 'plat/xilinx/zynqmp/plat_psci.c')
-rw-r--r-- | plat/xilinx/zynqmp/plat_psci.c | 73 |
1 files changed, 40 insertions, 33 deletions
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c index f579f795f2..c6c6c4baa0 100644 --- a/plat/xilinx/zynqmp/plat_psci.c +++ b/plat/xilinx/zynqmp/plat_psci.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,12 +17,12 @@ #include <plat/common/platform.h> #include <plat_private.h> -#include "pm_api_sys.h" #include "pm_client.h" +#include "zynqmp_pm_api_sys.h" -uintptr_t zynqmp_sec_entry; +static uintptr_t zynqmp_sec_entry; -void zynqmp_cpu_standby(plat_local_state_t cpu_state) +static void zynqmp_cpu_standby(plat_local_state_t cpu_state) { VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); @@ -29,17 +30,26 @@ void zynqmp_cpu_standby(plat_local_state_t cpu_state) wfi(); } -static int zynqmp_pwr_domain_on(u_register_t mpidr) +static int32_t zynqmp_pwr_domain_on(u_register_t mpidr) { - unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); + uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); const struct pm_proc *proc; + uint32_t buff[3]; + enum pm_ret_status ret; VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); - if (cpu_id == -1) + if (cpu_id == -1) { return PSCI_E_INTERN_FAIL; - + } proc = pm_get_proc(cpu_id); + + /* Check the APU proc status before wakeup */ + ret = pm_get_node_status(proc->node_id, buff); + if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) { + return PSCI_E_INTERN_FAIL; + } + /* Clear power down request */ pm_client_wakeup(proc); @@ -51,12 +61,13 @@ static int zynqmp_pwr_domain_on(u_register_t mpidr) static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) { - unsigned int cpu_id = plat_my_core_pos(); + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); + } /* Prevent interrupts from spuriously waking up this cpu */ gicv2_cpuif_disable(); @@ -74,8 +85,8 @@ static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) { - unsigned int state; - unsigned int cpu_id = plat_my_core_pos(); + uint32_t state; + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) @@ -97,21 +108,23 @@ static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) { - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); + } plat_arm_gic_pcpu_init(); gicv2_cpuif_enable(); } static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) { - unsigned int cpu_id = plat_my_core_pos(); + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); + } /* Clear the APU power control register for this cpu */ pm_client_wakeup(proc); @@ -140,8 +153,9 @@ static void __dead2 zynqmp_system_off(void) pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN, pm_get_shutdown_scope()); - while (1) + while (1) { wfi(); + } } static void __dead2 zynqmp_system_reset(void) @@ -153,41 +167,35 @@ static void __dead2 zynqmp_system_reset(void) pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, pm_get_shutdown_scope()); - while (1) + while (1) { wfi(); + } } -int zynqmp_validate_power_state(unsigned int power_state, +static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) { VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); - int pstate = psci_get_pstate_type(power_state); + uint32_t pstate = psci_get_pstate_type(power_state); assert(req_state); /* Sanity check the requested state */ - if (pstate == PSTATE_TYPE_STANDBY) + if (pstate == PSTATE_TYPE_STANDBY) { req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; - else + } else { req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; - + } /* We expect the 'state id' to be zero */ - if (psci_get_pstate_id(power_state)) + if (psci_get_pstate_id(power_state)) { return PSCI_E_INVALID_PARAMS; + } return PSCI_E_SUCCESS; } -int zynqmp_validate_ns_entrypoint(unsigned long ns_entrypoint) -{ - VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint); - - /* FIXME: Actually validate */ - return PSCI_E_SUCCESS; -} - -void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) +static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) { req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; @@ -206,7 +214,6 @@ static const struct plat_psci_ops zynqmp_psci_ops = { .system_off = zynqmp_system_off, .system_reset = zynqmp_system_reset, .validate_power_state = zynqmp_validate_power_state, - .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, }; |