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Diffstat (limited to 'plat/renesas/rzg/bl2_plat_setup.c')
-rw-r--r--plat/renesas/rzg/bl2_plat_setup.c53
1 files changed, 53 insertions, 0 deletions
diff --git a/plat/renesas/rzg/bl2_plat_setup.c b/plat/renesas/rzg/bl2_plat_setup.c
index 8851796ca5..ccc2562ee5 100644
--- a/plat/renesas/rzg/bl2_plat_setup.c
+++ b/plat/renesas/rzg/bl2_plat_setup.c
@@ -84,12 +84,20 @@ static void bl2_init_generic_timer(void);
#elif RCAR_LSI == RZ_G2N
#define TARGET_PRODUCT PRR_PRODUCT_M3N
#define TARGET_NAME "RZ/G2N"
+#elif RCAR_LSI == RZ_G2E
+#define TARGET_PRODUCT PRR_PRODUCT_E3
+#define TARGET_NAME "RZ/G2E"
#elif RCAR_LSI == RCAR_AUTO
#define TARGET_NAME "RZ/G2M"
#endif /* RCAR_LSI == RZ_G2M */
+#if (RCAR_LSI == RZ_G2E)
+#define GPIO_INDT (GPIO_INDT6)
+#define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U << 13U)
+#else
#define GPIO_INDT (GPIO_INDT1)
#define GPIO_BKUP_TRG_SHIFT (1U << 8U)
+#endif /* RCAR_LSI == RZ_G2E */
CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
< (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
@@ -438,6 +446,10 @@ static void bl2_populate_compatible_string(void *dt)
ret = fdt_setprop_string(dt, 0, "compatible",
"hoperun,hihope-rzg2n");
break;
+ case BOARD_EK874_RZ_G2E:
+ ret = fdt_setprop_string(dt, 0, "compatible",
+ "si-linux,cat874");
+ break;
default:
NOTICE("BL2: Cannot set compatible string, board unsupported\n");
panic();
@@ -463,6 +475,10 @@ static void bl2_populate_compatible_string(void *dt)
ret = fdt_appendprop_string(dt, 0, "compatible",
"renesas,r8a774b1");
break;
+ case PRR_PRODUCT_E3:
+ ret = fdt_appendprop_string(dt, 0, "compatible",
+ "renesas,r8a774c0");
+ break;
default:
NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
panic();
@@ -606,6 +622,18 @@ static void bl2_advertise_dram_size(uint32_t product)
/* 4GB(4GBx1) */
dram_config[1] = 0x100000000ULL;
break;
+ case PRR_PRODUCT_E3:
+#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
+ /* 1GB(512MBx2) */
+ dram_config[1] = 0x40000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
+ /* 2GB(512MBx4) */
+ dram_config[1] = 0x80000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
+ /* 4GB(1GBx4) */
+ dram_config[1] = 0x100000000ULL;
+#endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
+ break;
default:
NOTICE("BL2: Detected invalid DRAM entries\n");
break;
@@ -624,6 +652,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
const char *unknown = "unknown";
const char *cpu_ca57 = "CA57";
const char *cpu_ca53 = "CA53";
+ const char *product_g2e = "G2E";
const char *product_g2h = "G2H";
const char *product_g2m = "G2M";
const char *product_g2n = "G2N";
@@ -632,7 +661,14 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
const char *boot_qspi80 = "QSPI Flash(80MHz)";
const char *boot_emmc25x1 = "eMMC(25MHz x1)";
const char *boot_emmc50x8 = "eMMC(50MHz x8)";
+#if (RCAR_LSI == RZ_G2E)
+ uint32_t sscg;
+ const char *sscg_on = "PLL1 SSCG Clock select";
+ const char *sscg_off = "PLL1 nonSSCG Clock select";
+ const char *boot_hyper160 = "HyperFlash(150MHz)";
+#else
const char *boot_hyper160 = "HyperFlash(160MHz)";
+#endif /* RCAR_LSI == RZ_G2E */
#if RZG_LCS_STATE_DETECTION_ENABLE
uint32_t lcs;
const char *lcs_secure = "SE";
@@ -700,6 +736,9 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
case PRR_PRODUCT_M3N:
str = product_g2n;
break;
+ case PRR_PRODUCT_E3:
+ str = product_g2e;
+ break;
default:
str = unknown;
break;
@@ -721,12 +760,22 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor);
}
+#if (RCAR_LSI == RZ_G2E)
+ if (product == PRR_PRODUCT_E3) {
+ reg = mmio_read_32(RCAR_MODEMR);
+ sscg = reg & RCAR_SSCG_MASK;
+ str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
+ NOTICE("BL2: %s\n", str);
+ }
+#endif /* RCAR_LSI == RZ_G2E */
+
rzg_get_board_type(&type, &rev);
switch (type) {
case BOARD_HIHOPE_RZ_G2M:
case BOARD_HIHOPE_RZ_G2H:
case BOARD_HIHOPE_RZ_G2N:
+ case BOARD_EK874_RZ_G2E:
break;
default:
type = BOARD_UNKNOWN;
@@ -940,6 +989,9 @@ void bl2_platform_setup(void)
static void bl2_init_generic_timer(void)
{
+#if RCAR_LSI == RZ_G2E
+ uint32_t reg_cntfid = EXTAL_EBISU;
+#else
uint32_t reg_cntfid;
uint32_t modemr;
uint32_t modemr_pll;
@@ -955,6 +1007,7 @@ static void bl2_init_generic_timer(void)
/* Set frequency data in CNTFID0 */
reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
+#endif /* RCAR_LSI == RZ_G2E */
/* Update memory mapped and register based frequency */
write_cntfrq_el0((u_register_t)reg_cntfid);