diff options
Diffstat (limited to 'plat/renesas/common/include/rcar_def.h')
-rw-r--r-- | plat/renesas/common/include/rcar_def.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h index 6c5b295615..f1c255377b 100644 --- a/plat/renesas/common/include/rcar_def.h +++ b/plat/renesas/common/include/rcar_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,7 +31,7 @@ #define DRAM_LIMIT ULL(0x0000010000000000) #define DRAM1_BASE U(0x40000000) #define DRAM1_SIZE U(0x80000000) -#define DRAM1_NS_BASE (DRAM1_BASE + U(0x10000000)) +#define DRAM1_NS_BASE (DRAM1_BASE + U(0x08000000)) #define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE) #define DRAM_40BIT_BASE ULL(0x0400000000) #define DRAM_40BIT_SIZE ULL(0x0400000000) @@ -120,7 +120,6 @@ /* Timer control */ #define RCAR_CNTC_BASE U(0xE6080000) /* Reset */ -#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */ #define RCAR_MODEMR U(0xE6160060) /* Mode pin */ #define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */ #define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */ @@ -149,9 +148,13 @@ #define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */ #define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */ #define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */ +#define RCAR_SYSCEXTMASK U(0xE61802F8) /* External Request Mask */ + /* H3/H3-N, M3 v3.0, M3-N, E3 */ /* Product register */ #define RCAR_PRR U(0xFFF00044) #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ +#define RCAR_D3_CUT_VER10 U(0x00000000) /* D3 Ver.1.0 */ +#define RCAR_D3_CUT_VER11 U(0x00000010) /* D3 Ver.1.1 */ #define RCAR_MAJOR_MASK U(0x000000F0) #define RCAR_MINOR_MASK U(0x0000000F) #define PRR_PRODUCT_SHIFT U(8) |