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Diffstat (limited to 'plat/qemu/qemu/include/platform_def.h')
-rw-r--r--plat/qemu/qemu/include/platform_def.h177
1 files changed, 157 insertions, 20 deletions
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index fbcaa63a8f..4e0b50ad83 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,15 +23,14 @@
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
#else
-#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
/*
* Define the number of cores per cluster used in calculating core position.
* The cluster number is shifted by this value and added to the core ID,
* so its value represents log2(cores/cluster).
- * Default is 2**(2) = 4 cores per cluster.
+ * Default is 2**(4) = 16 cores per cluster.
*/
-#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2)
-
+#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(4)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER (U(1) << PLATFORM_CPU_PER_CLUSTER_SHIFT)
#define PLATFORM_CLUSTER_COUNT U(2)
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
@@ -80,11 +79,11 @@
#define SEC_ROM_BASE 0x00000000
#define SEC_ROM_SIZE 0x00020000
-#define NS_DRAM0_BASE 0x40000000
-#define NS_DRAM0_SIZE 0x3de00000
+#define NS_DRAM0_BASE ULL(0x40000000)
+#define NS_DRAM0_SIZE ULL(0xc0000000)
#define SEC_SRAM_BASE 0x0e000000
-#define SEC_SRAM_SIZE 0x00060000
+#define SEC_SRAM_SIZE 0x00100000
#define SEC_DRAM_BASE 0x0e100000
#define SEC_DRAM_SIZE 0x00f00000
@@ -118,6 +117,11 @@
#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
+#define TB_FW_CONFIG_BASE BL_RAM_BASE
+#define TB_FW_CONFIG_LIMIT (TB_FW_CONFIG_BASE + PAGE_SIZE)
+#define TOS_FW_CONFIG_BASE TB_FW_CONFIG_LIMIT
+#define TOS_FW_CONFIG_LIMIT (TOS_FW_CONFIG_BASE + PAGE_SIZE)
+
/*
* BL1 specific defines.
*
@@ -137,7 +141,7 @@
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
-#define BL2_BASE (BL31_BASE - 0x25000)
+#define BL2_BASE (BL31_BASE - 0x35000)
#define BL2_LIMIT BL31_BASE
/*
@@ -146,10 +150,18 @@
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth.
*/
-#define BL31_BASE (BL31_LIMIT - 0x20000)
-#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
+#define BL31_BASE (BL31_LIMIT - 0x60000)
+#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE - FW_HANDOFF_SIZE)
#define BL31_PROGBITS_LIMIT BL1_RW_BASE
+#if TRANSFER_LIST
+#define FW_HANDOFF_BASE BL31_LIMIT
+#define FW_HANDOFF_LIMIT (FW_HANDOFF_BASE + FW_HANDOFF_SIZE)
+#define FW_HANDOFF_SIZE 0x4000
+#else
+#define FW_HANDOFF_SIZE 0
+#endif
+
/*
* BL3-2 specific defines.
@@ -159,7 +171,8 @@
#define BL32_SRAM_BASE BL_RAM_BASE
#define BL32_SRAM_LIMIT BL31_BASE
#define BL32_DRAM_BASE SEC_DRAM_BASE
-#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
+#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
+ RME_GPT_DRAM_SIZE)
#define SEC_SRAM_ID 0
#define SEC_DRAM_ID 1
@@ -168,23 +181,27 @@
# define BL32_MEM_BASE BL_RAM_BASE
# define BL32_MEM_SIZE BL_RAM_SIZE
# define BL32_BASE BL32_SRAM_BASE
-# define BL32_LIMIT BL32_SRAM_LIMIT
+# define BL32_LIMIT (BL32_SRAM_LIMIT - FW_HANDOFF_SIZE)
#elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID
# define BL32_MEM_BASE SEC_DRAM_BASE
# define BL32_MEM_SIZE SEC_DRAM_SIZE
# define BL32_BASE BL32_DRAM_BASE
-# define BL32_LIMIT BL32_DRAM_LIMIT
+# define BL32_LIMIT (BL32_DRAM_LIMIT - FW_HANDOFF_SIZE)
#else
# error "Unsupported BL32_RAM_LOCATION_ID value"
#endif
+#if TRANSFER_LIST
+#define FW_NS_HANDOFF_BASE (NS_IMAGE_OFFSET - FW_HANDOFF_SIZE)
+#endif
+
#define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000)
#define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#define MAX_MMAP_REGIONS 11
-#define MAX_XLAT_TABLES 6
+#define MAX_MMAP_REGIONS (13 + MAX_MMAP_REGIONS_SPMC)
+#define MAX_XLAT_TABLES (6 + MAX_XLAT_TABLES_SPMC)
#define MAX_IO_DEVICES 4
#define MAX_IO_HANDLES 4
@@ -210,7 +227,7 @@
#define QEMU_FLASH1_SIZE 0x04000000
#define PLAT_QEMU_FIP_BASE 0x00040000
-#define PLAT_QEMU_FIP_MAX_SIZE 0x00400000
+#define PLAT_QEMU_FIP_MAX_SIZE (QEMU_FLASH0_SIZE - PLAT_QEMU_FIP_BASE)
#define DEVICE0_BASE 0x08000000
#define DEVICE0_SIZE 0x01000000
@@ -240,8 +257,7 @@
* interrupts.
*****************************************************************************/
#define PLATFORM_G1S_PROPS(grp) \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE), \
+ DESC_G1S_IRQ_SEC_SGI_0(grp) \
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
@@ -257,7 +273,19 @@
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_EDGE)
-#define PLATFORM_G0_PROPS(grp)
+#if SDEI_SUPPORT
+#define DESC_G0_IRQ_SEC_SGI(grp) \
+ INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
+ GIC_INTR_CFG_EDGE)
+#define DESC_G1S_IRQ_SEC_SGI_0(grp)
+#else
+#define DESC_G0_IRQ_SEC_SGI(grp)
+#define DESC_G1S_IRQ_SEC_SGI_0(grp) \
+ INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
+ GIC_INTR_CFG_EDGE),
+#endif
+
+#define PLATFORM_G0_PROPS(grp) DESC_G0_IRQ_SEC_SGI(grp)
/*
* DT related constants
@@ -266,8 +294,117 @@
#define PLAT_QEMU_DT_MAX_SIZE 0x100000
/*
+ * Platforms macros to support SDEI
+ */
+#define PLAT_PRI_BITS U(3)
+#define PLAT_SDEI_CRITICAL_PRI 0x60
+#define PLAT_SDEI_NORMAL_PRI 0x70
+#define PLAT_SDEI_SGI_PRIVATE QEMU_IRQ_SEC_SGI_0
+
+/*
* System counter
*/
#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
+/*
+ * Maximum size of Event Log buffer used in Measured Boot Event Log driver
+ */
+#define PLAT_EVENT_LOG_MAX_SIZE UL(0x400)
+
+#if SPMC_AT_EL3
+/*
+ * Number of Secure Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of
+ * supported secure partitions.
+ */
+#define SECURE_PARTITION_COUNT 1
+
+/*
+ * Number of Logical Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of
+ * supported logical partitions.
+ */
+#define MAX_EL3_LP_DESCS_COUNT 0
+
+/*
+ * Number of Normal World Partitions supported.
+ * SPMC at EL3, uses this count to configure the maximum number of
+ * supported normal world partitions.
+ */
+#define NS_PARTITION_COUNT 1
+
+#define MAX_MMAP_REGIONS_SPMC 2
+#define MAX_XLAT_TABLES_SPMC 4
+#else
+#define MAX_MMAP_REGIONS_SPMC 0
+#define MAX_XLAT_TABLES_SPMC 0
+#endif
+
+#if ENABLE_RME
+
+/*
+ * Reserve some space at the end of secure DRAM for the Granule Protection
+ * Tables
+ */
+#define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \
+ PLAT_QEMU_L0_GPT_SIZE)
+#define PLAT_QEMU_L0_GPT_SIZE (2 * PAGE_SIZE)
+
+#define PLAT_QEMU_L1_GPT_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
+ PLAT_QEMU_L1_GPT_SIZE)
+#define PLAT_QEMU_L1_GPT_END (PLAT_QEMU_L1_GPT_BASE + \
+ PLAT_QEMU_L1_GPT_SIZE - 1U)
+#define PLAT_QEMU_L1_GPT_SIZE UL(0x00100000) /* 1MB */
+
+#define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE
+#define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \
+ PLAT_QEMU_L0_GPT_SIZE)
+
+#ifndef __ASSEMBLER__
+/* L0 table greater than 4KB must be naturally aligned */
+CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0,
+ assert_l0_gpt_naturally_aligned);
+#endif
+
+/* Reserved some DRAM space for RMM (24MB) */
+#define REALM_DRAM_BASE (NS_DRAM0_BASE + PLAT_QEMU_DT_MAX_SIZE)
+#define REALM_DRAM_SIZE 0x01800000
+
+#define PLAT_QEMU_RMM_SIZE (REALM_DRAM_SIZE - RMM_SHARED_SIZE)
+#define PLAT_QEMU_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */
+
+#define RMM_BASE (REALM_DRAM_BASE)
+#define RMM_LIMIT (RMM_BASE + PLAT_QEMU_RMM_SIZE)
+#define RMM_SHARED_BASE (RMM_LIMIT)
+#define RMM_SHARED_SIZE PLAT_QEMU_RMM_SHARED_SIZE
+
+#define MAP_GPT_L0_REGION MAP_REGION_FLAT( \
+ PLAT_QEMU_L0_GPT_BASE, \
+ PLAT_QEMU_L0_GPT_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define MAP_GPT_L1_REGION MAP_REGION_FLAT( \
+ PLAT_QEMU_L1_GPT_BASE, \
+ PLAT_QEMU_L1_GPT_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+/*
+ * We add the RMM_SHARED size to RMM mapping to map the region as a block.
+ * Else we end up requiring more pagetables in BL2 for ROMLIB build.
+ */
+#define MAP_RMM_DRAM MAP_REGION_FLAT( \
+ RMM_BASE, \
+ (PLAT_QEMU_RMM_SIZE + \
+ RMM_SHARED_SIZE), \
+ MT_MEMORY | MT_RW | MT_REALM)
+
+#define MAP_RMM_SHARED_MEM MAP_REGION_FLAT( \
+ RMM_SHARED_BASE, \
+ RMM_SHARED_SIZE, \
+ MT_MEMORY | MT_RW | MT_REALM)
+#else /* !ENABLE_RME */
+
+#define RME_GPT_DRAM_SIZE 0
+
+#endif /* ENABLE_RME */
+
#endif /* PLATFORM_DEF_H */