diff options
Diffstat (limited to 'plat/mediatek/mt8195/include/platform_def.h')
-rw-r--r-- | plat/mediatek/mt8195/include/platform_def.h | 44 |
1 files changed, 39 insertions, 5 deletions
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h index f6eb742f34..8696f2a121 100644 --- a/plat/mediatek/mt8195/include/platform_def.h +++ b/plat/mediatek/mt8195/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,15 +15,43 @@ /* Aggregate of all devices for MMU mapping */ #define MTK_DEV_RNG0_BASE IO_PHYS -#define MTK_DEV_RNG0_SIZE 0x400000 -#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) -#define MTK_DEV_RNG1_SIZE 0xa110000 +#define MTK_DEV_RNG0_SIZE 0x10000000 #define MTK_DEV_RNG2_BASE MT_GIC_BASE #define MTK_DEV_RNG2_SIZE 0x600000 #define MTK_MCDI_SRAM_BASE 0x11B000 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 +#define APUSYS_BASE 0x19000000 +#define APUSYS_SCTRL_REVISER_BASE 0x19021000 +#define APUSYS_SCTRL_REVISER_SIZE 0x1000 +#define APUSYS_APU_S_S_4_BASE 0x190F2000 +#define APUSYS_APU_S_S_4_SIZE 0x1000 +#define APUSYS_APU_PLL_BASE 0x190F3000 +#define APUSYS_APU_PLL_SIZE 0x1000 +#define APUSYS_APU_ACC_BASE 0x190F4000 +#define APUSYS_APU_ACC_SIZE 0x1000 + +#define TOPCKGEN_BASE (IO_PHYS + 0x00000000) +#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) #define SPM_BASE (IO_PHYS + 0x00006000) +#define RGU_BASE (IO_PHYS + 0x00007000) +#define APMIXEDSYS (IO_PHYS + 0x0000C000) +#define DRM_BASE (IO_PHYS + 0x0000D000) +#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) +#define PERICFG_AO_BASE (IO_PHYS + 0x01003000) +#define VPPSYS0_BASE (IO_PHYS + 0x04000000) +#define VPPSYS1_BASE (IO_PHYS + 0x04f00000) +#define VDOSYS0_BASE (IO_PHYS + 0x0C01A000) +#define VDOSYS1_BASE (IO_PHYS + 0x0C100000) +#define DVFSRC_BASE (IO_PHYS + 0x00012000) + +/******************************************************************************* + * DP/eDP related constants + ******************************************************************************/ +#define EDP_SEC_BASE (IO_PHYS + 0x0C504000) +#define DP_SEC_BASE (IO_PHYS + 0x0C604000) +#define EDP_SEC_SIZE 0x1000 +#define DP_SEC_SIZE 0x1000 /******************************************************************************* * GPIO related constants @@ -50,6 +78,12 @@ #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) /******************************************************************************* + * EMI MPU related constants + ******************************************************************************/ +#define EMI_MPU_BASE (IO_PHYS + 0x00226000) +#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) + +/******************************************************************************* * System counter frequency related constants ******************************************************************************/ #define SYS_COUNTER_FREQ_IN_TICKS 13000000 @@ -99,7 +133,7 @@ * Platform memory map related constants ******************************************************************************/ #define TZRAM_BASE 0x54600000 -#define TZRAM_SIZE 0x00030000 +#define TZRAM_SIZE 0x00040000 /******************************************************************************* * BL31 specific defines. |