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-rw-r--r--plat/imx/imx7/picopi/picopi_bl2_el3_setup.c9
-rw-r--r--plat/imx/imx7/warp7/warp7_bl2_el3_setup.c9
-rw-r--r--plat/imx/imx8m/imx8m_psci_common.c63
-rw-r--r--plat/imx/imx8m/imx8mm/imx8mm_psci.c1
-rw-r--r--plat/imx/imx8m/imx8mm/include/platform_def.h4
-rw-r--r--plat/imx/imx8m/imx8mn/include/platform_def.h5
-rw-r--r--plat/imx/imx8m/imx8mn/platform.mk5
-rw-r--r--plat/imx/imx8m/imx8mp/include/platform_def.h9
-rw-r--r--plat/imx/imx8m/imx8mp/platform.mk5
-rw-r--r--plat/imx/imx8m/imx8mq/imx8mq_psci.c1
-rw-r--r--plat/imx/imx8m/include/imx8m_psci.h1
11 files changed, 92 insertions, 20 deletions
diff --git a/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
index 3cf5c36057..2df96aee09 100644
--- a/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
+++ b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,6 +43,8 @@
IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW | \
IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
+static struct mmc_device_info mmc_info;
+
static void picopi_setup_pinmux(void)
{
/* Configure UART5 TX */
@@ -93,14 +95,13 @@ static void picopi_setup_pinmux(void)
static void picopi_usdhc_setup(void)
{
imx_usdhc_params_t params;
- struct mmc_device_info info;
zeromem(&params, sizeof(imx_usdhc_params_t));
params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
params.clk_rate = 25000000;
params.bus_width = MMC_BUS_WIDTH_8;
- info.mmc_dev_type = MMC_IS_EMMC;
- imx_usdhc_init(&params, &info);
+ mmc_info.mmc_dev_type = MMC_IS_EMMC;
+ imx_usdhc_init(&params, &mmc_info);
}
static void picopi_setup_usb_clocks(void)
diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
index 935a411ac8..ec13ade0e6 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
+++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,6 +69,8 @@
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4)
+static struct mmc_device_info mmc_info;
+
static void warp7_setup_pinmux(void)
{
/* Configure UART1 TX */
@@ -99,14 +101,13 @@ static void warp7_setup_pinmux(void)
static void warp7_usdhc_setup(void)
{
imx_usdhc_params_t params;
- struct mmc_device_info info;
zeromem(&params, sizeof(imx_usdhc_params_t));
params.reg_base = PLAT_WARP7_BOOT_MMC_BASE;
params.clk_rate = 25000000;
params.bus_width = MMC_BUS_WIDTH_8;
- info.mmc_dev_type = MMC_IS_EMMC;
- imx_usdhc_init(&params, &info);
+ mmc_info.mmc_dev_type = MMC_IS_EMMC;
+ imx_usdhc_init(&params, &mmc_info);
}
static void warp7_setup_usb_clocks(void)
diff --git a/plat/imx/imx8m/imx8m_psci_common.c b/plat/imx/imx8m/imx8m_psci_common.c
index dbb772dc17..9dfd311d13 100644
--- a/plat/imx/imx8m/imx8m_psci_common.c
+++ b/plat/imx/imx8m/imx8m_psci_common.c
@@ -152,19 +152,45 @@ void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
}
-void __dead2 imx_system_reset(void)
+static void __dead2 imx_wdog_restart(bool external_reset)
{
uintptr_t wdog_base = IMX_WDOG_BASE;
unsigned int val;
- /* WDOG_B reset */
val = mmio_read_16(wdog_base);
-#ifdef IMX_WDOG_B_RESET
- val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_WDE |
- WDOG_WCR_WDT | WDOG_WCR_SRS;
-#else
- val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_SRS;
-#endif
+ /*
+ * Common watchdog init flags, for additional details check
+ * 6.6.4.1 Watchdog Control Register (WDOGx_WCR)
+ *
+ * Initial bit selection:
+ * WDOG_WCR_WDE - Enable the watchdog.
+ *
+ * 0x000E mask is used to keep previous values (that could be set
+ * in SPL) of WDBG and WDE/WDT (both are write-one once-only bits).
+ */
+ val = (val & 0x000E) | WDOG_WCR_WDE;
+ if (external_reset) {
+ /*
+ * To assert WDOG_B (external reset) we have
+ * to set WDA bit 0 (already set in previous step).
+ * SRS bits are required to be set to 1 (no effect on the
+ * system).
+ */
+ val |= WDOG_WCR_SRS;
+ } else {
+ /*
+ * To assert Software Reset Signal (internal reset) we have
+ * to set SRS bit to 0 (already set in previous step).
+ * SRE bit is required to be set to 1 when used in
+ * conjunction with the Software Reset Signal before
+ * SRS asserton, otherwise SRS bit will just automatically
+ * reset to 1.
+ *
+ * Also we set WDA to 1 (no effect on system).
+ */
+ val |= WDOG_WCR_SRE | WDOG_WCR_WDA;
+ }
+
mmio_write_16(wdog_base, val);
mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
@@ -173,6 +199,27 @@ void __dead2 imx_system_reset(void)
;
}
+void __dead2 imx_system_reset(void)
+{
+#ifdef IMX_WDOG_B_RESET
+ imx_wdog_restart(true);
+#else
+ imx_wdog_restart(false);
+#endif
+}
+
+int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
+{
+ imx_wdog_restart(false);
+
+ /*
+ * imx_wdog_restart cannot return (as it's a __dead function),
+ * however imx_system_reset2 has to return some value according
+ * to PSCI v1.1 spec.
+ */
+ return 0;
+}
+
void __dead2 imx_system_off(void)
{
mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV |
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_psci.c b/plat/imx/imx8m/imx8mm/imx8mm_psci.c
index e558724e80..815d3a2a51 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_psci.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_psci.c
@@ -28,6 +28,7 @@ static const plat_psci_ops_t imx_plat_psci_ops = {
.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
.system_reset = imx_system_reset,
+ .system_reset2 = imx_system_reset2,
.system_off = imx_system_off,
};
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index f8efa5659f..940d22bc14 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -42,7 +42,7 @@
#define BL31_BASE U(0x900000)
#define BL31_LIMIT U(0x920000)
#define IMX8MM_FIP_BASE U(0x40310000)
-#define IMX8MM_FIP_SIZE U(0x000200000)
+#define IMX8MM_FIP_SIZE U(0x000300000)
#define IMX8MM_FIP_LIMIT U(FIP_BASE + FIP_SIZE)
/* Define FIP image location on eMMC */
@@ -56,7 +56,7 @@
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
-#define PLAT_NS_IMAGE_SIZE U(0x00100000)
+#define PLAT_NS_IMAGE_SIZE U(0x00200000)
/* GICv3 base address */
#define PLAT_GICD_BASE U(0x38800000)
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h
index 2444e662ef..9c46d8d278 100644
--- a/plat/imx/imx8m/imx8mn/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -34,6 +34,11 @@
#define PLAT_WAIT_RET_STATE U(1)
#define PLAT_STOP_OFF_STATE U(3)
+#define PLAT_PRI_BITS U(3)
+#define PLAT_SDEI_CRITICAL_PRI 0x10
+#define PLAT_SDEI_NORMAL_PRI 0x20
+#define PLAT_SDEI_SGI_PRIVATE U(9)
+
#define BL31_BASE U(0x960000)
#define BL31_LIMIT U(0x980000)
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index 8c4ad1c210..208708918f 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -31,6 +31,8 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
plat/imx/common/imx_uart_console.S \
+ plat/imx/common/imx_ehf.c \
+ plat/imx/common/imx_sdei.c \
lib/cpus/aarch64/cortex_a53.S \
drivers/arm/tzc/tzc380.c \
drivers/delay_timer/delay_timer.c \
@@ -54,3 +56,6 @@ $(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
$(eval $(call add_define,IMX_BOOT_UART_BASE))
+
+EL3_EXCEPTION_HANDLING := 1
+SDEI_SUPPORT := 1
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index a5f265d0d7..832bed17ed 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -34,8 +34,13 @@
#define PLAT_WAIT_RET_STATE U(1)
#define PLAT_STOP_OFF_STATE U(3)
-#define BL31_BASE U(0x970000)
-#define BL31_LIMIT U(0x990000)
+#define BL31_BASE U(0x960000)
+#define BL31_LIMIT U(0x980000)
+
+#define PLAT_PRI_BITS U(3)
+#define PLAT_SDEI_CRITICAL_PRI 0x10
+#define PLAT_SDEI_NORMAL_PRI 0x20
+#define PLAT_SDEI_SGI_PRIVATE U(9)
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 1d11e3df47..6be2f9861c 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -28,6 +28,8 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/imx8mp/imx8mp_psci.c \
plat/imx/imx8m/imx8mp/gpc.c \
plat/imx/common/imx8_topology.c \
+ plat/imx/common/imx_ehf.c \
+ plat/imx/common/imx_sdei.c \
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
plat/imx/common/imx_uart_console.S \
@@ -54,3 +56,6 @@ $(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
$(eval $(call add_define,IMX_BOOT_UART_BASE))
+
+EL3_EXCEPTION_HANDLING := 1
+SDEI_SUPPORT := 1
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_psci.c b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
index 04e191ff89..662017d6fe 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_psci.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
@@ -117,6 +117,7 @@ static const plat_psci_ops_t imx_plat_psci_ops = {
.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
.system_reset = imx_system_reset,
+ .system_reset2 = imx_system_reset2,
.system_off = imx_system_off,
};
diff --git a/plat/imx/imx8m/include/imx8m_psci.h b/plat/imx/imx8m/include/imx8m_psci.h
index c33d25e824..7d14d1120d 100644
--- a/plat/imx/imx8m/include/imx8m_psci.h
+++ b/plat/imx/imx8m/include/imx8m_psci.h
@@ -19,5 +19,6 @@ void imx_cpu_standby(plat_local_state_t cpu_state);
void imx_domain_suspend(const psci_power_state_t *target_state);
void imx_domain_suspend_finish(const psci_power_state_t *target_state);
void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state);
+int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie);
#endif /* IMX8M_PSCI_H */