diff options
Diffstat (limited to 'plat/imx/imx8m/imx8mq/include/platform_def.h')
-rw-r--r-- | plat/imx/imx8m/imx8mq/include/platform_def.h | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index 9db3a137a3..b04f3915ec 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -1,9 +1,12 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <lib/utils_def.h> +#include <plat/common/common_def.h> + #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -31,10 +34,14 @@ #define PLAT_STOP_OFF_STATE U(3) #define BL31_BASE U(0x910000) -#define BL31_LIMIT U(0x920000) +#define BL31_SIZE SZ_64K +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) /* non-secure uboot base */ +#ifndef PLAT_NS_IMAGE_OFFSET #define PLAT_NS_IMAGE_OFFSET U(0x40200000) +#endif +#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) /* GICv3 base address */ #define PLAT_GICD_BASE U(0x38800000) @@ -43,12 +50,16 @@ #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) +#ifdef SPD_trusty +#define MAX_XLAT_TABLES 5 +#define MAX_MMAP_REGIONS 15 +#else #define MAX_XLAT_TABLES 4 #define MAX_MMAP_REGIONS 14 +#endif #define HAB_RVT_BASE U(0x00000880) /* HAB_RVT for i.MX8MQ */ -#define IMX_BOOT_UART_BASE U(0x30860000) #define IMX_BOOT_UART_CLK_IN_HZ 25000000 /* Select 25Mhz oscillator */ #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE #define PLAT_CRASH_UART_CLK_IN_HZ 25000000 @@ -74,6 +85,9 @@ #define IMX_DDRC_BASE U(0x3d400000) #define IMX_DDRPHY_BASE U(0x3c000000) #define IMX_DDR_IPS_BASE U(0x3d000000) +#define IMX_DDR_IPS_SIZE U(0x1800000) +#define IMX_DRAM_BASE U(0x40000000) +#define IMX_DRAM_SIZE U(0xc0000000) #define IMX_ROM_BASE U(0x00000000) #define IMX_ROM_SIZE U(0x20000) @@ -103,12 +117,20 @@ #define SRC_OTG1PHY_SCR U(0x20) #define SRC_OTG2PHY_SCR U(0x24) #define SRC_GPR1_OFFSET U(0x74) +#define SRC_GPR10_OFFSET U(0x98) +#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) #define SNVS_LPCR U(0x38) #define SNVS_LPCR_SRTC_ENV BIT(0) #define SNVS_LPCR_DP_EN BIT(5) #define SNVS_LPCR_TOP BIT(6) +#define SAVED_DRAM_TIMING_BASE U(0x40000000) + +#define HW_DRAM_PLL_CFG0 (IMX_ANAMIX_BASE + 0x60) +#define HW_DRAM_PLL_CFG1 (IMX_ANAMIX_BASE + 0x64) +#define HW_DRAM_PLL_CFG2 (IMX_ANAMIX_BASE + 0x68) +#define DRAM_PLL_CTRL HW_DRAM_PLL_CFG0 #define IOMUXC_GPR10 U(0x28) #define GPR_TZASC_EN BIT(0) @@ -118,7 +140,6 @@ #define OCRAM_S_SIZE U(0x8000) #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) -#define COUNTER_FREQUENCY 8000000 /* 8MHz */ +#define COUNTER_FREQUENCY 8333333 /* 25MHz / 3 */ -#define DEBUG_CONSOLE 0 #define IMX_WDOG_B_RESET |