diff options
Diffstat (limited to 'plat/arm/common/fconf/arm_fconf_io.c')
-rw-r--r-- | plat/arm/common/fconf/arm_fconf_io.c | 135 |
1 files changed, 128 insertions, 7 deletions
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c index 8e4469fb22..07f6a82721 100644 --- a/plat/arm/common/fconf/arm_fconf_io.c +++ b/plat/arm/common/fconf/arm_fconf_io.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,11 @@ #include <plat/arm/common/arm_fconf_io_storage.h> #include <platform_def.h> +#if PSA_FWU_SUPPORT +/* metadata entry details */ +static io_block_spec_t fwu_metadata_spec; +#endif /* PSA_FWU_SUPPORT */ + io_block_spec_t fip_block_spec = { /* * This is fixed FIP address used by BL1, BL2 loads partition table @@ -40,10 +45,21 @@ static const io_block_spec_t gpt_spec = { * each sector has 4 partition entries, and there are * 2 reserved sectors i.e. protective MBR and primary * GPT header hence length gets calculated as, - * length = 512 * (128/4 + 2) + * length = PLAT_PARTITION_BLOCK_SIZE * (128/4 + 2) */ - .length = PLAT_PARTITION_BLOCK_SIZE * - (PLAT_PARTITION_MAX_ENTRIES / 4 + 2), + .length = LBA(PLAT_PARTITION_MAX_ENTRIES / 4 + 2), +}; + +/* + * length will be assigned at runtime based on MBR header data. + * Backup GPT Header is present in Last LBA-1 and its entries + * are last 32 blocks starts at LBA-33, On runtime update these + * before device usage. Update offset to beginning LBA-33 and + * length to LBA-33. + */ +static io_block_spec_t bkup_gpt_spec = { + .offset = PLAT_ARM_FLASH_IMAGE_BASE, + .length = 0, }; #endif /* ARM_GPT_SUPPORT */ @@ -62,10 +78,17 @@ const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = { [SOC_FW_CONFIG_ID] = {UUID_SOC_FW_CONFIG}, [TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG}, [NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG}, + [RMM_IMAGE_ID] = {UUID_REALM_MONITOR_MGMT_FIRMWARE}, +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW}, +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* ARM_IO_IN_DTB */ #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT}, #if !ARM_IO_IN_DTB + [CCA_CONTENT_CERT_ID] = {UUID_CCA_CONTENT_CERT}, + [CORE_SWD_KEY_CERT_ID] = {UUID_CORE_SWD_KEY_CERT}, + [PLAT_KEY_CERT_ID] = {UUID_PLAT_KEY_CERT}, [TRUSTED_KEY_CERT_ID] = {UUID_TRUSTED_KEY_CERT}, [SCP_FW_KEY_CERT_ID] = {UUID_SCP_FW_KEY_CERT}, [SOC_FW_KEY_CERT_ID] = {UUID_SOC_FW_KEY_CERT}, @@ -79,6 +102,10 @@ const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = { [SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT}, [PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT}, #endif +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE}, + [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE}, +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* ARM_IO_IN_DTB */ #endif /* TRUSTED_BOARD_BOOT */ }; @@ -91,7 +118,26 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { (uintptr_t)&gpt_spec, open_memmap }, + [BKUP_GPT_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&bkup_gpt_spec, + open_memmap + }, #endif /* ARM_GPT_SUPPORT */ +#if PSA_FWU_SUPPORT + [FWU_METADATA_IMAGE_ID] = { + &memmap_dev_handle, + /* filled runtime from partition information */ + (uintptr_t)&fwu_metadata_spec, + open_memmap + }, + [BKUP_FWU_METADATA_IMAGE_ID] = { + &memmap_dev_handle, + /* filled runtime from partition information */ + (uintptr_t)&fwu_metadata_spec, + open_memmap + }, +#endif /* PSA_FWU_SUPPORT */ [FIP_IMAGE_ID] = { &memmap_dev_handle, (uintptr_t)&fip_block_spec, @@ -143,6 +189,11 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { (uintptr_t)&arm_uuid_spec[BL33_IMAGE_ID], open_fip }, + [RMM_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[RMM_IMAGE_ID], + open_fip + }, [HW_CONFIG_ID] = { &fip_dev_handle, (uintptr_t)&arm_uuid_spec[HW_CONFIG_ID], @@ -163,6 +214,13 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { (uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID], open_fip }, +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_IMAGE_ID], + open_fip + }, +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* ARM_IO_IN_DTB */ #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = { @@ -171,6 +229,21 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { open_fip }, #if !ARM_IO_IN_DTB + [CCA_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[CCA_CONTENT_CERT_ID], + open_fip + }, + [CORE_SWD_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[CORE_SWD_KEY_CERT_ID], + open_fip + }, + [PLAT_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[PLAT_KEY_CERT_ID], + open_fip + }, [TRUSTED_KEY_CERT_ID] = { &fip_dev_handle, (uintptr_t)&arm_uuid_spec[TRUSTED_KEY_CERT_ID], @@ -228,17 +301,55 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { open_fip }, #endif +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_KEY_CERT_ID], + open_fip + }, + [ETHOSN_NPU_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_CONTENT_CERT_ID], + open_fip + }, +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* ARM_IO_IN_DTB */ #endif /* TRUSTED_BOARD_BOOT */ }; #ifdef IMAGE_BL2 +#define FCONF_ARM_IO_UUID_NUM_BASE U(10) + +#if ETHOSN_NPU_TZMP1 +#define FCONF_ARM_IO_UUID_NUM_NPU U(1) +#else +#define FCONF_ARM_IO_UUID_NUM_NPU U(0) +#endif /* ETHOSN_NPU_TZMP1 */ + #if TRUSTED_BOARD_BOOT -#define FCONF_ARM_IO_UUID_NUMBER U(21) +#define FCONF_ARM_IO_UUID_NUM_TBB U(12) #else -#define FCONF_ARM_IO_UUID_NUMBER U(10) -#endif +#define FCONF_ARM_IO_UUID_NUM_TBB U(0) +#endif /* TRUSTED_BOARD_BOOT */ + +#if TRUSTED_BOARD_BOOT && defined(SPD_spmd) +#define FCONF_ARM_IO_UUID_NUM_SPD U(2) +#else +#define FCONF_ARM_IO_UUID_NUM_SPD U(0) +#endif /* TRUSTED_BOARD_BOOT && defined(SPD_spmd) */ + +#if TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 +#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(2) +#else +#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(0) +#endif /* TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 */ + +#define FCONF_ARM_IO_UUID_NUMBER FCONF_ARM_IO_UUID_NUM_BASE + \ + FCONF_ARM_IO_UUID_NUM_NPU + \ + FCONF_ARM_IO_UUID_NUM_TBB + \ + FCONF_ARM_IO_UUID_NUM_SPD + \ + FCONF_ARM_IO_UUID_NUM_NPU_TBB static io_uuid_spec_t fconf_arm_uuids[FCONF_ARM_IO_UUID_NUMBER]; static OBJECT_POOL_ARRAY(fconf_arm_uuids_pool, fconf_arm_uuids); @@ -260,7 +371,13 @@ static const struct policies_load_info load_info[FCONF_ARM_IO_UUID_NUMBER] = { {SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"}, {TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"}, {NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"}, +#if ETHOSN_NPU_TZMP1 + {ETHOSN_NPU_FW_IMAGE_ID, "ethosn_npu_fw_uuid"}, +#endif /* ETHOSN_NPU_TZMP1 */ #if TRUSTED_BOARD_BOOT + {CCA_CONTENT_CERT_ID, "cca_cert_uuid"}, + {CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"}, + {PLAT_KEY_CERT_ID, "plat_cert_uuid"}, {TRUSTED_KEY_CERT_ID, "t_key_cert_uuid"}, {SCP_FW_KEY_CERT_ID, "scp_fw_key_uuid"}, {SOC_FW_KEY_CERT_ID, "soc_fw_key_uuid"}, @@ -274,6 +391,10 @@ static const struct policies_load_info load_info[FCONF_ARM_IO_UUID_NUMBER] = { {SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"}, {PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"}, #endif +#if ETHOSN_NPU_TZMP1 + {ETHOSN_NPU_FW_KEY_CERT_ID, "ethosn_npu_fw_key_cert_uuid"}, + {ETHOSN_NPU_FW_CONTENT_CERT_ID, "ethosn_npu_fw_content_cert_uuid"}, +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* TRUSTED_BOARD_BOOT */ }; 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