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-rw-r--r--include/drivers/marvell/cache_llc.h4
-rw-r--r--include/drivers/st/stm32mp_clkfunc.h4
-rw-r--r--include/lib/cpus/aarch64/cortex_a77.h1
-rw-r--r--include/lib/cpus/aarch64/rainier.h2
4 files changed, 5 insertions, 6 deletions
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
index d6dd65382f..72111b374a 100644
--- a/include/drivers/marvell/cache_llc.h
+++ b/include/drivers/marvell/cache_llc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -57,6 +57,6 @@ int llc_sram_enable(int ap_index, int size);
void llc_sram_disable(int ap_index);
int llc_sram_test(int ap_index, int size, char *msg);
#endif /* LLC_SRAM */
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CACHE_LLC_H */
diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h
index 0902f445d1..c7e0b6e6fb 100644
--- a/include/drivers/st/stm32mp_clkfunc.h
+++ b/include/drivers/st/stm32mp_clkfunc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,14 +20,12 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
uint32_t dflt_value);
int fdt_get_rcc_node(void *fdt);
-uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count,
uint32_t *array);
int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_status(void);
-uintptr_t fdt_get_stgen_base(void);
int fdt_get_clock_id(int node);
#endif /* STM32MP_CLKFUNC_H */
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index 41aced8d28..ed84c0f4a1 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -16,6 +16,7 @@
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
diff --git a/include/lib/cpus/aarch64/rainier.h b/include/lib/cpus/aarch64/rainier.h
index 9ff1669563..978661ff69 100644
--- a/include/lib/cpus/aarch64/rainier.h
+++ b/include/lib/cpus/aarch64/rainier.h
@@ -10,7 +10,7 @@
#include <lib/utils_def.h>
/* RAINIER MIDR for revision 0 */
-#define RAINIER_MIDR U(0x3f0f4100)
+#define RAINIER_MIDR U(0x3f0f4120)
/* Exception Syndrome register EC code for IC Trap */
#define RAINIER_EC_IC_TRAP U(0x1f)