diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/common/fdt_fixup.h | 2 | ||||
-rw-r--r-- | include/drivers/arm/gicv3.h | 1 | ||||
-rw-r--r-- | include/drivers/marvell/ccu.h | 1 | ||||
-rw-r--r-- | include/drivers/measured_boot/event_log.h | 2 | ||||
-rw-r--r-- | include/drivers/raw_nand.h | 2 | ||||
-rw-r--r-- | include/drivers/st/etzpc.h | 3 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/cortex_a77.h | 7 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/generic.h | 18 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/rainier.h | 66 | ||||
-rw-r--r-- | include/lib/libc/string.h | 1 |
10 files changed, 100 insertions, 3 deletions
diff --git a/include/common/fdt_fixup.h b/include/common/fdt_fixup.h index 29d8b3aa08..2e9d49d53d 100644 --- a/include/common/fdt_fixup.h +++ b/include/common/fdt_fixup.h @@ -13,5 +13,7 @@ int fdt_add_reserved_memory(void *dtb, const char *node_name, uintptr_t base, size_t size); int fdt_add_cpus_node(void *dtb, unsigned int afflv0, unsigned int afflv1, unsigned int afflv2); +int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, + unsigned int gicr_frame_size); #endif /* FDT_FIXUP_H */ diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 18d5b73e2f..d8ac4cb334 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -488,6 +488,7 @@ void gicv3_distif_init(void); void gicv3_rdistif_init(unsigned int proc_num); void gicv3_rdistif_on(unsigned int proc_num); void gicv3_rdistif_off(unsigned int proc_num); +unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame); void gicv3_cpuif_enable(unsigned int proc_num); void gicv3_cpuif_disable(unsigned int proc_num); unsigned int gicv3_get_pending_interrupt_type(void); diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h index 413ffb972f..f8f0adf676 100644 --- a/include/drivers/marvell/ccu.h +++ b/include/drivers/marvell/ccu.h @@ -47,6 +47,7 @@ void ccu_dram_target_set(int ap_index, uint32_t target); void ccu_save_win_all(int ap_id); void ccu_restore_win_all(int ap_id); int ccu_is_win_enabled(int ap_index, uint32_t win_id); +void errata_wa_init(void); #endif #endif /* CCU_H */ diff --git a/include/drivers/measured_boot/event_log.h b/include/drivers/measured_boot/event_log.h index 10dfbb39dd..efde117626 100644 --- a/include/drivers/measured_boot/event_log.h +++ b/include/drivers/measured_boot/event_log.h @@ -20,8 +20,6 @@ * LOG_LEVEL_WARNING * LOG_LEVEL_VERBOSE */ -#define EVENT_LOG_LEVEL LOG_LEVEL_INFO - #if EVENT_LOG_LEVEL == LOG_LEVEL_ERROR #define LOG_EVENT ERROR #elif EVENT_LOG_LEVEL == LOG_LEVEL_NOTICE diff --git a/include/drivers/raw_nand.h b/include/drivers/raw_nand.h index 9018f02428..7152300945 100644 --- a/include/drivers/raw_nand.h +++ b/include/drivers/raw_nand.h @@ -169,7 +169,7 @@ struct rawnand_device { }; int nand_raw_init(unsigned long long *size, unsigned int *erase_size); -int nand_wait_ready(unsigned long delay); +int nand_wait_ready(unsigned int delay_ms); int nand_read_page_cmd(unsigned int page, unsigned int offset, uintptr_t buffer, unsigned int len); int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer, diff --git a/include/drivers/st/etzpc.h b/include/drivers/st/etzpc.h index 6e3fec1ea7..4cd2b4e0bb 100644 --- a/include/drivers/st/etzpc.h +++ b/include/drivers/st/etzpc.h @@ -7,6 +7,9 @@ #ifndef DRIVERS_ST_ETZPC_H #define DRIVERS_ST_ETZPC_H +#include <stdbool.h> +#include <stdint.h> + /* Define security level for each peripheral (DECPROT) */ enum etzpc_decprot_attributes { ETZPC_DECPROT_S_RW = 0, diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h index bbd647c607..41aced8d28 100644 --- a/include/lib/cpus/aarch64/cortex_a77.h +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -24,4 +24,11 @@ #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) +#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 +#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 +#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 + #endif /* CORTEX_A77_H */ diff --git a/include/lib/cpus/aarch64/generic.h b/include/lib/cpus/aarch64/generic.h new file mode 100644 index 0000000000..53df587618 --- /dev/null +++ b/include/lib/cpus/aarch64/generic.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserverd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AARCH64_GENERIC_H +#define AARCH64_GENERIC_H + +#include <lib/utils_def.h> + +/* + * 0x0 value on the MIDR implementer value is reserved for software use, + * so use an MIDR value of 0 for a default CPU library. + */ +#define AARCH64_GENERIC_MIDR U(0) + +#endif /* AARCH64_GENERIC_H */ diff --git a/include/lib/cpus/aarch64/rainier.h b/include/lib/cpus/aarch64/rainier.h new file mode 100644 index 0000000000..9ff1669563 --- /dev/null +++ b/include/lib/cpus/aarch64/rainier.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RAINIER_H +#define RAINIER_H + +#include <lib/utils_def.h> + +/* RAINIER MIDR for revision 0 */ +#define RAINIER_MIDR U(0x3f0f4100) + +/* Exception Syndrome register EC code for IC Trap */ +#define RAINIER_EC_IC_TRAP U(0x1f) + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 + +/* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */ +#define RAINIER_CORE_PWRDN_EN_MASK U(0x1) + +#define RAINIER_ACTLR_AMEN_BIT (U(1) << 4) + +#define RAINIER_AMU_NR_COUNTERS U(5) +#define RAINIER_AMU_GROUP0_MASK U(0x1f) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4 + +#define RAINIER_WS_THR_L2_MASK (ULL(3) << 24) +#define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) + +#define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) +#define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) +#define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + +#define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* RAINIER_H */ diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h index 91cbafbb74..9894483183 100644 --- a/include/lib/libc/string.h +++ b/include/lib/libc/string.h @@ -27,5 +27,6 @@ size_t strnlen(const char *s, size_t maxlen); char *strrchr(const char *p, int ch); size_t strlcpy(char * dst, const char * src, size_t dsize); size_t strlcat(char * dst, const char * src, size_t dsize); +char *strtok_r(char *s, const char *delim, char **last); #endif /* STRING_H */ |