diff options
Diffstat (limited to 'include')
426 files changed, 31140 insertions, 5002 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 54ec009534..7e759d8198 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,8 +16,10 @@ #define MIDR_IMPL_SHIFT U(24) #define MIDR_VAR_SHIFT U(20) #define MIDR_VAR_BITS U(4) +#define MIDR_VAR_MASK U(0xf) #define MIDR_REV_SHIFT U(0) #define MIDR_REV_BITS U(4) +#define MIDR_REV_MASK U(0xf) #define MIDR_PN_MASK U(0xfff) #define MIDR_PN_SHIFT U(4) @@ -102,16 +104,39 @@ /* CSSELR definitions */ #define LEVEL_SHIFT U(1) +/* ID_DFR0 definitions */ +#define ID_DFR0_PERFMON_SHIFT U(24) +#define ID_DFR0_PERFMON_MASK U(0xf) +#define ID_DFR0_PERFMON_PMUV3 U(3) +#define ID_DFR0_PERFMON_PMUV3P5 U(6) +#define ID_DFR0_COPTRC_SHIFT U(12) +#define ID_DFR0_COPTRC_MASK U(0xf) +#define ID_DFR0_COPTRC_SUPPORTED U(1) +#define ID_DFR0_COPTRC_LENGTH U(4) +#define ID_DFR0_TRACEFILT_SHIFT U(28) +#define ID_DFR0_TRACEFILT_MASK U(0xf) +#define ID_DFR0_TRACEFILT_SUPPORTED U(1) +#define ID_DFR0_TRACEFILT_LENGTH U(4) + /* ID_DFR1_EL1 definitions */ #define ID_DFR1_MTPMU_SHIFT U(0) #define ID_DFR1_MTPMU_MASK U(0xf) #define ID_DFR1_MTPMU_SUPPORTED U(1) +#define ID_DFR1_MTPMU_DISABLED U(15) + +/* ID_MMFR3 definitions */ +#define ID_MMFR3_PAN_SHIFT U(16) +#define ID_MMFR3_PAN_MASK U(0xf) /* ID_MMFR4 definitions */ #define ID_MMFR4_CNP_SHIFT U(12) #define ID_MMFR4_CNP_LENGTH U(4) #define ID_MMFR4_CNP_MASK U(0xf) +#define ID_MMFR4_CCIDX_SHIFT U(24) +#define ID_MMFR4_CCIDX_LENGTH U(4) +#define ID_MMFR4_CCIDX_MASK U(0xf) + /* ID_PFR0 definitions */ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) @@ -138,6 +163,11 @@ #define ID_PFR1_SEC_MASK U(0xf) #define ID_PFR1_ELx_ENABLED U(1) +/* ID_PFR2 definitions */ +#define ID_PFR2_SSBS_SHIFT U(4) +#define ID_PFR2_SSBS_MASK U(0xf) +#define SSBS_UNAVAILABLE U(0) + /* SCTLR definitions */ #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ (U(1) << 3)) @@ -164,7 +194,7 @@ #define SCTLR_AFE_BIT (U(1) << 29) #define SCTLR_TE_BIT (U(1) << 30) #define SCTLR_DSSBS_BIT (U(1) << 31) -#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ +#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) /* SDCR definitions */ @@ -172,10 +202,11 @@ #define SDCR_SPD_LEGACY U(0x0) #define SDCR_SPD_DISABLE U(0x2) #define SDCR_SPD_ENABLE U(0x3) -#define SDCR_SCCD_BIT (U(1) << 23) #define SDCR_SPME_BIT (U(1) << 17) -#define SDCR_RESET_VAL U(0x0) +#define SDCR_TTRF_BIT (U(1) << 19) +#define SDCR_SCCD_BIT (U(1) << 23) #define SDCR_MTPME_BIT (U(1) << 28) +#define SDCR_RESET_VAL U(0x0) /* HSCTLR definitions */ #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ @@ -242,13 +273,14 @@ /* HCPTR definitions */ #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) #define TCPAC_BIT (U(1) << 31) -#define TAM_BIT (U(1) << 30) +#define TAM_SHIFT U(30) +#define TAM_BIT (U(1) << TAM_SHIFT) #define TTA_BIT (U(1) << 20) #define TCP11_BIT (U(1) << 11) #define TCP10_BIT (U(1) << 10) #define HCPTR_RESET_VAL HCPTR_RES1 -/* VTTBR defintions */ +/* VTTBR definitions */ #define VTTBR_RESET_VAL ULL(0x0) #define VTTBR_VMID_MASK ULL(0xff) #define VTTBR_VMID_SHIFT U(48) @@ -283,7 +315,7 @@ #define CPACR_CP10_SHIFT U(20) #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ (U(0x3) << CPACR_CP10_SHIFT)) -#define CPACR_RESET_VAL U(0x0) +#define CPACR_RESET_VAL U(0x0) /* FPEXC definitions */ #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) @@ -442,6 +474,10 @@ #define PMCR_LP_BIT (U(1) << 7) #define PMCR_LC_BIT (U(1) << 6) #define PMCR_DP_BIT (U(1) << 5) +#define PMCR_X_BIT (U(1) << 4) +#define PMCR_C_BIT (U(1) << 2) +#define PMCR_P_BIT (U(1) << 1) +#define PMCR_E_BIT (U(1) << 0) #define PMCR_RESET_VAL U(0x0) /******************************************************************************* @@ -483,13 +519,13 @@ #define CNTP_CTL U(0x2c) /* Physical timer control register bit fields shifts and masks */ -#define CNTP_CTL_ENABLE_SHIFT 0 -#define CNTP_CTL_IMASK_SHIFT 1 -#define CNTP_CTL_ISTATUS_SHIFT 2 +#define CNTP_CTL_ENABLE_SHIFT 0 +#define CNTP_CTL_IMASK_SHIFT 1 +#define CNTP_CTL_ISTATUS_SHIFT 2 -#define CNTP_CTL_ENABLE_MASK U(1) -#define CNTP_CTL_IMASK_MASK U(1) -#define CNTP_CTL_ISTATUS_MASK U(1) +#define CNTP_CTL_ENABLE_MASK U(1) +#define CNTP_CTL_IMASK_MASK U(1) +#define CNTP_CTL_ISTATUS_MASK U(1) /* MAIR macros */ #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) @@ -515,10 +551,13 @@ #define DCISW p15, 0, c7, c6, 2 #define CTR p15, 0, c0, c0, 1 #define CNTFRQ p15, 0, c14, c0, 0 +#define ID_MMFR3 p15, 0, c0, c1, 7 #define ID_MMFR4 p15, 0, c0, c2, 6 +#define ID_DFR0 p15, 0, c0, c1, 2 #define ID_DFR1 p15, 0, c0, c3, 5 #define ID_PFR0 p15, 0, c0, c1, 0 #define ID_PFR1 p15, 0, c0, c1, 1 +#define ID_PFR2 p15, 0, c0, c3, 4 #define MAIR0 p15, 0, c10, c2, 0 #define MAIR1 p15, 0, c10, c2, 1 #define TTBCR p15, 0, c2, c0, 2 @@ -546,6 +585,7 @@ #define CLIDR p15, 1, c0, c0, 1 #define CSSELR p15, 2, c0, c0, 0 #define CCSIDR p15, 1, c0, c0, 0 +#define CCSIDR2 p15, 1, c0, c0, 2 #define HTCR p15, 4, c2, c0, 2 #define HMAIR0 p15, 4, c10, c2, 0 #define ATS1CPR p15, 0, c7, c8, 0 @@ -599,6 +639,12 @@ #define ICC_ASGI1R_EL1_64 p15, 1, c12 #define ICC_SGI0R_EL1_64 p15, 2, c12 +/* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */ +#define DFSR p15, 0, c5, c0, 0 +#define IFSR p15, 0, c5, c0, 1 +#define DFAR p15, 0, c6, c0, 0 +#define IFAR p15, 0, c6, c0, 2 + /******************************************************************************* * Definitions of MAIR encodings for device and normal memory ******************************************************************************/ @@ -715,8 +761,25 @@ #define AMEVTYPER1E p15, 0, c13, c15, 6 #define AMEVTYPER1F p15, 0, c13, c15, 7 +/* AMCNTENSET0 definitions */ +#define AMCNTENSET0_Pn_SHIFT U(0) +#define AMCNTENSET0_Pn_MASK U(0xffff) + +/* AMCNTENSET1 definitions */ +#define AMCNTENSET1_Pn_SHIFT U(0) +#define AMCNTENSET1_Pn_MASK U(0xffff) + +/* AMCNTENCLR0 definitions */ +#define AMCNTENCLR0_Pn_SHIFT U(0) +#define AMCNTENCLR0_Pn_MASK U(0xffff) + +/* AMCNTENCLR1 definitions */ +#define AMCNTENCLR1_Pn_SHIFT U(0) +#define AMCNTENCLR1_Pn_MASK U(0xffff) + /* AMCR definitions */ -#define AMCR_CG1RZ_BIT (ULL(1) << 17) +#define AMCR_CG1RZ_SHIFT U(17) +#define AMCR_CG1RZ_BIT (ULL(1) << AMCR_CG1RZ_SHIFT) /* AMCFGR definitions */ #define AMCFGR_NCG_SHIFT U(28) @@ -725,6 +788,8 @@ #define AMCFGR_N_MASK U(0xff) /* AMCGCR definitions */ +#define AMCGCR_CG0NC_SHIFT U(0) +#define AMCGCR_CG0NC_MASK U(0xff) #define AMCGCR_CG1NC_SHIFT U(8) #define AMCGCR_CG1NC_MASK U(0xff) @@ -737,5 +802,6 @@ #define DSU_CLUSTER_PWR_OFF 0 #define DSU_CLUSTER_PWR_ON 1 #define DSU_CLUSTER_PWR_MASK U(1) +#define DSU_CLUSTER_MEM_RET BIT(1) #endif /* ARCH_H */ diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h index ddf09680be..b52e4d062e 100644 --- a/include/arch/aarch32/arch_features.h +++ b/include/arch/aarch32/arch_features.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,17 +10,198 @@ #include <stdbool.h> #include <arch_helpers.h> +#include <common/feat_detect.h> + +#define ISOLATE_FIELD(reg, feat) \ + ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK))) static inline bool is_armv7_gentimer_present(void) { - return ((read_id_pfr1() >> ID_PFR1_GENTIMER_SHIFT) & - ID_PFR1_GENTIMER_MASK) != 0U; + return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER) != 0U; } static inline bool is_armv8_2_ttcnp_present(void) { - return ((read_id_mmfr4() >> ID_MMFR4_CNP_SHIFT) & - ID_MMFR4_CNP_MASK) != 0U; + return ISOLATE_FIELD(read_id_mmfr4(), ID_MMFR4_CNP) != 0U; +} + +static unsigned int read_feat_amu_id_field(void) +{ + return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_AMU); +} + +static inline bool is_feat_amu_supported(void) +{ + if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_amu_id_field() >= ID_PFR0_AMU_V1; +} + +static inline bool is_feat_amuv1p1_supported(void) +{ + if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_amu_id_field() >= ID_PFR0_AMU_V1P1; +} + +static inline unsigned int read_feat_trf_id_field(void) +{ + return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_TRACEFILT); +} + +static inline bool is_feat_trf_supported(void) +{ + if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_trf_id_field() != 0U; +} + +static inline unsigned int read_feat_coptrc_id_field(void) +{ + return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_COPTRC); +} + +static inline bool is_feat_sys_reg_trace_supported(void) +{ + if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_coptrc_id_field() != 0U; +} + +static inline unsigned int read_feat_dit_id_field(void) +{ + return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_DIT); +} + +static inline bool is_feat_dit_supported(void) +{ + if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_dit_id_field() != 0U; +} + +static inline unsigned int read_feat_pan_id_field(void) +{ + return ISOLATE_FIELD(read_id_mmfr3(), ID_MMFR3_PAN); +} + +static inline bool is_feat_pan_supported(void) +{ + if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_pan_id_field() != 0U; +} + +static inline bool is_feat_pan_present(void) +{ + return read_feat_pan_id_field() != 0U; +} + +static inline unsigned int is_feat_ssbs_present(void) +{ + return ((read_id_pfr2() >> ID_PFR2_SSBS_SHIFT) & + ID_PFR2_SSBS_MASK) != SSBS_UNAVAILABLE; +} + +/* + * TWED, ECV, CSV2, RAS are only used by the AArch64 EL2 context switch + * code. In fact, EL2 context switching is only needed for AArch64 (since + * there is no secure AArch32 EL2), so just disable these features here. + */ +static inline bool is_feat_twed_supported(void) { return false; } +static inline bool is_feat_ecv_supported(void) { return false; } +static inline bool is_feat_ecv_v2_supported(void) { return false; } +static inline bool is_feat_csv2_2_supported(void) { return false; } +static inline bool is_feat_csv2_3_supported(void) { return false; } +static inline bool is_feat_ras_supported(void) { return false; } + +/* The following features are supported in AArch64 only. */ +static inline bool is_feat_vhe_supported(void) { return false; } +static inline bool is_feat_sel2_supported(void) { return false; } +static inline bool is_feat_fgt_supported(void) { return false; } +static inline bool is_feat_tcr2_supported(void) { return false; } +static inline bool is_feat_spe_supported(void) { return false; } +static inline bool is_feat_rng_supported(void) { return false; } +static inline bool is_feat_gcs_supported(void) { return false; } +static inline bool is_feat_mte2_supported(void) { return false; } +static inline bool is_feat_mpam_supported(void) { return false; } +static inline bool is_feat_hcx_supported(void) { return false; } +static inline bool is_feat_sve_supported(void) { return false; } +static inline bool is_feat_brbe_supported(void) { return false; } +static inline bool is_feat_trbe_supported(void) { return false; } +static inline bool is_feat_nv2_supported(void) { return false; } +static inline bool is_feat_sme_supported(void) { return false; } +static inline bool is_feat_sme2_supported(void) { return false; } +static inline bool is_feat_s2poe_supported(void) { return false; } +static inline bool is_feat_s1poe_supported(void) { return false; } +static inline bool is_feat_sxpoe_supported(void) { return false; } +static inline bool is_feat_s2pie_supported(void) { return false; } +static inline bool is_feat_s1pie_supported(void) { return false; } +static inline bool is_feat_sxpie_supported(void) { return false; } +static inline bool is_feat_uao_present(void) { return false; } +static inline bool is_feat_nmi_present(void) { return false; } +static inline bool is_feat_ebep_present(void) { return false; } +static inline bool is_feat_sebep_present(void) { return false; } + +static inline unsigned int read_feat_pmuv3_id_field(void) +{ + return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_PERFMON); +} + +static inline unsigned int read_feat_mtpmu_id_field(void) +{ + return ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU); +} + +static inline bool is_feat_mtpmu_supported(void) +{ + if (DISABLE_MTPMU == FEAT_STATE_DISABLED) { + return false; + } + + if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) { + return true; + } + + unsigned int mtpmu = read_feat_mtpmu_id_field(); + + return mtpmu != 0U && mtpmu != ID_DFR1_MTPMU_DISABLED; } #endif /* ARCH_FEATURES_H */ diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h index 726baf596e..3244d3b2ae 100644 --- a/include/arch/aarch32/arch_helpers.h +++ b/include/arch/aarch32/arch_helpers.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +8,7 @@ #ifndef ARCH_HELPERS_H #define ARCH_HELPERS_H +#include <assert.h> #include <cdefs.h> #include <stdbool.h> #include <stdint.h> @@ -216,9 +218,13 @@ DEFINE_SYSREG_RW_FUNCS(cpsr) ******************************************************************************/ DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR) DEFINE_COPROCR_READ_FUNC(midr, MIDR) +DEFINE_COPROCR_READ_FUNC(id_mmfr3, ID_MMFR3) DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4) +DEFINE_COPROCR_READ_FUNC(id_dfr0, ID_DFR0) +DEFINE_COPROCR_READ_FUNC(id_dfr1, ID_DFR1) DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0) DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1) +DEFINE_COPROCR_READ_FUNC(id_pfr2, ID_PFR2) DEFINE_COPROCR_READ_FUNC(isr, ISR) DEFINE_COPROCR_READ_FUNC(clidr, CLIDR) DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64) @@ -281,10 +287,12 @@ DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0) DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1) DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64) DEFINE_COPROCR_WRITE_FUNC_64(icc_sgi1r, ICC_SGI1R_EL1_64) +DEFINE_COPROCR_WRITE_FUNC_64(icc_asgi1r, ICC_ASGI1R_EL1_64) +DEFINE_COPROCR_RW_FUNCS(sdcr, SDCR) DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR) DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL) -DEFINE_COPROCR_READ_FUNC(pmcr, PMCR) +DEFINE_COPROCR_RW_FUNCS(pmcr, PMCR) /* * Address translation @@ -347,6 +355,17 @@ DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC) */ DEFINE_COPROCR_RW_FUNCS(clusterpwrdn, CLUSTERPWRDN) +/* + * RNDR is AArch64 only, so just provide a placeholder here to make the + * linker happy. + */ +static inline u_register_t read_rndr(void) +{ + assert(1); + + return 0; +} + /* Previously defined accessor functions with incomplete register names */ #define dsb() dsbsy() #define dmb() dmbsy() @@ -400,6 +419,8 @@ static inline unsigned int get_current_el(void) #define read_ctr_el0() read_ctr() #define write_icc_sgi0r_el1(_v) write64_icc_sgi0r_el1(_v) +#define write_icc_sgi1r(_v) write64_icc_sgi1r(_v) +#define write_icc_asgi1r(_v) write64_icc_asgi1r(_v) #define read_daif() read_cpsr() #define write_daif(flags) write_cpsr(flags) diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S index 483f9fe056..3ba86e956d 100644 --- a/include/arch/aarch32/asm_macros.S +++ b/include/arch/aarch32/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include <arch.h> #include <common/asm_macros_common.S> +#include <lib/cpus/cpu_ops.h> #include <lib/spinlock.h> /* @@ -24,8 +25,6 @@ stcopr _reg, _coproc #endif -#define WORD_SIZE 4 - /* * Co processor register accessors */ @@ -49,14 +48,14 @@ .macro dcache_line_size reg, tmp ldcopr \tmp, CTR ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH - mov \reg, #WORD_SIZE + mov \reg, #CPU_WORD_SIZE lsl \reg, \reg, \tmp .endm .macro icache_line_size reg, tmp ldcopr \tmp, CTR and \tmp, \tmp, #CTR_IMINLINE_MASK - mov \reg, #WORD_SIZE + mov \reg, #CPU_WORD_SIZE lsl \reg, \reg, \tmp .endm @@ -121,6 +120,14 @@ .endm #endif + /* Macro for error synchronization */ + .macro synchronize_errors + /* Complete any stores that may return an abort */ + dsb sy + /* Synchronise the CPU context with the completion of the dsb */ + isb + .endm + #if (ARM_ARCH_MAJOR == 7) /* ARMv7 does not support stl instruction */ .macro stl _reg, _write_lock diff --git a/include/arch/aarch32/console_macros.S b/include/arch/aarch32/console_macros.S index 996cb327f3..726b28186f 100644 --- a/include/arch/aarch32/console_macros.S +++ b/include/arch/aarch32/console_macros.S @@ -29,12 +29,20 @@ .endif str r1, [r0, #CONSOLE_T_PUTC] + /* + * If ENABLE_CONSOLE_GETC support is disabled, but a getc callback is + * specified nonetheless, the assembler will abort on encountering the + * CONSOLE_T_GETC macro, which is undefined. + */ .ifne \getc ldr r1, =console_\_driver\()_getc + str r1, [r0, #CONSOLE_T_GETC] .else +#if ENABLE_CONSOLE_GETC mov r1, #0 + str r1, [r0, #CONSOLE_T_GETC] +#endif .endif - str r1, [r0, #CONSOLE_T_GETC] .ifne \flush ldr r1, =console_\_driver\()_flush diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 7fff4c754e..697eb82c1f 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,11 +63,23 @@ * cp11 field is ignored, but is set to same value as cp10. The cp10 * field is set to allow access to Advanced SIMD and floating point * features from both Security states. + * + * NSACR.NSTRCDIS: When system register trace implemented, Set to one + * so that NS System register accesses to all implemented trace + * registers are disabled. + * When system register trace is not implemented, this bit is RES0 and + * hence set to zero. * --------------------------------------------------------------------- */ ldcopr r0, NSACR and r0, r0, #NSACR_IMP_DEF_MASK orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS) + ldcopr r1, ID_DFR0 + ubfx r1, r1, #ID_DFR0_COPTRC_SHIFT, #ID_DFR0_COPTRC_LENGTH + cmp r1, #ID_DFR0_COPTRC_SUPPORTED + bne 1f + orr r0, r0, #NSTRCDIS_BIT +1: stcopr r0, NSACR isb @@ -119,9 +131,22 @@ * in Secure state. This bit is RES0 in versions of the architecture * earlier than ARMv8.5, setting it to 1 doesn't have any effect on * them. + * + * SDCR.TTRF: Set to one so that access to trace filter control + * registers in non-monitor mode generate Monitor trap exception, + * unless the access generates a higher priority exception when + * trace filter control(FEAT_TRF) is implemented. + * When FEAT_TRF is not implemented, this bit is RES0. * --------------------------------------------------------------------- */ - ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT) + ldr r0, =((SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | \ + SDCR_SCCD_BIT) & ~SDCR_TTRF_BIT) + ldcopr r1, ID_DFR0 + ubfx r1, r1, #ID_DFR0_TRACEFILT_SHIFT, #ID_DFR0_TRACEFILT_LENGTH + cmp r1, #ID_DFR0_TRACEFILT_SUPPORTED + bne 1f + orr r0, r0, #SDCR_TTRF_BIT +1: stcopr r0, SDCR /* --------------------------------------------------------------------- @@ -252,10 +277,6 @@ cps #MODE32_mon isb -#if DISABLE_MTPMU - bl mtpmu_disable -#endif - .if \_warm_boot_mailbox /* ------------------------------------------------------------- * This code will be executed for both warm and cold resets. @@ -349,19 +370,36 @@ * --------------------------------------------------------------------- */ .if \_init_c_runtime -#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3) +#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && RESET_TO_BL2) /* ----------------------------------------------------------------- * Invalidate the RW memory used by the image. This * includes the data and NOBITS sections. This is done to * safeguard against possible corruption of this memory by * dirty cache lines in a system cache as a result of use by - * an earlier boot loader stage. + * an earlier boot loader stage. If PIE is enabled however, + * RO sections including the GOT may be modified during + * pie fixup. Therefore, to be on the safe side, invalidate + * the entire image region if PIE is enabled. * ----------------------------------------------------------------- */ +#if ENABLE_PIE +#if SEPARATE_CODE_AND_RODATA + ldr r0, =__TEXT_START__ +#else + ldr r0, =__RO_START__ +#endif /* SEPARATE_CODE_AND_RODATA */ +#else ldr r0, =__RW_START__ +#endif /* ENABLE_PIE */ ldr r1, =__RW_END__ sub r1, r1, r0 bl inv_dcache_range +#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION + ldr r0, =__BL2_NOLOAD_START__ + ldr r1, =__BL2_NOLOAD_END__ + sub r1, r1, r0 + bl inv_dcache_range +#endif #endif /* @@ -384,7 +422,8 @@ /* Restore r12 */ mov r12, r7 -#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) +#if defined(IMAGE_BL1) || \ + (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) /* ----------------------------------------------------- * Copy data from ROM to RAM. * ----------------------------------------------------- diff --git a/include/arch/aarch32/smccc_helpers.h b/include/arch/aarch32/smccc_helpers.h index 2ce7874ef2..8876da9e47 100644 --- a/include/arch/aarch32/smccc_helpers.h +++ b/include/arch/aarch32/smccc_helpers.h @@ -90,21 +90,21 @@ typedef struct smc_ctx { * ensure that the assembler and the compiler view of the offsets of * the structure members is the same. */ -CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \ +CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), assert_smc_ctx_greg_r0_offset_mismatch); -CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \ +CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), assert_smc_ctx_greg_r1_offset_mismatch); -CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \ +CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), assert_smc_ctx_greg_r2_offset_mismatch); -CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \ +CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), assert_smc_ctx_greg_r3_offset_mismatch); -CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \ +CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), assert_smc_ctx_greg_r4_offset_mismatch); -CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \ +CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), assert_smc_ctx_sp_usr_offset_mismatch); -CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \ +CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), assert_smc_ctx_lr_mon_offset_mismatch); -CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \ +CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), assert_smc_ctx_spsr_mon_offset_mismatch); CASSERT((sizeof(smc_ctx_t) & 0x7U) == 0U, assert_smc_ctx_not_aligned); diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 9ef9c26894..ee86b7e957 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -75,10 +75,24 @@ #define INVALID_MPID U(0xFFFFFFFF) /******************************************************************************* + * Definitions for Exception vector offsets + ******************************************************************************/ +#define CURRENT_EL_SP0 0x0 +#define CURRENT_EL_SPX 0x200 +#define LOWER_EL_AARCH64 0x400 +#define LOWER_EL_AARCH32 0x600 + +#define SYNC_EXCEPTION 0x0 +#define IRQ_EXCEPTION 0x80 +#define FIQ_EXCEPTION 0x100 +#define SERROR_EXCEPTION 0x180 + +/******************************************************************************* * Definitions for CPU system register interface to GICv3 ******************************************************************************/ #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 #define ICC_SGI1R S3_0_C12_C11_5 +#define ICC_ASGI1R S3_0_C12_C11_6 #define ICC_SRE_EL1 S3_0_C12_C12_5 #define ICC_SRE_EL2 S3_4_C12_C9_5 #define ICC_SRE_EL3 S3_6_C12_C12_5 @@ -99,7 +113,6 @@ /******************************************************************************* * Definitions for EL2 system registers for save/restore routine ******************************************************************************/ - #define CNTPOFF_EL2 S3_4_C14_C0_6 #define HAFGRTR_EL2 S3_4_C3_C1_6 #define HDFGRTR_EL2 S3_4_C3_C1_4 @@ -109,18 +122,21 @@ #define HFGWTR_EL2 S3_4_C1_C1_5 #define ICH_HCR_EL2 S3_4_C12_C11_0 #define ICH_VMCR_EL2 S3_4_C12_C11_7 -#define MPAMVPM0_EL2 S3_4_C10_C5_0 -#define MPAMVPM1_EL2 S3_4_C10_C5_1 -#define MPAMVPM2_EL2 S3_4_C10_C5_2 -#define MPAMVPM3_EL2 S3_4_C10_C5_3 -#define MPAMVPM4_EL2 S3_4_C10_C5_4 -#define MPAMVPM5_EL2 S3_4_C10_C5_5 -#define MPAMVPM6_EL2 S3_4_C10_C5_6 -#define MPAMVPM7_EL2 S3_4_C10_C5_7 +#define MPAMVPM0_EL2 S3_4_C10_C6_0 +#define MPAMVPM1_EL2 S3_4_C10_C6_1 +#define MPAMVPM2_EL2 S3_4_C10_C6_2 +#define MPAMVPM3_EL2 S3_4_C10_C6_3 +#define MPAMVPM4_EL2 S3_4_C10_C6_4 +#define MPAMVPM5_EL2 S3_4_C10_C6_5 +#define MPAMVPM6_EL2 S3_4_C10_C6_6 +#define MPAMVPM7_EL2 S3_4_C10_C6_7 #define MPAMVPMV_EL2 S3_4_C10_C4_1 #define TRFCR_EL2 S3_4_C1_C2_1 +#define VNCR_EL2 S3_4_C2_C2_0 #define PMSCR_EL2 S3_4_C9_C9_0 #define TFSR_EL2 S3_4_C5_C6_0 +#define CONTEXTIDR_EL2 S3_4_C13_C0_1 +#define TTBR1_EL2 S3_4_C2_C0_1 /******************************************************************************* * Generic timer memory mapped registers & offsets @@ -154,62 +170,145 @@ #define DCCSW U(0x2) #endif +#define ID_REG_FIELD_MASK ULL(0xf) + /* ID_AA64PFR0_EL1 definitions */ -#define ID_AA64PFR0_EL0_SHIFT U(0) -#define ID_AA64PFR0_EL1_SHIFT U(4) -#define ID_AA64PFR0_EL2_SHIFT U(8) -#define ID_AA64PFR0_EL3_SHIFT U(12) -#define ID_AA64PFR0_AMU_SHIFT U(44) -#define ID_AA64PFR0_AMU_MASK ULL(0xf) -#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) -#define ID_AA64PFR0_AMU_V1 U(0x1) -#define ID_AA64PFR0_AMU_V1P1 U(0x2) -#define ID_AA64PFR0_ELX_MASK ULL(0xf) -#define ID_AA64PFR0_GIC_SHIFT U(24) -#define ID_AA64PFR0_GIC_WIDTH U(4) -#define ID_AA64PFR0_GIC_MASK ULL(0xf) -#define ID_AA64PFR0_SVE_SHIFT U(32) -#define ID_AA64PFR0_SVE_MASK ULL(0xf) -#define ID_AA64PFR0_SEL2_SHIFT U(36) -#define ID_AA64PFR0_SEL2_MASK ULL(0xf) -#define ID_AA64PFR0_MPAM_SHIFT U(40) -#define ID_AA64PFR0_MPAM_MASK ULL(0xf) -#define ID_AA64PFR0_DIT_SHIFT U(48) -#define ID_AA64PFR0_DIT_MASK ULL(0xf) -#define ID_AA64PFR0_DIT_LENGTH U(4) -#define ID_AA64PFR0_DIT_SUPPORTED U(1) -#define ID_AA64PFR0_CSV2_SHIFT U(56) -#define ID_AA64PFR0_CSV2_MASK ULL(0xf) -#define ID_AA64PFR0_CSV2_LENGTH U(4) +#define ID_AA64PFR0_EL0_SHIFT U(0) +#define ID_AA64PFR0_EL1_SHIFT U(4) +#define ID_AA64PFR0_EL2_SHIFT U(8) +#define ID_AA64PFR0_EL3_SHIFT U(12) + +#define ID_AA64PFR0_AMU_SHIFT U(44) +#define ID_AA64PFR0_AMU_MASK ULL(0xf) +#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) +#define ID_AA64PFR0_AMU_V1 ULL(0x1) +#define ID_AA64PFR0_AMU_V1P1 U(0x2) + +#define ID_AA64PFR0_ELX_MASK ULL(0xf) + +#define ID_AA64PFR0_GIC_SHIFT U(24) +#define ID_AA64PFR0_GIC_WIDTH U(4) +#define ID_AA64PFR0_GIC_MASK ULL(0xf) + +#define ID_AA64PFR0_SVE_SHIFT U(32) +#define ID_AA64PFR0_SVE_MASK ULL(0xf) +#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) +#define ID_AA64PFR0_SVE_LENGTH U(4) + +#define ID_AA64PFR0_SEL2_SHIFT U(36) +#define ID_AA64PFR0_SEL2_MASK ULL(0xf) + +#define ID_AA64PFR0_MPAM_SHIFT U(40) +#define ID_AA64PFR0_MPAM_MASK ULL(0xf) + +#define ID_AA64PFR0_DIT_SHIFT U(48) +#define ID_AA64PFR0_DIT_MASK ULL(0xf) +#define ID_AA64PFR0_DIT_LENGTH U(4) +#define ID_AA64PFR0_DIT_SUPPORTED U(1) + +#define ID_AA64PFR0_CSV2_SHIFT U(56) +#define ID_AA64PFR0_CSV2_MASK ULL(0xf) +#define ID_AA64PFR0_CSV2_LENGTH U(4) +#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) +#define ID_AA64PFR0_CSV2_3_SUPPORTED ULL(0x3) + +#define ID_AA64PFR0_FEAT_RME_SHIFT U(52) +#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) +#define ID_AA64PFR0_FEAT_RME_LENGTH U(4) +#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) +#define ID_AA64PFR0_FEAT_RME_V1 U(1) + +#define ID_AA64PFR0_RAS_SHIFT U(28) +#define ID_AA64PFR0_RAS_MASK ULL(0xf) +#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) +#define ID_AA64PFR0_RAS_LENGTH U(4) /* Exception level handling */ #define EL_IMPL_NONE ULL(0) #define EL_IMPL_A64ONLY ULL(1) #define EL_IMPL_A64_A32 ULL(2) +/* ID_AA64DFR0_EL1.TraceVer definitions */ +#define ID_AA64DFR0_TRACEVER_SHIFT U(4) +#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) +#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) +#define ID_AA64DFR0_TRACEVER_LENGTH U(4) +#define ID_AA64DFR0_TRACEFILT_SHIFT U(40) +#define ID_AA64DFR0_TRACEFILT_MASK U(0xf) +#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) +#define ID_AA64DFR0_TRACEFILT_LENGTH U(4) +#define ID_AA64DFR0_PMUVER_LENGTH U(4) +#define ID_AA64DFR0_PMUVER_SHIFT U(8) +#define ID_AA64DFR0_PMUVER_MASK U(0xf) +#define ID_AA64DFR0_PMUVER_PMUV3 U(1) +#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7) +#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) + +/* ID_AA64DFR0_EL1.SEBEP definitions */ +#define ID_AA64DFR0_SEBEP_SHIFT U(24) +#define ID_AA64DFR0_SEBEP_MASK ULL(0xf) +#define SEBEP_IMPLEMENTED ULL(1) + /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ -#define ID_AA64DFR0_PMS_SHIFT U(32) -#define ID_AA64DFR0_PMS_MASK ULL(0xf) +#define ID_AA64DFR0_PMS_SHIFT U(32) +#define ID_AA64DFR0_PMS_MASK ULL(0xf) +#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) +#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) + +/* ID_AA64DFR0_EL1.TraceBuffer definitions */ +#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) +#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) +#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ #define ID_AA64DFR0_MTPMU_SHIFT U(48) #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) +#define ID_AA64DFR0_MTPMU_DISABLED ULL(15) + +/* ID_AA64DFR0_EL1.BRBE definitions */ +#define ID_AA64DFR0_BRBE_SHIFT U(52) +#define ID_AA64DFR0_BRBE_MASK ULL(0xf) +#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) + +/* ID_AA64DFR1_EL1 definitions */ +#define ID_AA64DFR1_EBEP_SHIFT U(48) +#define ID_AA64DFR1_EBEP_MASK ULL(0xf) +#define EBEP_IMPLEMENTED ULL(1) /* ID_AA64ISAR0_EL1 definitions */ -#define ID_AA64ISAR0_RNDR_SHIFT U(60) -#define ID_AA64ISAR0_RNDR_MASK ULL(0xf) +#define ID_AA64ISAR0_RNDR_SHIFT U(60) +#define ID_AA64ISAR0_RNDR_MASK ULL(0xf) /* ID_AA64ISAR1_EL1 definitions */ -#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 -#define ID_AA64ISAR1_GPI_SHIFT U(28) -#define ID_AA64ISAR1_GPI_MASK ULL(0xf) -#define ID_AA64ISAR1_GPA_SHIFT U(24) -#define ID_AA64ISAR1_GPA_MASK ULL(0xf) -#define ID_AA64ISAR1_API_SHIFT U(8) -#define ID_AA64ISAR1_API_MASK ULL(0xf) -#define ID_AA64ISAR1_APA_SHIFT U(4) -#define ID_AA64ISAR1_APA_MASK ULL(0xf) +#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 + +#define ID_AA64ISAR1_GPI_SHIFT U(28) +#define ID_AA64ISAR1_GPI_MASK ULL(0xf) +#define ID_AA64ISAR1_GPA_SHIFT U(24) +#define ID_AA64ISAR1_GPA_MASK ULL(0xf) + +#define ID_AA64ISAR1_API_SHIFT U(8) +#define ID_AA64ISAR1_API_MASK ULL(0xf) +#define ID_AA64ISAR1_APA_SHIFT U(4) +#define ID_AA64ISAR1_APA_MASK ULL(0xf) + +#define ID_AA64ISAR1_SB_SHIFT U(36) +#define ID_AA64ISAR1_SB_MASK ULL(0xf) +#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) +#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) + +/* ID_AA64ISAR2_EL1 definitions */ +#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 + +/* ID_AA64PFR2_EL1 definitions */ +#define ID_AA64PFR2_EL1 S3_0_C0_C4_2 + +#define ID_AA64ISAR2_GPA3_SHIFT U(8) +#define ID_AA64ISAR2_GPA3_MASK ULL(0xf) + +#define ID_AA64ISAR2_APA3_SHIFT U(12) +#define ID_AA64ISAR2_APA3_MASK ULL(0xf) /* ID_AA64MMFR0_EL1 definitions */ #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) @@ -237,6 +336,7 @@ #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1) #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) @@ -248,6 +348,7 @@ #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2) /* ID_AA64MMFR1_EL1 definitions */ #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) @@ -262,29 +363,94 @@ #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) +#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) +#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) + +#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) +#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) +#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) +#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) + /* ID_AA64MMFR2_EL1 definitions */ -#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 -#define ID_AA64MMFR2_EL1_ST_SHIFT U(28) -#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_ST_SHIFT U(28) +#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) -#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) -#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) +#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) -/* ID_AA64PFR1_EL1 definitions */ -#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) -#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) +#define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) -#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ +#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) +#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) + +#define ID_AA64MMFR2_EL1_NV_SHIFT U(24) +#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) +#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) + +/* ID_AA64MMFR3_EL1 definitions */ +#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 + +#define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) +#define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) + +#define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) +#define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) + +#define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) +#define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) + +#define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) +#define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) + +#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) +#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) + +/* ID_AA64PFR1_EL1 definitions */ #define ID_AA64PFR1_EL1_BT_SHIFT U(0) #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) - #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ +#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) +#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) +#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ + #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) +#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) +#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) + +#define ID_AA64PFR1_EL1_NMI_SHIFT U(36) +#define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) +#define NMI_IMPLEMENTED ULL(1) + +#define ID_AA64PFR1_EL1_GCS_SHIFT U(44) +#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) +#define GCS_IMPLEMENTED ULL(1) + +#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) +#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) + +/* ID_AA64PFR2_EL1 definitions */ +#define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) +#define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) + +#define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) +#define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) + +#define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) +#define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) + +#define VDISR_EL2 S3_4_C12_C1_1 +#define VSESR_EL2 S3_4_C5_C2_3 + /* Memory Tagging Extension is not implemented */ #define MTE_UNIMPLEMENTED U(0) /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ @@ -300,6 +466,13 @@ #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) +#define ID_AA64PFR1_EL1_SME_SHIFT U(24) +#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) +#define ID_AA64PFR1_EL1_SME_WIDTH U(4) +#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) +#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) +#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) + /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) #define ID_PFR1_VIRTEXT_MASK U(0xf) @@ -359,6 +532,8 @@ #define SCTLR_ITFSB_BIT (ULL(1) << 37) #define SCTLR_TCF0_SHIFT U(38) #define SCTLR_TCF0_MASK ULL(3) +#define SCTLR_ENTP2_BIT (ULL(1) << 60) +#define SCTLR_SPINTMASK_BIT (ULL(1) << 62) /* Tag Check Faults in EL0 have no effect on the PE */ #define SCTLR_TCF0_NO_EFFECT U(0) @@ -389,7 +564,8 @@ #define SCTLR_ATA0_BIT (ULL(1) << 42) #define SCTLR_ATA_BIT (ULL(1) << 43) -#define SCTLR_DSSBS_BIT (ULL(1) << 44) +#define SCTLR_DSSBS_SHIFT U(44) +#define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) #define SCTLR_TWEDEn_BIT (ULL(1) << 45) #define SCTLR_TWEDEL_SHIFT U(46) #define SCTLR_TWEDEL_MASK ULL(0xf) @@ -404,16 +580,30 @@ #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) #define CPACR_EL1_FP_TRAP_ALL UL(0x2) #define CPACR_EL1_FP_TRAP_NONE UL(0x3) +#define CPACR_EL1_SMEN_SHIFT U(24) +#define CPACR_EL1_SMEN_MASK ULL(0x3) /* SCR definitions */ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) +#define SCR_NSE_SHIFT U(62) +#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) +#define SCR_GPF_BIT (UL(1) << 48) #define SCR_TWEDEL_SHIFT U(30) #define SCR_TWEDEL_MASK ULL(0xf) -#define SCR_AMVOFFEN_BIT (UL(1) << 35) +#define SCR_PIEN_BIT (UL(1) << 45) +#define SCR_TCR2EN_BIT (UL(1) << 43) +#define SCR_TRNDR_BIT (UL(1) << 40) +#define SCR_GCSEn_BIT (UL(1) << 39) +#define SCR_HXEn_BIT (UL(1) << 38) +#define SCR_ENTP2_SHIFT U(41) +#define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) +#define SCR_AMVOFFEN_SHIFT U(35) +#define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) #define SCR_TWEDEn_BIT (UL(1) << 29) #define SCR_ECVEN_BIT (UL(1) << 28) #define SCR_FGTEN_BIT (UL(1) << 27) #define SCR_ATA_BIT (UL(1) << 26) +#define SCR_EnSCXT_BIT (UL(1) << 25) #define SCR_FIEN_BIT (UL(1) << 21) #define SCR_EEL2_BIT (UL(1) << 18) #define SCR_API_BIT (UL(1) << 17) @@ -430,13 +620,18 @@ #define SCR_FIQ_BIT (UL(1) << 2) #define SCR_IRQ_BIT (UL(1) << 1) #define SCR_NS_BIT (UL(1) << 0) -#define SCR_VALID_BIT_MASK U(0x2f8f) +#define SCR_VALID_BIT_MASK U(0x24000002F8F) #define SCR_RESET_VAL SCR_RES1_BITS /* MDCR_EL3 definitions */ #define MDCR_EnPMSN_BIT (ULL(1) << 36) #define MDCR_MPMX_BIT (ULL(1) << 35) #define MDCR_MCCD_BIT (ULL(1) << 34) +#define MDCR_SBRBE_SHIFT U(32) +#define MDCR_SBRBE_MASK ULL(0x3) +#define MDCR_NSTB(x) ((x) << 24) +#define MDCR_NSTB_EL1 ULL(0x3) +#define MDCR_NSTBE_BIT (ULL(1) << 26) #define MDCR_MTPME_BIT (ULL(1) << 28) #define MDCR_TDCC_BIT (ULL(1) << 27) #define MDCR_SCCD_BIT (ULL(1) << 23) @@ -452,17 +647,20 @@ #define MDCR_SPD32_ENABLE ULL(0x3) #define MDCR_NSPB(x) ((x) << 12) #define MDCR_NSPB_EL1 ULL(0x3) +#define MDCR_NSPBE_BIT (ULL(1) << 11) #define MDCR_TDOSA_BIT (ULL(1) << 10) #define MDCR_TDA_BIT (ULL(1) << 9) #define MDCR_TPM_BIT (ULL(1) << 6) -#define MDCR_EL3_RESET_VAL ULL(0x0) +#define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT /* MDCR_EL2 definitions */ #define MDCR_EL2_MTPME (U(1) << 28) -#define MDCR_EL2_HLP (U(1) << 26) -#define MDCR_EL2_HCCD (U(1) << 23) +#define MDCR_EL2_HLP_BIT (U(1) << 26) +#define MDCR_EL2_E2TB(x) ((x) << 24) +#define MDCR_EL2_E2TB_EL1 U(0x3) +#define MDCR_EL2_HCCD_BIT (U(1) << 23) #define MDCR_EL2_TTRF (U(1) << 19) -#define MDCR_EL2_HPMD (U(1) << 17) +#define MDCR_EL2_HPMD_BIT (U(1) << 17) #define MDCR_EL2_TPMS (U(1) << 14) #define MDCR_EL2_E2PB(x) ((x) << 12) #define MDCR_EL2_E2PB_EL1 U(0x3) @@ -473,6 +671,7 @@ #define MDCR_EL2_HPME_BIT (U(1) << 7) #define MDCR_EL2_TPM_BIT (U(1) << 6) #define MDCR_EL2_TPMCR_BIT (U(1) << 5) +#define MDCR_EL2_HPMN_MASK U(0x1f) #define MDCR_EL2_RESET_VAL U(0x0) /* HSTR_EL2 definitions */ @@ -491,13 +690,19 @@ #define VTTBR_BADDR_SHIFT U(0) /* HCR definitions */ -#define HCR_AMVOFFEN_BIT (ULL(1) << 51) +#define HCR_RESET_VAL ULL(0x0) +#define HCR_AMVOFFEN_SHIFT U(51) +#define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) +#define HCR_TEA_BIT (ULL(1) << 47) #define HCR_API_BIT (ULL(1) << 41) #define HCR_APK_BIT (ULL(1) << 40) #define HCR_E2H_BIT (ULL(1) << 34) +#define HCR_HCD_BIT (ULL(1) << 29) #define HCR_TGE_BIT (ULL(1) << 27) #define HCR_RW_SHIFT U(31) #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) +#define HCR_TWE_BIT (ULL(1) << 14) +#define HCR_TWI_BIT (ULL(1) << 13) #define HCR_AMO_BIT (ULL(1) << 5) #define HCR_IMO_BIT (ULL(1) << 4) #define HCR_FMO_BIT (ULL(1) << 3) @@ -525,26 +730,41 @@ /* CPTR_EL3 definitions */ #define TCPAC_BIT (U(1) << 31) -#define TAM_BIT (U(1) << 30) +#define TAM_SHIFT U(30) +#define TAM_BIT (U(1) << TAM_SHIFT) #define TTA_BIT (U(1) << 20) +#define ESM_BIT (U(1) << 12) #define TFP_BIT (U(1) << 10) #define CPTR_EZ_BIT (U(1) << 8) -#define CPTR_EL3_RESET_VAL U(0x0) +#define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ + ~(CPTR_EZ_BIT | ESM_BIT)) /* CPTR_EL2 definitions */ #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) #define CPTR_EL2_TCPAC_BIT (U(1) << 31) -#define CPTR_EL2_TAM_BIT (U(1) << 30) +#define CPTR_EL2_TAM_SHIFT U(30) +#define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) +#define CPTR_EL2_SMEN_MASK ULL(0x3) +#define CPTR_EL2_SMEN_SHIFT U(24) #define CPTR_EL2_TTA_BIT (U(1) << 20) +#define CPTR_EL2_TSM_BIT (U(1) << 12) #define CPTR_EL2_TFP_BIT (U(1) << 10) #define CPTR_EL2_TZ_BIT (U(1) << 8) #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 +/* VTCR_EL2 definitions */ +#define VTCR_RESET_VAL U(0x0) +#define VTCR_EL2_MSA (U(1) << 31) + /* CPSR/SPSR definitions */ #define DAIF_FIQ_BIT (U(1) << 0) #define DAIF_IRQ_BIT (U(1) << 1) #define DAIF_ABT_BIT (U(1) << 2) #define DAIF_DBG_BIT (U(1) << 3) +#define SPSR_V_BIT (U(1) << 28) +#define SPSR_C_BIT (U(1) << 29) +#define SPSR_Z_BIT (U(1) << 30) +#define SPSR_N_BIT (U(1) << 31) #define SPSR_DAIF_SHIFT U(6) #define SPSR_DAIF_MASK U(0xf) @@ -565,16 +785,32 @@ #define SPSR_M_MASK U(0x1) #define SPSR_M_AARCH64 U(0x0) #define SPSR_M_AARCH32 U(0x1) +#define SPSR_M_EL1H U(0x5) +#define SPSR_M_EL2H U(0x9) #define SPSR_EL_SHIFT U(2) #define SPSR_EL_WIDTH U(2) -#define SPSR_SSBS_BIT_AARCH64 BIT_64(12) -#define SPSR_SSBS_BIT_AARCH32 BIT_64(23) +#define SPSR_BTYPE_SHIFT_AARCH64 U(10) +#define SPSR_BTYPE_MASK_AARCH64 U(0x3) +#define SPSR_SSBS_SHIFT_AARCH64 U(12) +#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) +#define SPSR_SSBS_SHIFT_AARCH32 U(23) +#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) +#define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) +#define SPSR_IL_BIT BIT_64(20) +#define SPSR_SS_BIT BIT_64(21) +#define SPSR_PAN_BIT BIT_64(22) +#define SPSR_UAO_BIT_AARCH64 BIT_64(23) +#define SPSR_DIT_BIT BIT(24) +#define SPSR_TCO_BIT_AARCH64 BIT_64(25) +#define SPSR_PM_BIT_AARCH64 BIT_64(32) +#define SPSR_PPEND_BIT BIT(33) +#define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) +#define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) #define DISABLE_ALL_EXCEPTIONS \ (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) - #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) /* @@ -589,7 +825,7 @@ #define HI_VECTOR_BASE U(0xFFFF0000) /* - * TCR defintions + * TCR definitions */ #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) @@ -752,6 +988,7 @@ #define ESR_EC_LENGTH U(6) #define ESR_ISS_SHIFT U(0) #define ESR_ISS_LENGTH U(25) +#define ESR_IL_BIT (U(1) << 25) #define EC_UNKNOWN U(0x0) #define EC_WFE_WFI U(0x1) #define EC_AARCH32_CP15_MRC_MCR U(0x3) @@ -769,6 +1006,7 @@ #define EC_AARCH64_HVC U(0x16) #define EC_AARCH64_SMC U(0x17) #define EC_AARCH64_SYS U(0x18) +#define EC_IMP_DEF_EL3 U(0x1f) #define EC_IABORT_LOWER_EL U(0x20) #define EC_IABORT_CUR_EL U(0x21) #define EC_PC_ALIGN U(0x22) @@ -857,6 +1095,27 @@ #define ZCR_EL2_LEN_MASK U(0xf) /******************************************************************************* + * Definitions for system register interface to SME as needed in EL3 + ******************************************************************************/ +#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 +#define SMCR_EL3 S3_6_C1_C2_6 + +/* ID_AA64SMFR0_EL1 definitions */ +#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) +#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) +#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) +#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) +#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) +#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) +#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) + +/* SMCR_ELx definitions */ +#define SMCR_ELX_LEN_SHIFT U(0) +#define SMCR_ELX_LEN_MAX U(0x1ff) +#define SMCR_ELX_FA64_BIT (U(1) << 31) +#define SMCR_ELX_EZT0_BIT (U(1) << 30) + +/******************************************************************************* * Definitions of MAIR encodings for device and normal memory ******************************************************************************/ /* @@ -918,13 +1177,15 @@ #define PMBLIMITR_EL1 S3_0_C9_C10_0 /******************************************************************************* - * Definitions for system register interface to MPAM + * Definitions for system register interface, shifts and masks for MPAM ******************************************************************************/ #define MPAMIDR_EL1 S3_0_C10_C4_4 #define MPAM2_EL2 S3_4_C10_C5_0 #define MPAMHCR_EL2 S3_4_C10_C4_0 #define MPAM3_EL3 S3_6_C10_C5_0 +#define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) +#define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) /******************************************************************************* * Definitions for system register interface to AMU for FEAT_AMUv1 ******************************************************************************/ @@ -985,6 +1246,22 @@ #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 +/* AMCNTENSET0_EL0 definitions */ +#define AMCNTENSET0_EL0_Pn_SHIFT U(0) +#define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) + +/* AMCNTENSET1_EL0 definitions */ +#define AMCNTENSET1_EL0_Pn_SHIFT U(0) +#define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) + +/* AMCNTENCLR0_EL0 definitions */ +#define AMCNTENCLR0_EL0_Pn_SHIFT U(0) +#define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) + +/* AMCNTENCLR1_EL0 definitions */ +#define AMCNTENCLR1_EL0_Pn_SHIFT U(0) +#define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) + /* AMCFGR_EL0 definitions */ #define AMCFGR_EL0_NCG_SHIFT U(28) #define AMCFGR_EL0_NCG_MASK U(0xf) @@ -992,12 +1269,16 @@ #define AMCFGR_EL0_N_MASK U(0xff) /* AMCGCR_EL0 definitions */ +#define AMCGCR_EL0_CG0NC_SHIFT U(0) +#define AMCGCR_EL0_CG0NC_MASK U(0xff) #define AMCGCR_EL0_CG1NC_SHIFT U(8) #define AMCGCR_EL0_CG1NC_MASK U(0xff) /* MPAM register definitions */ #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) +#define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) +#define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) @@ -1016,7 +1297,8 @@ #define AMCG1IDR_VOFF_SHIFT U(16) /* New bit added to AMCR_EL0 */ -#define AMCR_CG1RZ_BIT (ULL(0x1) << 17) +#define AMCR_CG1RZ_SHIFT U(17) +#define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) /* * Definitions for virtual offset registers for architected activity monitor @@ -1049,6 +1331,14 @@ #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 /******************************************************************************* + * Realm management extension register definitions + ******************************************************************************/ +#define GPCCR_EL3 S3_6_C2_C1_6 +#define GPTBR_EL3 S3_6_C2_C1_4 + +#define SCXTNUM_EL2 S3_4_C13_C0_7 + +/******************************************************************************* * RAS system registers ******************************************************************************/ #define DISR_EL1 S3_0_C12_C1_1 @@ -1070,7 +1360,8 @@ #define ERXMISC0_EL1 S3_0_C5_C5_0 #define ERXMISC1_EL1 S3_0_C5_C5_1 -#define ERXCTLR_ED_BIT (U(1) << 0) +#define ERXCTLR_ED_SHIFT U(0) +#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) #define ERXCTLR_UE_BIT (U(1) << 4) #define ERXPFGCTL_UC_BIT (U(1) << 1) @@ -1110,6 +1401,62 @@ #define RGSR_EL1 S3_0_C1_C0_5 #define GCR_EL1 S3_0_C1_C0_6 +#define GCR_EL1_RRND_BIT (UL(1) << 16) + +/******************************************************************************* + * Armv8.5 - Random Number Generator Registers + ******************************************************************************/ +#define RNDR S3_3_C2_C4_0 +#define RNDRRS S3_3_C2_C4_1 + +/******************************************************************************* + * FEAT_HCX - Extended Hypervisor Configuration Register + ******************************************************************************/ +#define HCRX_EL2 S3_4_C1_C2_2 +#define HCRX_EL2_MSCEn_BIT (UL(1) << 11) +#define HCRX_EL2_MCE2_BIT (UL(1) << 10) +#define HCRX_EL2_CMOW_BIT (UL(1) << 9) +#define HCRX_EL2_VFNMI_BIT (UL(1) << 8) +#define HCRX_EL2_VINMI_BIT (UL(1) << 7) +#define HCRX_EL2_TALLINT_BIT (UL(1) << 6) +#define HCRX_EL2_SMPME_BIT (UL(1) << 5) +#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) +#define HCRX_EL2_FnXS_BIT (UL(1) << 3) +#define HCRX_EL2_EnASR_BIT (UL(1) << 2) +#define HCRX_EL2_EnALS_BIT (UL(1) << 1) +#define HCRX_EL2_EnAS0_BIT (UL(1) << 0) +#define HCRX_EL2_INIT_VAL ULL(0x0) + +/******************************************************************************* + * FEAT_FGT - Definitions for Fine-Grained Trap registers + ******************************************************************************/ +#define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) +#define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) +#define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) + +/******************************************************************************* + * FEAT_TCR2 - Extended Translation Control Register + ******************************************************************************/ +#define TCR2_EL2 S3_4_C2_C0_3 + +/******************************************************************************* + * Permission indirection and overlay + ******************************************************************************/ + +#define PIRE0_EL2 S3_4_C10_C2_2 +#define PIR_EL2 S3_4_C10_C2_3 +#define POR_EL2 S3_4_C10_C2_4 +#define S2PIR_EL2 S3_4_C10_C2_5 + +/******************************************************************************* + * FEAT_GCS - Guarded Control Stack Registers + ******************************************************************************/ +#define GCSCR_EL2 S3_4_C2_C5_0 +#define GCSPR_EL2 S3_4_C2_C5_1 +#define GCSCR_EL1 S3_0_C2_C5_0 + +#define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) + /******************************************************************************* * Definitions for DynamicIQ Shared Unit registers ******************************************************************************/ @@ -1119,5 +1466,21 @@ #define DSU_CLUSTER_PWR_OFF 0 #define DSU_CLUSTER_PWR_ON 1 #define DSU_CLUSTER_PWR_MASK U(1) +#define DSU_CLUSTER_MEM_RET BIT(1) + +/******************************************************************************* + * Definitions for CPU Power/Performance Management registers + ******************************************************************************/ + +#define CPUPPMCR_EL3 S3_6_C15_C2_0 +#define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) +#define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) + +#define CPUMPMMCR_EL3 S3_6_C15_C2_1 +#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) +#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) + +/* alternative system register encoding for the "sb" speculation barrier */ +#define SYSREG_SB S0_3_C3_C0_7 #endif /* ARCH_H */ diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 47a797a178..7582fc65d4 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,29 @@ #include <stdbool.h> #include <arch_helpers.h> +#include <common/feat_detect.h> + +#define ISOLATE_FIELD(reg, feat) \ + ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK)) + +#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \ +static inline bool is_ ## name ## _supported(void) \ +{ \ + if ((guard) == FEAT_STATE_DISABLED) { \ + return false; \ + } \ + if ((guard) == FEAT_STATE_ALWAYS) { \ + return true; \ + } \ + return read_func() >= (idvalue); \ +} + +#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \ +static unsigned int read_ ## name ## _id_field(void) \ +{ \ + return ISOLATE_FIELD(read_ ## idreg(), idfield); \ +} \ +CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard) static inline bool is_armv7_gentimer_present(void) { @@ -17,21 +40,52 @@ static inline bool is_armv7_gentimer_present(void) return true; } +CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, + ENABLE_FEAT_PAN) +static inline bool is_feat_pan_present(void) +{ + return read_feat_pan_id_field() != 0U; +} + +CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, + ENABLE_FEAT_VHE) + static inline bool is_armv8_2_ttcnp_present(void) { return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) & ID_AA64MMFR2_EL1_CNP_MASK) != 0U; } +static inline bool is_feat_uao_present(void) +{ + return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_UAO_SHIFT) & + ID_AA64MMFR2_EL1_UAO_MASK) != 0U; +} + +static inline bool is_feat_pacqarma3_present(void) +{ + uint64_t mask_id_aa64isar2 = + (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | + (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT); + + /* If any of the fields is not zero, QARMA3 algorithm is present */ + return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U; +} + static inline bool is_armv8_3_pauth_present(void) { - uint64_t mask = (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | - (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | - (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | - (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); + uint64_t mask_id_aa64isar1 = + (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | + (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | + (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | + (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); - /* If any of the fields is not zero, PAuth is present */ - return (read_id_aa64isar1_el1() & mask) != 0U; + /* + * If any of the fields is not zero or QARMA3 is present, + * PAuth is present + */ + return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || + is_feat_pacqarma3_present()); } static inline bool is_armv8_4_ttst_present(void) @@ -51,43 +105,87 @@ static inline unsigned int get_armv8_5_mte_support(void) return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & ID_AA64PFR1_EL1_MTE_MASK); } +static inline unsigned int is_feat_mte2_present(void) +{ + return get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX; +} + +static inline bool is_feat_ssbs_present(void) +{ + return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) & + ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_UNAVAILABLE; +} -static inline bool is_armv8_4_sel2_present(void) +static inline bool is_feat_nmi_present(void) { - return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) & - ID_AA64PFR0_SEL2_MASK) == 1ULL; + return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_NMI_SHIFT) & + ID_AA64PFR1_EL1_NMI_MASK) == NMI_IMPLEMENTED; } -static inline bool is_armv8_6_twed_present(void) +static inline bool is_feat_gcs_present(void) { - return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_TWED_SHIFT) & - ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED); + return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_GCS_SHIFT) & + ID_AA64PFR1_EL1_GCS_MASK) == GCS_IMPLEMENTED; } -static inline bool is_armv8_6_fgt_present(void) +static inline bool is_feat_ebep_present(void) { - return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) & - ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED; + return ((read_id_aa64dfr1_el1() >> ID_AA64DFR1_EBEP_SHIFT) & + ID_AA64DFR1_EBEP_MASK) == EBEP_IMPLEMENTED; } -static inline unsigned long int get_armv8_6_ecv_support(void) +static inline bool is_feat_sebep_present(void) { - return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) & - ID_AA64MMFR0_EL1_ECV_MASK); + return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_SEBEP_SHIFT) & + ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED; } -static inline bool is_armv8_5_rng_present(void) +CREATE_FEATURE_FUNCS_VER(feat_mte2, get_armv8_5_mte_support, MTE_IMPLEMENTED_ELX, + ENABLE_FEAT_MTE2) +CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, + ENABLE_FEAT_SEL2) +CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, + ENABLE_FEAT_TWED) +CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, + ENABLE_FEAT_FGT) +CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, + ENABLE_FEAT_ECV) +CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field, + ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV) + +CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, + ENABLE_FEAT_RNG) +CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, + ENABLE_FEAT_TCR2) + +CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, + ENABLE_FEAT_S2POE) +CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, + ENABLE_FEAT_S1POE) +static inline bool is_feat_sxpoe_supported(void) { - return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) & - ID_AA64ISAR0_RNDR_MASK); + return is_feat_s1poe_supported() || is_feat_s2poe_supported(); } -static inline bool is_armv8_6_feat_amuv1p1_present(void) +CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, + ENABLE_FEAT_S2PIE) +CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, + ENABLE_FEAT_S1PIE) +static inline bool is_feat_sxpie_supported(void) { - return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) & - ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1P1); + return is_feat_s1pie_supported() || is_feat_s2pie_supported(); } +/* FEAT_GCS: Guarded Control Stack */ +CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, + ENABLE_FEAT_GCS) + +/* FEAT_AMU: Activity Monitors Extension */ +CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, + ENABLE_FEAT_AMU) +CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field, + ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1) + /* * Return MPAM version: * @@ -97,7 +195,7 @@ static inline bool is_armv8_6_feat_amuv1p1_present(void) * 0x11: v1.1 Armv8.4 or later * */ -static inline unsigned int get_mpam_version(void) +static inline unsigned int read_feat_mpam_version(void) { return (unsigned int)((((read_id_aa64pfr0_el1() >> ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | @@ -105,4 +203,154 @@ static inline unsigned int get_mpam_version(void) ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); } +CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U, + ENABLE_FEAT_MPAM) + +/* FEAT_HCX: Extended Hypervisor Configuration Register */ +CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, + ENABLE_FEAT_HCX) + +static inline bool is_feat_rng_trap_present(void) +{ + return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) & + ID_AA64PFR1_EL1_RNDR_TRAP_MASK) + == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED); +} + +static inline unsigned int get_armv9_2_feat_rme_support(void) +{ + /* + * Return the RME version, zero if not supported. This function can be + * used as both an integer value for the RME version or compared to zero + * to detect RME presence. + */ + return (unsigned int)(read_id_aa64pfr0_el1() >> + ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK; +} + +/********************************************************************************* + * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction) + ********************************************************************************/ +static inline unsigned int read_feat_sb_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT); +} + +/* + * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59] + * of id_aa64pfr0_el1 register and can be used to check for below features: + * FEAT_CSV2_2: Cache Speculation Variant CSV2_2. + * FEAT_CSV2_3: Cache Speculation Variant CSV2_3. + * 0b0000 - Feature FEAT_CSV2 is not implemented. + * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3 + * are not implemented. + * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not + * implemented. + * 0b0011 - Feature FEAT_CSV2_3 is implemented. + */ +static inline unsigned int read_feat_csv2_id_field(void) +{ + return (unsigned int)(read_id_aa64pfr0_el1() >> + ID_AA64PFR0_CSV2_SHIFT) & ID_AA64PFR0_CSV2_MASK; +} + +CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field, + ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2) +CREATE_FEATURE_FUNCS_VER(feat_csv2_3, read_feat_csv2_id_field, + ID_AA64PFR0_CSV2_3_SUPPORTED, ENABLE_FEAT_CSV2_3) + +/* FEAT_SPE: Statistical Profiling Extension */ +CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, + ENABLE_SPE_FOR_NS) + +/* FEAT_SVE: Scalable Vector Extension */ +CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, + ENABLE_SVE_FOR_NS) + +/* FEAT_RAS: Reliability, Accessibility, Serviceability */ +CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, + ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS) + +/* FEAT_DIT: Data Independent Timing instructions */ +CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, + ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT) + +CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, + ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS) + +/* FEAT_TRF: TraceFilter */ +CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, + ENABLE_TRF_FOR_NS) + +/* FEAT_NV2: Enhanced Nested Virtualization */ +CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0) +CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field, + ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS) + +/* FEAT_BRBE: Branch Record Buffer Extension */ +CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, + ENABLE_BRBE_FOR_NS) + +/* FEAT_TRBE: Trace Buffer Extension */ +CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, + ENABLE_TRBE_FOR_NS) + +static inline unsigned int read_feat_sme_fa64_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64smfr0_el1(), + ID_AA64SMFR0_EL1_SME_FA64_SHIFT); +} +/* FEAT_SMEx: Scalar Matrix Extension */ +CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, + ENABLE_SME_FOR_NS) +CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field, + ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS) + +/******************************************************************************* + * Function to get hardware granularity support + ******************************************************************************/ + +static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void) +{ + return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), + ID_AA64MMFR0_EL1_TGRAN4_SHIFT); +} + +static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void) +{ + return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), + ID_AA64MMFR0_EL1_TGRAN16_SHIFT); +} + +static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void) +{ + return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), + ID_AA64MMFR0_EL1_TGRAN64_SHIFT); +} + +static inline unsigned int read_feat_pmuv3_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT); +} + +static inline unsigned int read_feat_mtpmu_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT); +} + +static inline bool is_feat_mtpmu_supported(void) +{ + if (DISABLE_MTPMU == FEAT_STATE_DISABLED) { + return false; + } + + if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) { + return true; + } + + unsigned int mtpmu = read_feat_mtpmu_id_field(); + + return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED); +} + #endif /* ARCH_FEATURES_H */ diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index a41b3258e1..6356cab12f 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,6 +27,14 @@ static inline u_register_t read_ ## _name(void) \ return v; \ } +#define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \ +static inline u_register_t read_ ## _name(void) \ +{ \ + u_register_t v; \ + __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \ + return v; \ +} + #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ static inline void write_ ## _name(u_register_t v) \ { \ @@ -58,6 +66,14 @@ static inline void write_ ## _name(u_register_t v) \ #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) +/* Define read function for ID register (w/o volatile qualifier) */ +#define DEFINE_IDREG_READ_FUNC(_name) \ + _DEFINE_SYSREG_READ_FUNC_NV(_name, _name) + +/* Define read function for renamed ID register (w/o volatile qualifier) */ +#define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) + /********************************************************************** * Macros to create inline functions for system instructions *********************************************************************/ @@ -224,6 +240,8 @@ DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) DEFINE_SYSOP_PARAM_FUNC(xpaci) void flush_dcache_range(uintptr_t addr, size_t size); +void flush_dcache_to_popa_range(uintptr_t addr, size_t size); +void flush_dcache_to_popa_range_mte2(uintptr_t addr, size_t size); void clean_dcache_range(uintptr_t addr, size_t size); void inv_dcache_range(uintptr_t addr, size_t size); bool is_dcache_enabled(void); @@ -233,8 +251,10 @@ void dcsw_op_all(u_register_t op_type); void disable_mmu_el1(void); void disable_mmu_el3(void); +void disable_mpu_el2(void); void disable_mmu_icache_el1(void); void disable_mmu_icache_el3(void); +void disable_mpu_icache_el2(void); /******************************************************************************* * Misc. accessor prototypes @@ -244,13 +264,16 @@ void disable_mmu_icache_el3(void); #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) DEFINE_SYSREG_RW_FUNCS(par_el1) -DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) -DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1) -DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) -DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) -DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) -DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) -DEFINE_SYSREG_READ_FUNC(id_afr0_el1) +DEFINE_IDREG_READ_FUNC(id_pfr1_el1) +DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1) +DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1) +DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1) +DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1) +DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1) +DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1) +DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1) +DEFINE_IDREG_READ_FUNC(id_aa64dfr1_el1) +DEFINE_IDREG_READ_FUNC(id_afr0_el1) DEFINE_SYSREG_READ_FUNC(CurrentEl) DEFINE_SYSREG_READ_FUNC(ctr_el0) DEFINE_SYSREG_RW_FUNCS(daif) @@ -263,6 +286,8 @@ DEFINE_SYSREG_RW_FUNCS(elr_el3) DEFINE_SYSREG_RW_FUNCS(mdccsr_el0) DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0) DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0) +DEFINE_SYSREG_RW_FUNCS(sp_el1) +DEFINE_SYSREG_RW_FUNCS(sp_el2) DEFINE_SYSOP_FUNC(wfi) DEFINE_SYSOP_FUNC(wfe) @@ -272,8 +297,10 @@ DEFINE_SYSOP_TYPE_FUNC(dmb, sy) DEFINE_SYSOP_TYPE_FUNC(dmb, st) DEFINE_SYSOP_TYPE_FUNC(dmb, ld) DEFINE_SYSOP_TYPE_FUNC(dsb, ish) +DEFINE_SYSOP_TYPE_FUNC(dsb, osh) DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) +DEFINE_SYSOP_TYPE_FUNC(dsb, oshst) DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) DEFINE_SYSOP_TYPE_FUNC(dmb, osh) @@ -359,10 +386,10 @@ void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, /******************************************************************************* * System register accessor prototypes ******************************************************************************/ -DEFINE_SYSREG_READ_FUNC(midr_el1) +DEFINE_IDREG_READ_FUNC(midr_el1) DEFINE_SYSREG_READ_FUNC(mpidr_el1) -DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) -DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1) +DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1) +DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1) DEFINE_SYSREG_RW_FUNCS(scr_el3) DEFINE_SYSREG_RW_FUNCS(hcr_el2) @@ -439,6 +466,11 @@ DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) DEFINE_SYSREG_READ_FUNC(cntpct_el0) DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) +DEFINE_SYSREG_RW_FUNCS(cntv_ctl_el0) +DEFINE_SYSREG_RW_FUNCS(cntv_cval_el0) +DEFINE_SYSREG_RW_FUNCS(cntkctl_el1) + +DEFINE_SYSREG_RW_FUNCS(vtcr_el2) #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ CNTP_CTL_ENABLE_MASK) @@ -453,6 +485,9 @@ DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) +DEFINE_SYSREG_RW_FUNCS(tpidr_el0) +DEFINE_SYSREG_RW_FUNCS(tpidr_el1) +DEFINE_SYSREG_RW_FUNCS(tpidr_el2) DEFINE_SYSREG_RW_FUNCS(tpidr_el3) DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) @@ -460,6 +495,13 @@ DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) DEFINE_SYSREG_RW_FUNCS(vpidr_el2) DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) +DEFINE_SYSREG_RW_FUNCS(hacr_el2) +DEFINE_SYSREG_RW_FUNCS(hpfar_el2) + +DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2) +DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2) + DEFINE_SYSREG_READ_FUNC(isr_el1) DEFINE_SYSREG_RW_FUNCS(mdcr_el2) @@ -467,6 +509,16 @@ DEFINE_SYSREG_RW_FUNCS(mdcr_el3) DEFINE_SYSREG_RW_FUNCS(hstr_el2) DEFINE_SYSREG_RW_FUNCS(pmcr_el0) +DEFINE_SYSREG_RW_FUNCS(csselr_el1) +DEFINE_SYSREG_RW_FUNCS(tpidrro_el0) +DEFINE_SYSREG_RW_FUNCS(contextidr_el1) +DEFINE_SYSREG_RW_FUNCS(spsr_abt) +DEFINE_SYSREG_RW_FUNCS(spsr_und) +DEFINE_SYSREG_RW_FUNCS(spsr_irq) +DEFINE_SYSREG_RW_FUNCS(spsr_fiq) +DEFINE_SYSREG_RW_FUNCS(dacr32_el2) +DEFINE_SYSREG_RW_FUNCS(ifsr32_el2) + /* GICv3 System Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) @@ -485,6 +537,7 @@ DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R) DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0) @@ -495,16 +548,14 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) -DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) -DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) -DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) -DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) - DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) +DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3) + DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) @@ -515,26 +566,100 @@ DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) -/* Armv8.2 Registers */ -DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2) + +/* Armv8.1 VHE Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2) + +/* Armv8.2 ID Registers */ +DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) + +/* Armv8.2 RAS Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2) + +/* Armv8.2 MPAM Registers */ +DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm0_el2, MPAMVPM0_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm1_el2, MPAMVPM1_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm2_el2, MPAMVPM2_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm3_el2, MPAMVPM3_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm4_el2, MPAMVPM4_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm5_el2, MPAMVPM5_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm6_el2, MPAMVPM6_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm7_el2, MPAMVPM7_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpmv_el2, MPAMVPMV_EL2) /* Armv8.3 Pointer Authentication Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) +/* Armv8.4 Data Independent Timing Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT) + +/* Armv8.4 FEAT_TRF Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2) + /* Armv8.5 MTE Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2) /* Armv8.5 FEAT_RNG Registers */ -DEFINE_SYSREG_READ_FUNC(rndr) -DEFINE_SYSREG_READ_FUNC(rndrrs) +DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR) +DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS) + +/* Armv8.6 FEAT_FGT Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2) + +/* ARMv8.6 FEAT_ECV Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2) + +/* FEAT_HCX Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) + +/* Armv8.9 system registers */ +DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1) + +/* FEAT_TCR2 Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2) + +/* FEAT_SxPIE Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2) + +/* FEAT_SxPOE Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2) + +/* FEAT_GCS Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1) /* DynamIQ Shared Unit power management */ DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) +/* CPU Power/Performance Management registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3) + +/* Armv9.2 RME Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3) + #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) @@ -578,7 +703,27 @@ static inline uint64_t el_implemented(unsigned int el) } } -/* Previously defined accesor functions with incomplete register names */ +/* + * TLBIPAALLOS instruction + * (TLB Inivalidate GPT Information by PA, + * All Entries, Outer Shareable) + */ +static inline void tlbipaallos(void) +{ + __asm__("SYS #6,c8,c1,#4"); +} + +/* + * Invalidate TLBs of GPT entries by Physical address, last level. + * + * @pa: the starting address for the range + * of invalidation + * @size: size of the range of invalidation + */ +void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size); + + +/* Previously defined accessor functions with incomplete register names */ #define read_current_el() read_CurrentEl() @@ -617,7 +762,7 @@ static inline uint64_t el_implemented(unsigned int el) isb(); \ } #else -#define AT(_at_inst, _va) _at_inst(_va); +#define AT(_at_inst, _va) _at_inst(_va) #endif #endif /* ARCH_HELPERS_H */ diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index 464c05be1a..d09ad0f0d7 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S @@ -10,10 +10,6 @@ #include <common/asm_macros_common.S> #include <lib/spinlock.h> -#if ENABLE_BTI && !ARM_ARCH_AT_LEAST(8, 5) -#error Branch Target Identification requires ARM_ARCH_MINOR >= 5 -#endif - /* * TLBI instruction with type specifier that implements the workaround for * errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76. @@ -29,12 +25,50 @@ #endif - .macro func_prologue + /* + * Create a stack frame at the start of an assembly function. Will also + * add all necessary call frame information (cfi) directives for a + * pretty stack trace. This is necessary as there is quite a bit of + * flexibility within a stack frame and the stack pointer can move + * around throughout the function. If the debugger isn't told where to + * find things, it gets lost, gives up and displays nothing. So inform + * the debugger of what's where. Anchor the Canonical Frame Address + * (CFA; the thing used to track what's where) to the frame pointer as + * that's not expected to change in the function body and no extra + * bookkeeping will be necessary, allowing free movement of the sp + * + * _frame_size: requested space for caller to use. Must be a mutliple + * of 16 for stack pointer alignment + */ + .macro func_prologue _frame_size=0 + .if \_frame_size & 0xf + .error "frame_size must have stack pointer alignment (multiple of 16)" + .endif + + /* put frame record at top of frame */ stp x29, x30, [sp, #-0x10]! mov x29,sp + .if \_frame_size + sub sp, sp, #\_frame_size + .endif + + /* point CFA to start of frame record, i.e. x29 + 0x10 */ + .cfi_def_cfa x29, 0x10 + /* inform it about x29, x30 locations */ + .cfi_offset x30, -0x8 + .cfi_offset x29, -0x10 .endm - .macro func_epilogue + /* + * Clear stack frame at the end of an assembly function. + * + * _frame_size: the value passed to func_prologue + */ + .macro func_epilogue _frame_size=0 + /* remove requested space */ + .if \_frame_size + add sp, sp, #\_frame_size + .endif ldp x29, x30, [sp], #0x10 .endm @@ -190,11 +224,12 @@ .space SPINLOCK_ASM_SIZE .endm -#if RAS_EXTENSION + /* + * With RAS extension executes esb instruction, else NOP + */ .macro esb .inst 0xd503221f .endm -#endif /* * Helper macro to read system register value into x0 @@ -219,17 +254,67 @@ .endm /* + * The "sb" instruction was introduced later into the architecture, + * so not all toolchains understand it. Some deny its usage unless + * a supported processor is specified on the build command line. + * Use sb's system register encoding to work around this, we already + * guard the sb execution with a feature flag. + */ + + .macro sb_barrier_insn + msr SYSREG_SB, xzr + .endm + + /* + * Macro for using speculation barrier instruction introduced by + * FEAT_SB, if it's enabled. + */ + .macro speculation_barrier +#if ENABLE_FEAT_SB + sb_barrier_insn +#else + dsb sy + isb +#endif + .endm + + /* * Macro for mitigating against speculative execution beyond ERET. Uses the * speculation barrier instruction introduced by FEAT_SB, if it's enabled. */ .macro exception_return eret #if ENABLE_FEAT_SB - sb + sb_barrier_insn #else dsb nsh isb #endif .endm + /* + * Macro to unmask External Aborts by changing PSTATE.A bit. + * Put explicit synchronization event to ensure newly unmasked interrupt + * is taken immediately. + */ + .macro unmask_async_ea + msr daifclr, #DAIF_ABT_BIT + isb + .endm + + /* Macro for error synchronization on exception boundries. + * With FEAT_RAS enabled, it is assumed that FEAT_IESB is also present + * and enabled. + * FEAT_IESB provides an implicit error synchronization event at exception + * entry and exception return, so there is no need for any explicit instruction. + */ + .macro synchronize_errors +#if !ENABLE_FEAT_RAS + /* Complete any stores that may return an abort */ + dsb sy + /* Synchronise the CPU context with the completion of the dsb */ + isb +#endif + .endm + #endif /* ASM_MACROS_S */ diff --git a/include/arch/aarch64/console_macros.S b/include/arch/aarch64/console_macros.S index 3285d855af..8adb9cdb1e 100644 --- a/include/arch/aarch64/console_macros.S +++ b/include/arch/aarch64/console_macros.S @@ -30,12 +30,19 @@ str xzr, [x0, #CONSOLE_T_PUTC] .endif + /* + * If ENABLE_CONSOLE_GETC support is disabled, but a getc callback is + * specified nonetheless, the assembler will abort on encountering the + * CONSOLE_T_GETC macro, which is undefined. + */ .ifne \getc adrp x1, console_\_driver\()_getc add x1, x1, :lo12:console_\_driver\()_getc str x1, [x0, #CONSOLE_T_GETC] .else +#if ENABLE_CONSOLE_GETC str xzr, [x0, #CONSOLE_T_GETC] +#endif .endif .ifne \flush diff --git a/include/arch/aarch64/el2_common_macros.S b/include/arch/aarch64/el2_common_macros.S new file mode 100644 index 0000000000..9609c0d8c7 --- /dev/null +++ b/include/arch/aarch64/el2_common_macros.S @@ -0,0 +1,418 @@ +/* + * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EL2_COMMON_MACROS_S +#define EL2_COMMON_MACROS_S + +#include <arch.h> +#include <asm_macros.S> +#include <context.h> +#include <lib/xlat_tables/xlat_tables_defs.h> + +#include <platform_def.h> + + /* + * Helper macro to initialise system registers at EL2. + */ + .macro el2_arch_init_common + + /* --------------------------------------------------------------------- + * SCTLR_EL2 has already been initialised - read current value before + * modifying. + * + * SCTLR_EL2.I: Enable the instruction cache. + * + * SCTLR_EL2.SA: Enable Stack Alignment check. A SP alignment fault + * exception is generated if a load or store instruction executed at + * EL2 uses the SP as the base address and the SP is not aligned to a + * 16-byte boundary. + * + * SCTLR_EL2.A: Enable Alignment fault checking. All instructions that + * load or store one or more registers have an alignment check that the + * address being accessed is aligned to the size of the data element(s) + * being accessed. + * --------------------------------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el2 + orr x0, x0, x1 + msr sctlr_el2, x0 + isb + + /* --------------------------------------------------------------------- + * Initialise HCR_EL2, setting all fields rather than relying on HW. + * All fields are architecturally UNKNOWN on reset. The following fields + * do not change during the TF lifetime. The remaining fields are set to + * zero here but are updated ahead of transitioning to a lower EL in the + * function cm_init_context_common(). + * + * HCR_EL2.TWE: Set to zero so that execution of WFE instructions at + * EL2, EL1 and EL0 are not trapped to EL2. + * + * HCR_EL2.TWI: Set to zero so that execution of WFI instructions at + * EL2, EL1 and EL0 are not trapped to EL2. + * + * HCR_EL2.HCD: Set to zero to enable HVC calls at EL1 and above, + * from both Security states and both Execution states. + * + * HCR_EL2.TEA: Set to one to route External Aborts and SError + * Interrupts to EL2 when executing at any EL. + * + * HCR_EL2.{API,APK}: For Armv8.3 pointer authentication feature, + * disable traps to EL2 when accessing key registers or using + * pointer authentication instructions from lower ELs. + * --------------------------------------------------------------------- + */ + mov_imm x0, ((HCR_RESET_VAL | HCR_TEA_BIT) \ + & ~(HCR_TWE_BIT | HCR_TWI_BIT | HCR_HCD_BIT)) +#if CTX_INCLUDE_PAUTH_REGS + /* + * If the pointer authentication registers are saved during world + * switches, enable pointer authentication everywhere, as it is safe to + * do so. + */ + orr x0, x0, #(HCR_API_BIT | HCR_APK_BIT) +#endif /* CTX_INCLUDE_PAUTH_REGS */ + msr hcr_el2, x0 + + /* --------------------------------------------------------------------- + * Initialise MDCR_EL2, setting all fields rather than relying on + * hw. Some fields are architecturally UNKNOWN on reset. + * + * MDCR_EL2.TDOSA: Set to zero so that EL2 and EL2 System register + * access to the powerdown debug registers do not trap to EL2. + * + * MDCR_EL2.TDA: Set to zero to allow EL0, EL1 and EL2 access to the + * debug registers, other than those registers that are controlled by + * MDCR_EL2.TDOSA. + * + * MDCR_EL2.TPM: Set to zero so that EL0, EL1, and EL2 System + * register accesses to all Performance Monitors registers do not trap + * to EL2. + * + * MDCR_EL2.HPMD: Set to zero so that event counting by the program- + * mable counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If + * ARMv8.2 Debug is not implemented this bit does not have any effect + * on the counters unless there is support for the implementation + * defined authentication interface + * ExternalSecureNoninvasiveDebugEnabled(). + * --------------------------------------------------------------------- + */ + mov_imm x0, ((MDCR_EL2_RESET_VAL | \ + MDCR_SPD32(MDCR_SPD32_DISABLE)) \ + & ~(MDCR_EL2_HPMD_BIT | MDCR_TDOSA_BIT | \ + MDCR_TDA_BIT | MDCR_TPM_BIT)) + + msr mdcr_el2, x0 + + /* --------------------------------------------------------------------- + * Initialise PMCR_EL0 setting all fields rather than relying + * on hw. Some fields are architecturally UNKNOWN on reset. + * + * PMCR_EL0.DP: Set to one so that the cycle counter, + * PMCCNTR_EL0 does not count when event counting is prohibited. + * + * PMCR_EL0.X: Set to zero to disable export of events. + * + * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 + * counts on every clock cycle. + * --------------------------------------------------------------------- + */ + mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_DP_BIT) & \ + ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) + + msr pmcr_el0, x0 + + /* --------------------------------------------------------------------- + * Enable External Aborts and SError Interrupts now that the exception + * vectors have been setup. + * --------------------------------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------------------------------- + * Initialise CPTR_EL2, setting all fields rather than relying on hw. + * All fields are architecturally UNKNOWN on reset. + * + * CPTR_EL2.TCPAC: Set to zero so that any accesses to CPACR_EL1 do + * not trap to EL2. + * + * CPTR_EL2.TTA: Set to zero so that System register accesses to the + * trace registers do not trap to EL2. + * + * CPTR_EL2.TFP: Set to zero so that accesses to the V- or Z- registers + * by Advanced SIMD, floating-point or SVE instructions (if implemented) + * do not trap to EL2. + */ + + mov_imm x0, (CPTR_EL2_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) + msr cptr_el2, x0 + + /* + * If Data Independent Timing (DIT) functionality is implemented, + * always enable DIT in EL2 + */ + mrs x0, id_aa64pfr0_el1 + ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH + cmp x0, #ID_AA64PFR0_DIT_SUPPORTED + bne 1f + mov x0, #DIT_BIT + msr DIT, x0 +1: + .endm + +/* ----------------------------------------------------------------------------- + * This is the super set of actions that need to be performed during a cold boot + * or a warm boot in EL2. This code is shared by BL1 and BL31. + * + * This macro will always perform reset handling, architectural initialisations + * and stack setup. The rest of the actions are optional because they might not + * be needed, depending on the context in which this macro is called. This is + * why this macro is parameterised ; each parameter allows to enable/disable + * some actions. + * + * _init_sctlr: + * Whether the macro needs to initialise SCTLR_EL2, including configuring + * the endianness of data accesses. + * + * _warm_boot_mailbox: + * Whether the macro needs to detect the type of boot (cold/warm). The + * detection is based on the platform entrypoint address : if it is zero + * then it is a cold boot, otherwise it is a warm boot. In the latter case, + * this macro jumps on the platform entrypoint address. + * + * _secondary_cold_boot: + * Whether the macro needs to identify the CPU that is calling it: primary + * CPU or secondary CPU. The primary CPU will be allowed to carry on with + * the platform initialisations, while the secondaries will be put in a + * platform-specific state in the meantime. + * + * If the caller knows this macro will only be called by the primary CPU + * then this parameter can be defined to 0 to skip this step. + * + * _init_memory: + * Whether the macro needs to initialise the memory. + * + * _init_c_runtime: + * Whether the macro needs to initialise the C runtime environment. + * + * _exception_vectors: + * Address of the exception vectors to program in the VBAR_EL2 register. + * + * _pie_fixup_size: + * Size of memory region to fixup Global Descriptor Table (GDT). + * + * A non-zero value is expected when firmware needs GDT to be fixed-up. + * + * ----------------------------------------------------------------------------- + */ + .macro el2_entrypoint_common \ + _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ + _init_memory, _init_c_runtime, _exception_vectors, \ + _pie_fixup_size + + .if \_init_sctlr + /* ------------------------------------------------------------- + * This is the initialisation of SCTLR_EL2 and so must ensure + * that all fields are explicitly set rather than relying on hw. + * Some fields reset to an IMPLEMENTATION DEFINED value and + * others are architecturally UNKNOWN on reset. + * + * SCTLR.EE: Set the CPU endianness before doing anything that + * might involve memory reads or writes. Set to zero to select + * Little Endian. + * + * SCTLR_EL2.WXN: For the EL2 translation regime, this field can + * force all memory regions that are writeable to be treated as + * XN (Execute-never). Set to zero so that this control has no + * effect on memory access permissions. + * + * SCTLR_EL2.SA: Set to zero to disable Stack Alignment check. + * + * SCTLR_EL2.A: Set to zero to disable Alignment fault checking. + * + * SCTLR.DSSBS: Set to zero to disable speculation store bypass + * safe behaviour upon exception entry to EL2. + * ------------------------------------------------------------- + */ + mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ + | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) + msr sctlr_el2, x0 + isb + .endif /* _init_sctlr */ + + .if \_warm_boot_mailbox + /* ------------------------------------------------------------- + * This code will be executed for both warm and cold resets. + * Now is the time to distinguish between the two. + * Query the platform entrypoint address and if it is not zero + * then it means it is a warm boot so jump to this address. + * ------------------------------------------------------------- + */ + bl plat_get_my_entrypoint + cbz x0, do_cold_boot + br x0 + + do_cold_boot: + .endif /* _warm_boot_mailbox */ + + .if \_pie_fixup_size +#if ENABLE_PIE + /* + * ------------------------------------------------------------ + * If PIE is enabled fixup the Global descriptor Table only + * once during primary core cold boot path. + * + * Compile time base address, required for fixup, is calculated + * using "pie_fixup" label present within first page. + * ------------------------------------------------------------ + */ + pie_fixup: + ldr x0, =pie_fixup + and x0, x0, #~(PAGE_SIZE_MASK) + mov_imm x1, \_pie_fixup_size + add x1, x1, x0 + bl fixup_gdt_reloc +#endif /* ENABLE_PIE */ + .endif /* _pie_fixup_size */ + + /* --------------------------------------------------------------------- + * Set the exception vectors. + * --------------------------------------------------------------------- + */ + adr x0, \_exception_vectors + msr vbar_el2, x0 + isb + + /* --------------------------------------------------------------------- + * It is a cold boot. + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el2_arch_init_common + + .if \_secondary_cold_boot + /* ------------------------------------------------------------- + * Check if this is a primary or secondary CPU cold boot. + * The primary CPU will set up the platform while the + * secondaries are placed in a platform-specific state until the + * primary CPU performs the necessary actions to bring them out + * of that state and allows entry into the OS. + * ------------------------------------------------------------- + */ + bl plat_is_my_cpu_primary + cbnz w0, do_primary_cold_boot + + /* This is a cold boot on a secondary CPU */ + bl plat_secondary_cold_boot_setup + /* plat_secondary_cold_boot_setup() is not supposed to return */ + bl el2_panic + do_primary_cold_boot: + .endif /* _secondary_cold_boot */ + + /* --------------------------------------------------------------------- + * Initialize memory now. Secondary CPU initialization won't get to this + * point. + * --------------------------------------------------------------------- + */ + + .if \_init_memory + bl platform_mem_init + .endif /* _init_memory */ + + /* --------------------------------------------------------------------- + * Init C runtime environment: + * - Zero-initialise the NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section (if any). + * - Relocate the data section from ROM to RAM, if required. + * --------------------------------------------------------------------- + */ + .if \_init_c_runtime + adrp x0, __BSS_START__ + add x0, x0, :lo12:__BSS_START__ + + adrp x1, __BSS_END__ + add x1, x1, :lo12:__BSS_END__ + sub x1, x1, x0 + bl zeromem + +#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && \ + RESET_TO_BL2 && BL2_IN_XIP_MEM) + adrp x0, __DATA_RAM_START__ + add x0, x0, :lo12:__DATA_RAM_START__ + adrp x1, __DATA_ROM_START__ + add x1, x1, :lo12:__DATA_ROM_START__ + adrp x2, __DATA_RAM_END__ + add x2, x2, :lo12:__DATA_RAM_END__ + sub x2, x2, x0 + bl memcpy16 +#endif + .endif /* _init_c_runtime */ + + /* --------------------------------------------------------------------- + * Use SP_EL0 for the C runtime stack. + * --------------------------------------------------------------------- + */ + msr spsel, #0 + + /* --------------------------------------------------------------------- + * Allocate a stack whose memory will be marked as Normal-IS-WBWA when + * the MMU is enabled. There is no risk of reading stale stack memory + * after enabling the MMU as only the primary CPU is running at the + * moment. + * --------------------------------------------------------------------- + */ + bl plat_set_my_stack + +#if STACK_PROTECTOR_ENABLED + .if \_init_c_runtime + bl update_stack_protector_canary + .endif /* _init_c_runtime */ +#endif + .endm + + .macro apply_at_speculative_wa +#if ERRATA_SPECULATIVE_AT + /* + * This function expects x30 has been saved. + * Also, save x29 which will be used in the called function. + */ + str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] + bl save_and_update_ptw_el1_sys_regs + ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] +#endif + .endm + + .macro restore_ptw_el1_sys_regs +#if ERRATA_SPECULATIVE_AT + /* ----------------------------------------------------------- + * In case of ERRATA_SPECULATIVE_AT, must follow below order + * to ensure that page table walk is not enabled until + * restoration of all EL1 system registers. TCR_EL1 register + * should be updated at the end which restores previous page + * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB + * ensures that CPU does below steps in order. + * + * 1. Ensure all other system registers are written before + * updating SCTLR_EL1 using ISB. + * 2. Restore SCTLR_EL1 register. + * 3. Ensure SCTLR_EL1 written successfully using ISB. + * 4. Restore TCR_EL1 register. + * ----------------------------------------------------------- + */ + isb + ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] + msr sctlr_el1, x28 + isb + msr tcr_el1, x29 +#endif + .endm + +#endif /* EL2_COMMON_MACROS_S */ diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index b610b37bd1..26c7578929 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <arch.h> #include <asm_macros.S> +#include <assert_macros.S> #include <context.h> #include <lib/xlat_tables/xlat_tables_defs.h> @@ -58,36 +59,26 @@ * zero here but are updated ahead of transitioning to a lower EL in the * function cm_init_context_common(). * - * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at - * EL2, EL1 and EL0 are not trapped to EL3. - * - * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at - * EL2, EL1 and EL0 are not trapped to EL3. - * * SCR_EL3.SIF: Set to one to disable instruction fetches from * Non-secure memory. * - * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from - * both Security states and both Execution states. - * * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts * to EL3 when executing at any EL. * - * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, - * disable traps to EL3 when accessing key registers or using pointer - * authentication instructions from lower ELs. + * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled. + * + * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate + * against ERRATA_V2_3099206. * --------------------------------------------------------------------- */ - mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ - & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) -#if CTX_INCLUDE_PAUTH_REGS - /* - * If the pointer authentication registers are saved during world - * switches, enable pointer authentication everywhere, as it is safe to - * do so. - */ - orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) + mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) +#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 + mrs x1, id_aa64pfr0_el1 + and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT) + cbz x1, 1f + orr x0, x0, #SCR_EEL2_BIT #endif +1: msr scr_el3, x0 /* --------------------------------------------------------------------- @@ -107,65 +98,14 @@ * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the * debug registers, other than those registers that are controlled by * MDCR_EL3.TDOSA. - * - * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register - * accesses to all Performance Monitors registers do not trap to EL3. - * - * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is - * prohibited in Secure state. This bit is RES0 in versions of the - * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 - * doesn't have any effect on them. - * - * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is - * prohibited in EL3. This bit is RES0 in versions of the - * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 - * doesn't have any effect on them. - * - * MDCR_EL3.SPME: Set to zero so that event counting by the programmable - * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 - * Debug is not implemented this bit does not have any effect on the - * counters unless there is support for the implementation defined - * authentication interface ExternalSecureNoninvasiveDebugEnabled(). - * --------------------------------------------------------------------- */ mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ - MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ - MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ - MDCR_TDA_BIT | MDCR_TPM_BIT)) + MDCR_SPD32(MDCR_SPD32_DISABLE)) & \ + ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT)) msr mdcr_el3, x0 /* --------------------------------------------------------------------- - * Initialise PMCR_EL0 setting all fields rather than relying - * on hw. Some fields are architecturally UNKNOWN on reset. - * - * PMCR_EL0.LP: Set to one so that event counter overflow, that - * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment - * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU - * is implemented. This bit is RES0 in versions of the architecture - * earlier than ARMv8.5, setting it to 1 doesn't have any effect - * on them. - * - * PMCR_EL0.LC: Set to one so that cycle counter overflow, that - * is recorded in PMOVSCLR_EL0[31], occurs on the increment - * that changes PMCCNTR_EL0[63] from 1 to 0. - * - * PMCR_EL0.DP: Set to one so that the cycle counter, - * PMCCNTR_EL0 does not count when event counting is prohibited. - * - * PMCR_EL0.X: Set to zero to disable export of events. - * - * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 - * counts on every clock cycle. - * --------------------------------------------------------------------- - */ - mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ - PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ - ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) - - msr pmcr_el0, x0 - - /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception * vectors have been setup. * --------------------------------------------------------------------- @@ -175,31 +115,33 @@ /* --------------------------------------------------------------------- * Initialise CPTR_EL3, setting all fields rather than relying on hw. * All fields are architecturally UNKNOWN on reset. - * - * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, - * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. - * - * CPTR_EL3.TTA: Set to zero so that System register accesses to the - * trace registers do not trap to EL3. - * - * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers - * by Advanced SIMD, floating-point or SVE instructions (if implemented) - * do not trap to EL3. + * --------------------------------------------------------------------- */ - mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) + mov_imm x0, CPTR_EL3_RESET_VAL msr cptr_el3, x0 /* * If Data Independent Timing (DIT) functionality is implemented, - * always enable DIT in EL3 + * always enable DIT in EL3. + * First assert that the FEAT_DIT build flag matches the feature id + * register value for DIT. */ +#if ENABLE_FEAT_DIT +#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1 mrs x0, id_aa64pfr0_el1 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH +#if ENABLE_FEAT_DIT > 1 + cbz x0, 1f +#else cmp x0, #ID_AA64PFR0_DIT_SUPPORTED - bne 1f + ASM_ASSERT(eq) +#endif + +#endif /* ENABLE_ASSERTIONS */ mov x0, #DIT_BIT msr DIT, x0 1: +#endif .endm /* ----------------------------------------------------------------------------- @@ -278,14 +220,14 @@ */ mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) +#if ENABLE_FEAT_RAS + /* If FEAT_RAS is present assume FEAT_IESB is also present */ + orr x0, x0, #SCTLR_IESB_BIT +#endif msr sctlr_el3, x0 isb .endif /* _init_sctlr */ -#if DISABLE_MTPMU - bl mtpmu_disable -#endif - .if \_warm_boot_mailbox /* ------------------------------------------------------------- * This code will be executed for both warm and cold resets. @@ -329,6 +271,7 @@ msr vbar_el3, x0 isb +#if !(defined(IMAGE_BL2) && ENABLE_RME) /* --------------------------------------------------------------------- * It is a cold boot. * Perform any processor specific actions upon reset e.g. cache, TLB @@ -336,6 +279,7 @@ * --------------------------------------------------------------------- */ bl reset_handler +#endif el3_arch_init_common @@ -378,17 +322,31 @@ * --------------------------------------------------------------------- */ .if \_init_c_runtime -#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) +#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ + ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME)) /* ------------------------------------------------------------- * Invalidate the RW memory used by the BL31 image. This * includes the data and NOBITS sections. This is done to * safeguard against possible corruption of this memory by * dirty cache lines in a system cache as a result of use by - * an earlier boot loader stage. + * an earlier boot loader stage. If PIE is enabled however, + * RO sections including the GOT may be modified during + * pie fixup. Therefore, to be on the safe side, invalidate + * the entire image region if PIE is enabled. * ------------------------------------------------------------- */ +#if ENABLE_PIE +#if SEPARATE_CODE_AND_RODATA + adrp x0, __TEXT_START__ + add x0, x0, :lo12:__TEXT_START__ +#else + adrp x0, __RO_START__ + add x0, x0, :lo12:__RO_START__ +#endif /* SEPARATE_CODE_AND_RODATA */ +#else adrp x0, __RW_START__ add x0, x0, :lo12:__RW_START__ +#endif /* ENABLE_PIE */ adrp x1, __RW_END__ add x1, x1, :lo12:__RW_END__ sub x1, x1, x0 @@ -401,6 +359,14 @@ sub x1, x1, x0 bl inv_dcache_range #endif +#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION + adrp x0, __BL2_NOLOAD_START__ + add x0, x0, :lo12:__BL2_NOLOAD_START__ + adrp x1, __BL2_NOLOAD_END__ + add x1, x1, :lo12:__BL2_NOLOAD_END__ + sub x1, x1, x0 + bl inv_dcache_range +#endif #endif adrp x0, __BSS_START__ add x0, x0, :lo12:__BSS_START__ @@ -419,7 +385,8 @@ bl zeromem #endif -#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) +#if defined(IMAGE_BL1) || \ + (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) adrp x0, __DATA_RAM_START__ add x0, x0, :lo12:__DATA_RAM_START__ adrp x1, __DATA_ROM_START__ @@ -456,13 +423,12 @@ .macro apply_at_speculative_wa #if ERRATA_SPECULATIVE_AT /* - * Explicitly save x30 so as to free up a register and to enable - * branching and also, save x29 which will be used in the called - * function + * This function expects x30 has been saved. + * Also, save x29 which will be used in the called function. */ - stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] + str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] bl save_and_update_ptw_el1_sys_regs - ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] + ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] #endif .endm @@ -491,4 +457,20 @@ #endif .endm +/* ----------------------------------------------------------------- + * The below macro reads SCR_EL3 from the context structure to + * determine the security state of the context upon ERET. + * ------------------------------------------------------------------ + */ + .macro get_security_state _ret:req, _scr_reg:req + ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 + cmp \_ret, #1 + beq realm_state + bfi \_ret, \_scr_reg, #0, #1 + b end + realm_state: + mov \_ret, #2 + end: + .endm + #endif /* EL3_COMMON_MACROS_S */ diff --git a/include/arch/aarch64/smccc_helpers.h b/include/arch/aarch64/smccc_helpers.h index fac6fd9cf9..950a811d60 100644 --- a/include/arch/aarch64/smccc_helpers.h +++ b/include/arch/aarch64/smccc_helpers.h @@ -9,12 +9,26 @@ #include <lib/smccc.h> +/* Definitions to help the assembler access the SMC/ERET args structure */ +#define SMC_ARGS_SIZE 0x40 +#define SMC_ARG0 0x0 +#define SMC_ARG1 0x8 +#define SMC_ARG2 0x10 +#define SMC_ARG3 0x18 +#define SMC_ARG4 0x20 +#define SMC_ARG5 0x28 +#define SMC_ARG6 0x30 +#define SMC_ARG7 0x38 +#define SMC_ARGS_END 0x40 + #ifndef __ASSEMBLER__ #include <stdbool.h> #include <context.h> +#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */ + /* Convenience macros to return from SMC handler */ #define SMC_RET0(_h) { \ return (uint64_t) (_h); \ @@ -61,6 +75,24 @@ #define SMC_SET_GP(_h, _g, _v) \ write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v)) + +/* Useful for SMCCCv1.2 */ +#define SMC_RET18(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7, _x8, _x9, \ + _x10, _x11, _x12, _x13, _x14, _x15, _x16, _x17) { \ + SMC_SET_GP(_h, CTX_GPREG_X8, _x8); \ + SMC_SET_GP(_h, CTX_GPREG_X9, _x9); \ + SMC_SET_GP(_h, CTX_GPREG_X10, _x10); \ + SMC_SET_GP(_h, CTX_GPREG_X11, _x11); \ + SMC_SET_GP(_h, CTX_GPREG_X12, _x12); \ + SMC_SET_GP(_h, CTX_GPREG_X13, _x13); \ + SMC_SET_GP(_h, CTX_GPREG_X14, _x14); \ + SMC_SET_GP(_h, CTX_GPREG_X15, _x15); \ + SMC_SET_GP(_h, CTX_GPREG_X16, _x16); \ + SMC_SET_GP(_h, CTX_GPREG_X17, _x17); \ + SMC_RET8(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6), \ + (_x7)); \ +} + /* * Convenience macros to access EL3 context registers using handle provided to * SMC handler. These take the offset values defined in context.h @@ -82,6 +114,49 @@ _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \ } while (false) +typedef struct { + uint64_t _regs[SMC_ARGS_END >> 3]; +} __aligned(CACHE_WRITEBACK_GRANULE) smc_args_t; + +/* + * Ensure that the assembler's view of the size of the tsp_args is the + * same as the compilers. + */ +CASSERT(sizeof(smc_args_t) == SMC_ARGS_SIZE, assert_sp_args_size_mismatch); + +static inline smc_args_t smc_helper(uint32_t func, uint64_t arg0, + uint64_t arg1, uint64_t arg2, + uint64_t arg3, uint64_t arg4, + uint64_t arg5, uint64_t arg6) +{ + smc_args_t ret_args = {0}; + + register uint64_t r0 __asm__("x0") = func; + register uint64_t r1 __asm__("x1") = arg0; + register uint64_t r2 __asm__("x2") = arg1; + register uint64_t r3 __asm__("x3") = arg2; + register uint64_t r4 __asm__("x4") = arg3; + register uint64_t r5 __asm__("x5") = arg4; + register uint64_t r6 __asm__("x6") = arg5; + register uint64_t r7 __asm__("x7") = arg6; + + /* Output registers, also used as inputs ('+' constraint). */ + __asm__ volatile("smc #0" + : "+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3), "+r"(r4), + "+r"(r5), "+r"(r6), "+r"(r7)); + + ret_args._regs[0] = r0; + ret_args._regs[1] = r1; + ret_args._regs[2] = r2; + ret_args._regs[3] = r3; + ret_args._regs[4] = r4; + ret_args._regs[5] = r5; + ret_args._regs[6] = r6; + ret_args._regs[7] = r7; + + return ret_args; +} + #endif /*__ASSEMBLER__*/ #endif /* SMCCC_HELPERS_H */ diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h index 21d3ae7b7c..7cd7e727ca 100644 --- a/include/bl1/bl1.h +++ b/include/bl1/bl1.h @@ -90,8 +90,8 @@ void bl1_plat_prepare_exit(entry_point_info_t *ep_info); /* * Check if the total number of FWU SMC calls are as expected. */ -CASSERT(FWU_NUM_SMC_CALLS == \ - (FWU_SMC_FID_END - FWU_SMC_FID_START + 1),\ +CASSERT(FWU_NUM_SMC_CALLS == + (FWU_SMC_FID_END - FWU_SMC_FID_START + 1), assert_FWU_NUM_SMC_CALLS_mismatch); /* Utility functions */ diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h index 3deb0a51d2..ed5374e042 100644 --- a/include/bl31/bl31.h +++ b/include/bl31/bl31.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,8 +19,8 @@ void bl31_set_next_image_type(uint32_t security_state); uint32_t bl31_get_next_image_type(void); void bl31_prepare_next_image_entry(void); void bl31_register_bl32_init(int32_t (*func)(void)); +void bl31_register_rmm_init(int32_t (*func)(void)); void bl31_warm_entrypoint(void); void bl31_main(void); -void bl31_lib_init(void); #endif /* BL31_H */ diff --git a/include/bl31/ea_handle.h b/include/bl31/ea_handle.h index 68f012c14f..7cd7b6a1c8 100644 --- a/include/bl31/ea_handle.h +++ b/include/bl31/ea_handle.h @@ -21,4 +21,6 @@ /* RAS event signalled as peripheral interrupt */ #define ERROR_INTERRUPT 3 +#define ASYNC_EA_REPLAY_COUNTER U(100) + #endif /* EA_HANDLE_H */ diff --git a/include/bl31/ehf.h b/include/bl31/ehf.h index c13d28c357..63943a926a 100644 --- a/include/bl31/ehf.h +++ b/include/bl31/ehf.h @@ -30,7 +30,7 @@ .ehf_handler = EHF_NO_HANDLER_, \ } -/* Macro for platforms to regiter its exception priorities */ +/* Macro for platforms to register its exception priorities */ #define EHF_REGISTER_PRIORITIES(priorities, num, bits) \ const ehf_priorities_t exception_data = { \ .num_priorities = (num), \ diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index 935bf77665..8b9dfb6460 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -107,15 +107,23 @@ static inline int32_t validate_ns_interrupt_rm(uint32_t x) static inline int32_t validate_el3_interrupt_rm(uint32_t x) { -#if EL3_EXCEPTION_HANDLING +#if EL3_EXCEPTION_HANDLING && SPM_MM /* * With EL3 exception handling, EL3 interrupts are always routed to EL3 - * from both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is - * the only valid routing model. + * from Non-secure and from secure only if SPM_MM is present. + * Therefore INTR_EL3_VALID_RM1 is the only valid routing model. */ if (x == INTR_EL3_VALID_RM1) return 0; #else + /* + * When EL3_EXCEPTION_HANDLING is not defined both routing modes are + * valid. This is the most common case. The exception to this rule is + * when EL3_EXCEPTION_HANDLING is defined but also when the SPMC lives + * at S-EL2. In this case, Group0 Interrupts are trapped to the SPMC + * when running in S-EL0 and S-EL1. The SPMC may handle the interrupt + * itself, delegate it to an SP or forward to EL3 for handling. + */ if ((x == INTR_EL3_VALID_RM0) || (x == INTR_EL3_VALID_RM1)) return 0; #endif diff --git a/include/bl31/sync_handle.h b/include/bl31/sync_handle.h new file mode 100644 index 0000000000..394252b7b5 --- /dev/null +++ b/include/bl31/sync_handle.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2022, ARM Limited. All rights reserved. + * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRAP_HANDLE_H +#define TRAP_HANDLE_H + +#include <stdbool.h> +#include <context.h> + +#define ISS_SYSREG_OPCODE_MASK 0x3ffc1eUL +#define ISS_SYSREG_REG_MASK 0x0003e0UL +#define ISS_SYSREG_REG_SHIFT 5U +#define ISS_SYSREG_DIRECTION_MASK 0x000001UL + +#define ISS_SYSREG_OPCODE_RNDR 0x30c808U +#define ISS_SYSREG_OPCODE_IMPDEF 0x303c00U +#define ISS_SYSREG_OPCODE_RNDRRS 0x32c808U + +#define TRAP_RET_UNHANDLED -1 +#define TRAP_RET_REPEAT 0 +#define TRAP_RET_CONTINUE 1 + +#ifndef __ASSEMBLER__ +static inline unsigned int get_sysreg_iss_rt(uint64_t esr) +{ + return (esr & ISS_SYSREG_REG_MASK) >> ISS_SYSREG_REG_SHIFT; +} + +static inline bool is_sysreg_iss_write(uint64_t esr) +{ + return !(esr & ISS_SYSREG_DIRECTION_MASK); +} + +/** + * handle_sysreg_trap() - Handle AArch64 system register traps from lower ELs + * @esr_el3: The content of ESR_EL3, containing the trap syndrome information + * @ctx: Pointer to the lower EL context, containing saved registers + * + * Called by the exception handler when a synchronous trap identifies as a + * system register trap (EC=0x18). ESR contains the encoding of the op[x] and + * CRm/CRn fields, to identify the system register, and the target/source + * GPR plus the direction (MRS/MSR). The lower EL's context can be altered + * by the function, to inject back the result of the emulation. + * + * Return: indication how to proceed with the trap: + * TRAP_RET_UNHANDLED(-1): trap is unhandled, trigger panic + * TRAP_RET_REPEAT(0): trap was handled, return to the trapping instruction + * (repeating it) + * TRAP_RET_CONTINUE(1): trap was handled, return to the next instruction + * (continuing after it) + */ +int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); + +/* Handler for injecting UNDEF exception to lower EL */ +void inject_undef64(cpu_context_t *ctx); + +u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el); + +/* Prototypes for system register emulation handlers provided by platforms. */ +int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx); +int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx); + +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/include/bl32/pnc/pnc.h b/include/bl32/pnc/pnc.h new file mode 100644 index 0000000000..03a32147a6 --- /dev/null +++ b/include/bl32/pnc/pnc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PNC_H__ +#define __PNC_H__ + +#define SMC_YIELD 0xbf000000 +#define SMC_ACTION_FROM_S 0xbf000001 +#define SMC_GET_SHAREDMEM 0xbf000002 +#define SMC_CONFIG_SHAREDMEM 0xbf000003 +#define SMC_ACTION_FROM_NS 0xbf000004 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +void *pncd_context_switch_to(unsigned long security_state); +int plat_pncd_setup(void); +uintptr_t plat_pncd_smc_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, + u_register_t x4, void *cookie, void *handle, + u_register_t flags); + +#endif /* __ASSEMBLER__ */ + +#endif /* __PNC_H__ */ diff --git a/include/bl32/sp_min/platform_sp_min.h b/include/bl32/sp_min/platform_sp_min.h index 971f66185d..a7dffff9ef 100644 --- a/include/bl32/sp_min/platform_sp_min.h +++ b/include/bl32/sp_min/platform_sp_min.h @@ -9,6 +9,8 @@ #include <stdint.h> +#include <common/bl_common.h> + /******************************************************************************* * Mandatory SP_MIN functions ******************************************************************************/ diff --git a/include/bl32/tsp/tsp.h b/include/bl32/tsp/tsp.h index 637e14abf7..285bfbe295 100644 --- a/include/bl32/tsp/tsp.h +++ b/include/bl32/tsp/tsp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,6 +41,7 @@ #define TSP_MUL 0x2002 #define TSP_DIV 0x2003 #define TSP_HANDLE_SEL1_INTR_AND_RETURN 0x2004 +#define TSP_CHECK_DIT 0x2005 /* * Identify a TSP service from function ID filtering the last 16 bits from the diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 77fb1f679e..4c8a17c5ba 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -81,6 +81,14 @@ #define __RODATA_END__ Load$$__RODATA_EPILOGUE__$$Base #define __RT_SVC_DESCS_START__ Load$$__RT_SVC_DESCS__$$Base #define __RT_SVC_DESCS_END__ Load$$__RT_SVC_DESCS__$$Limit +#if SPMC_AT_EL3 +#define __EL3_LP_DESCS_START__ Load$$__EL3_LP_DESCS__$$Base +#define __EL3_LP_DESCS_END__ Load$$__EL3_LP_DESCS__$$Limit +#endif +#if ENABLE_SPMD_LP +#define __SPMD_LP_DESCS_START__ Load$$__SPMD_LP_DESCS__$$Base +#define __SPMD_LP_DESCS_END__ Load$$__SPMD_LP_DESCS__$$Limit +#endif #define __RW_START__ Load$$LR$$LR_RW_DATA$$Base #define __RW_END__ Load$$LR$$LR_END$$Base #define __SPM_SHIM_EXCEPTIONS_START__ Load$$__SPM_SHIM_EXCEPTIONS__$$Base @@ -106,6 +114,10 @@ IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END); IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END); #endif +#if SEPARATE_NOBITS_REGION +IMPORT_SYM(uintptr_t, __NOBITS_START__, BL_NOBITS_BASE); +IMPORT_SYM(uintptr_t, __NOBITS_END__, BL_NOBITS_END); +#endif IMPORT_SYM(uintptr_t, __RW_END__, BL_END); #if defined(IMAGE_BL1) @@ -122,6 +134,8 @@ IMPORT_SYM(uintptr_t, __BL31_START__, BL31_START); IMPORT_SYM(uintptr_t, __BL31_END__, BL31_END); #elif defined(IMAGE_BL32) IMPORT_SYM(uintptr_t, __BL32_END__, BL32_END); +#elif defined(IMAGE_RMM) +IMPORT_SYM(uintptr_t, __RMM_END__, RMM_END); #endif /* IMAGE_BLX */ /* The following symbols are only exported from the BL2 at EL3 linker script. */ @@ -168,6 +182,7 @@ void dyn_disable_auth(void); extern const char build_message[]; extern const char version_string[]; +const char *get_version(void); void print_entry_point_info(const entry_point_info_t *ep_info); uintptr_t page_align(uintptr_t value, unsigned dir); diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h index 5147e37650..b6dd0f0061 100644 --- a/include/common/bl_common.ld.h +++ b/include/common/bl_common.ld.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,7 +24,7 @@ #define CPU_OPS \ . = ALIGN(STRUCT_ALIGN); \ __CPU_OPS_START__ = .; \ - KEEP(*(cpu_ops)) \ + KEEP(*(.cpu_ops)) \ __CPU_OPS_END__ = .; #define PARSER_LIB_DESCS \ @@ -36,13 +36,32 @@ #define RT_SVC_DESCS \ . = ALIGN(STRUCT_ALIGN); \ __RT_SVC_DESCS_START__ = .; \ - KEEP(*(rt_svc_descs)) \ + KEEP(*(.rt_svc_descs)) \ __RT_SVC_DESCS_END__ = .; +#if SPMC_AT_EL3 +#define EL3_LP_DESCS \ + . = ALIGN(STRUCT_ALIGN); \ + __EL3_LP_DESCS_START__ = .; \ + KEEP(*(.el3_lp_descs)) \ + __EL3_LP_DESCS_END__ = .; +#else +#define EL3_LP_DESCS +#endif + +#if ENABLE_SPMD_LP +#define SPMD_LP_DESCS \ + . = ALIGN(STRUCT_ALIGN); \ + __SPMD_LP_DESCS_START__ = .; \ + KEEP(*(.spmd_lp_descs)) \ + __SPMD_LP_DESCS_END__ = .; +#else +#define SPMD_LP_DESCS +#endif #define PMF_SVC_DESCS \ . = ALIGN(STRUCT_ALIGN); \ __PMF_SVC_DESCS_START__ = .; \ - KEEP(*(pmf_svc_descs)) \ + KEEP(*(.pmf_svc_descs)) \ __PMF_SVC_DESCS_END__ = .; #define FCONF_POPULATOR \ @@ -70,7 +89,9 @@ */ #define BASE_XLAT_TABLE \ . = ALIGN(16); \ - *(base_xlat_table) + __BASE_XLAT_TABLE_START__ = .; \ + *(.base_xlat_table) \ + __BASE_XLAT_TABLE_END__ = .; #if PLAT_RO_XLAT_TABLES #define BASE_XLAT_TABLE_RO BASE_XLAT_TABLE @@ -87,7 +108,9 @@ PARSER_LIB_DESCS \ CPU_OPS \ GOT \ - BASE_XLAT_TABLE_RO + BASE_XLAT_TABLE_RO \ + EL3_LP_DESCS \ + SPMD_LP_DESCS /* * .data must be placed at a lower address than the stacks if the stack @@ -122,9 +145,9 @@ #if !(defined(IMAGE_BL31) && RECLAIM_INIT_CODE) #define STACK_SECTION \ - stacks (NOLOAD) : { \ + .stacks (NOLOAD) : { \ __STACKS_START__ = .; \ - *(tzfw_normal_stacks) \ + *(.tzfw_normal_stacks) \ __STACKS_END__ = .; \ } #endif @@ -157,7 +180,7 @@ . = ALIGN(CACHE_WRITEBACK_GRANULE); \ __BAKERY_LOCK_START__ = .; \ __PERCPU_BAKERY_LOCK_START__ = .; \ - *(bakery_lock) \ + *(.bakery_lock) \ . = ALIGN(CACHE_WRITEBACK_GRANULE); \ __PERCPU_BAKERY_LOCK_END__ = .; \ __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); \ @@ -178,7 +201,7 @@ #define PMF_TIMESTAMP \ . = ALIGN(CACHE_WRITEBACK_GRANULE); \ __PMF_TIMESTAMP_START__ = .; \ - KEEP(*(pmf_timestamp_array)) \ + KEEP(*(.pmf_timestamp_array)) \ . = ALIGN(CACHE_WRITEBACK_GRANULE); \ __PMF_PERCPU_TIMESTAMP_END__ = .; \ __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); \ @@ -203,14 +226,16 @@ } /* - * The xlat_table section is for full, aligned page tables (4K). + * The .xlat_table section is for full, aligned page tables (4K). * Removing them from .bss avoids forcing 4K alignment on * the .bss section. The tables are initialized to zero by the translation * tables library. */ #define XLAT_TABLE_SECTION \ - xlat_table (NOLOAD) : { \ - *(xlat_table) \ + .xlat_table (NOLOAD) : { \ + __XLAT_TABLE_START__ = .; \ + *(.xlat_table) \ + __XLAT_TABLE_END__ = .; \ } #endif /* BL_COMMON_LD_H */ diff --git a/include/common/debug.h b/include/common/debug.h index ed0e8bf97c..5ea541da0b 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -61,8 +61,10 @@ #if LOG_LEVEL >= LOG_LEVEL_ERROR # define ERROR(...) tf_log(LOG_MARKER_ERROR __VA_ARGS__) +# define ERROR_NL() tf_log_newline(LOG_MARKER_ERROR) #else # define ERROR(...) no_tf_log(LOG_MARKER_ERROR __VA_ARGS__) +# define ERROR_NL() #endif #if LOG_LEVEL >= LOG_LEVEL_NOTICE @@ -89,26 +91,44 @@ # define VERBOSE(...) no_tf_log(LOG_MARKER_VERBOSE __VA_ARGS__) #endif +const char *get_el_str(unsigned int el); + #if ENABLE_BACKTRACE void backtrace(const char *cookie); -const char *get_el_str(unsigned int el); #else #define backtrace(x) #endif -void __dead2 do_panic(void); +void __dead2 el3_panic(void); +void __dead2 elx_panic(void); #define panic() \ do { \ backtrace(__func__); \ console_flush(); \ - do_panic(); \ + el3_panic(); \ + } while (false) + +#if CRASH_REPORTING +/* -------------------------------------------------------------------- + * do_lower_el_panic assumes it's called due to a panic from a lower EL + * This call will not return. + * -------------------------------------------------------------------- + */ +#define lower_el_panic() \ + do { \ + console_flush(); \ + elx_panic(); \ } while (false) +#else +#define lower_el_panic() +#endif /* Function called when stack protection check code detects a corrupted stack */ void __dead2 __stack_chk_fail(void); void tf_log(const char *fmt, ...) __printflike(1, 2); +void tf_log_newline(const char log_fmt[2]); void tf_log_set_max_level(unsigned int log_level); #endif /* __ASSEMBLER__ */ diff --git a/include/common/ep_info.h b/include/common/ep_info.h index 4bfa1fa6ad..771572ce9c 100644 --- a/include/common/ep_info.h +++ b/include/common/ep_info.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,14 +18,21 @@ #define SECURE EP_SECURE #define NON_SECURE EP_NON_SECURE +#define REALM EP_REALM +#if ENABLE_RME +#define sec_state_is_valid(s) (((s) == SECURE) || \ + ((s) == NON_SECURE) || \ + ((s) == REALM)) +#else #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE)) +#endif #define PARAM_EP_SECURITY_MASK EP_SECURITY_MASK #define NON_EXECUTABLE EP_NON_EXECUTABLE #define EXECUTABLE EP_EXECUTABLE -/* Secure or Non-secure image */ +/* Get/set security state of an image */ #define GET_SECURITY_STATE(x) ((x) & EP_SECURITY_MASK) #define SET_SECURITY_STATE(x, security) \ ((x) = ((x) & ~EP_SECURITY_MASK) | (security)) diff --git a/include/common/fdt_fixup.h b/include/common/fdt_fixup.h index 2e9d49d53d..9531bdb770 100644 --- a/include/common/fdt_fixup.h +++ b/include/common/fdt_fixup.h @@ -7,13 +7,32 @@ #ifndef FDT_FIXUP_H #define FDT_FIXUP_H +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#define INVALID_BASE_ADDR ((uintptr_t)~0UL) + +struct psci_cpu_idle_state { + const char *name; + uint32_t power_state; + bool local_timer_stop; + uint32_t entry_latency_us; + uint32_t exit_latency_us; + uint32_t min_residency_us; + uint32_t wakeup_latency_us; +}; + int dt_add_psci_node(void *fdt); int dt_add_psci_cpu_enable_methods(void *fdt); int fdt_add_reserved_memory(void *dtb, const char *node_name, uintptr_t base, size_t size); int fdt_add_cpus_node(void *dtb, unsigned int afflv0, unsigned int afflv1, unsigned int afflv2); -int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, +int fdt_add_cpu_idle_states(void *dtb, const struct psci_cpu_idle_state *state); +int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, uintptr_t gicr_base, unsigned int gicr_frame_size); +int fdt_set_mac_address(void *dtb, unsigned int ethernet_idx, + const uint8_t *mac_addr); #endif /* FDT_FIXUP_H */ diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h index e8b39335d4..abbf9764b9 100644 --- a/include/common/fdt_wrappers.h +++ b/include/common/fdt_wrappers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #define FDT_WRAPPERS_H #include <libfdt_env.h> +#include <libfdt.h> /* Number of cells, given total length in bytes. Each cell is 4 bytes long */ #define NCELLS(len) ((len) / 4U) @@ -41,11 +42,31 @@ int fdt_get_stdout_node_offset(const void *dtb); uint64_t fdtw_translate_address(const void *dtb, int bus_node, uint64_t base_address); +int fdtw_for_each_cpu(const void *fdt, + int (*callback)(const void *dtb, int node, uintptr_t mpidr)); + +int fdtw_find_or_add_subnode(void *fdt, int parentoffset, const char *name); + static inline uint32_t fdt_blob_size(const void *dtb) { - const uint32_t *dtb_header = dtb; + const uint32_t *dtb_header = (const uint32_t *)dtb; return fdt32_to_cpu(dtb_header[1]); } +static inline bool fdt_node_is_enabled(const void *fdt, int node) +{ + int len; + const void *prop = fdt_getprop(fdt, node, "status", &len); + + /* A non-existing status property means the device is enabled. */ + return (prop == NULL) || (len == 5 && strcmp((const char *)prop, + "okay") == 0); +} + +#define fdt_for_each_compatible_node(dtb, node, compatible_str) \ +for (node = fdt_node_offset_by_compatible(dtb, -1, compatible_str); \ + node >= 0; \ + node = fdt_node_offset_by_compatible(dtb, node, compatible_str)) + #endif /* FDT_WRAPPERS_H */ diff --git a/include/common/feat_detect.h b/include/common/feat_detect.h new file mode 100644 index 0000000000..788dfb31f0 --- /dev/null +++ b/include/common/feat_detect.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FEAT_DETECT_H +#define FEAT_DETECT_H + +/* Function Prototypes */ +void detect_arch_features(void); + +/* Macro Definitions */ +#define FEAT_STATE_DISABLED 0 +#define FEAT_STATE_ALWAYS 1 +#define FEAT_STATE_CHECK 2 + +#endif /* FEAT_DETECT_H */ diff --git a/include/common/interrupt_props.h b/include/common/interrupt_props.h index 07bafaae54..681c896876 100644 --- a/include/common/interrupt_props.h +++ b/include/common/interrupt_props.h @@ -19,7 +19,7 @@ } typedef struct interrupt_prop { - unsigned int intr_num:10; + unsigned int intr_num:13; unsigned int intr_pri:8; unsigned int intr_grp:2; unsigned int intr_cfg:2; diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h index 472a32a1f7..26e8d6f283 100644 --- a/include/common/runtime_svc.h +++ b/include/common/runtime_svc.h @@ -72,7 +72,7 @@ typedef struct rt_svc_desc { */ #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ static const rt_svc_desc_t __svc_desc_ ## _name \ - __section("rt_svc_descs") __used = { \ + __section(".rt_svc_descs") __used = { \ .start_oen = (_start), \ .end_oen = (_end), \ .call_type = (_type), \ @@ -90,11 +90,11 @@ typedef struct rt_svc_desc { * 3. ensure that the assembler and the compiler see the handler * routine at the same offset. */ -CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC), \ +CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC), assert_sizeof_rt_svc_desc_mismatch); -CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init), \ +CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init), assert_rt_svc_desc_init_offset_mismatch); -CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \ +CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), assert_rt_svc_desc_handle_offset_mismatch); diff --git a/include/common/tbbr/cot_def.h b/include/common/tbbr/cot_def.h index 800ad07eb2..bf23917bbf 100644 --- a/include/common/tbbr/cot_def.h +++ b/include/common/tbbr/cot_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,13 +7,20 @@ #ifndef COT_DEF_H #define COT_DEF_H +/* + * Guard here with availability of mbedtls config since PLAT=lx2162aqds + * uses custom tbbr from 'drivers/nxp/auth/tbbr/tbbr_cot.c' and also may + * build without mbedtls folder only with TRUSTED_BOOT enabled. + */ #ifdef MBEDTLS_CONFIG_FILE -#include MBEDTLS_CONFIG_FILE +#include <mbedtls/version.h> #endif /* TBBR CoT definitions */ #if defined(SPD_spmd) #define COT_MAX_VERIFIED_PARAMS 8 +#elif defined(ARM_COT_cca) +#define COT_MAX_VERIFIED_PARAMS 8 #else #define COT_MAX_VERIFIED_PARAMS 4 #endif @@ -25,7 +32,12 @@ * buffers must be big enough to hold either. As RSA keys are bigger than ECDSA * ones for all key sizes we support, they impose the minimum size of these * buffers. + * + * If the platform employs its own mbedTLS configuration, it is the platform's + * responsibility to define TF_MBEDTLS_USE_RSA or TF_MBEDTLS_USE_ECDSA to + * establish the appropriate PK_DER_LEN size. */ +#ifdef MBEDTLS_CONFIG_FILE #if TF_MBEDTLS_USE_RSA #if TF_MBEDTLS_KEY_SIZE == 1024 #define PK_DER_LEN 162 @@ -38,9 +50,17 @@ #else #error "Invalid value for TF_MBEDTLS_KEY_SIZE" #endif -#else /* Only using ECDSA keys. */ -#define PK_DER_LEN 91 +#elif TF_MBEDTLS_USE_ECDSA +#if TF_MBEDTLS_KEY_SIZE == 384 +#define PK_DER_LEN 120 +#elif TF_MBEDTLS_KEY_SIZE == 256 +#define PK_DER_LEN 92 +#else +#error "Invalid value for TF_MBEDTLS_KEY_SIZE" #endif +#else +#error "Invalid value of algorithm" +#endif /* TF_MBEDTLS_USE_RSA */ #if TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA256 #define HASH_DER_LEN 51 @@ -51,5 +71,6 @@ #else #error "Invalid value for TF_MBEDTLS_HASH_ALG_ID" #endif +#endif /* MBEDTLS_CONFIG_FILE */ #endif /* COT_DEF_H */ diff --git a/include/common/hw_crc32.h b/include/common/tf_crc32.h index 0d14d57392..38c56a50dc 100644 --- a/include/common/hw_crc32.h +++ b/include/common/tf_crc32.h @@ -4,13 +4,13 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef HW_CRC32_H -#define HW_CRC32_H +#ifndef TF_CRC32_H +#define TF_CRC32_H #include <stddef.h> #include <stdint.h> /* compute CRC using Arm intrinsic function */ -uint32_t hw_crc32(uint32_t crc, const unsigned char *buf, size_t size); +uint32_t tf_crc32(uint32_t crc, const unsigned char *buf, size_t size); -#endif /* HW_CRC32_H */ +#endif /* TF_CRC32_H */ diff --git a/include/common/uuid.h b/include/common/uuid.h index 5651d0d583..634880449f 100644 --- a/include/common/uuid.h +++ b/include/common/uuid.h @@ -1,15 +1,21 @@ /* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef UUID_H -#define UUID_H +#ifndef UUID_COMMON_H +#define UUID_COMMON_H + +#include <stdbool.h> +#include <stdint.h> #define UUID_BYTES_LENGTH 16 #define UUID_STRING_LENGTH 36 int read_uuid(uint8_t *dest, char *uuid); +bool uuid_match(uint32_t *uuid1, uint32_t *uuid2); +void copy_uuid(uint32_t *to_uuid, uint32_t *from_uuid); +bool is_null_uuid(uint32_t *uuid); -#endif /* UUID_H */ +#endif /* UUID_COMMON_H */ diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h index 222820b120..8b90c7f0c2 100644 --- a/include/drivers/allwinner/axp.h +++ b/include/drivers/allwinner/axp.h @@ -47,6 +47,13 @@ int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask); int axp_check_id(void); void axp_power_off(void); + +#if SUNXI_SETUP_REGULATORS == 1 void axp_setup_regulators(const void *fdt); +#else +static inline void axp_setup_regulators(const void *fdt) +{ +} +#endif #endif /* AXP_H */ diff --git a/include/drivers/arm/arm_gicv3_common.h b/include/drivers/arm/arm_gicv3_common.h index b88b59fbf1..d1e93be670 100644 --- a/include/drivers/arm/arm_gicv3_common.h +++ b/include/drivers/arm/arm_gicv3_common.h @@ -17,4 +17,12 @@ #define WAKER_SL_BIT (1U << WAKER_SL_SHIFT) #define WAKER_QSC_BIT (1U << WAKER_QSC_SHIFT) +#define IIDR_MODEL_ARM_GIC_600 U(0x0200043b) +#define IIDR_MODEL_ARM_GIC_600AE U(0x0300043b) +#define IIDR_MODEL_ARM_GIC_700 U(0x0400043b) + +#define PIDR_COMPONENT_ARM_DIST U(0x492) +#define PIDR_COMPONENT_ARM_REDIST U(0x493) +#define PIDR_COMPONENT_ARM_ITS U(0x494) + #endif /* ARM_GICV3_COMMON_H */ diff --git a/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h b/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h deleted file mode 100644 index 2cb8938d2b..0000000000 --- a/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_CRYPTO_BOOT_DEFS_H -#define _CC_CRYPTO_BOOT_DEFS_H - -/*! @file -@brief This file contains SBROM definitions -*/ - -/*! Version counters value. */ -typedef enum { - - CC_SW_VERSION_COUNTER1 = 1, /*!< Counter 1 - trusted version. */ - CC_SW_VERSION_COUNTER2, /*!< Counter 2 - non trusted version. */ - - CC_SW_VERSION_MAX = 0x7FFFFFFF - -} CCSbSwVersionId_t; - -/* HASH boot key definition */ -typedef enum { - CC_SB_HASH_BOOT_KEY_0_128B = 0, /*!< 128-bit truncated SHA256 digest of public key 0. */ - CC_SB_HASH_BOOT_KEY_1_128B = 1, /*!< 128-bit truncated SHA256 digest of public key 1. */ - CC_SB_HASH_BOOT_KEY_256B = 2, /*!< 256-bit SHA256 digest of public key. */ - CC_SB_HASH_BOOT_NOT_USED = 0xFF, - CC_SB_HASH_MAX_NUM = 0x7FFFFFFF, /*!\internal use external 128-bit truncated SHA256 digest */ -} CCSbPubKeyIndexType_t; - - -#endif diff --git a/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h deleted file mode 100644 index 212a710be0..0000000000 --- a/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*! -@file -@brief This file contains the platform-dependent definitions that are used in the SBROM code. -*/ - -#ifndef _CC_PAL_SB_PLAT_H -#define _CC_PAL_SB_PLAT_H - -#include "cc_pal_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! Definition of DMA address type, can be 32 bits or 64 bits according to CryptoCell's HW. */ -typedef uint64_t CCDmaAddr_t; -/*! Definition of CryptoCell address type, can be 32 bits or 64 bits according to platform. */ -typedef uintptr_t CCAddr_t; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types.h b/include/drivers/arm/cryptocell/712/cc_pal_types.h deleted file mode 100644 index 8c09b23cc7..0000000000 --- a/include/drivers/arm/cryptocell/712/cc_pal_types.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CC_PAL_TYPES_H -#define CC_PAL_TYPES_H - -/*! -@file -@brief This file contains platform-dependent definitions and types. -*/ - -#include "cc_pal_types_plat.h" - -typedef enum { - CC_FALSE = 0, - CC_TRUE = 1 -} CCBool; - -#define CC_SUCCESS 0UL -#define CC_FAIL 1UL - -#define CC_1K_SIZE_IN_BYTES 1024 -#define CC_BITS_IN_BYTE 8 -#define CC_BITS_IN_32BIT_WORD 32 -#define CC_32BIT_WORD_SIZE (sizeof(uint32_t)) - -#define CC_OK CC_SUCCESS - -#define CC_UNUSED_PARAM(prm) ((void)prm) - -#define CC_MAX_UINT32_VAL (0xFFFFFFFF) - -#define CALC_FULL_BYTES(numBits) (((numBits) + (CC_BITS_IN_BYTE - 1))/CC_BITS_IN_BYTE) -#define CALC_FULL_32BIT_WORDS(numBits) (((numBits) + (CC_BITS_IN_32BIT_WORD - 1))/CC_BITS_IN_32BIT_WRD) -#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) (((sizeBytes) + CC_32BIT_WORD_SIZE - 1)/CC_32BIT_WORD_SIZE) - -#endif diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h deleted file mode 100644 index 84100245b2..0000000000 --- a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*! @file -@brief This file contains basic type definitions that are platform-dependent. -*/ -#ifndef _CC_PAL_TYPES_PLAT_H -#define _CC_PAL_TYPES_PLAT_H -/* Host specific types for standard (ISO-C99) compilant platforms */ - -#include <stddef.h> -#include <stdint.h> - -typedef uint32_t CCStatus; - -#define CCError_t CCStatus -#define CC_INFINITE 0xFFFFFFFF - -#define CEXPORT_C -#define CIMPORT_C - -#endif /*_CC_PAL_TYPES_PLAT_H*/ diff --git a/include/drivers/arm/cryptocell/712/cc_sec_defs.h b/include/drivers/arm/cryptocell/712/cc_sec_defs.h deleted file mode 100644 index d41921855b..0000000000 --- a/include/drivers/arm/cryptocell/712/cc_sec_defs.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_SEC_DEFS_H -#define _CC_SEC_DEFS_H - -/*! -@file -@brief This file contains general hash definitions and types. -*/ - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! The hashblock size in words. */ -#define HASH_BLOCK_SIZE_IN_WORDS 16 -/*! The hash - SHA2 results in words. */ -#define HASH_RESULT_SIZE_IN_WORDS 8 -#define HASH_RESULT_SIZE_IN_BYTES 32 - -/*! Definition for hash result array. */ -typedef uint32_t CCHashResult_t[HASH_RESULT_SIZE_IN_WORDS]; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/crypto_driver.h b/include/drivers/arm/cryptocell/712/crypto_driver.h deleted file mode 100644 index 18104dd7d4..0000000000 --- a/include/drivers/arm/cryptocell/712/crypto_driver.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CRYPTO_DRIVER_H -#define _CRYPTO_DRIVER_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_sb_plat.h" -#include "cc_sec_defs.h" - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ -/*! - * @brief This function gives the functionality of integrated hash - * - * @param[in] hwBaseAddress - CryptoCell base address - * @param[out] hashResult - the HASH result. - * - */ -CCError_t SBROM_CryptoHash(unsigned long hwBaseAddress, CCDmaAddr_t inputDataAddr, uint32_t BlockSize, - CCHashResult_t hashResult); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/nvm.h b/include/drivers/arm/cryptocell/712/nvm.h deleted file mode 100644 index a70289fb89..0000000000 --- a/include/drivers/arm/cryptocell/712/nvm.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _NVM__H -#define _NVM__H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_crypto_boot_defs.h" -#include "cc_pal_types.h" -#include "cc_sec_defs.h" - -/*------------------------------------ - DEFINES --------------------------------------*/ - -/** - * @brief This function reads the LCS from the SRAM/NVM - * - * @param[in] hwBaseAddress - CryptoCell base address - * - * @param[in/out] lcs_ptr - pointer to memory to store the LCS - * - * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h - */ -CCError_t NVM_GetLCS(unsigned long hwBaseAddress, uint32_t *lcs_ptr); - -/** - * @brief The NVM_ReadHASHPubKey function is a NVM interface function - - * The function retrieves the HASH of the device Public key from the SRAM/NVM - * - * @param[in] hwBaseAddress - CryptoCell base address - * - * @param[in] pubKeyIndex - Index of HASH in the OTP - * - * @param[out] PubKeyHASH - the public key HASH. - * - * @param[in] hashSizeInWords - hash size (valid values: 4W, 8W) - * - * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h - */ - -CCError_t NVM_ReadHASHPubKey(unsigned long hwBaseAddress, CCSbPubKeyIndexType_t pubKeyIndex, CCHashResult_t PubKeyHASH, uint32_t hashSizeInWords); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/nvm_otp.h b/include/drivers/arm/cryptocell/712/nvm_otp.h deleted file mode 100644 index 390d62bc1d..0000000000 --- a/include/drivers/arm/cryptocell/712/nvm_otp.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _NVM_OTP_H -#define _NVM_OTP_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_crypto_boot_defs.h" -#include "cc_pal_types.h" - -/*------------------------------------ - DEFINES --------------------------------------*/ - - - -/** - * @brief The NVM_GetSwVersion function is a NVM interface function - - * The function retrieves the SW version from the SRAM/NVM. - * In case of OTP, we support up to 16 anti-rollback counters (taken from the certificate) - * - * @param[in] hwBaseAddress - CryptoCell base address - * - * @param[in] counterId - relevant only for OTP (valid values: 1,2) - * - * @param[out] swVersion - the minimum SW version - * - * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h - */ -CCError_t NVM_GetSwVersion(unsigned long hwBaseAddress, CCSbSwVersionId_t counterId, uint32_t *swVersion); - - -/** - * @brief The NVM_SetSwVersion function is a NVM interface function - - * The function writes the SW version into the SRAM/NVM. - * In case of OTP, we support up to 16 anti-rollback counters (taken from the certificate) - * - * @param[in] hwBaseAddress - CryptoCell base address - * - * @param[in] counterId - relevant only for OTP (valid values: 1,2) - * - * @param[in] swVersion - the minimum SW version - * - * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h - */ -CCError_t NVM_SetSwVersion(unsigned long hwBaseAddress, CCSbSwVersionId_t counterId, uint32_t swVersion); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/rsa.h b/include/drivers/arm/cryptocell/712/rsa.h deleted file mode 100644 index 825214d20f..0000000000 --- a/include/drivers/arm/cryptocell/712/rsa.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef RSA_H -#define RSA_H - -/* - * All the includes that are needed for code using this module to - * compile correctly should be #included here. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_types.h" - -/************************ Defines ******************************/ - -/* the modulus size in bits */ -#if (KEY_SIZE == 2048) -#define RSA_MOD_SIZE_IN_BITS 2048UL -#elif (KEY_SIZE == 3072) -#define RSA_MOD_SIZE_IN_BITS 3072UL -#else -#error Unsupported CryptoCell key size requested -#endif - -#define RSA_MOD_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_MOD_SIZE_IN_BITS)) -#define RSA_MOD_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_MOD_SIZE_IN_BITS)) -#define RSA_MOD_SIZE_IN_256BITS (RSA_MOD_SIZE_IN_WORDS/8) -#define RSA_EXP_SIZE_IN_BITS 17UL -#define RSA_EXP_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_EXP_SIZE_IN_BITS)) - -/* - * @brief The RSA_CalcNp calculates Np value and saves it into Np_ptr: - * - * - - * @param[in] hwBaseAddress - HW base address. Relevant for HW - * implementation, for SW it is ignored. - * @N_ptr[in] - The pointer to the modulus buffer. - * @Np_ptr[out] - pointer to Np vector buffer. Its size must be >= 160. - */ -void RSA_CalcNp(unsigned long hwBaseAddress, - uint32_t *N_ptr, - uint32_t *Np_ptr); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h b/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h deleted file mode 100644 index de835461fd..0000000000 --- a/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SBROM_BSV_API_H -#define _SBROM_BSV_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! @file -@brief This file contains all SBROM library APIs and definitions. -*/ -#include "cc_pal_types.h" - -/* Life cycle state definitions */ -#define CC_BSV_CHIP_MANUFACTURE_LCS 0x0 /*!< CM lifecycle value. */ -#define CC_BSV_DEVICE_MANUFACTURE_LCS 0x1 /*!< DM lifecycle value. */ -#define CC_BSV_SECURITY_DISABLED_LCS 0x3 /*!< SD lifecycle value. */ -#define CC_BSV_SECURE_LCS 0x5 /*!< Secure lifecycle value. */ -#define CC_BSV_RMA_LCS 0x7 /*!< RMA lifecycle value. */ - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - -/*! -@brief This function should be the first ARM TrustZone CryptoCell TEE SBROM library API called. -It verifies the HW product and version numbers. - -@return CC_OK On success. -@return A non-zero value from sbrom_bsv_error.h on failure. -*/ -CCError_t CC_BsvSbromInit( - unsigned long hwBaseAddress /*!< [in] HW registers base address. */ - ); - - -/*! -@brief This function can be used for checking the LCS value, after CC_BsvLcsGetAndInit was called by the Boot ROM. - -@return CC_OK On success. -@return A non-zero value from sbrom_bsv_error.h on failure. -*/ -CCError_t CC_BsvLcsGet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - uint32_t *pLcs /*!< [out] Returned lifecycle state. */ - ); - -/*! -@brief This function retrieves the HW security lifecycle state, performs validity checks, -and additional initializations in case the LCS is RMA (sets the Kce to fixed value). -\note Invalid LCS results in an error returned. -In this case, the customer's code must completely disable the device. - -@return CC_OK On success. -@return A non-zero value from sbrom_bsv_error.h on failure. -*/ -CCError_t CC_BsvLcsGetAndInit( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - uint32_t *pLcs /*!< [out] Returned lifecycle state. */ - ); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/secureboot_base_func.h b/include/drivers/arm/cryptocell/712/secureboot_base_func.h deleted file mode 100644 index 6db596e0d7..0000000000 --- a/include/drivers/arm/cryptocell/712/secureboot_base_func.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SECURE_BOOT_BASE_FUNC_H -#define _SECURE_BOOT_BASE_FUNC_H - - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_types.h" -#include "secureboot_gen_defs.h" - - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - -/** - * @brief This function calculates the HASH over the given data and than verify - * RSA signature on that hashed data - * - * @param[in] hwBaseAddr - CryptoCell base address - * @param[in] pData - pointer to the data to be verified - * @param[in] pNParams - a pointer to the public key parameters - * @param[in] pSignature - a pointer to the signature structure - * @param[in] sizeOfData - size of the data to calculate the HASH on (in bytes) - * @param[in] RSAAlg - RSA algorithm to use - * - * @return CCError_t - On success the value CC_OK is returned, - * on failure - a value from BootImagesVerifier_error.h - */ -CCError_t CCSbVerifySignature(unsigned long hwBaseAddress, - uint32_t *pData, - CCSbNParams_t *pNParams, - CCSbSignature_t *pSignature, - uint32_t sizeOfData, - CCSbRsaAlg_t RSAAlg); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h deleted file mode 100644 index ed1f2835c8..0000000000 --- a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SECURE_BOOT_GEN_DEFS_H -#define _SECURE_BOOT_GEN_DEFS_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! @file -@brief This file contains all of the definitions and structures that are used for the secure boot. -*/ - -#include "cc_pal_sb_plat.h" -#include "cc_sec_defs.h" - - -/* General definitions */ -/***********************/ - -/*RSA definitions*/ -#if (KEY_SIZE == 2048) -#define SB_RSA_MOD_SIZE_IN_WORDS 64 -#elif (KEY_SIZE == 3072) -#define SB_RSA_MOD_SIZE_IN_WORDS 96 -#else -#error Unsupported CryptoCell key size requested -#endif - -#define SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS 5 - - -/*! Public key data structure. */ -typedef struct { - uint32_t N[SB_RSA_MOD_SIZE_IN_WORDS]; /*!< N public key, big endian representation. */ - uint32_t Np[SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS]; /*!< Np (Barrett n' value). */ -} CCSbNParams_t; - -/*! Signature structure. */ -typedef struct { - uint32_t sig[SB_RSA_MOD_SIZE_IN_WORDS]; /*!< RSA PSS signature. */ -} CCSbSignature_t; - - -/********* Supported algorithms definitions ***********/ - -/*! RSA supported algorithms */ -/* Note: this applies to either 2k or 3k based on CryptoCell SBROM library - * version - it means 2k in version 1 and 3k in version 2 (yes, really). - */ -typedef enum { - RSA_PSS = 0x01, /*!< RSA PSS after hash SHA 256 */ - RSA_PKCS15 = 0x02, /*!< RSA PKX15 */ - RSA_Last = 0x7FFFFFFF -} CCSbRsaAlg_t; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/712/util.h b/include/drivers/arm/cryptocell/712/util.h deleted file mode 100644 index 18fb5999dc..0000000000 --- a/include/drivers/arm/cryptocell/712/util.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef UTIL_H -#define UTIL_H - -/* - * All the includes that are needed for code using this module to - * compile correctly should be #included here. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/************************ Defines ******************************/ - -/* invers the bytes on a word- used for output from HASH */ -#ifdef BIG__ENDIAN -#define UTIL_INVERSE_UINT32_BYTES(val) (val) -#else -#define UTIL_INVERSE_UINT32_BYTES(val) \ - (((val) >> 24) | (((val) & 0x00FF0000) >> 8) | (((val) & 0x0000FF00) << 8) | (((val) & 0x000000FF) << 24)) -#endif - -/* invers the bytes on a word - used for input data for HASH */ -#ifdef BIG__ENDIAN -#define UTIL_REVERT_UINT32_BYTES(val) \ - (((val) >> 24) | (((val) & 0x00FF0000) >> 8) | (((val) & 0x0000FF00) << 8) | (((val) & 0x000000FF) << 24)) -#else -#define UTIL_REVERT_UINT32_BYTES(val) (val) -#endif - - /* ------------------------------------------------------------ - ** - * @brief This function executes a reverse bytes copying from one buffer to another buffer. - * - * @param[in] dst_ptr - The pointer to destination buffer. - * @param[in] src_ptr - The pointer to source buffer. - * @param[in] size - The size in bytes. - * - */ - -void UTIL_ReverseMemCopy(uint8_t *dst_ptr, uint8_t *src_ptr, uint32_t size); - - - /* ------------------------------------------------------------ - ** - * @brief This function executes a reversed byte copy on a specified buffer. - * - * on a 6 byte byffer: - * - * buff[5] <---> buff[0] - * buff[4] <---> buff[1] - * buff[3] <---> buff[2] - * - * @param[in] dst_ptr - The counter buffer. - * @param[in] src_ptr - The counter size in bytes. - * - */ -void UTIL_ReverseBuff(uint8_t *buff_ptr, uint32_t size); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/drivers/arm/cryptocell/713/bsv_api.h b/include/drivers/arm/cryptocell/713/bsv_api.h deleted file mode 100644 index dc494735c1..0000000000 --- a/include/drivers/arm/cryptocell/713/bsv_api.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_API_H -#define _BSV_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file contains the Boot Services APIs and definitions. - -@defgroup cc_bsv_api CryptoCell Boot Services APIs and definitions -@{ -@ingroup cc_bsv -*/ - -#include "cc_pal_types.h" -#include "cc_sec_defs.h" -#include "cc_boot_defs.h" - -/* Life cycle state definitions. */ -#define CC_BSV_CHIP_MANUFACTURE_LCS 0x0 /*!< The CM life-cycle state (LCS) value. */ -#define CC_BSV_DEVICE_MANUFACTURE_LCS 0x1 /*!< The DM life-cycle state (LCS) value. */ -#define CC_BSV_SECURE_LCS 0x5 /*!< The Secure life-cycle state (LCS) value. */ -#define CC_BSV_RMA_LCS 0x7 /*!< The RMA life-cycle state (LCS) value. */ -#define CC_BSV_INVALID_LCS 0xff /*!< The invalid life-cycle state (LCS) value. */ - -/*---------------------------- - TYPES ------------------------------------*/ - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - - -/*! -@brief This function verifies the product and version numbers of the HW, and initializes it. - -\warning This function must be the first CryptoCell-7xx SBROM library API called. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvInit( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); - -/*! -@brief This function retrieves the HW LCS and performs validity checks. - -If the LCS is RMA, it also sets the OTP secret keys to a fixed value. - -@note An error is returned if there is an invalid LCS. If this happens, your code must -completely disable the device. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvGetAndInitLcs( - unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - uint32_t *pLcs /*!< [out] The value of the current LCS. */ - ); - -/*! -@brief This function retrieves the LCS from the NVM manager. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvLcsGet( - unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - uint32_t *pLcs /*!< [out] The value of the current LCS. */ - ); - -/*! -@brief This function reads software revocation counter from OTP memory, according to the provided sw version index. -SW version is stored in NVM counter and represented by ones. Meaning seVersion=5 would be stored as binary 0b11111; -hence: - the maximal of trusted is 32 - the maximal of non-trusted is 224 - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSwVersionGet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCSbSwVersionId_t id, /*!< [in] Enumeration defining the trusted/non-trusted counter to read. */ - uint32_t *swVersion /*!< [out] The value of the requested counter as read from OTP memory. */ - ); - -/*! -@brief This function sets the NVM counter according to swVersionID (trusted/non-trusted). - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSwVersionSet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCSbSwVersionId_t id, /*!< [in] Enumeration defining the trusted/non-trusted counter to read. */ - uint32_t swVersion /*!< [in] New value of the counter to be programmed in OTP memory. */ - ); - -/*! -@brief This function sets the "fatal error" flag in the NVM manager, to disable the use of -any HW keys or security services. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvFatalErrorSet( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); - -/*! -@brief This function retrieves the public key hash from OTP memory, according to the provided index. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvPubKeyHashGet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCSbPubKeyIndexType_t keyIndex, /*!< [in] Enumeration defining the key hash to retrieve: 128-bit HBK0, 128-bit HBK1, or 256-bit HBK. */ - uint32_t *hashedPubKey, /*!< [out] A buffer to contain the public key HASH. */ - uint32_t hashResultSizeWords /*!< [in] The size of the hash in 32-bit words: - - Must be 4 for 128-bit hash. - - Must be 8 for 256bit hash. */ - ); - -/*! -@brief This function permanently sets the RMA LCS for the ICV and the OEM. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvRMAModeEnable( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); - -/*! -@brief This function is called by the ICV code, to disable the OEM code from changing the ICV RMA bit flag. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvICVRMAFlagBitLock( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); - -/*! -@brief This function locks the defined ICV class keys from further usage. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvICVKeyLock( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCBool_t isICVProvisioningKeyLock, /*!< [in] Should the provisioning key be locked. */ - CCBool_t isICVCodeEncKeyLock /*!< [in] Should the encryption key be locked. */ - ); - - -/*! -@brief This function retrieves the value of "secure disable" bit. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSecureDisableGet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCBool_t *isSDEnabled /*!< [out] The value of the SD Enable bit. */ - ); - - -/*! -@brief This function derives the platform key (Kplt) from the Kpicv, and then decrypts the customer key (Kcst) -from the EKcst (burned in the OTP). The decryption is done only in Secure and RMA LCS mode using AES-ECB. -The customer ROM should invoke this function during early boot, prior to running any non-ROM code, only if Kcst exists. -The resulting Kcst is saved in a HW register. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvCustomerKeyDecrypt( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); -#ifdef __cplusplus -} -#endif - -/*! -@brief This function derives the unique SoC_ID for the device, as hashed (Hbk || AES_CMAC (HUK)). - -@note SoC_ID is required to create debug certificates. - -The OEM or ICV must provide a method for a developer to discover the SoC_ID of a target -device without having to first enable debugging. -One suggested implementation is to have the device ROM code compute the SoC_ID and place -it in a specific location in the flash memory, from where it can be accessed by the developer. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSocIDCompute( - unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - CCHashResult_t hashResult /*!< [out] The derived SoC_ID. */ - ); - -#endif /* _BSV_API_H */ - -/** -@} - */ - diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_api.h b/include/drivers/arm/cryptocell/713/bsv_crypto_api.h deleted file mode 100644 index 1e60579317..0000000000 --- a/include/drivers/arm/cryptocell/713/bsv_crypto_api.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_CRYPTO_API_H -#define _BSV_CRYPTO_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file contains the cryptographic ROM APIs of the Boot Services. - -@defgroup cc_bsv_crypto_api CryptoCell Boot Services cryptographic ROM APIs -@{ -@ingroup cc_bsv -*/ - -#include "cc_pal_types.h" -#include "cc_sec_defs.h" -#include "cc_address_defs.h" -#include "bsv_crypto_defs.h" - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - -/*! -@brief This function calculates the SHA-256 digest over contiguous memory -in an integrated operation. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSha256( - unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - uint8_t *pDataIn, /*!< [in] A pointer to the input buffer to be hashed. The buffer must be contiguous. */ - size_t dataSize, /*!< [in] The size of the data to be hashed, in bytes. */ - CCHashResult_t hashBuff /*!< [out] A pointer to a word-aligned 32-byte buffer. */ - ); - - -/*! -@brief This function allows you to calculate SHA256 digest of an image with decryption base on AES-CTR, -with HW or user key. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. (in this case, hashBuff will be returned clean, while the output data should be cleaned by the user). -*/ -CCError_t CC_BsvCryptoImageDecrypt( unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - CCBsvflowMode_t flow, /*!< [in] The supported operations are: HASH, AES to HASH, AES and HASH. */ - CCBsvKeyType_t keyType, /*!< [in] The key type to use: Kce, Kceicv, or user key. */ - uint8_t *pUserKey, /*!< [in] A pointer to the user key buffer in case keyType is CC_BSV_USER_KEY. */ - size_t userKeySize, /*!< [in] The user key size in bytes (128bits) in case keyType is CC_BSV_USER_KEY. */ - uint8_t *pIvBuf, /*!< [in] A pointer to the IV / counter buffer. */ - uint8_t *pInputData, /*!< [in] A pointer to the input data. */ - uint8_t *pOutputData, /*!< [out] A pointer to the output buffer. (optional – should be null in case of hash only). */ - size_t dataSize, /*!< [in] The size of the input data in bytes. MUST be multiple of AES block size. */ - CCHashResult_t hashBuff /*!< [out] A pointer to a word-aligned 32-byte digest output buffer. */ - ); - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ - diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h b/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h deleted file mode 100644 index 406e1effbb..0000000000 --- a/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_CRYPTO_ASYM_API_H -#define _BSV_CRYPTO_ASYM_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file contains the cryptographic Asymmetric ROM APIs of the Boot Services. - -@defgroup cc_bsv_crypto_asym_api CryptoCell Boot Services cryptographic Asymmetric ROM APIs -@{ -@ingroup cc_bsv -*/ - -#include "cc_pal_types.h" -#include "cc_pka_hw_plat_defs.h" -#include "cc_sec_defs.h" -#include "bsv_crypto_api.h" - -/*! Defines the workspace size in bytes needed for internal Asymmetric operations. */ -#define BSV_RSA_WORKSPACE_MIN_SIZE (4*BSV_CERT_RSA_KEY_SIZE_IN_BYTES +\ - 2*RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES) - -/*! Definition for the RSA public modulus array. */ -typedef uint32_t CCBsvNBuff_t[BSV_CERT_RSA_KEY_SIZE_IN_WORDS]; - -/*! Definition for the RSA Barrett mod tag array. */ -typedef uint32_t CCBsvNpBuff_t[RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES]; - -/*! Definition for the RSA signature array. */ -typedef uint32_t CCBsvSignature_t[BSV_CERT_RSA_KEY_SIZE_IN_WORDS]; - - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - -/*! -@brief This function performs the primitive operation of RSA, meaning exponent and modulus. - outBuff = (pInBuff ^ Exp) mod NBuff. ( Exp = 0x10001 ) - - The function supports 2k and 3K bit size of modulus, based on compile time define. - There are no restriction on pInBuff location, however its size must be equal to BSV_RSA_KEY_SIZE_IN_BYTES and its - value must be smaller than the modulus. - - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvRsaPrimVerify (unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - CCBsvNBuff_t NBuff, /*!< [in] The modulus buffer big endian format. */ - CCBsvNpBuff_t NpBuff, /*!< [in] The barret tag buffer big endian format - optional. */ - uint32_t *pInBuff, /*!< [in] The DataIn buffer to be encrypted. */ - size_t inBuffSize, /*!< [in] The DataIn buffer size in bytes, must be BSV_RSA_KEY_SIZE_IN_BYTES. */ - CCBsvSignature_t pOutBuff, /*!< [out] The encrypted buffer in big endian format. */ - uint32_t *pWorkSpace, /*!< [in] The pointer to user allocated buffer for internal use. */ - size_t workBufferSize /*!< [in] The size in bytes of pWorkSpace, must be at-least BSV_RSA_WORKSPACE_MIN_SIZE. */ -); - - -/*! -@brief This function performs RSA PSS verify. - - The function should support 2k and 3K bit size of modulus, based on compile time define. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvRsaPssVerify (unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - CCBsvNBuff_t NBuff, /*!< [in] The modulus buffer big endian format. */ - CCBsvNpBuff_t NpBuff, /*!< [in] The barret tag buffer big endian format - optional. */ - CCBsvSignature_t signature, /*!< [in] The signature buffer to verify - big endian format. */ - CCHashResult_t hashedData, /*!< [in] The data-in buffer to be verified as sha256 digest. */ - uint32_t *pWorkSpace, /*!< [in] The pointer to user allocated buffer for internal use. */ - size_t workBufferSize, /*!< [in] The size in bytes of pWorkSpace, must be at-least BSV_RSA_WORKSPACE_MIN_SIZE. */ - CCBool_t *pIsVerified /*!< [out] The flag indicates whether the signature is verified or not. - If verified value will be CC_TRUE, otherwise CC_FALSE */ -); - - - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ - diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h b/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h deleted file mode 100644 index 9ea354deba..0000000000 --- a/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_CRYPTO_DEFS_H -#define _BSV_CRYPTO_DEFS_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file contains the definitions of the cryptographic ROM APIs. - -@defgroup cc_bsv_crypto_defs CryptoCell Boot Services cryptographic ROM API definitions -@{ -@ingroup cc_bsv -*/ - -/*! AES supported HW key code table. */ -typedef enum { - - CC_BSV_USER_KEY = 0, /*!< Definition for a user key. */ - CC_BSV_HUK_KEY = 1, /*!< Definition for the HW unique key. */ - CC_BSV_RTL_KEY = 2, /*!< Definition for the RTL key. */ - CC_BSV_SESSION_KEY = 3, /*!< Definition for the Session key. */ - CC_BSV_CE_KEY = 4, /*!< Definition for the Kce. */ - CC_BSV_PLT_KEY = 5, /*!< Definition for the Platform key. */ - CC_BSV_KCST_KEY = 6, /*!< Definition for Kcst. */ - CC_BSV_ICV_PROV_KEY = 0xd, /*!< Definition for the Kpicv. */ - CC_BSV_ICV_CE_KEY = 0xe, /*!< Definition for the Kceicv. */ - CC_BSV_PROV_KEY = 0xf, /*!< Definition for the Kcp. */ - CC_BSV_END_OF_KEY_TYPE = INT32_MAX, /*!< Reserved. */ -}CCBsvKeyType_t; - -/*! AES directions. */ -typedef enum bsvAesDirection { - BSV_AES_DIRECTION_ENCRYPT = 0, /*!< Encrypt.*/ - BSV_AES_DIRECTION_DECRYPT = 1, /*!< Decrypt.*/ - BSV_AES_NUM_OF_ENCRYPT_MODES, /*!< The maximal number of operations. */ - BSV_AES_DIRECTION_RESERVE32B = INT32_MAX /*!< Reserved.*/ -}bsvAesDirection_t; - -/*! Definitions of the cryptographic flow supported as part of the Secure Boot. */ -typedef enum { - CC_BSV_CRYPTO_HASH_MODE = 0, /*!< Hash mode only. */ - CC_BSV_CRYPTO_AES_CTR_AND_HASH_MODE = 1, /*!< Data goes into the AES and Hash engines. */ - CC_BSV_CRYPTO_AES_CTR_TO_HASH_MODE = 2 /*!< Data goes into the AES and from the AES to the Hash engine. */ -}CCBsvflowMode_t; - -/*! CryptoImage HW completion sequence mode */ -typedef enum -{ - BSV_CRYPTO_COMPLETION_NO_WAIT = 0, /*!< The driver waits only before reading the output. */ - BSV_CRYPTO_COMPLETION_WAIT_UPON_END = 1 /*!< The driver waits after each chunk of data. */ -}bsvCryptoCompletionMode_t; - - -/*! AES-CMAC result size, in words. */ -#define CC_BSV_CMAC_RESULT_SIZE_IN_WORDS 4 /* 128b */ -/*! AES-CMAC result size, in bytes. */ -#define CC_BSV_CMAC_RESULT_SIZE_IN_BYTES 16 /* 128b */ -/*! AES-CCM 128bit key size, in bytes. */ -#define CC_BSV_CCM_KEY_SIZE_BYTES 16 -/*! AES-CCM 128bit key size, in words. */ -#define CC_BSV_CCM_KEY_SIZE_WORDS 4 -/*! AES-CCM NONCE size, in bytes. */ -#define CC_BSV_CCM_NONCE_SIZE_BYTES 12 - - -/*! AES-CMAC result buffer. */ -typedef uint32_t CCBsvCmacResult_t[CC_BSV_CMAC_RESULT_SIZE_IN_WORDS]; -/*! AES-CCM key buffer.*/ -typedef uint32_t CCBsvCcmKey_t[CC_BSV_CCM_KEY_SIZE_WORDS]; -/*! AES-CCM nonce buffer.*/ -typedef uint8_t CCBsvCcmNonce_t[CC_BSV_CCM_NONCE_SIZE_BYTES]; -/*! AES-CCM MAC buffer.*/ -typedef uint8_t CCBsvCcmMacRes_t[CC_BSV_CMAC_RESULT_SIZE_IN_BYTES]; - - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ - diff --git a/include/drivers/arm/cryptocell/713/bsv_error.h b/include/drivers/arm/cryptocell/713/bsv_error.h deleted file mode 100644 index 4d72e60aa6..0000000000 --- a/include/drivers/arm/cryptocell/713/bsv_error.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_ERROR_H -#define _BSV_ERROR_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file defines the error code types that are returned from the Boot Services APIs. - -@defgroup cc_bsv_error CryptoCell Boot Services error codes -@{ -@ingroup cc_bsv -*/ - -/*! Defines the base address for Boot Services errors. */ -#define CC_BSV_BASE_ERROR 0x0B000000 -/*! Defines the base address for Boot Services cryptographic errors. */ -#define CC_BSV_CRYPTO_ERROR 0x0C000000 - -/*! Illegal input parameter. */ -#define CC_BSV_ILLEGAL_INPUT_PARAM_ERR (CC_BSV_BASE_ERROR + 0x00000001) -/*! Illegal HUK value. */ -#define CC_BSV_ILLEGAL_HUK_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000002) -/*! Illegal Kcp value. */ -#define CC_BSV_ILLEGAL_KCP_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000003) -/*! Illegal Kce value. */ -#define CC_BSV_ILLEGAL_KCE_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000004) -/*! Illegal Kpicv value. */ -#define CC_BSV_ILLEGAL_KPICV_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000005) -/*! Illegal Kceicv value. */ -#define CC_BSV_ILLEGAL_KCEICV_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000006) -/*! Illegal EKcst value. */ -#define CC_BSV_ILLEGAL_EKCST_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000007) -/*! Hash boot key not programmed in the OTP. */ -#define CC_BSV_HASH_NOT_PROGRAMMED_ERR (CC_BSV_BASE_ERROR + 0x00000008) -/*! Illegal Hash boot key zero count in the OTP. */ -#define CC_BSV_HBK_ZERO_COUNT_ERR (CC_BSV_BASE_ERROR + 0x00000009) -/*! Illegal LCS. */ -#define CC_BSV_ILLEGAL_LCS_ERR (CC_BSV_BASE_ERROR + 0x0000000A) -/*! OTP write compare failure. */ -#define CC_BSV_OTP_WRITE_CMP_FAIL_ERR (CC_BSV_BASE_ERROR + 0x0000000B) -/*! OTP access error */ -#define CC_BSV_OTP_ACCESS_ERR (CC_BSV_BASE_ERROR + 0x0000000C) -/*! Erase key in OTP failed. */ -#define CC_BSV_ERASE_KEY_FAILED_ERR (CC_BSV_BASE_ERROR + 0x0000000D) -/*! Illegal PIDR. */ -#define CC_BSV_ILLEGAL_PIDR_ERR (CC_BSV_BASE_ERROR + 0x0000000E) -/*! Illegal CIDR. */ -#define CC_BSV_ILLEGAL_CIDR_ERR (CC_BSV_BASE_ERROR + 0x0000000F) -/*! Device failed to move to fatal error state. */ -#define CC_BSV_FAILED_TO_SET_FATAL_ERR (CC_BSV_BASE_ERROR + 0x00000010) -/*! Failed to set RMA LCS. */ -#define CC_BSV_FAILED_TO_SET_RMA_ERR (CC_BSV_BASE_ERROR + 0x00000011) -/*! Illegal RMA indication. */ -#define CC_BSV_ILLEGAL_RMA_INDICATION_ERR (CC_BSV_BASE_ERROR + 0x00000012) -/*! Boot Services version is not initialized. */ -#define CC_BSV_VER_IS_NOT_INITIALIZED_ERR (CC_BSV_BASE_ERROR + 0x00000013) -/*! APB secure mode is locked. */ -#define CC_BSV_APB_SECURE_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000014) -/*! APB privilege mode is locked. */ -#define CC_BSV_APB_PRIVILEG_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000015) -/*! Illegal operation. */ -#define CC_BSV_ILLEGAL_OPERATION_ERR (CC_BSV_BASE_ERROR + 0x00000016) -/*! Illegal asset size. */ -#define CC_BSV_ILLEGAL_ASSET_SIZE_ERR (CC_BSV_BASE_ERROR + 0x00000017) -/*! Illegal asset value. */ -#define CC_BSV_ILLEGAL_ASSET_VAL_ERR (CC_BSV_BASE_ERROR + 0x00000018) -/*! Kpicv is locked. */ -#define CC_BSV_KPICV_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000019) -/*! Illegal SW version. */ -#define CC_BSV_ILLEGAL_SW_VERSION_ERR (CC_BSV_BASE_ERROR + 0x0000001A) -/*! AO write operation. */ -#define CC_BSV_AO_WRITE_FAILED_ERR (CC_BSV_BASE_ERROR + 0x0000001B) -/*! Chip state is already initialized. */ -#define CC_BSV_CHIP_INITIALIZED_ERR (CC_BSV_BASE_ERROR + 0x0000001C) -/*! SP is not enabled. */ -#define CC_BSV_SP_NOT_ENABLED_ERR (CC_BSV_BASE_ERROR + 0x0000001D) -/*! Production secure provisioning - header fields. */ -#define CC_BSV_PROD_PKG_HEADER_ERR (CC_BSV_BASE_ERROR + 0x0000001E) -/*! Production secure provisioning - header MAC. */ -#define CC_BSV_PROD_PKG_HEADER_MAC_ERR (CC_BSV_BASE_ERROR + 0x0000001F) -/*! Overrun buffer or size. */ -#define CC_BSV_OVERRUN_ERR (CC_BSV_BASE_ERROR + 0x00000020) -/*! Kceicv is locked. */ -#define CC_BSV_KCEICV_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000021) -/*! Chip indication is CHIP_STATE_ERROR. */ -#define CC_BSV_CHIP_INDICATION_ERR (CC_BSV_BASE_ERROR + 0x00000022) -/*! Device is locked in fatal error state. */ -#define CC_BSV_FATAL_ERR_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000023) -/*! Device has security disable feature enabled. */ -#define CC_BSV_SECURE_DISABLE_ERROR (CC_BSV_BASE_ERROR + 0x00000024) -/*! Device has Kcst in disabled state */ -#define CC_BSV_KCST_DISABLE_ERROR (CC_BSV_BASE_ERROR + 0x00000025) - - -/*! Illegal data-in pointer. */ -#define CC_BSV_CRYPTO_INVALID_DATA_IN_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000001) -/*! Illegal data-out pointer. */ -#define CC_BSV_CRYPTO_INVALID_DATA_OUT_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000002) -/*! Illegal data size. */ -#define CC_BSV_CRYPTO_INVALID_DATA_SIZE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000003) -/*! Illegal key type. */ -#define CC_BSV_CRYPTO_INVALID_KEY_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000004) -/*! Illegal key size. */ -#define CC_BSV_CRYPTO_INVALID_KEY_SIZE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000005) -/*! Invalid key pointer. */ -#define CC_BSV_CRYPTO_INVALID_KEY_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000006) -/*! Illegal key DMA type. */ -#define CC_BSV_CRYPTO_INVALID_KEY_DMA_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000007) -/*! Illegal IV pointer. */ -#define CC_BSV_CRYPTO_INVALID_IV_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000008) -/*! Illegal cipher mode. */ -#define CC_BSV_CRYPTO_INVALID_CIPHER_MODE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000009) -/*! Illegal result buffer pointer. */ -#define CC_BSV_CRYPTO_INVALID_RESULT_BUFFER_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000A) -/*! Invalid DMA type. */ -#define CC_BSV_CRYPTO_INVALID_DMA_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000B) -/*! Invalid in/out buffers overlapping. */ -#define CC_BSV_CRYPTO_DATA_OUT_DATA_IN_OVERLAP_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000C) -/*! Invalid KDF label size. */ -#define CC_BSV_CRYPTO_ILLEGAL_KDF_LABEL_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000D) -/*! Invalid KDF Context size. */ -#define CC_BSV_CRYPTO_ILLEGAL_KDF_CONTEXT_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000E) -/*! Invalid CCM key. */ -#define CC_BSV_CCM_INVALID_KEY_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000f) -/*! Invalid CCM Nonce. */ -#define CC_BSV_CCM_INVALID_NONCE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000010) -/*! Invalid CCM associated data. */ -#define CC_BSV_CCM_INVALID_ASSOC_DATA_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000011) -/*! Invalid CCM text data. */ -#define CC_BSV_CCM_INVALID_TEXT_DATA_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000012) -/*! Invalid CCM-MAC buffer. */ -#define CC_BSV_CCM_INVALID_MAC_BUF_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000013) -/*! CCM-MAC comparison failed. */ -#define CC_BSV_CCM_TAG_LENGTH_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000014) -/*! CCM-MAC comparison failed. */ -#define CC_BSV_CCM_MAC_INVALID_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000015) -/*! Illegal flow mode. */ -#define CC_BSV_CRYPTO_INVALID_FLOW_MODE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000016) - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ - - - diff --git a/include/drivers/arm/cryptocell/713/cc_address_defs.h b/include/drivers/arm/cryptocell/713/cc_address_defs.h deleted file mode 100644 index 0abc15c709..0000000000 --- a/include/drivers/arm/cryptocell/713/cc_address_defs.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_ADDRESS_DEFS_H -#define _CC_ADDRESS_DEFS_H - -/*! -@file -@brief This file contains general definitions. -*/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_types.h" - -/************************ Defines ******************************/ - -/** - * Address types within CC - */ -/*! Definition of DMA address type, can be 32 bits or 64 bits according to CryptoCell's HW. */ -typedef uint64_t CCDmaAddr_t; -/*! Definition of CryptoCell address type, can be 32 bits or 64 bits according to platform. */ -typedef uint64_t CCAddr_t; -/*! Definition of CC SRAM address type, can be 32 bits according to CryptoCell's HW. */ -typedef uint32_t CCSramAddr_t; - -/* - * CCSramAddr_t is being cast into pointer type which can be 64 bit. - */ -/*! Definition of MACRO that casts SRAM addresses to pointer types. */ -#define CCSramAddr2Ptr(sramAddr) ((uintptr_t)sramAddr) - -#ifdef __cplusplus -} -#endif - -#endif - -/** - @} - */ - - diff --git a/include/drivers/arm/cryptocell/713/cc_boot_defs.h b/include/drivers/arm/cryptocell/713/cc_boot_defs.h deleted file mode 100644 index 4d29a6d006..0000000000 --- a/include/drivers/arm/cryptocell/713/cc_boot_defs.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_BOOT_DEFS_H -#define _CC_BOOT_DEFS_H - -/*! - @file - @brief This file contains general definitions of types and enums of Boot APIs. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! Version counters value. */ -typedef enum { - - CC_SW_VERSION_TRUSTED = 0, /*!< Trusted counter. */ - CC_SW_VERSION_NON_TRUSTED, /*!< Non trusted counter. */ - CC_SW_VERSION_MAX = 0x7FFFFFFF /*!< Reserved */ -} CCSbSwVersionId_t; - -/*! The hash boot key definition. */ -typedef enum { - CC_SB_HASH_BOOT_KEY_0_128B = 0, /*!< Hbk0: 128-bit truncated SHA-256 digest of PubKB0. Used by ICV */ - CC_SB_HASH_BOOT_KEY_1_128B = 1, /*!< Hbk1: 128-bit truncated SHA-256 digest of PubKB1. Used by OEM */ - CC_SB_HASH_BOOT_KEY_256B = 2, /*!< Hbk: 256-bit SHA-256 digest of public key. */ - CC_SB_HASH_BOOT_NOT_USED = 0xF, /*!< Hbk is not used. */ - CC_SB_HASH_MAX_NUM = 0x7FFFFFFF, /*!< Reserved. */ -} CCSbPubKeyIndexType_t; - -/*! Chip state. */ -typedef enum { - CHIP_STATE_NOT_INITIALIZED = 0, /*! Chip is not initialized. */ - CHIP_STATE_TEST = 1, /*! Chip is in Production state. */ - CHIP_STATE_PRODUCTION = 2, /*! Chip is in Production state. */ - CHIP_STATE_ERROR = 3, /*! Chip is in Error state. */ -} CCBsvChipState_t; -#ifdef __cplusplus -} -#endif - -#endif /*_CC_BOOT_DEFS_H */ - -/** -@} - */ diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types.h b/include/drivers/arm/cryptocell/713/cc_pal_types.h deleted file mode 100644 index 4ab3960d37..0000000000 --- a/include/drivers/arm/cryptocell/713/cc_pal_types.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CC_PAL_TYPES_H -#define CC_PAL_TYPES_H - -/*! -@file -@brief This file contains platform-dependent definitions and types of the PAL layer. - -@defgroup cc_pal_types CryptoCell platform-dependent PAL layer definitions and types -@{ -@ingroup cc_pal - - @{ - @ingroup cc_pal - @} -*/ - -#include "cc_pal_types_plat.h" - -/*! Definition of Boolean type.*/ -typedef enum { - /*! Boolean false.*/ - CC_FALSE = 0, - /*! Boolean true.*/ - CC_TRUE = 1 -} CCBool_t; - -/*! Success. */ -#define CC_SUCCESS 0UL -/*! Failure. */ -#define CC_FAIL 1UL - -/*! Success (OK). */ -#define CC_OK 0 - -/*! This macro handles unused parameters in the code, to avoid compilation warnings. */ -#define CC_UNUSED_PARAM(prm) ((void)prm) - -/*! The maximal uint32 value.*/ -#define CC_MAX_UINT32_VAL (0xFFFFFFFF) - - -/* Minimal and Maximal macros */ -#ifdef min -/*! Definition for minimal calculation. */ -#define CC_MIN(a,b) min( a , b ) -#else -/*! Definition for minimal calculation. */ -#define CC_MIN( a , b ) ( ( (a) < (b) ) ? (a) : (b) ) -#endif - -#ifdef max -/*! Definition for maximal calculation. */ -#define CC_MAX(a,b) max( a , b ) -#else -/*! Definition for maximal calculation.. */ -#define CC_MAX( a , b ) ( ( (a) > (b) ) ? (a) : (b) ) -#endif - -/*! This macro calculates the number of full Bytes from bits, where seven bits are one Byte. */ -#define CALC_FULL_BYTES(numBits) ((numBits)/CC_BITS_IN_BYTE + (((numBits) & (CC_BITS_IN_BYTE-1)) > 0)) -/*! This macro calculates the number of full 32-bit words from bits where 31 bits are one word. */ -#define CALC_FULL_32BIT_WORDS(numBits) ((numBits)/CC_BITS_IN_32BIT_WORD + (((numBits) & (CC_BITS_IN_32BIT_WORD-1)) > 0)) -/*! This macro calculates the number of full 32-bit words from Bytes where three Bytes are one word. */ -#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) ((sizeBytes)/CC_32BIT_WORD_SIZE + (((sizeBytes) & (CC_32BIT_WORD_SIZE-1)) > 0)) -/*! This macro calculates the number of full 32-bit words from 64-bits dwords. */ -#define CALC_32BIT_WORDS_FROM_64BIT_DWORD(sizeWords) (sizeWords * CC_32BIT_WORD_IN_64BIT_DWORD) -/*! This macro rounds up bits to 32-bit words. */ -#define ROUNDUP_BITS_TO_32BIT_WORD(numBits) (CALC_FULL_32BIT_WORDS(numBits) * CC_BITS_IN_32BIT_WORD) -/*! This macro rounds up bits to Bytes. */ -#define ROUNDUP_BITS_TO_BYTES(numBits) (CALC_FULL_BYTES(numBits) * CC_BITS_IN_BYTE) -/*! This macro rounds up bytes to 32-bit words. */ -#define ROUNDUP_BYTES_TO_32BIT_WORD(sizeBytes) (CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) * CC_32BIT_WORD_SIZE) -/*! This macro calculates the number Bytes from words. */ -#define CALC_WORDS_TO_BYTES(numwords) ((numwords)*CC_32BIT_WORD_SIZE) -/*! Definition of 1 KB in Bytes. */ -#define CC_1K_SIZE_IN_BYTES 1024 -/*! Definition of number of bits in a Byte. */ -#define CC_BITS_IN_BYTE 8 -/*! Definition of number of bits in a 32-bits word. */ -#define CC_BITS_IN_32BIT_WORD 32 -/*! Definition of number of Bytes in a 32-bits word. */ -#define CC_32BIT_WORD_SIZE 4 -/*! Definition of number of 32-bits words in a 64-bits dword. */ -#define CC_32BIT_WORD_IN_64BIT_DWORD 2 - - -#endif - -/** -@} - */ - - - diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h deleted file mode 100644 index 984847217b..0000000000 --- a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*! @file -@brief This file contains basic type definitions that are platform-dependent. -*/ -#ifndef _CC_PAL_TYPES_PLAT_H -#define _CC_PAL_TYPES_PLAT_H -/* Host specific types for standard (ISO-C99) compilant platforms */ - -#include <stddef.h> -#include <stdint.h> - -typedef uint32_t CCStatus; - -#define CCError_t CCStatus -#define CC_INFINITE 0xFFFFFFFF - -#define CEXPORT_C -#define CIMPORT_C - -#endif /*_CC_PAL_TYPES_PLAT_H*/ diff --git a/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h b/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h deleted file mode 100644 index 1a1bce0ab5..0000000000 --- a/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_PKA_HW_PLAT_DEFS_H -#define _CC_PKA_HW_PLAT_DEFS_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - -#include "cc_pal_types.h" -/*! -@file -@brief Contains the enums and definitions that are used in the PKA code (definitions that are platform dependent). -*/ - -/*! The size of the PKA engine word. */ -#define CC_PKA_WORD_SIZE_IN_BITS 128 - -/*! The maximal supported size of modulus in RSA in bits. */ -#define CC_RSA_MAX_VALID_KEY_SIZE_VALUE_IN_BITS 4096 -/*! The maximal supported size of key-generation in RSA in bits. */ -#define CC_RSA_MAX_KEY_GENERATION_HW_SIZE_BITS 4096 - -/*! Secure boot/debug certificate RSA public modulus key size in bits. */ -#if (KEY_SIZE == 3072) - #define BSV_CERT_RSA_KEY_SIZE_IN_BITS 3072 -#else - #define BSV_CERT_RSA_KEY_SIZE_IN_BITS 2048 -#endif -/*! Secure boot/debug certificate RSA public modulus key size in bytes. */ -#define BSV_CERT_RSA_KEY_SIZE_IN_BYTES (BSV_CERT_RSA_KEY_SIZE_IN_BITS/CC_BITS_IN_BYTE) -/*! Secure boot/debug certificate RSA public modulus key size in words. */ -#define BSV_CERT_RSA_KEY_SIZE_IN_WORDS (BSV_CERT_RSA_KEY_SIZE_IN_BITS/CC_BITS_IN_32BIT_WORD) - -/*! The maximal count of extra bits in PKA operations. */ -#define PKA_EXTRA_BITS 8 -/*! The number of memory registers in PKA operations. */ -#define PKA_MAX_COUNT_OF_PHYS_MEM_REGS 32 - -/*! Size of buffer for Barrett modulus tag in words. */ -#define RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_WORDS 5 -/*! Size of buffer for Barrett modulus tag in bytes. */ -#define RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES (RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_WORDS*CC_32BIT_WORD_SIZE) - - - -#ifdef __cplusplus -} -#endif - -#endif //_CC_PKA_HW_PLAT_DEFS_H - -/** - @} - */ - diff --git a/include/drivers/arm/cryptocell/713/cc_sec_defs.h b/include/drivers/arm/cryptocell/713/cc_sec_defs.h deleted file mode 100644 index 8fb698ff59..0000000000 --- a/include/drivers/arm/cryptocell/713/cc_sec_defs.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_SEC_DEFS_H -#define _CC_SEC_DEFS_H - -/*! -@file -@brief This file contains general definitions and types. -*/ - - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_types.h" - -/*! Hashblock size in words. */ -#define HASH_BLOCK_SIZE_IN_WORDS 16 -/*! Hash - SHA2 results in words. */ -#define HASH_RESULT_SIZE_IN_WORDS 8 -/*! Hash - SHA2 results in bytes. */ -#define HASH_RESULT_SIZE_IN_BYTES 32 - -/*! Definition for hash result array. */ -typedef uint32_t CCHashResult_t[HASH_RESULT_SIZE_IN_WORDS]; - -/*! Definition for converting pointer to Host address. */ -#define CONVERT_TO_ADDR(ptr) (unsigned long)ptr - -/*! Definition for converting pointer to SRAM address. */ -#define CONVERT_TO_SRAM_ADDR(ptr) (0xFFFFFFFF & ptr) - -/*! The data size of the signed SW image, in bytes. */ -/*!\internal ContentCertImageRecord_t includes: HS(8W) + 64-b dstAddr(2W) + imgSize(1W) + isCodeEncUsed(1W) */ -#define SW_REC_SIGNED_DATA_SIZE_IN_BYTES 48 - -/*! The data size of the unsigned SW image, in bytes. */ -/*!\internal CCSbSwImgAddData_t includes: 64-b srcAddr(2W)*/ -#define SW_REC_NONE_SIGNED_DATA_SIZE_IN_BYTES 8 - -/*! The additional data size - storage address and length of the unsigned SW image, in words. */ -#define SW_REC_NONE_SIGNED_DATA_SIZE_IN_WORDS SW_REC_NONE_SIGNED_DATA_SIZE_IN_BYTES/CC_32BIT_WORD_SIZE - -/*! The additional data section size, in bytes. */ -#define CC_SB_MAX_SIZE_ADDITIONAL_DATA_BYTES 128 - -/*! Indication of whether or not to load the SW image to memory. */ -#define CC_SW_COMP_NO_MEM_LOAD_INDICATION 0xFFFFFFFFFFFFFFFFUL - -/*! Indication of product version, stored in certificate version field. */ -#define CC_SB_CERT_VERSION_PROJ_PRD 0x713 - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ - - - diff --git a/include/drivers/arm/cryptocell/cc_rotpk.h b/include/drivers/arm/cryptocell/cc_rotpk.h deleted file mode 100644 index 93984960e2..0000000000 --- a/include/drivers/arm/cryptocell/cc_rotpk.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_ROTPK_H -#define _CC_ROTPK_H - -int cc_get_rotpk_hash(unsigned char *dst, unsigned int len, - unsigned int *flags); - -#endif diff --git a/include/drivers/arm/css/scmi.h b/include/drivers/arm/css/scmi.h index adce7a62ca..96e1924698 100644 --- a/include/drivers/arm/css/scmi.h +++ b/include/drivers/arm/css/scmi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,10 +25,16 @@ #define MAKE_SCMI_VERSION(maj, min) \ ((((maj) & 0xffff) << 16) | ((min) & 0xffff)) -/* Macro to check if the driver is compatible with the SCMI version reported */ +/* + * Check that the driver's version is same or higher than the reported SCMI + * version. We accept lower major version numbers, as all affected protocols + * so far stay backwards compatible. This might need to be revisited in the + * future. + */ #define is_scmi_version_compatible(drv, scmi) \ + ((GET_SCMI_MAJOR_VER(drv) > GET_SCMI_MAJOR_VER(scmi)) || \ ((GET_SCMI_MAJOR_VER(drv) == GET_SCMI_MAJOR_VER(scmi)) && \ - (GET_SCMI_MINOR_VER(drv) <= GET_SCMI_MINOR_VER(scmi))) + (GET_SCMI_MINOR_VER(drv) <= GET_SCMI_MINOR_VER(scmi)))) /* SCMI Protocol identifiers */ #define SCMI_PWR_DMN_PROTO_ID 0x11 @@ -117,6 +123,8 @@ typedef struct scmi_channel_plat_info { void (*ring_doorbell)(struct scmi_channel_plat_info *plat_info); /* cookie is unused now. But added for future enhancements. */ void *cookie; + /* Delay in micro-seconds while polling the channel status. */ + uint32_t delay; } scmi_channel_plat_info_t; @@ -162,7 +170,7 @@ int scmi_ap_core_set_reset_addr(void *p, uint64_t reset_addr, uint32_t attr); int scmi_ap_core_get_reset_addr(void *p, uint64_t *reset_addr, uint32_t *attr); /* API to get the platform specific SCMI channel information. */ -scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id); +scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id); /* API to override default PSCI callbacks for platforms that support SCMI. */ const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops); diff --git a/include/drivers/arm/css/sds.h b/include/drivers/arm/css/sds.h index db4cbaaf56..ab95775127 100644 --- a/include/drivers/arm/css/sds.h +++ b/include/drivers/arm/css/sds.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,12 +79,33 @@ typedef enum { SDS_ACCESS_MODE_CACHED, } sds_access_mode_t; -int sds_init(void); -int sds_struct_exists(unsigned int structure_id); -int sds_struct_read(uint32_t structure_id, unsigned int fld_off, void *data, - size_t size, sds_access_mode_t mode); -int sds_struct_write(uint32_t structure_id, unsigned int fld_off, void *data, - size_t size, sds_access_mode_t mode); +/* + * The following structure describes a SDS memory region. Its items are used + * to track and maintain the state of the memory region reserved for usage + * by the SDS framework. + * + * The base address of the SDS memory region is platform specific. The + * SDS description structure must already contain the address when it is + * returned by the plat_sds_get_regions() platform API during SDS region + * initialization. + * The size of the SDS memory region is dynamically discovered during the + * initialization of the region and written into the 'size' item of the + * SDS description structure. + */ +typedef struct { + uintptr_t base; /* Pointer to the base of the SDS memory region */ + size_t size; /* Size of the SDS memory region in bytes */ +} sds_region_desc_t; + +/* API to get the platform specific SDS region description(s) */ +sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count); + +int sds_init(unsigned int region_id); +int sds_struct_exists(unsigned int region_id, unsigned int structure_id); +int sds_struct_read(unsigned int region_id, uint32_t structure_id, + unsigned int fld_off, void *data, size_t size, sds_access_mode_t mode); +int sds_struct_write(unsigned int region_id, uint32_t structure_id, + unsigned int fld_off, void *data, size_t size, sds_access_mode_t mode); #endif /*__ASSEMBLER__ */ #endif /* SDS_H */ diff --git a/include/drivers/arm/dcc.h b/include/drivers/arm/dcc.h index 1f1fd03e0f..072bed52f1 100644 --- a/include/drivers/arm/dcc.h +++ b/include/drivers/arm/dcc.h @@ -15,5 +15,6 @@ * framework. */ int console_dcc_register(void); +void console_dcc_unregister(void); #endif /* DCC */ diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h index 6de2abb85f..51ce65d48b 100644 --- a/include/drivers/arm/ethosn.h +++ b/include/drivers/arm/ethosn.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,16 @@ #define ETHOSN_FNUM_IS_SEC U(0x51) #define ETHOSN_FNUM_HARD_RESET U(0x52) #define ETHOSN_FNUM_SOFT_RESET U(0x53) -/* 0x54-0x5F reserved for future use */ +#define ETHOSN_FNUM_IS_SLEEPING U(0x54) +#define ETHOSN_FNUM_GET_FW_PROP U(0x55) +#define ETHOSN_FNUM_BOOT_FW U(0x56) +/* 0x57-0x5F reserved for future use */ + +/* Properties for ETHOSN_FNUM_TZMP_GET_FW_PROP */ +#define ETHOSN_FW_PROP_VERSION U(0xF00) +#define ETHOSN_FW_PROP_MEM_INFO U(0xF01) +#define ETHOSN_FW_PROP_OFFSETS U(0xF02) +#define ETHOSN_FW_PROP_VA_MAP U(0xF03) /* SMC64 function IDs */ #define ETHOSN_FID_64(func_num) U(0xC2000000 | func_num) @@ -38,21 +47,33 @@ #define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE) /* Service version */ -#define ETHOSN_VERSION_MAJOR U(0) -#define ETHOSN_VERSION_MINOR U(1) +#define ETHOSN_VERSION_MAJOR U(4) +#define ETHOSN_VERSION_MINOR U(0) /* Return codes for function calls */ #define ETHOSN_SUCCESS 0 #define ETHOSN_NOT_SUPPORTED -1 /* -2 Reserved for NOT_REQUIRED */ -/* -3 Reserved for INVALID_PARAMETER */ +#define ETHOSN_INVALID_PARAMETER -3 #define ETHOSN_FAILURE -4 -#define ETHOSN_CORE_IDX_OUT_OF_RANGE -5 +#define ETHOSN_UNKNOWN_CORE_ADDRESS -5 +#define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6 +#define ETHOSN_INVALID_CONFIGURATION -7 +#define ETHOSN_INVALID_STATE -8 + +/* + * Argument types for soft and hard resets to indicate whether to reset + * and reconfigure the NPU or only halt it + */ +#define ETHOSN_RESET_TYPE_FULL U(0) +#define ETHOSN_RESET_TYPE_HALT U(1) + +int ethosn_smc_setup(void); uintptr_t ethosn_smc_handler(uint32_t smc_fid, - u_register_t core_idx, - u_register_t x2, - u_register_t x3, + u_register_t core_addr, + u_register_t asset_alloc_idx, + u_register_t reset_type, u_register_t x4, void *cookie, void *handle, diff --git a/include/drivers/arm/ethosn_cert.h b/include/drivers/arm/ethosn_cert.h new file mode 100644 index 0000000000..7aa887d7f2 --- /dev/null +++ b/include/drivers/arm/ethosn_cert.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ETHOSN_CERT_H +#define ETHOSN_CERT_H + +#include "ethosn_oid.h" +#include <tbbr/tbb_ext.h> +#include <tbbr/tbb_key.h> + +/* Arm(R) Ethos(TM)-N NPU Certificates */ +#define ETHOSN_NPU_FW_KEY_CERT_DEF { \ + .id = ETHOSN_NPU_FW_KEY_CERT, \ + .opt = "npu-fw-key-cert", \ + .help_msg = "Arm(R) Ethos(TM)-N NPU Firmware Key Certificate (output file)", \ + .fn = NULL, \ + .cn = "NPU Firmware Key Certificate", \ + .key = NON_TRUSTED_WORLD_KEY, \ + .issuer = ETHOSN_NPU_FW_KEY_CERT, \ + .ext = { \ + NON_TRUSTED_FW_NVCOUNTER_EXT, \ + ETHOSN_NPU_FW_CONTENT_CERT_PK_EXT, \ + }, \ + .num_ext = 2 \ +} + +#define ETHOSN_NPU_FW_CONTENT_CERT_DEF { \ + .id = ETHOSN_NPU_FW_CONTENT_CERT, \ + .opt = "npu-fw-cert", \ + .help_msg = "Arm(R) Ethos(TM)-N NPU Firmware Content Certificate (output file)",\ + .fn = NULL, \ + .cn = "NPU Firmware Content Certificate", \ + .key = ETHOSN_NPU_FW_CONTENT_CERT_KEY, \ + .issuer = ETHOSN_NPU_FW_CONTENT_CERT, \ + .ext = { \ + NON_TRUSTED_FW_NVCOUNTER_EXT, \ + ETHOSN_NPU_FW_HASH_EXT, \ + }, \ + .num_ext = 2 \ +} + +/* NPU Extensions */ +#define ETHOSN_NPU_FW_CONTENT_CERT_PK_EXT_DEF { \ + .oid = ETHOSN_NPU_FW_CONTENT_CERT_PK_OID, \ + .help_msg = "Arm(R) Ethos(TM)-N NPU Firmware content certificate public key", \ + .sn = "NPUFirmwareContentCertPK", \ + .ln = "NPU Firmware content cerificate public key", \ + .asn1_type = V_ASN1_OCTET_STRING, \ + .type = EXT_TYPE_PKEY, \ + .attr.key = ETHOSN_NPU_FW_CONTENT_CERT_KEY \ +} + +#define ETHOSN_NPU_FW_HASH_EXT_DEF { \ + .oid = ETHOSN_NPU_FW_BINARY_OID, \ + .opt = "npu-fw", \ + .help_msg = "Arm(R) Ethos(TM)-N NPU Firmware image file (input file)", \ + .sn = "NPUFirmwareHash", \ + .ln = "NPU Firmware Hash (SHA256)", \ + .asn1_type = V_ASN1_OCTET_STRING, \ + .type = EXT_TYPE_HASH \ +} + +/* NPU Keys */ +#define ETHOSN_NPU_FW_CONTENT_CERT_KEY_DEF { \ + .id = ETHOSN_NPU_FW_CONTENT_CERT_KEY, \ + .opt = "npu-fw-key", \ + .help_msg = "Arm(R) Ethos(TM)-N NPU Firmware Content Certificate key (input/output file)",\ + .desc = "NPU Firmware Content Certificate key" \ +} + +#endif /* ETHOSN_CERT_H */ diff --git a/include/drivers/arm/ethosn_fip.h b/include/drivers/arm/ethosn_fip.h new file mode 100644 index 0000000000..f2c7f932c2 --- /dev/null +++ b/include/drivers/arm/ethosn_fip.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ETHOSN_FIP_H +#define ETHOSN_FIP_H + +#define UUID_ETHOSN_FW_KEY_CERTIFICATE \ + { { 0x56, 0x66, 0xd0, 0x04 }, { 0xab, 0x98 }, { 0x40, 0xaa }, \ + 0x89, 0x88, { 0xb7, 0x2a, 0x3, 0xa2, 0x56, 0xe2 } } + +#define UUID_ETHOSN_FW_CONTENT_CERTIFICATE \ + { { 0xa5, 0xc4, 0x18, 0xda }, { 0x43, 0x0f }, { 0x48, 0xb1 }, \ + 0x88, 0xcd, { 0x93, 0xf6, 0x78, 0x89, 0xd9, 0xed } } + +#define UUID_ETHOSN_FW \ + { { 0xcf, 0xd4, 0x99, 0xb5 }, { 0xa3, 0xbc }, { 0x4a, 0x7e }, \ + 0x98, 0xcb, { 0x48, 0xa4, 0x1c, 0xb8, 0xda, 0xe1 } } + +#define ETHOSN_FW_KEY_CERTIFICATE_DEF \ + { "Arm(R) Ethos(TM)-N NPU Firmware Key Certificate", \ + UUID_ETHOSN_FW_KEY_CERTIFICATE, \ + "npu-fw-key-cert" } + +#define ETHOSN_FW_CONTENT_CERTIFICATE_DEF \ + { "Arm(R) Ethos(TM)-N NPU Firmware Content Certificate",\ + UUID_ETHOSN_FW_CONTENT_CERTIFICATE, \ + "npu-fw-cert" } + +#define ETHOSN_FW_DEF \ + { "Arm(R) Ethos(TM)-N NPU Firmware", \ + UUID_ETHOSN_FW, \ + "npu-fw" } + +#endif /* ETHOSN_FIP_H */ diff --git a/include/drivers/arm/ethosn_oid.h b/include/drivers/arm/ethosn_oid.h new file mode 100644 index 0000000000..a83cd09cb4 --- /dev/null +++ b/include/drivers/arm/ethosn_oid.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ETHOSN_OID_H +#define ETHOSN_OID_H + +/* Arm(R) Ethos(TM)-N NPU Platform OID */ +#define ETHOSN_NPU_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2300.1" +#define ETHOSN_NPU_FW_BINARY_OID "1.3.6.1.4.1.4128.2300.2" + +#endif /* ETHOSN_OID_H */ diff --git a/include/drivers/arm/gic600_multichip.h b/include/drivers/arm/gic600_multichip.h index bda406bba3..978d7357c3 100644 --- a/include/drivers/arm/gic600_multichip.h +++ b/include/drivers/arm/gic600_multichip.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,8 +16,11 @@ */ #define GIC600_MAX_MULTICHIP 16 -/* SPI IDs array consist of min and max ids */ -#define GIC600_SPI_IDS_SIZE 2 +typedef struct multichip_spi_ids_desc { + uintptr_t gicd_base; + uint32_t spi_id_min; + uint32_t spi_id_max; +} multichip_spi_ids_desc_t; /******************************************************************************* * GIC-600 multichip data structure describes platform specific attributes @@ -37,19 +41,23 @@ * The 'chip_addrs' field contains array of chip addresses. These addresses are * implementation specific values. * - * The 'spi_ids' field contains array of minimum and maximum SPI interrupt ids - * that each chip owns. Note that SPI interrupt ids can range from 32 to 960 and - * it should be group of 32 (i.e., SPI minimum and (SPI maximum + 1) should be - * a multiple of 32). If a chip doesn't own any SPI interrupts a value of {0, 0} - * should be passed. + * The 'multichip_spi_ids_desc_t' field contains array of descriptors used to + * provide minimum and maximum SPI interrupt ids that each chip owns and the + * corresponding chip base address. Note that SPI interrupt ids can range from + * 32 to 960 and it should be group of 32 (i.e., SPI minimum and (SPI maximum + + * 1) should be a multiple of 32). If a chip doesn't own any SPI interrupts a + * value of {0, 0, 0} should be passed. ******************************************************************************/ struct gic600_multichip_data { uintptr_t rt_owner_base; unsigned int rt_owner; unsigned int chip_count; uint64_t chip_addrs[GIC600_MAX_MULTICHIP]; - unsigned int spi_ids[GIC600_MAX_MULTICHIP][GIC600_SPI_IDS_SIZE]; + multichip_spi_ids_desc_t spi_ids[GIC600_MAX_MULTICHIP]; }; +uintptr_t gic600_multichip_gicd_base_for_spi(uint32_t spi_id); void gic600_multichip_init(struct gic600_multichip_data *multichip_data); +bool gic600_multichip_is_initialized(void); + #endif /* GIC600_MULTICHIP_H */ diff --git a/include/drivers/arm/gic600ae_fmu.h b/include/drivers/arm/gic600ae_fmu.h new file mode 100644 index 0000000000..d2a92ddfda --- /dev/null +++ b/include/drivers/arm/gic600ae_fmu.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GIC600AE_FMU_H +#define GIC600AE_FMU_H + +/******************************************************************************* + * GIC600-AE FMU register offsets and constants + ******************************************************************************/ +#define GICFMU_ERRFR_LO U(0x000) +#define GICFMU_ERRFR_HI U(0x004) +#define GICFMU_ERRCTLR_LO U(0x008) +#define GICFMU_ERRCTLR_HI U(0x00C) +#define GICFMU_ERRSTATUS_LO U(0x010) +#define GICFMU_ERRSTATUS_HI U(0x014) +#define GICFMU_ERRGSR_LO U(0xE00) +#define GICFMU_ERRGSR_HI U(0xE04) +#define GICFMU_KEY U(0xEA0) +#define GICFMU_PINGCTLR U(0xEA4) +#define GICFMU_PINGNOW U(0xEA8) +#define GICFMU_SMEN U(0xEB0) +#define GICFMU_SMINJERR U(0xEB4) +#define GICFMU_PINGMASK_LO U(0xEC0) +#define GICFMU_PINGMASK_HI U(0xEC4) +#define GICFMU_STATUS U(0xF00) +#define GICFMU_ERRIDR U(0xFC8) + +/* ERRCTLR bits */ +#define FMU_ERRCTLR_ED_BIT BIT(0) +#define FMU_ERRCTLR_CE_EN_BIT BIT(1) +#define FMU_ERRCTLR_UI_BIT BIT(2) +#define FMU_ERRCTLR_CI_BIT BIT(3) + +/* SMEN constants */ +#define FMU_SMEN_BLK_SHIFT U(8) +#define FMU_SMEN_SMID_SHIFT U(24) +#define FMU_SMEN_EN_BIT BIT(0) + +/* Error record IDs */ +#define FMU_BLK_GICD U(0) +#define FMU_BLK_SPICOL U(1) +#define FMU_BLK_WAKERQ U(2) +#define FMU_BLK_ITS0 U(4) +#define FMU_BLK_ITS1 U(5) +#define FMU_BLK_ITS2 U(6) +#define FMU_BLK_ITS3 U(7) +#define FMU_BLK_ITS4 U(8) +#define FMU_BLK_ITS5 U(9) +#define FMU_BLK_ITS6 U(10) +#define FMU_BLK_ITS7 U(11) +#define FMU_BLK_PPI0 U(12) +#define FMU_BLK_PPI1 U(13) +#define FMU_BLK_PPI2 U(14) +#define FMU_BLK_PPI3 U(15) +#define FMU_BLK_PPI4 U(16) +#define FMU_BLK_PPI5 U(17) +#define FMU_BLK_PPI6 U(18) +#define FMU_BLK_PPI7 U(19) +#define FMU_BLK_PPI8 U(20) +#define FMU_BLK_PPI9 U(21) +#define FMU_BLK_PPI10 U(22) +#define FMU_BLK_PPI11 U(23) +#define FMU_BLK_PPI12 U(24) +#define FMU_BLK_PPI13 U(25) +#define FMU_BLK_PPI14 U(26) +#define FMU_BLK_PPI15 U(27) +#define FMU_BLK_PPI16 U(28) +#define FMU_BLK_PPI17 U(29) +#define FMU_BLK_PPI18 U(30) +#define FMU_BLK_PPI19 U(31) +#define FMU_BLK_PPI20 U(32) +#define FMU_BLK_PPI21 U(33) +#define FMU_BLK_PPI22 U(34) +#define FMU_BLK_PPI23 U(35) +#define FMU_BLK_PPI24 U(36) +#define FMU_BLK_PPI25 U(37) +#define FMU_BLK_PPI26 U(38) +#define FMU_BLK_PPI27 U(39) +#define FMU_BLK_PPI28 U(40) +#define FMU_BLK_PPI29 U(41) +#define FMU_BLK_PPI30 U(42) +#define FMU_BLK_PPI31 U(43) +#define FMU_BLK_PRESENT_MASK U(0xFFFFFFFFFFF) + +/* Safety Mechanism limit */ +#define FMU_SMID_GICD_MAX U(33) +#define FMU_SMID_PPI_MAX U(12) +#define FMU_SMID_ITS_MAX U(14) +#define FMU_SMID_SPICOL_MAX U(5) +#define FMU_SMID_WAKERQ_MAX U(2) + +/* MBIST Safety Mechanism ID */ +#define GICD_MBIST_REQ_ERROR U(23) +#define GICD_FMU_CLKGATE_ERROR U(33) +#define PPI_MBIST_REQ_ERROR U(10) +#define PPI_FMU_CLKGATE_ERROR U(12) +#define ITS_MBIST_REQ_ERROR U(13) +#define ITS_FMU_CLKGATE_ERROR U(14) + +/* ERRSTATUS bits */ +#define FMU_ERRSTATUS_BLKID_SHIFT U(32) +#define FMU_ERRSTATUS_BLKID_MASK U(0xFF) +#define FMU_ERRSTATUS_V_BIT BIT(30) +#define FMU_ERRSTATUS_UE_BIT BIT(29) +#define FMU_ERRSTATUS_OV_BIT BIT(27) +#define FMU_ERRSTATUS_CE_BITS (BIT(25) | BIT(24)) +#define FMU_ERRSTATUS_CLEAR (FMU_ERRSTATUS_V_BIT | FMU_ERRSTATUS_UE_BIT | \ + FMU_ERRSTATUS_OV_BIT | FMU_ERRSTATUS_CE_BITS) +#define FMU_ERRSTATUS_IERR_MASK U(0xFF) +#define FMU_ERRSTATUS_IERR_SHIFT U(8) +#define FMU_ERRSTATUS_SERR_MASK U(0xFF) + +/* PINGCTLR constants */ +#define FMU_PINGCTLR_INTDIFF_SHIFT U(16) +#define FMU_PINGCTLR_TIMEOUTVAL_SHIFT U(4) +#define FMU_PINGCTLR_EN_BIT BIT(0) + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +#include <arch_helpers.h> + +/******************************************************************************* + * GIC600 FMU EL3 driver API + ******************************************************************************/ +uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n); +uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n); +uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n); +uint64_t gic_fmu_read_errgsr(uintptr_t base); +uint32_t gic_fmu_read_pingctlr(uintptr_t base); +uint32_t gic_fmu_read_pingnow(uintptr_t base); +uint64_t gic_fmu_read_pingmask(uintptr_t base); +uint32_t gic_fmu_read_status(uintptr_t base); +uint32_t gic_fmu_read_erridr(uintptr_t base); +void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val); +void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val); +void gic_fmu_write_pingctlr(uintptr_t base, uint32_t val); +void gic_fmu_write_pingnow(uintptr_t base, uint32_t val); +void gic_fmu_write_smen(uintptr_t base, uint32_t val); +void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val); +void gic_fmu_write_pingmask(uintptr_t base, uint64_t val); +void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid); + +void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask, bool errctlr_ce_en, bool errctlr_ue_en); +void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask, + unsigned int timeout_val, unsigned int interval_diff); +void gic600_fmu_print_sm_info(uint64_t base, unsigned int blk, unsigned int smid); +int gic600_fmu_probe(uint64_t base, int *probe_data); +int gic600_fmu_ras_handler(uint64_t base, int probe_data); + +#endif /* __ASSEMBLER__ */ + +#endif /* GIC600AE_FMU_H */ diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h index ebcb216d6b..bebd9cefff 100644 --- a/include/drivers/arm/gicv2.h +++ b/include/drivers/arm/gicv2.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. + * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +9,7 @@ #define GICV2_H #include <drivers/arm/gic_common.h> +#include <platform_def.h> /******************************************************************************* * GICv2 miscellaneous definitions @@ -30,7 +32,14 @@ #define GICD_SGIR U(0xF00) #define GICD_CPENDSGIR U(0xF10) #define GICD_SPENDSGIR U(0xF20) + +/* + * Some GICv2 implementations violate the specification and have this register + * at a different address. Allow overriding it in platform_def.h as workaround. + */ +#ifndef GICD_PIDR2_GICV2 #define GICD_PIDR2_GICV2 U(0xFE8) +#endif #define ITARGETSR_SHIFT 2 #define GIC_TARGET_CPU_MASK U(0xff) @@ -42,13 +51,15 @@ #define SGIR_TGTLSTFLT_MASK U(0x3) #define SGIR_TGTLST_SHIFT 16 #define SGIR_TGTLST_MASK U(0xff) +#define SGIR_NSATT (U(0x1) << 16) #define SGIR_INTID_MASK ULL(0xf) #define SGIR_TGT_SPECIFIC U(0) -#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \ +#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, nsatt, intid) \ ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \ (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \ + ((nsatt) ? SGIR_NSATT : U(0)) | \ ((intid) & SGIR_INTID_MASK)) /******************************************************************************* @@ -119,6 +130,7 @@ #ifndef __ASSEMBLER__ #include <cdefs.h> +#include <stdbool.h> #include <stdint.h> #include <common/interrupt_props.h> @@ -176,8 +188,8 @@ unsigned int gicv2_get_interrupt_active(unsigned int id); void gicv2_enable_interrupt(unsigned int id); void gicv2_disable_interrupt(unsigned int id); void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); -void gicv2_set_interrupt_type(unsigned int id, unsigned int type); -void gicv2_raise_sgi(int sgi_num, int proc_num); +void gicv2_set_interrupt_group(unsigned int id, unsigned int group); +void gicv2_raise_sgi(int sgi_num, bool ns, int proc_num); void gicv2_set_spi_routing(unsigned int id, int proc_num); void gicv2_set_interrupt_pending(unsigned int id); void gicv2_clear_interrupt_pending(unsigned int id); diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index d8ac4cb334..bfda31bbfd 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -76,6 +76,8 @@ #endif /* GIC_EXT_INTID */ +#define GIC_REV(r, p) ((r << 4) | p) + /******************************************************************************* * GICv3 and 3.1 specific Distributor interface register offsets and constants ******************************************************************************/ @@ -104,6 +106,8 @@ #define GICD_IROUTER U(0x6000) #define GICD_IROUTERE U(0x8000) +#define GICD_PIDR0_GICV3 U(0xffe0) +#define GICD_PIDR1_GICV3 U(0xffe4) #define GICD_PIDR2_GICV3 U(0xffe8) #define IGRPMODR_SHIFT 5 @@ -153,11 +157,8 @@ /******************************************************************************* * Common GIC Redistributor interface registers & constants ******************************************************************************/ -#if GIC_ENABLE_V4_EXTN -#define GICR_PCPUBASE_SHIFT 0x12 -#else -#define GICR_PCPUBASE_SHIFT 0x11 -#endif +#define GICR_V4_PCPUBASE_SHIFT 0x12 +#define GICR_V3_PCPUBASE_SHIFT 0x11 #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */ #define GICR_CTLR U(0x0) #define GICR_IIDR U(0x04) @@ -193,6 +194,15 @@ #define GICR_CTLR_UWP_SHIFT 31 #define GICR_CTLR_UWP_MASK U(0x1) #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT) +#define GICR_CTLR_DPG1S_SHIFT 26 +#define GICR_CTLR_DPG1S_MASK U(0x1) +#define GICR_CTLR_DPG1S_BIT BIT_32(GICR_CTLR_DPG1S_SHIFT) +#define GICR_CTLR_DPG1NS_SHIFT 25 +#define GICR_CTLR_DPG1NS_MASK U(0x1) +#define GICR_CTLR_DPG1NS_BIT BIT_32(GICR_CTLR_DPG1NS_SHIFT) +#define GICR_CTLR_DPG0_SHIFT 24 +#define GICR_CTLR_DPG0_MASK U(0x1) +#define GICR_CTLR_DPG0_BIT BIT_32(GICR_CTLR_DPG0_SHIFT) #define GICR_CTLR_RWP_SHIFT 3 #define GICR_CTLR_RWP_MASK U(0x1) #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT) @@ -212,23 +222,53 @@ #define TYPER_AFF_VAL_SHIFT 32 #define TYPER_PROC_NUM_SHIFT 8 #define TYPER_LAST_SHIFT 4 +#define TYPER_VLPI_SHIFT 1 #define TYPER_AFF_VAL_MASK U(0xffffffff) #define TYPER_PROC_NUM_MASK U(0xffff) #define TYPER_LAST_MASK U(0x1) #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT) +#define TYPER_VLPI_BIT BIT_32(TYPER_VLPI_SHIFT) #define TYPER_PPI_NUM_SHIFT U(27) #define TYPER_PPI_NUM_MASK U(0x1f) /* GICR_IIDR bit definitions */ -#define IIDR_PRODUCT_ID_MASK U(0xff000000) -#define IIDR_VARIANT_MASK U(0x000f0000) -#define IIDR_REVISION_MASK U(0x0000f000) -#define IIDR_IMPLEMENTER_MASK U(0x00000fff) -#define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK | \ - IIDR_IMPLEMENTER_MASK) +#define IIDR_PRODUCT_ID_MASK U(0xff) +#define IIDR_VARIANT_MASK U(0xf) +#define IIDR_REV_MASK U(0xf) +#define IIDR_IMPLEMENTER_MASK U(0xfff) +#define IIDR_PRODUCT_ID_SHIFT 24 +#define IIDR_VARIANT_SHIFT 16 +#define IIDR_REV_SHIFT 12 +#define IIDR_IMPLEMENTER_SHIFT 0 +#define IIDR_PRODUCT_ID_BIT BIT_32(IIDR_PRODUCT_ID_SHIFT) +#define IIDR_VARIANT_BIT BIT_32(IIDR_VARIANT_SHIFT) +#define IIDR_REV_BIT BIT_32(IIDR_REVISION_SHIFT) +#define IIDR_IMPLEMENTER_BIT BIT_32(IIDR_IMPLEMENTER_SHIFT) + +#define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK << IIDR_PRODUCT_ID_SHIFT | \ + IIDR_IMPLEMENTER_MASK << IIDR_IMPLEMENTER_SHIFT) + +#define GIC_PRODUCT_ID_GIC600 U(0x2) +#define GIC_PRODUCT_ID_GIC600AE U(0x3) +#define GIC_PRODUCT_ID_GIC700 U(0x4) + +/* + * Note that below revisions and variants definations are as per GIC600/GIC600AE + * specification. + */ +#define GIC_REV_P0 U(0x1) +#define GIC_REV_P1 U(0x3) +#define GIC_REV_P2 U(0x4) +#define GIC_REV_P3 U(0x5) +#define GIC_REV_P4 U(0x6) +#define GIC_REV_P6 U(0x7) + +#define GIC_VARIANT_R0 U(0x0) +#define GIC_VARIANT_R1 U(0x1) +#define GIC_VARIANT_R2 U(0x2) /******************************************************************************* * GICv3 and 3.1 CPU interface registers & constants @@ -275,7 +315,7 @@ #define SGIR_IRM_SHIFT 40 #define SGIR_IRM_MASK ULL(0x1) #define SGIR_AFF3_SHIFT 48 -#define SGIR_AFF_MASK ULL(0xf) +#define SGIR_AFF_MASK ULL(0xff) #define SGIR_IRM_TO_AFF U(0) @@ -302,6 +342,8 @@ #define GITS_CTLR_ENABLED_BIT BIT_32(0) #define GITS_CTLR_QUIESCENT_BIT BIT_32(1) +#define GITS_TYPER_VSGI BIT_64(39) + #ifndef __ASSEMBLER__ #include <stdbool.h> @@ -312,6 +354,27 @@ #include <drivers/arm/gic_common.h> #include <lib/utils_def.h> +typedef enum { + GICV3_G1S, + GICV3_G1NS, + GICV3_G0 +} gicv3_irq_group_t; + +static inline uintptr_t gicv3_redist_size(uint64_t typer_val) +{ +#if GIC_ENABLE_V4_EXTN + if ((typer_val & TYPER_VLPI_BIT) != 0U) { + return 1U << GICR_V4_PCPUBASE_SHIFT; + } else { + return 1U << GICR_V3_PCPUBASE_SHIFT; + } +#else + return 1U << GICR_V3_PCPUBASE_SHIFT; +#endif +} + +unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame); + static inline bool gicv3_is_intr_id_special_identifier(unsigned int id) { return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT); @@ -493,7 +556,7 @@ void gicv3_cpuif_enable(unsigned int proc_num); void gicv3_cpuif_disable(unsigned int proc_num); unsigned int gicv3_get_pending_interrupt_type(void); unsigned int gicv3_get_pending_interrupt_id(void); -unsigned int gicv3_get_interrupt_type(unsigned int id, +unsigned int gicv3_get_interrupt_group(unsigned int id, unsigned int proc_num); void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx); void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx); @@ -516,14 +579,28 @@ void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num); void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num); void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, unsigned int priority); -void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, - unsigned int type); -void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target); +void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num, + unsigned int group); +void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, + u_register_t target); void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr); void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num); void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num); unsigned int gicv3_set_pmr(unsigned int mask); +unsigned int gicv3_deactivate_priority(unsigned int mask); + +void gicv3_get_component_prodid_rev(const uintptr_t gicd_base, + unsigned int *gic_prod_id, + uint8_t *gic_rev); +void gicv3_check_erratas_applies(const uintptr_t gicd_base); +#if GIC600_ERRATA_WA_2384374 +void gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base); +#else +static inline void gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base) +{ +} +#endif /* GIC600_ERRATA_WA_2384374 */ #endif /* __ASSEMBLER__ */ #endif /* GICV3_H */ diff --git a/include/drivers/arm/mhu.h b/include/drivers/arm/mhu.h new file mode 100644 index 0000000000..31c6a8119a --- /dev/null +++ b/include/drivers/arm/mhu.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MHU_H +#define MHU_H + +#include <stddef.h> +#include <stdint.h> + +/** + * Generic MHU error enumeration types. + */ +enum mhu_error_t { + MHU_ERR_NONE = 0, + MHU_ERR_NOT_INIT = -1, + MHU_ERR_ALREADY_INIT = -2, + MHU_ERR_UNSUPPORTED_VERSION = -3, + MHU_ERR_UNSUPPORTED = -4, + MHU_ERR_INVALID_ARG = -5, + MHU_ERR_BUFFER_TOO_SMALL = -6, + MHU_ERR_GENERAL = -7, +}; + +/** + * Initializes sender MHU. + * + * mhu_sender_base Base address of sender MHU. + * + * Returns mhu_error_t error code. + * + * This function must be called before mhu_send_data(). + */ +enum mhu_error_t mhu_init_sender(uintptr_t mhu_sender_base); + + +/** + * Initializes receiver MHU. + * + * mhu_receiver_base Base address of receiver MHU. + * + * Returns mhu_error_t error code. + * + * This function must be called before mhu_receive_data(). + */ +enum mhu_error_t mhu_init_receiver(uintptr_t mhu_receiver_base); + +/** + * Sends data over MHU. + * + * send_buffer Pointer to buffer containing the data to be transmitted. + * size Size of the data to be transmitted in bytes. + * + * Returns mhu_error_t error code. + * + * The send_buffer must be 4-byte aligned and its length must be at least + * (4 - (size % 4)) bytes bigger than the data size to prevent buffer + * over-reading. + */ +enum mhu_error_t mhu_send_data(const uint8_t *send_buffer, size_t size); + +/** + * Receives data from MHU. + * + * receive_buffer Pointer the buffer where to store the received data. + * size As input the size of the receive_buffer, as output the + * number of bytes received. As a limitation, + * the size of the buffer must be a multiple of 4. + * + * Returns mhu_error_t error code. + * + * The receive_buffer must be 4-byte aligned and its length must be a + * multiple of 4. + */ +enum mhu_error_t mhu_receive_data(uint8_t *receive_buffer, size_t *size); + +/** + * Gets the maximum amount of bytes that can be transmitted in a single send by MHU. + * + * Returns The amount of bytes that can be sent or received in a single message. + */ +size_t mhu_get_max_message_size(void); + +#endif /* MHU_H */ diff --git a/include/drivers/arm/rss_comms.h b/include/drivers/arm/rss_comms.h new file mode 100644 index 0000000000..b96c79f7c1 --- /dev/null +++ b/include/drivers/arm/rss_comms.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef RSS_COMMS_H +#define RSS_COMMS_H + +#include <stdint.h> + +int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base); + +#endif /* RSS_COMMS_H */ diff --git a/include/drivers/arm/sbsa.h b/include/drivers/arm/sbsa.h index 9403634f7a..4ca71942ed 100644 --- a/include/drivers/arm/sbsa.h +++ b/include/drivers/arm/sbsa.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,12 @@ #include <stdint.h> -/* Register Offsets */ +/* SBSA Secure Watchdog Register Offsets */ +/* Refresh frame */ +#define SBSA_WDOG_WRR_OFFSET UL(0x000) +#define SBSA_WDOG_WRR_REFRESH UL(0x1) + +/* Control and status frame */ #define SBSA_WDOG_WCS_OFFSET UL(0x000) #define SBSA_WDOG_WOR_LOW_OFFSET UL(0x008) #define SBSA_WDOG_WOR_HIGH_OFFSET UL(0x00C) @@ -20,5 +25,6 @@ void sbsa_wdog_start(uintptr_t base, uint64_t ms); void sbsa_wdog_stop(uintptr_t base); +void sbsa_wdog_refresh(uintptr_t refresh_base); #endif /* SBSA_H */ diff --git a/include/drivers/arm/smmu_v3.h b/include/drivers/arm/smmu_v3.h index a820a4421d..37da56f6e3 100644 --- a/include/drivers/arm/smmu_v3.h +++ b/include/drivers/arm/smmu_v3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,13 +9,39 @@ #include <stdint.h> #include <lib/utils_def.h> +#include <platform_def.h> /* SMMUv3 register offsets from device base */ +#define SMMU_CR0 U(0x0020) +#define SMMU_CR0ACK U(0x0024) #define SMMU_GBPA U(0x0044) #define SMMU_S_IDR1 U(0x8004) #define SMMU_S_INIT U(0x803c) #define SMMU_S_GBPA U(0x8044) +/* + * TODO: SMMU_ROOT_PAGE_OFFSET is platform specific. + * Currently defined as a command line model parameter. + */ +#if ENABLE_RME + +#define SMMU_ROOT_PAGE_OFFSET (PLAT_ARM_SMMUV3_ROOT_REG_OFFSET) +#define SMMU_ROOT_IDR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0000) +#define SMMU_ROOT_IIDR U(SMMU_ROOT_PAGE_OFFSET + 0x0008) +#define SMMU_ROOT_CR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0020) +#define SMMU_ROOT_CR0ACK U(SMMU_ROOT_PAGE_OFFSET + 0x0024) +#define SMMU_ROOT_GPT_BASE U(SMMU_ROOT_PAGE_OFFSET + 0x0028) +#define SMMU_ROOT_GPT_BASE_CFG U(SMMU_ROOT_PAGE_OFFSET + 0x0030) +#define SMMU_ROOT_GPF_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0038) +#define SMMU_ROOT_GPT_CFG_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0040) +#define SMMU_ROOT_TLBI U(SMMU_ROOT_PAGE_OFFSET + 0x0050) +#define SMMU_ROOT_TLBI_CTRL U(SMMU_ROOT_PAGE_OFFSET + 0x0058) + +#endif /* ENABLE_RME */ + +/* SMMU_CR0 and SMMU_CR0ACK register fields */ +#define SMMU_CR0_SMMUEN (1UL << 0) + /* SMMU_GBPA register fields */ #define SMMU_GBPA_UPDATE (1UL << 31) #define SMMU_GBPA_ABORT (1UL << 20) @@ -30,7 +56,16 @@ #define SMMU_S_GBPA_UPDATE (1UL << 31) #define SMMU_S_GBPA_ABORT (1UL << 20) +/* SMMU_ROOT_IDR0 register fields */ +#define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0) + +/* SMMU_ROOT_CR0 register fields */ +#define SMMU_ROOT_CR0_GPCEN (1UL << 1) +#define SMMU_ROOT_CR0_ACCESSEN (1UL << 0) + int smmuv3_init(uintptr_t smmu_base); int smmuv3_security_init(uintptr_t smmu_base); +int smmuv3_ns_set_abort_all(uintptr_t smmu_base); + #endif /* SMMU_V3_H */ diff --git a/include/drivers/arm/tzc380.h b/include/drivers/arm/tzc380.h index a8098a2f62..9bd5f21d7b 100644 --- a/include/drivers/arm/tzc380.h +++ b/include/drivers/arm/tzc380.h @@ -121,6 +121,11 @@ #define TZC_REGION_SIZE_8E U(0x3e) #define TZC_REGION_SIZE_16E U(0x3f) +#define TZC_SUBREGION_DIS_SHIFT 0x8 +#define TZC_SUBREGION_DIS_MASK U(0xff) +#define TZC_ATTR_SUBREG_DIS(s) (((s) & TZC_SUBREGION_DIS_MASK) \ + << TZC_SUBREGION_DIS_SHIFT) + #define TZC_REGION_SIZE_SHIFT 0x1 #define TZC_REGION_SIZE_MASK U(0x7e) #define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT) diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h index 5f8a48f570..765c130ebb 100644 --- a/include/drivers/arm/tzc400.h +++ b/include/drivers/arm/tzc400.h @@ -109,6 +109,7 @@ void tzc400_configure_region(unsigned int filters, unsigned long long region_top, unsigned int sec_attr, unsigned int nsaid_permissions); +void tzc400_update_filters(unsigned int region, unsigned int filters); void tzc400_set_action(unsigned int action); void tzc400_enable_filters(void); void tzc400_disable_filters(void); diff --git a/include/drivers/auth/auth_mod.h b/include/drivers/auth/auth_mod.h index d1fd52c868..28aa40784a 100644 --- a/include/drivers/auth/auth_mod.h +++ b/include/drivers/auth/auth_mod.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,9 +7,6 @@ #ifndef AUTH_MOD_H #define AUTH_MOD_H -#if TRUSTED_BOARD_BOOT - -#include <common/tbbr/cot_def.h> #include <common/tbbr/tbbr_img_def.h> #include <drivers/auth/auth_common.h> #include <drivers/auth/img_parser_mod.h> @@ -46,7 +43,13 @@ typedef struct auth_img_desc_s { #endif /* COT_DESC_IN_DTB && !IMAGE_BL1 */ /* Public functions */ +#if TRUSTED_BOARD_BOOT void auth_mod_init(void); +#else +static inline void auth_mod_init(void) +{ +} +#endif /* TRUSTED_BOARD_BOOT */ int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id); int auth_mod_verify_img(unsigned int img_id, void *img_ptr, @@ -85,6 +88,4 @@ extern unsigned int auth_img_flags[MAX_NUMBER_IDS]; #endif -#endif /* TRUSTED_BOARD_BOOT */ - #endif /* AUTH_MOD_H */ diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h index 71cf67306d..bec19da2c3 100644 --- a/include/drivers/auth/crypto_mod.h +++ b/include/drivers/auth/crypto_mod.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,10 @@ #ifndef CRYPTO_MOD_H #define CRYPTO_MOD_H +#define CRYPTO_AUTH_VERIFY_ONLY 1 +#define CRYPTO_HASH_CALC_ONLY 2 +#define CRYPTO_AUTH_VERIFY_AND_HASH_CALC 3 + /* Return values */ enum crypto_ret_value { CRYPTO_SUCCESS = 0, @@ -25,6 +29,16 @@ enum crypto_dec_algo { CRYPTO_GCM_DECRYPT = 0 }; +/* Message digest algorithm */ +enum crypto_md_algo { + CRYPTO_MD_SHA256, + CRYPTO_MD_SHA384, + CRYPTO_MD_SHA512, +}; + +/* Maximum size as per the known stronger hash algorithm i.e.SHA512 */ +#define CRYPTO_MD_MAX_SIZE 64U + /* * Cryptographic library descriptor */ @@ -32,7 +46,7 @@ typedef struct crypto_lib_desc_s { const char *name; /* Initialize library. This function is not expected to fail. All errors - * must be handled inside the function, asserting or panicing in case of + * must be handled inside the function, asserting or panicking in case of * a non-recoverable error */ void (*init)(void); @@ -47,11 +61,14 @@ typedef struct crypto_lib_desc_s { int (*verify_hash)(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); -#if MEASURED_BOOT /* Calculate a hash. Return hash value */ - int (*calc_hash)(unsigned int alg, void *data_ptr, - unsigned int data_len, unsigned char *output); -#endif /* MEASURED_BOOT */ + int (*calc_hash)(enum crypto_md_algo md_alg, void *data_ptr, + unsigned int data_len, + unsigned char output[CRYPTO_MD_MAX_SIZE]); + + /* Convert Public key (optional) */ + int (*convert_pk)(void *full_pk_ptr, unsigned int full_pk_len, + void **hashed_pk_ptr, unsigned int *hashed_pk_len); /* * Authenticated decryption. Return one of the @@ -65,45 +82,54 @@ typedef struct crypto_lib_desc_s { } crypto_lib_desc_t; /* Public functions */ +#if CRYPTO_SUPPORT void crypto_mod_init(void); +#else +static inline void crypto_mod_init(void) +{ +} +#endif /* CRYPTO_SUPPORT */ + +#if (CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY) || \ + (CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC) int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, void *sig_ptr, unsigned int sig_len, void *sig_alg_ptr, unsigned int sig_alg_len, void *pk_ptr, unsigned int pk_len); int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); +#endif /* (CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY) || \ + (CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC) */ + int crypto_mod_auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr, size_t len, const void *key, unsigned int key_len, unsigned int key_flags, const void *iv, unsigned int iv_len, const void *tag, unsigned int tag_len); -#if MEASURED_BOOT -int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, - unsigned int data_len, unsigned char *output); +#if (CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY) || \ + (CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC) +int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr, + unsigned int data_len, + unsigned char output[CRYPTO_MD_MAX_SIZE]); +#endif /* (CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY) || \ + (CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC) */ + +int crypto_mod_convert_pk(void *full_pk_ptr, unsigned int full_pk_len, + void **hashed_pk_ptr, unsigned int *hashed_pk_len); /* Macro to register a cryptographic library */ #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ - _calc_hash, _auth_decrypt) \ + _calc_hash, _auth_decrypt, _convert_pk) \ const crypto_lib_desc_t crypto_lib_desc = { \ .name = _name, \ .init = _init, \ .verify_signature = _verify_signature, \ .verify_hash = _verify_hash, \ .calc_hash = _calc_hash, \ - .auth_decrypt = _auth_decrypt \ - } -#else -#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ - _auth_decrypt) \ - const crypto_lib_desc_t crypto_lib_desc = { \ - .name = _name, \ - .init = _init, \ - .verify_signature = _verify_signature, \ - .verify_hash = _verify_hash, \ - .auth_decrypt = _auth_decrypt \ + .auth_decrypt = _auth_decrypt, \ + .convert_pk = _convert_pk \ } -#endif /* MEASURED_BOOT */ extern const crypto_lib_desc_t crypto_lib_desc; diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config-3.h index ad39fa9067..923fc5467f 100644 --- a/include/drivers/auth/mbedtls/mbedtls_config.h +++ b/include/drivers/auth/mbedtls/mbedtls_config-3.h @@ -1,10 +1,14 @@ /* - * Copyright (c) 2015-2020, Arm Limited. All rights reserved. + * Copyright (c) 2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef MBEDTLS_CONFIG_H -#define MBEDTLS_CONFIG_H + +/** + * This set of compile-time options may be used to enable + * or disable features selectively, and reduce the global + * memory footprint. + */ /* * Key algorithms currently supported on mbed TLS libraries @@ -37,10 +41,6 @@ #define MBEDTLS_PKCS1_V21 -#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION -#define MBEDTLS_X509_CHECK_KEY_USAGE -#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE - #define MBEDTLS_ASN1_PARSE_C #define MBEDTLS_ASN1_WRITE_C @@ -62,18 +62,35 @@ #if TF_MBEDTLS_USE_ECDSA #define MBEDTLS_ECDSA_C #define MBEDTLS_ECP_C +#if TF_MBEDTLS_KEY_SIZE == 384 +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#else #define MBEDTLS_ECP_DP_SECP256R1_ENABLED -#define MBEDTLS_ECP_NO_INTERNAL_RNG +#endif #endif #if TF_MBEDTLS_USE_RSA #define MBEDTLS_RSA_C #define MBEDTLS_X509_RSASSA_PSS_SUPPORT #endif +/* The library does not currently support enabling SHA-256 without SHA-224. */ +#define MBEDTLS_SHA224_C #define MBEDTLS_SHA256_C -#if (TF_MBEDTLS_HASH_ALG_ID != TF_MBEDTLS_SHA256) +/* + * If either Trusted Boot or Measured Boot require a stronger algorithm than + * SHA-256, pull in SHA-512 support. Library currently needs to have SHA_384 + * support when enabling SHA-512. + */ +#if (TF_MBEDTLS_HASH_ALG_ID != TF_MBEDTLS_SHA256) /* TBB hash algo */ +#define MBEDTLS_SHA384_C +#define MBEDTLS_SHA512_C +#else + /* TBB uses SHA-256, what about measured boot? */ +#if defined(TF_MBEDTLS_MBOOT_USE_SHA512) +#define MBEDTLS_SHA384_C #define MBEDTLS_SHA512_C #endif +#endif #define MBEDTLS_VERSION_C @@ -130,4 +147,11 @@ #endif #endif -#endif /* MBEDTLS_CONFIG_H */ +/* + * Warn if errors from certain functions are ignored. + * + * The warnings are always enabled (where supported) for critical functions + * where ignoring the return value is almost always a bug. This macro extends + * the warnings to more functions. + */ +#define MBEDTLS_CHECK_RETURN_WARNING diff --git a/include/drivers/auth/mbedtls/psa_mbedtls_config.h b/include/drivers/auth/mbedtls/psa_mbedtls_config.h new file mode 100644 index 0000000000..ad825f0aa7 --- /dev/null +++ b/include/drivers/auth/mbedtls/psa_mbedtls_config.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2023, Arm Ltd. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSA_MBEDTLS_CONFIG_H +#define PSA_MBEDTLS_CONFIG_H + +#include "mbedtls_config-3.h" + +#define MBEDTLS_PSA_CRYPTO_C + +/* + * Using PSA crypto API requires an RNG right now. If we don't define the macro + * below then we get build errors. + * + * This is a functionality gap in mbedTLS. The technical limitation is that + * psa_crypto_init() is all-or-nothing, and fixing that would require separate + * initialization of the keystore, the RNG, etc. + * + * By defining MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG, we pretend using an external + * RNG. As a result, the PSA crypto init code does nothing when it comes to + * initializing the RNG, as we are supposed to take care of that ourselves. + */ +#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +#endif /* PSA_MBEDTLS_CONFIG_H */ diff --git a/include/drivers/auth/tbbr_cot_common.h b/include/drivers/auth/tbbr_cot_common.h index a51faee1aa..b4f2d220fc 100644 --- a/include/drivers/auth/tbbr_cot_common.h +++ b/include/drivers/auth/tbbr_cot_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020,2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef TBBR_COT_COMMON_H #define TBBR_COT_COMMON_H +#include <common/tbbr/cot_def.h> #include <drivers/auth/auth_mod.h> extern unsigned char tb_fw_hash_buf[HASH_DER_LEN]; diff --git a/include/drivers/brcm/emmc/emmc_csl_sdprot.h b/include/drivers/brcm/emmc/emmc_csl_sdprot.h index 597e1e0876..580194034b 100644 --- a/include/drivers/brcm/emmc/emmc_csl_sdprot.h +++ b/include/drivers/brcm/emmc/emmc_csl_sdprot.h @@ -139,7 +139,7 @@ * The Common I/O area shall be implemented on all SDIO cards and * is accessed the the host via I/O reads and writes to function 0, * the registers within the CIA are provided to enable/disable - * the operationo fthe i/o funciton. + * the operationo fthe i/o function. */ /* cccr_sdio_rev */ @@ -303,7 +303,7 @@ #define SBSDIO_CIS_BASE_COMMON 0x1000 /* function 0(common) cis size in bytes */ #define SBSDIO_CIS_FUNC0_LIMIT 0x020 -/* funciton 1 cis size in bytes */ +/* function 1 cis size in bytes */ #define SBSDIO_CIS_SIZE_LIMIT 0x200 /* cis offset addr is < 17 bits */ #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF @@ -313,7 +313,7 @@ /* indirect cis access (in sprom) */ /* 8 control bytes first, CIS starts from 8th uint8_t */ #define SBSDIO_SPROM_CIS_OFFSET 0x8 -/* sdio uint8_t mode: maximum length of one data comamnd */ +/* sdio uint8_t mode: maximum length of one data command */ #define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* 4317 supports less */ #define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52 diff --git a/include/drivers/brcm/i2c/i2c.h b/include/drivers/brcm/i2c/i2c.h index 24d42e208a..2cc81d5b3e 100644 --- a/include/drivers/brcm/i2c/i2c.h +++ b/include/drivers/brcm/i2c/i2c.h @@ -78,7 +78,7 @@ uint32_t i2c_get_bus_speed(uint32_t bus_id); * * Description: * This function reads I2C data from a device without specifying - * a command regsiter. + * a command register. * * Parameters: * bus_id - I2C bus ID @@ -95,7 +95,7 @@ int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value); * * Description: * This function send I2C data to a device without specifying - * a command regsiter. + * a command register. * * Parameters: * bus_id - I2C bus ID diff --git a/include/drivers/cadence/cdns_combo_phy.h b/include/drivers/cadence/cdns_combo_phy.h new file mode 100644 index 0000000000..f5dabdafad --- /dev/null +++ b/include/drivers/cadence/cdns_combo_phy.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_COMBOPHY_H +#define CDN_COMBOPHY_H + +/* SRS */ +#define SDMMC_CDN_SRS02 0x8 +#define SDMMC_CDN_SRS03 0xC +#define SDMMC_CDN_SRS04 0x10 +#define SDMMC_CDN_SRS05 0x14 +#define SDMMC_CDN_SRS06 0x18 +#define SDMMC_CDN_SRS07 0x1C +#define SDMMC_CDN_SRS09 0x24 +#define SDMMC_CDN_SRS10 0x28 +#define SDMMC_CDN_SRS11 0x2C +#define SDMMC_CDN_SRS12 0x30 +#define SDMMC_CDN_SRS13 0x34 +#define SDMMC_CDN_SRS14 0x38 + +/* SRS03 */ +/* Response Type Select + * Defines the expected response length. + */ +#define SDMMC_CDN_RTS 16 + +/* Command CRC Check Enable + * When set to 1, the host checks if the CRC field of the response is valid. + * When 0, the CRC check is disabled and the CRC field of the response is ignored. + */ +#define SDMMC_CDN_CRCCE 19 + +/* Command Index + * This field contains a command number (index) of the command to be sent. + */ +#define SDMMC_CDN_CIDX 24 + +/* SRS09 */ +/* Card Inserted + * Indicates if the card is inserted inside the slot. + */ +#define SDMMC_CDN_CI 16 + +/* SRS10 */ +/* Data Transfer Width + * Bit used to configure DAT bus width to 1 or 4. + */ +#define SDMMC_CDN_DTW 1 + +/* Extended Data Transfer Width + * This bit is to enable/disable 8-bit DAT bus width mode. + */ +#define SDMMC_CDN_EDTW 5 + +/* SD Bus Power for VDD1 + * When set to 1, the VDD1 voltage is supplied to card/device. + */ +#define SDMMC_CDN_BP 8 + +/* SD Bus Voltage Select + * This field is used to configure VDD1 voltage level. + */ +#define SDMMC_CDN_BVS 9 + +/* SRS11 */ +/* Internal Clock Enable + * This field is designated to controls (enable/disable) external clock generator. + */ +#define SDMMC_CDN_ICE 0 + +/* Internal Clock Stable + * When 1, indicates that the clock on sdmclk pin of the host is stable. + * When 0, indicates that the clock is not stable . + */ +#define SDMMC_CDN_ICS 1 + +/* SD Clock Enable + * When set, SDCLK clock is enabled. + * When clear, SDCLK clock is stopped. + */ +#define SDMMC_CDN_SDCE 2 + +/* USDCLK Frequency Select + * This is used to calculate frequency of USDCLK clock. + */ +#define SDMMC_CDN_USDCLKFS 6 + +/* SDCLK Frequency Select + * This is used to calculate frequency of SDCLK clock. + */ +#define SDMMC_CDN_SDCLKFS 8 + +/* Data Timeout Counter Value + * This value determines the interval by which DAT line timeouts are detected + */ +#define SDMMC_CDN_DTCV 16 + +/* SRS12 */ +/* Command Complete + * Generated when the end bit of the response is received. + */ +#define SDMMC_CDN_CC 0 + +/* Transfer Complete + * Generated when the transfer which uses the DAT line is complete. + */ +#define SDMMC_CDN_TC 1 + +/* Error Interrupt + * The software can check for an error by reading this single bit first. + */ +#define SDMMC_CDN_EINT 15 + +/* SRS14 */ +/* Command Complete Interrupt Enable */ +#define SDMMC_CDN_CC_IE 0 + +/* Transfer Complete Interrupt Enable */ +#define SDMMC_CDN_TC_IE 1 + +/* DMA Interrupt Enable */ +#define SDMMC_CDN_DMAINT_IE 3 + +/* Combo PHY DLL registers */ +#define CP_DLL_REG_BASE (0x10B92000) +#define CP_DLL_DQ_TIMING_REG (0x00) +#define CP_DLL_DQS_TIMING_REG (0x04) +#define CP_DLL_GATE_LPBK_CTRL_REG (0x08) +#define CP_DLL_MASTER_CTRL_REG (0x0C) +#define CP_DLL_SLAVE_CTRL_REG (0x10) +#define CP_DLL_IE_TIMING_REG (0x14) + +#define CP_DQ_TIMING_REG_SDR (0x00000002) +#define CP_DQS_TIMING_REG_SDR (0x00100004) +#define CP_GATE_LPBK_CTRL_REG_SDR (0x00D80000) +#define CP_DLL_MASTER_CTRL_REG_SDR (0x00800000) +#define CP_DLL_SLAVE_CTRL_REG_SDR (0x00000000) + +#define CP_DLL(_reg) (CP_DLL_REG_BASE \ + + (CP_DLL_##_reg)) + +/* Control Timing Block registers */ +#define CP_CTB_REG_BASE (0x10B92080) +#define CP_CTB_CTRL_REG (0x00) +#define CP_CTB_TSEL_REG (0x04) +#define CP_CTB_GPIO_CTRL0 (0x08) +#define CP_CTB_GPIO_CTRL1 (0x0C) +#define CP_CTB_GPIO_STATUS0 (0x10) +#define CP_CTB_GPIO_STATUS1 (0x14) + +#define CP_CTRL_REG_SDR (0x00004040) +#define CP_TSEL_REG_SDR (0x00000000) + +#define CP_CTB(_reg) (CP_CTB_REG_BASE \ + + (CP_CTB_##_reg)) + +/* Combo PHY */ +#define SDMMC_CDN_REG_BASE 0x10808200 +#define PHY_DQ_TIMING_REG 0x2000 +#define PHY_DQS_TIMING_REG 0x2004 +#define PHY_GATE_LPBK_CTRL_REG 0x2008 +#define PHY_DLL_MASTER_CTRL_REG 0x200C +#define PHY_DLL_SLAVE_CTRL_REG 0x2010 +#define PHY_CTRL_REG 0x2080 +#define PHY_REG_ADDR_MASK 0xFFFF +#define PHY_REG_DATA_MASK 0xFFFFFFFF + +/* PHY_DQS_TIMING_REG */ +#define CP_USE_EXT_LPBK_DQS(x) ((x) << 22) //0x1 +#define CP_USE_LPBK_DQS(x) ((x) << 21) //0x1 +#define CP_USE_PHONY_DQS(x) ((x) << 20) //0x1 +#define CP_USE_PHONY_DQS_CMD(x) ((x) << 19) //0x1 + +/* PHY_GATE_LPBK_CTRL_REG */ +#define CP_SYNC_METHOD(x) ((x) << 31) //0x1 +#define CP_SW_HALF_CYCLE_SHIFT(x) ((x) << 28) //0x1 +#define CP_RD_DEL_SEL(x) ((x) << 19) //0x3f +#define CP_UNDERRUN_SUPPRESS(x) ((x) << 18) //0x1 +#define CP_GATE_CFG_ALWAYS_ON(x) ((x) << 6) //0x1 + +/* PHY_DLL_MASTER_CTRL_REG */ +#define CP_DLL_BYPASS_MODE(x) ((x) << 23) //0x1 +#define CP_DLL_START_POINT(x) ((x) << 0) //0xff + +/* PHY_DLL_SLAVE_CTRL_REG */ +#define CP_READ_DQS_CMD_DELAY(x) ((x) << 24) //0xff +#define CP_CLK_WRDQS_DELAY(x) ((x) << 16) //0xff +#define CP_CLK_WR_DELAY(x) ((x) << 8) //0xff +#define CP_READ_DQS_DELAY(x) ((x) << 0) //0xff + +/* PHY_DQ_TIMING_REG */ +#define CP_IO_MASK_ALWAYS_ON(x) ((x) << 31) //0x1 +#define CP_IO_MASK_END(x) ((x) << 27) //0x7 +#define CP_IO_MASK_START(x) ((x) << 24) //0x7 +#define CP_DATA_SELECT_OE_END(x) ((x) << 0) //0x7 + +/* PHY_CTRL_REG */ +#define CP_PHONY_DQS_TIMING_MASK 0x3F +#define CP_PHONY_DQS_TIMING_SHIFT 4 + +/* Shared Macros */ +#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ + (SDMMC_CDN_##_reg)) + +struct cdns_sdmmc_combo_phy { + uint32_t cp_clk_wr_delay; + uint32_t cp_clk_wrdqs_delay; + uint32_t cp_data_select_oe_end; + uint32_t cp_dll_bypass_mode; + uint32_t cp_dll_locked_mode; + uint32_t cp_dll_start_point; + uint32_t cp_gate_cfg_always_on; + uint32_t cp_io_mask_always_on; + uint32_t cp_io_mask_end; + uint32_t cp_io_mask_start; + uint32_t cp_rd_del_sel; + uint32_t cp_read_dqs_cmd_delay; + uint32_t cp_read_dqs_delay; + uint32_t cp_sw_half_cycle_shift; + uint32_t cp_sync_method; + uint32_t cp_underrun_suppress; + uint32_t cp_use_ext_lpbk_dqs; + uint32_t cp_use_lpbk_dqs; + uint32_t cp_use_phony_dqs; + uint32_t cp_use_phony_dqs_cmd; +}; + +/* Function Prototype */ + +int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, + uint32_t phy_reg_data, uint32_t phy_reg_data_value); +int cdns_sd_card_detect(void); +int cdns_emmc_card_reset(void); + +#endif diff --git a/include/drivers/cadence/cdns_nand.h b/include/drivers/cadence/cdns_nand.h new file mode 100644 index 0000000000..f20627ba52 --- /dev/null +++ b/include/drivers/cadence/cdns_nand.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_NAND_H +#define CDN_NAND_H + +#include <drivers/cadence/cdns_combo_phy.h> + +/* NAND flash device information */ +typedef struct cnf_dev_info { + uint8_t type; + uint8_t nluns; + uint8_t sector_cnt; + uint16_t npages_per_block; + uint16_t sector_size; + uint16_t last_sector_size; + uint16_t page_size; + uint16_t spare_size; + uint32_t nblocks_per_lun; + uint32_t block_size; + unsigned long long total_size; +} cnf_dev_info_t; + +/* Shared Macros */ + +/* Default values */ +#define CNF_DEF_VOL_ID 0 +#define CNF_DEF_DEVICE 0 +#define CNF_DEF_TRD 0 +#define CNF_READ_SINGLE_PAGE 1 +#define CNF_DEF_DELAY_US 500 +#define CNF_READ_INT_DELAY_US 10 + +/* Work modes */ +#define CNF_WORK_MODE_CDMA 0 +#define CNF_WORK_MODE_PIO 1 + +/* Command types */ +#define CNF_CT_SET_FEATURE 0x0100 +#define CNF_CT_RESET_ASYNC 0x1100 +#define CNF_CT_RESET_SYNC 0x1101 +#define CNF_CT_RESET_LUN 0x1102 +#define CNF_CT_ERASE 0x1000 +#define CNF_CT_PAGE_PROGRAM 0x2100 +#define CNF_CT_PAGE_READ 0x2200 + +/* Interrupts enable or disable */ +#define CNF_INT_EN 1 +#define CNF_INT_DIS 0 + +/* Device types */ +#define CNF_DT_UNKNOWN 0x00 +#define CNF_DT_ONFI 0x01 +#define CNF_DT_JEDEC 0x02 +#define CNF_DT_LEGACY 0x03 + +/* Command and status registers */ +#define CNF_CMDREG_REG_BASE SOCFPGA_NAND_REG_BASE + +/* DMA maximum burst size 0-127*/ +#define CNF_DMA_BURST_SIZE_MAX 127 + +/* DMA settings register field offsets */ +#define CNF_DMA_SETTINGS_BURST 0 +#define CNF_DMA_SETTINGS_OTE 16 +#define CNF_DMA_SETTINGS_SDMA_ERR 17 + +#define CNF_DMA_MASTER_SEL 1 +#define CNF_DMA_SLAVE_SEL 0 + +/* DMA FIFO trigger level register field offsets */ +#define CNF_FIFO_TLEVEL_POS 0 +#define CNF_FIFO_TLEVEL_DMA_SIZE 16 +#define CNF_DMA_PREFETCH_SIZE (1024 / 8) + +#define CNF_GET_CTRL_BUSY(x) (x & (1 << 8)) +#define CNF_GET_INIT_COMP(x) (x & (1 << 9)) + +/* Command register0 field offsets */ +#define CNF_CMDREG0_CT 30 +#define CNF_CMDREG0_TRD 24 +#define CNF_CMDREG0_INTR 20 +#define CNF_CMDREG0_DMA 21 +#define CNF_CMDREG0_VOL 16 +#define CNF_CMDREG0_CMD 0 +#define CNF_CMDREG4_MEM 24 + +/* Command status register field offsets */ +#define CNF_ECMD BIT(0) +#define CNF_EECC BIT(1) +#define CNF_EMAX BIT(2) +#define CNF_EDEV BIT(12) +#define CNF_EDQS BIT(13) +#define CNF_EFAIL BIT(14) +#define CNF_CMPLT BIT(15) +#define CNF_EBUS BIT(16) +#define CNF_EDI BIT(17) +#define CNF_EPAR BIT(18) +#define CNF_ECTX BIT(19) +#define CNF_EPRO BIT(20) +#define CNF_EIDX BIT(24) + +#define CNF_CMDREG_CMD_REG0 0x00 +#define CNF_CMDREG_CMD_REG1 0x04 +#define CNF_CMDREG_CMD_REG2 0x08 +#define CNF_CMDREG_CMD_REG3 0x0C +#define CNF_CMDREG_CMD_STAT_PTR 0x10 +#define CNF_CMDREG_CMD_STAT 0x14 +#define CNF_CMDREG_CMD_REG4 0x20 +#define CNF_CMDREG_CTRL_STATUS 0x118 +#define CNF_CMDREG_TRD_STATUS 0x120 + +#define CNF_CMDREG(_reg) (CNF_CMDREG_REG_BASE \ + + (CNF_CMDREG_##_reg)) + +/* Controller configuration registers */ +#define CNF_LSB16_MASK 0xFFFF +#define CNF_GET_NPAGES_PER_BLOCK(x) (x & CNF_LSB16_MASK) + +#define CNF_GET_SCTR_SIZE(x) (x & CNF_LSB16_MASK) +#define CNF_GET_LAST_SCTR_SIZE(x) ((x >> 16) & CNF_LSB16_MASK) + +#define CNF_GET_PAGE_SIZE(x) (x & CNF_LSB16_MASK) +#define CNF_GET_SPARE_SIZE(x) ((x >> 16) & CNF_LSB16_MASK) + +#define CNF_CTRLCFG_REG_BASE 0x10B80400 +#define CNF_CTRLCFG_TRANS_CFG0 0x00 +#define CNF_CTRLCFG_TRANS_CFG1 0x04 +#define CNF_CTRLCFG_LONG_POLL 0x08 +#define CNF_CTRLCFG_SHORT_POLL 0x0C +#define CNF_CTRLCFG_DEV_STAT 0x10 +#define CNF_CTRLCFG_DEV_LAYOUT 0x24 +#define CNF_CTRLCFG_ECC_CFG0 0x28 +#define CNF_CTRLCFG_ECC_CFG1 0x2C +#define CNF_CTRLCFG_MULTIPLANE_CFG 0x34 +#define CNF_CTRLCFG_CACHE_CFG 0x38 +#define CNF_CTRLCFG_DMA_SETTINGS 0x3C +#define CNF_CTRLCFG_FIFO_TLEVEL 0x54 + +#define CNF_CTRLCFG(_reg) (CNF_CTRLCFG_REG_BASE \ + + (CNF_CTRLCFG_##_reg)) + +/* Data integrity registers */ +#define CNF_DI_PAR_EN 0 +#define CNF_DI_CRC_EN 1 + +#define CNF_DI_REG_BASE 0x10B80700 +#define CNF_DI_CONTROL 0x00 +#define CNF_DI_INJECT0 0x04 +#define CNF_DI_INJECT1 0x08 +#define CNF_DI_ERR_REG_ADDR 0x0C +#define CNF_DI_INJECT2 0x10 + +#define CNF_DI(_reg) (CNF_DI_REG_BASE \ + + (CNF_DI_##_reg)) + +/* Controller parameter registers */ +#define CNF_NTHREADS_MASK 0x07 +#define CNF_GET_NLUNS(x) (x & 0xFF) +#define CNF_GET_DEV_TYPE(x) ((x >> 30) & 0x03) +#define CNF_GET_NTHREADS(x) (1 << (x & CNF_NTHREADS_MASK)) + +#define CNF_CTRLPARAM_REG_BASE 0x10B80800 +#define CNF_CTRLPARAM_VERSION 0x00 +#define CNF_CTRLPARAM_FEATURE 0x04 +#define CNF_CTRLPARAM_MFR_ID 0x08 +#define CNF_CTRLPARAM_DEV_AREA 0x0C +#define CNF_CTRLPARAM_DEV_PARAMS0 0x10 +#define CNF_CTRLPARAM_DEV_PARAMS1 0x14 +#define CNF_CTRLPARAM_DEV_FEATUERS 0x18 +#define CNF_CTRLPARAM_DEV_BLOCKS_PLUN 0x1C + +#define CNF_CTRLPARAM(_reg) (CNF_CTRLPARAM_REG_BASE \ + + (CNF_CTRLPARAM_##_reg)) + +/* Protection mechanism registers */ +#define CNF_PROT_REG_BASE 0x10B80900 +#define CNF_PROT_CTRL0 0x00 +#define CNF_PROT_DOWN0 0x04 +#define CNF_PROT_UP0 0x08 +#define CNF_PROT_CTRL1 0x10 +#define CNF_PROT_DOWN1 0x14 +#define CNF_PROT_UP1 0x18 + +#define CNF_PROT(_reg) (CNF_PROT_REG_BASE \ + + (CNF_PROT_##_reg)) + +/* Mini controller registers */ +#define CNF_MINICTRL_REG_BASE 0x10B81000 + +/* Operation work modes */ +#define CNF_OPR_WORK_MODE_SDR 0 +#define CNF_OPR_WORK_MODE_NVDDR 1 +#define CNF_OPR_WORK_MODE_TOGGLE_NVDDR2_3 2 +#define CNF_OPR_WORK_MODE_RES 3 + +/* Mini controller common settings register field offsets */ +#define CNF_CMN_SETTINGS_OPR_MASK 0x00000003 +#define CNF_CMN_SETTINGS_WR_WUP 20 +#define CNF_CMN_SETTINGS_RD_WUP 16 +#define CNF_CMN_SETTINGS_DEV16 8 +#define CNF_CMN_SETTINGS_OPR 0 + +/* Async mode register field offsets */ +#define CNF_ASYNC_TIMINGS_TRH 24 +#define CNF_ASYNC_TIMINGS_TRP 16 +#define CNF_ASYNC_TIMINGS_TWH 8 +#define CNF_ASYNC_TIMINGS_TWP 0 + +/* Mini controller DLL PHY controller register field offsets */ +#define CNF_DLL_PHY_RST_N 24 +#define CNF_DLL_PHY_EXT_WR_MODE 17 +#define CNF_DLL_PHY_EXT_RD_MODE 16 + +#define CNF_MINICTRL_WP_SETTINGS 0x00 +#define CNF_MINICTRL_RBN_SETTINGS 0x04 +#define CNF_MINICTRL_CMN_SETTINGS 0x08 +#define CNF_MINICTRL_SKIP_BYTES_CFG 0x0C +#define CNF_MINICTRL_SKIP_BYTES_OFFSET 0x10 +#define CNF_MINICTRL_TOGGLE_TIMINGS0 0x14 +#define CNF_MINICTRL_TOGGLE_TIMINGS1 0x18 +#define CNF_MINICTRL_ASYNC_TOGGLE_TIMINGS 0x1C +#define CNF_MINICTRL_SYNC_TIMINGS 0x20 +#define CNF_MINICTRL_DLL_PHY_CTRL 0x34 + +#define CNF_MINICTRL(_reg) (CNF_MINICTRL_REG_BASE \ + + (CNF_MINICTRL_##_reg)) + +/* + * @brief Nand IO MTD initialization routine + * + * @total_size: [out] Total size of the NAND flash device + * @erase_size: [out] Minimum erase size of the NAND flash device + * Return: 0 on success, a negative errno on failure + */ +int cdns_nand_init_mtd(unsigned long long *total_size, + unsigned int *erase_size); + +/* + * @brief Read bytes from the NAND flash device + * + * @offset: Byte offset to read from in device + * @buffer: [out] Bytes read from device + * @length: Number of bytes to read + * @out_length: [out] Number of bytes read from device + * Return: 0 on success, a negative errno on failure + */ +int cdns_nand_read(unsigned int offset, uintptr_t buffer, + size_t length, size_t *out_length); + +/* NAND Flash Controller/Host initialization */ +int cdns_nand_host_init(void); + +#endif diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h new file mode 100644 index 0000000000..6452725354 --- /dev/null +++ b/include/drivers/cadence/cdns_sdmmc.h @@ -0,0 +1,474 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_MMC_H +#define CDN_MMC_H + +#include <drivers/cadence/cdns_combo_phy.h> +#include <drivers/mmc.h> +#include "socfpga_plat_def.h" + +#if MMC_DEVICE_TYPE == 0 +#define CONFIG_DMA_ADDR_T_64BIT 0 +#endif + +#define MMC_REG_BASE SOCFPGA_MMC_REG_BASE +#define COMBO_PHY_REG 0x0 +#define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7 +#define SDHC_DLL_RESET_MASK 0x00000001 +/* HRS09 */ +#define SDHC_PHY_SW_RESET BIT(0) +#define SDHC_PHY_INIT_COMPLETE BIT(1) +#define SDHC_EXTENDED_RD_MODE(x) ((x) << 2) +#define EXTENDED_WR_MODE 3 +#define SDHC_EXTENDED_WR_MODE(x) ((x) << 3) +#define RDCMD_EN 15 +#define SDHC_RDCMD_EN(x) ((x) << 15) +#define SDHC_RDDATA_EN(x) ((x) << 16) + +/* CMD_DATA_OUTPUT */ +#define SDHC_CDNS_HRS16 0x40 + +/* This value determines the interval by which DAT line timeouts are detected */ +/* The interval can be computed as below: */ +/* • 1111b - Reserved */ +/* • 1110b - t_sdmclk*2(27+2) */ +/* • 1101b - t_sdmclk*2(26+2) */ +#define READ_CLK 0xa << 16 +#define WRITE_CLK 0xe << 16 +#define DTC_VAL 0xE + +/* SRS00 */ +/* System Address / Argument 2 / 32-bit block count + * This field is used as: + * • 32-bit Block Count register + * • SDMA system memory address + * • Auto CMD23 Argument + */ +#define SAAR (1) + +/* SRS01 */ +/* Transfer Block Size + * This field defines block size for block data transfers + */ +#define BLOCK_SIZE 0 + +/* SDMA Buffer Boundary + * System address boundary can be set for SDMA engine. + */ +#define SDMA_BUF 7 << 12 + +/* Block Count For Current Transfer + * To set the number of data blocks can be defined for next transfer + */ +#define BLK_COUNT_CT 16 + +/* SRS03 */ +#define CMD_START (U(1) << 31) +#define CMD_USE_HOLD_REG (1 << 29) +#define CMD_UPDATE_CLK_ONLY (1 << 21) +#define CMD_SEND_INIT (1 << 15) +#define CMD_STOP_ABORT_CMD (4 << 22) +#define CMD_RESUME_CMD (2 << 22) +#define CMD_SUSPEND_CMD (1 << 22) +#define DATA_PRESENT (1 << 21) +#define CMD_IDX_CHK_ENABLE (1 << 20) +#define CMD_WRITE (0 << 4) +#define CMD_READ (1 << 4) +#define MULTI_BLK_READ (1 << 5) +#define RESP_ERR (1 << 7) +#define CMD_CHECK_RESP_CRC (1 << 19) +#define RES_TYPE_SEL_48 (2 << 16) +#define RES_TYPE_SEL_136 (1 << 16) +#define RES_TYPE_SEL_48_B (3 << 16) +#define RES_TYPE_SEL_NO (0 << 16) +#define DMA_ENABLED (1 << 0) +#define BLK_CNT_EN (1 << 1) +#define AUTO_CMD_EN (2 << 2) +#define COM_IDX 24 +#define ERROR_INT (1 << 15) +#define INT_SBE (1 << 13) +#define INT_HLE (1 << 12) +#define INT_FRUN (1 << 11) +#define INT_DRT (1 << 9) +#define INT_RTO (1 << 8) +#define INT_DCRC (1 << 7) +#define INT_RCRC (1 << 6) +#define INT_RXDR (1 << 5) +#define INT_TXDR (1 << 4) +#define INT_DTO (1 << 3) +#define INT_CMD_DONE (1 << 0) +#define TRAN_COMP (1 << 1) + +/* SRS09 */ +#define STATUS_DATA_BUSY BIT(2) + +/* SRS10 */ +/* LED Control + * State of this bit directly drives led port of the host + * in order to control the external LED diode + * Default value 0 << 1 + */ +#define LEDC BIT(0) +#define LEDC_OFF 0 << 1 + +/* Data Transfer Width + * Bit used to configure DAT bus width to 1 or 4 + * Default value 1 << 1 + */ +#define DT_WIDTH BIT(1) +#define DTW_4BIT 1 << 1 + +/* Extended Data Transfer Width + * This bit is to enable/disable 8-bit DAT bus width mode + * Default value 1 << 5 + */ +#define EDTW_8BIT 1 << 5 + +/* High Speed Enable + * Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1) + */ +#define HS_EN BIT(2) + +/* here 0 defines the 64 Kb size */ +#define MAX_64KB_PAGE 0 +#define EMMC_DESC_SIZE (1<<20) + +/* SRS11 */ +/* Software Reset For All + * When set to 1, the entire slot is reset + * After completing the reset operation, SRFA bit is automatically cleared + */ +#define SRFA BIT(24) + +/* Software Reset For CMD Line + * When set to 1, resets the logic related to the command generation and response checking + */ +#define SRCMD BIT(25) + +/* Software Reset For DAT Line + * When set to 1, resets the logic related to the data path, + * including data buffers and the DMA logic + */ +#define SRDAT BIT(26) + +/* SRS15 */ +/* UHS Mode Select + * Used to select one of UHS-I modes. + * • 000b - SDR12 + * • 001b - SDR25 + * • 010b - SDR50 + * • 011b - SDR104 + * • 100b - DDR50 + */ +#define SDR12_MODE 0 << 16 +#define SDR25_MODE 1 << 16 +#define SDR50_MODE 2 << 16 +#define SDR104_MODE 3 << 16 +#define DDR50_MODE 4 << 16 +/* 1.8V Signaling Enable + * • 0 - for Default Speed, High Speed mode + * • 1 - for UHS-I mode + */ +#define V18SE BIT(19) + +/* CMD23 Enable + * In result of Card Identification process, + * Host Driver set this bit to 1 if Card supports CMD23 + */ +#define CMD23_EN BIT(27) + +/* Host Version 4.00 Enable + * • 0 - Version 3.00 + * • 1 - Version 4.00 + */ +#define HV4E BIT(28) +/* Conf depends on SRS15.HV4E */ +#define SDMA 0 << 3 +#define ADMA2_32 2 << 3 +#define ADMA2_64 3 << 3 + +/* Preset Value Enable + * Setting this bit to 1 triggers an automatically update of SRS11 + */ +#define PVE BIT(31) + +#define BIT_AD_32 0 << 29 +#define BIT_AD_64 1 << 29 + +/* SW RESET REG*/ +#define SDHC_CDNS_HRS00 (0x00) +#define SDHC_CDNS_HRS00_SWR BIT(0) + +/* PHY access port */ +#define SDHC_CDNS_HRS04 0x10 +#define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0) + +/* PHY data access port */ +#define SDHC_CDNS_HRS05 0x14 + +/* eMMC control registers */ +#define SDHC_CDNS_HRS06 0x18 + +/* SRS */ +#define SDHC_CDNS_SRS_BASE 0x200 +#define SDHC_CDNS_SRS00 0x200 +#define SDHC_CDNS_SRS01 0x204 +#define SDHC_CDNS_SRS02 0x208 +#define SDHC_CDNS_SRS03 0x20c +#define SDHC_CDNS_SRS04 0x210 +#define SDHC_CDNS_SRS05 0x214 +#define SDHC_CDNS_SRS06 0x218 +#define SDHC_CDNS_SRS07 0x21C +#define SDHC_CDNS_SRS08 0x220 +#define SDHC_CDNS_SRS09 0x224 +#define SDHC_CDNS_SRS09_CI BIT(16) +#define SDHC_CDNS_SRS10 0x228 +#define SDHC_CDNS_SRS11 0x22C +#define SDHC_CDNS_SRS12 0x230 +#define SDHC_CDNS_SRS13 0x234 +#define SDHC_CDNS_SRS14 0x238 +#define SDHC_CDNS_SRS15 0x23c +#define SDHC_CDNS_SRS21 0x254 +#define SDHC_CDNS_SRS22 0x258 +#define SDHC_CDNS_SRS23 0x25c + +/* HRS07 */ +#define SDHC_CDNS_HRS07 0x1c +#define SDHC_IDELAY_VAL(x) ((x) << 0) +#define SDHC_RW_COMPENSATE(x) ((x) << 16) + +/* PHY reset port */ +#define SDHC_CDNS_HRS09 0x24 + +/* HRS10 */ +/* PHY reset port */ +#define SDHC_CDNS_HRS10 0x28 + +/* HCSDCLKADJ DATA; DDR Mode */ +#define SDHC_HCSDCLKADJ(x) ((x) << 16) + +/* Pinmux headers will reomove after ATF driver implementation */ +#define PINMUX_SDMMC_SEL 0x0 +#define PIN0SEL 0x00 +#define PIN1SEL 0x04 +#define PIN2SEL 0x08 +#define PIN3SEL 0x0C +#define PIN4SEL 0x10 +#define PIN5SEL 0x14 +#define PIN6SEL 0x18 +#define PIN7SEL 0x1C +#define PIN8SEL 0x20 +#define PIN9SEL 0x24 +#define PIN10SEL 0x28 + +/* HRS16 */ +#define SDHC_WRCMD0_DLY(x) ((x) << 0) +#define SDHC_WRCMD1_DLY(x) ((x) << 4) +#define SDHC_WRDATA0_DLY(x) ((x) << 8) +#define SDHC_WRDATA1_DLY(x) ((x) << 12) +#define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16) +#define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20) +#define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24) +#define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28) + +/* Shared Macros */ +#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ + (SDMMC_CDN_##_reg)) + +/* Refer to atf/tools/cert_create/include/debug.h */ +#define BIT_32(nr) (U(1) << (nr)) + +/* MMC Peripheral Definition */ +#define SOCFPGA_MMC_BLOCK_SIZE U(8192) +#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1)) +#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000) +#define MMC_RESPONSE_NONE 0 +#define SDHC_CDNS_SRS03_VALUE 0x01020013 + +/* Value randomly chosen for eMMC RCA, it should be > 1 */ +#define MMC_FIX_RCA 6 +#define RCA_SHIFT_OFFSET 16 + +#define CMD_EXTCSD_PARTITION_CONFIG 179 +#define CMD_EXTCSD_BUS_WIDTH 183 +#define CMD_EXTCSD_HS_TIMING 185 +#define CMD_EXTCSD_SEC_CNT 212 + +#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) +#define PART_CFG_PARTITION1_ACCESS (U(1) << 0) + +/* Values in EXT CSD register */ +#define MMC_BUS_WIDTH_1 U(0) +#define MMC_BUS_WIDTH_4 U(1) +#define MMC_BUS_WIDTH_8 U(2) +#define MMC_BUS_WIDTH_DDR_4 U(5) +#define MMC_BUS_WIDTH_DDR_8 U(6) +#define MMC_BOOT_MODE_BACKWARD (U(0) << 3) +#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) +#define MMC_BOOT_MODE_DDR (U(2) << 3) + +#define EXTCSD_SET_CMD (U(0) << 24) +#define EXTCSD_SET_BITS (U(1) << 24) +#define EXTCSD_CLR_BITS (U(2) << 24) +#define EXTCSD_WRITE_BYTES (U(3) << 24) +#define EXTCSD_CMD(x) (((x) & 0xff) << 16) +#define EXTCSD_VALUE(x) (((x) & 0xff) << 8) +#define EXTCSD_CMD_SET_NORMAL U(1) + +#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) +#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) +#define CSD_TRAN_SPEED_MULT_SHIFT 3 + +#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) +#define STATUS_READY_FOR_DATA BIT(8) +#define STATUS_SWITCH_ERROR BIT(7) +#define MMC_GET_STATE(x) (((x) >> 9) & 0xf) +#define MMC_STATE_IDLE 0 +#define MMC_STATE_READY 1 +#define MMC_STATE_IDENT 2 +#define MMC_STATE_STBY 3 +#define MMC_STATE_TRAN 4 +#define MMC_STATE_DATA 5 +#define MMC_STATE_RCV 6 +#define MMC_STATE_PRG 7 +#define MMC_STATE_DIS 8 +#define MMC_STATE_BTST 9 +#define MMC_STATE_SLP 10 + +#define MMC_FLAG_CMD23 (U(1) << 0) + +#define CMD8_CHECK_PATTERN U(0xAA) +#define VHS_2_7_3_6_V BIT(8) + +/*ADMA table component*/ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 + +enum sd_opcode { + SD_GO_IDLE_STATE = 0, + SD_ALL_SEND_CID = 2, + SD_SEND_RELATIVE_ADDR = 3, + SDIO_SEND_OP_COND = 5, /* SDIO cards only */ + SD_SWITCH = 6, + SD_SELECT_CARD = 7, + SD_SEND_IF_COND = 8, + SD_SEND_CSD = 9, + SD_SEND_CID = 10, + SD_VOL_SWITCH = 11, + SD_STOP_TRANSMISSION = 12, + SD_SEND_STATUS = 13, + SD_GO_INACTIVE_STATE = 15, + SD_SET_BLOCK_SIZE = 16, + SD_READ_SINGLE_BLOCK = 17, + SD_READ_MULTIPLE_BLOCK = 18, + SD_SEND_TUNING_BLOCK = 19, + SD_SET_BLOCK_COUNT = 23, + SD_WRITE_SINGLE_BLOCK = 24, + SD_WRITE_MULTIPLE_BLOCK = 25, + SD_ERASE_BLOCK_START = 32, + SD_ERASE_BLOCK_END = 33, + SD_ERASE_BLOCK_OPERATION = 38, + SD_APP_CMD = 55, + SD_SPI_READ_OCR = 58, /* SPI mode only */ + SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */ +}; + +enum sd_app_cmd { + SD_APP_SET_BUS_WIDTH = 6, + SD_APP_SEND_STATUS = 13, + SD_APP_SEND_NUM_WRITTEN_BLK = 22, + SD_APP_SET_WRITE_BLK_ERASE_CNT = 23, + SD_APP_SEND_OP_COND = 41, + SD_APP_CLEAR_CARD_DETECT = 42, + SD_APP_SEND_SCR = 51, +}; + +struct cdns_sdmmc_sdhc { + uint32_t sdhc_extended_rd_mode; + uint32_t sdhc_extended_wr_mode; + uint32_t sdhc_hcsdclkadj; + uint32_t sdhc_idelay_val; + uint32_t sdhc_rdcmd_en; + uint32_t sdhc_rddata_en; + uint32_t sdhc_rw_compensate; + uint32_t sdhc_sdcfsh; + uint32_t sdhc_sdcfsl; + uint32_t sdhc_wrcmd0_dly; + uint32_t sdhc_wrcmd0_sdclk_dly; + uint32_t sdhc_wrcmd1_dly; + uint32_t sdhc_wrcmd1_sdclk_dly; + uint32_t sdhc_wrdata0_dly; + uint32_t sdhc_wrdata0_sdclk_dly; + uint32_t sdhc_wrdata1_dly; + uint32_t sdhc_wrdata1_sdclk_dly; +}; + +enum sdmmc_device_mode { + SD_DS_ID, /* Identification */ + SD_DS, /* Default speed */ + SD_HS, /* High speed */ + SD_UHS_SDR12, /* Ultra high speed SDR12 */ + SD_UHS_SDR25, /* Ultra high speed SDR25 */ + SD_UHS_SDR50, /* Ultra high speed SDR`50 */ + SD_UHS_SDR104, /* Ultra high speed SDR104 */ + SD_UHS_DDR50, /* Ultra high speed DDR50 */ + EMMC_SDR_BC, /* SDR backward compatible */ + EMMC_SDR, /* SDR */ + EMMC_DDR, /* DDR */ + EMMC_HS200, /* High speed 200Mhz in SDR */ + EMMC_HS400, /* High speed 200Mhz in DDR */ + EMMC_HS400es, /* High speed 200Mhz in SDR with enhanced strobe*/ +}; + +struct cdns_sdmmc_params { + uintptr_t reg_base; + uintptr_t reg_pinmux; + uintptr_t reg_phy; + uintptr_t desc_base; + size_t desc_size; + int clk_rate; + int bus_width; + unsigned int flags; + enum sdmmc_device_mode cdn_sdmmc_dev_mode; + enum mmc_device_type cdn_sdmmc_dev_type; + uint32_t combophy; +}; + +/* read and write API */ +size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size); +size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size); + +struct cdns_idmac_desc { + /*8 bit attribute*/ + uint8_t attr; + /*reserved bits in desc*/ + uint8_t reserved; + /*page length for the descriptor*/ + uint16_t len; + /*lower 32 bits for buffer (64 bit addressing)*/ + uint32_t addr_lo; +#if CONFIG_DMA_ADDR_T_64BIT == 1 + /*higher 32 bits for buffer (64 bit addressing)*/ + uint32_t addr_hi; +} __aligned(8); +#else +} __packed; +#endif + + + +/* Function Prototype */ +int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg, +struct cdns_sdmmc_sdhc *mmc_sdhc_reg); +void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg, +struct cdns_sdmmc_sdhc *sdhc_reg); +#endif diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h index 30ca910b92..327c1d9ba6 100644 --- a/include/drivers/cadence/cdns_uart.h +++ b/include/drivers/cadence/cdns_uart.h @@ -22,6 +22,7 @@ #define UART_SR_INTR_REMPTY_BIT 1 #define UART_SR_INTR_TFUL_BIT 4 #define UART_SR_INTR_TEMPTY_BIT 3 +#define UART_SR_INTR_TACTIVE_BIT 11 #define R_UART_TX 0x30 #define R_UART_RX 0x30 diff --git a/include/drivers/clk.h b/include/drivers/clk.h new file mode 100644 index 0000000000..a18f41ffca --- /dev/null +++ b/include/drivers/clk.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CLK_H +#define CLK_H + +#include <stdbool.h> + +struct clk_ops { + int (*enable)(unsigned long id); + void (*disable)(unsigned long id); + unsigned long (*get_rate)(unsigned long id); + int (*get_parent)(unsigned long id); + bool (*is_enabled)(unsigned long id); +}; + +int clk_enable(unsigned long id); +void clk_disable(unsigned long id); +unsigned long clk_get_rate(unsigned long id); +bool clk_is_enabled(unsigned long id); +int clk_get_parent(unsigned long id); + +void clk_register(const struct clk_ops *ops); + +#endif /* CLK_H */ diff --git a/include/drivers/console.h b/include/drivers/console.h index 99bf960418..fa4eb9462d 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,10 +12,16 @@ #define CONSOLE_T_NEXT (U(0) * REGSZ) #define CONSOLE_T_FLAGS (U(1) * REGSZ) #define CONSOLE_T_PUTC (U(2) * REGSZ) +#if ENABLE_CONSOLE_GETC #define CONSOLE_T_GETC (U(3) * REGSZ) #define CONSOLE_T_FLUSH (U(4) * REGSZ) #define CONSOLE_T_BASE (U(5) * REGSZ) #define CONSOLE_T_DRVDATA (U(6) * REGSZ) +#else +#define CONSOLE_T_FLUSH (U(3) * REGSZ) +#define CONSOLE_T_BASE (U(4) * REGSZ) +#define CONSOLE_T_DRVDATA (U(5) * REGSZ) +#endif #define CONSOLE_FLAG_BOOT (U(1) << 0) #define CONSOLE_FLAG_RUNTIME (U(1) << 1) @@ -42,12 +48,16 @@ typedef struct console { */ u_register_t flags; int (*const putc)(int character, struct console *console); +#if ENABLE_CONSOLE_GETC int (*const getc)(struct console *console); +#endif void (*const flush)(struct console *console); uintptr_t base; /* Additional private driver data may follow here. */ } console_t; +extern console_t *console_list; + /* offset macro assertions for console_t */ #include <drivers/console_assertions.h> @@ -73,8 +83,10 @@ void console_set_scope(console_t *console, unsigned int scope); void console_switch_state(unsigned int new_state); /* Output a character on all consoles registered for the current state. */ int console_putc(int c); +#if ENABLE_CONSOLE_GETC /* Read a character (blocking) from any console registered for current state. */ int console_getc(void); +#endif /* Flush all consoles registered for the current state. */ void console_flush(void); diff --git a/include/drivers/console_assertions.h b/include/drivers/console_assertions.h index 00caa31416..9f0657326d 100644 --- a/include/drivers/console_assertions.h +++ b/include/drivers/console_assertions.h @@ -19,8 +19,10 @@ CASSERT(CONSOLE_T_FLAGS == __builtin_offsetof(console_t, flags), assert_console_t_flags_offset_mismatch); CASSERT(CONSOLE_T_PUTC == __builtin_offsetof(console_t, putc), assert_console_t_putc_offset_mismatch); +#if ENABLE_CONSOLE_GETC CASSERT(CONSOLE_T_GETC == __builtin_offsetof(console_t, getc), assert_console_t_getc_offset_mismatch); +#endif CASSERT(CONSOLE_T_FLUSH == __builtin_offsetof(console_t, flush), assert_console_t_flush_offset_mismatch); CASSERT(CONSOLE_T_DRVDATA == sizeof(console_t), diff --git a/include/drivers/fwu/fwu.h b/include/drivers/fwu/fwu.h new file mode 100644 index 0000000000..18e8a31633 --- /dev/null +++ b/include/drivers/fwu/fwu.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FWU_H +#define FWU_H + +#include <stdbool.h> + +#define FWU_BANK_STATE_ACCEPTED 0xFCU +#define FWU_BANK_STATE_VALID 0xFEU +#define FWU_BANK_STATE_INVALID 0xFFU + +#define INVALID_BOOT_IDX 0xFFFFFFFFU + +void fwu_init(void); +uint32_t fwu_get_active_bank_state(void); +uint32_t fwu_get_alternate_boot_bank(void); +const struct fwu_metadata *fwu_get_metadata(void); + +#endif /* FWU_H */ diff --git a/include/drivers/fwu/fwu_metadata.h b/include/drivers/fwu/fwu_metadata.h new file mode 100644 index 0000000000..b441300e41 --- /dev/null +++ b/include/drivers/fwu/fwu_metadata.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * FWU metadata information as per the specification section 4.1: + * https://developer.arm.com/documentation/den0118/latest/ + * + */ + +#ifndef FWU_METADATA_H +#define FWU_METADATA_H + +#include <stdint.h> +#include <tools_share/uuid.h> + +#define NR_OF_MAX_FW_BANKS 4 + +/* Properties of image in a bank */ +struct fwu_image_bank_info { + + /* GUID of the image in this bank */ + struct efi_guid img_guid; + + /* [0]: bit describing the image acceptance status – + * 1 means the image is accepted + * [31:1]: MBZ + */ + uint32_t accepted; + + /* reserved (MBZ) */ + uint32_t reserved; + +} __packed; + +/* Image entry information */ +struct fwu_image_entry { + + /* GUID identifying the image type */ + struct efi_guid img_type_guid; + + /* GUID of the storage volume where the image is located */ + struct efi_guid location_guid; + + /* Properties of images with img_type_guid in the different FW banks */ + struct fwu_image_bank_info img_bank_info[NR_OF_FW_BANKS]; + +} __packed; + +/* Firmware Image descriptor */ +struct fwu_fw_store_descriptor { + + /* Number of Banks */ + uint8_t num_banks; + + /* Reserved */ + uint8_t reserved; + + /* Number of images per bank */ + uint16_t num_images; + + /* Size of image_entry(all banks) in bytes */ + uint16_t img_entry_size; + + /* Size of image bank info structure in bytes */ + uint16_t bank_info_entry_size; + + /* Array of fwu_image_entry structs */ + struct fwu_image_entry img_entry[NR_OF_IMAGES_IN_FW_BANK]; + +} __packed; + +/* + * FWU metadata filled by the updater and consumed by TF-A for + * various purposes as below: + * 1. Get active FW bank. + * 2. Rollback to previous working FW bank. + * 3. Get properties of all images present in all banks. + */ +struct fwu_metadata { + + /* Metadata CRC value */ + uint32_t crc_32; + + /* Metadata version */ + uint32_t version; + + /* Bank index with which device boots */ + uint32_t active_index; + + /* Previous bank index with which device booted successfully */ + uint32_t previous_active_index; + + /* Size of the entire metadata in bytes */ + uint32_t metadata_size; + + /* Offset of the image descriptor structure */ + uint16_t desc_offset; + + /* Reserved */ + uint16_t reserved1; + + /* Bank state */ + uint8_t bank_state[NR_OF_MAX_FW_BANKS]; + + /* Reserved */ + uint32_t reserved2; + +#if PSA_FWU_METADATA_FW_STORE_DESC + /* Image entry information */ + struct fwu_fw_store_descriptor fw_desc; +#endif + +} __packed; + +#endif /* FWU_METADATA_H */ diff --git a/include/drivers/gpio.h b/include/drivers/gpio.h index 99c18a4bb5..9bba993c61 100644 --- a/include/drivers/gpio.h +++ b/include/drivers/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,7 @@ #define GPIO_PULL_NONE ARM_TF_GPIO_PULL_NONE #define GPIO_PULL_UP ARM_TF_GPIO_PULL_UP #define GPIO_PULL_DOWN ARM_TF_GPIO_PULL_DOWN +#define GPIO_PULL_REPEATER ARM_TF_GPIO_PULL_REPEATER typedef struct gpio_ops { int (*get_direction)(int gpio); diff --git a/include/drivers/io/io_dummy.h b/include/drivers/io/io_dummy.h deleted file mode 100644 index edfc6993e4..0000000000 --- a/include/drivers/io/io_dummy.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef IO_DUMMY_H -#define IO_DUMMY_H - -int register_io_dev_dummy(const struct io_dev_connector **dev_con); - -#endif /* IO_DUMMY_H */ diff --git a/include/drivers/io/io_mtd.h b/include/drivers/io/io_mtd.h index 1395ff6019..2b5d9b1017 100644 --- a/include/drivers/io/io_mtd.h +++ b/include/drivers/io/io_mtd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,11 +44,22 @@ typedef struct io_mtd_ops { * Return 0 on success, a negative error code otherwise. */ int (*write)(unsigned int offset, uintptr_t buffer, size_t length); + + /* + * Look for an offset to be added to the given offset. + * + * @base: Base address of the area. + * @offset: Offset in bytes to start read operation. + * @extra_offset: [out] Offset to be added to the previous offset. + * Return 0 on success, a negative error code otherwise. + */ + int (*seek)(uintptr_t base, unsigned int offset, size_t *extra_offset); } io_mtd_ops_t; typedef struct io_mtd_dev_spec { unsigned long long device_size; unsigned int erase_size; + size_t offset; io_mtd_ops_t ops; } io_mtd_dev_spec_t; diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h index f2d641c2d0..31793832d0 100644 --- a/include/drivers/io/io_storage.h +++ b/include/drivers/io/io_storage.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,12 +19,10 @@ typedef enum { IO_TYPE_INVALID, IO_TYPE_SEMIHOSTING, IO_TYPE_MEMMAP, - IO_TYPE_DUMMY, IO_TYPE_FIRMWARE_IMAGE_PACKAGE, IO_TYPE_BLOCK, IO_TYPE_MTD, IO_TYPE_MMC, - IO_TYPE_STM32IMAGE, IO_TYPE_ENCRYPTED, IO_TYPE_MAX } io_type_t; diff --git a/include/drivers/marvell/uart/a3700_console.h b/include/drivers/marvell/uart/a3700_console.h index 12d2cdc523..ce673a138f 100644 --- a/include/drivers/marvell/uart/a3700_console.h +++ b/include/drivers/marvell/uart/a3700_console.h @@ -9,6 +9,7 @@ #define A3700_CONSOLE_H #include <drivers/console.h> +#include <platform_def.h> /* MVEBU UART Registers */ #define UART_RX_REG 0x00 diff --git a/include/drivers/measured_boot/event_log.h b/include/drivers/measured_boot/event_log/event_log.h index efde117626..b44526aa48 100644 --- a/include/drivers/measured_boot/event_log.h +++ b/include/drivers/measured_boot/event_log/event_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,9 @@ #include <stdint.h> #include <common/debug.h> -#include <drivers/measured_boot/tcg.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/auth/crypto_mod.h> +#include <drivers/measured_boot/event_log/tcg.h> /* * Set Event Log debug level to one of: @@ -35,42 +37,17 @@ #endif /* Number of hashing algorithms supported */ -#define HASH_ALG_COUNT 1U +#define HASH_ALG_COUNT 1U -#define INVALID_ID MAX_NUMBER_IDS +#define EVLOG_INVALID_ID UINT32_MAX #define MEMBER_SIZE(type, member) sizeof(((type *)0)->member) -#define BL2_STRING "BL_2" -#define BL31_STRING "BL_31" -#define BL32_STRING "BL_32" -#define BL32_EXTRA1_IMAGE_STRING "BL32_EXTRA1_IMAGE" -#define BL32_EXTRA2_IMAGE_STRING "BL32_EXTRA2_IMAGE" -#define BL33_STRING "BL_33" -#define GPT_IMAGE_STRING "GPT" -#define HW_CONFIG_STRING "HW_CONFIG" -#define NT_FW_CONFIG_STRING "NT_FW_CONFIG" -#define SCP_BL2_IMAGE_STRING "SCP_BL2_IMAGE" -#define SOC_FW_CONFIG_STRING "SOC_FW_CONFIG" -#define STM32_IMAGE_STRING "STM32" -#define TOS_FW_CONFIG_STRING "TOS_FW_CONFIG" - typedef struct { unsigned int id; const char *name; unsigned int pcr; -} image_data_t; - -typedef struct { - const image_data_t *images_data; - int (*set_nt_fw_info)(uintptr_t config_base, -#ifdef SPD_opteed - uintptr_t log_addr, -#endif - size_t log_size, uintptr_t *ns_log_addr); - int (*set_tos_fw_info)(uintptr_t config_base, uintptr_t log_addr, - size_t log_size); -} measured_boot_data_t; +} event_log_metadata_t; #define ID_EVENT_SIZE (sizeof(id_event_headers_t) + \ (sizeof(id_event_algorithm_size_t) * HASH_ALG_COUNT) + \ @@ -88,10 +65,18 @@ typedef struct { sizeof(event2_data_t)) /* Functions' declarations */ -void event_log_init(void); -int event_log_finalise(uint8_t **log_addr, size_t *log_size); +void event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish); +void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish); +void event_log_write_specid_event(void); +void event_log_write_header(void); void dump_event_log(uint8_t *log_addr, size_t log_size); -const measured_boot_data_t *plat_get_measured_boot_data(void); -int tpm_record_measurement(uintptr_t data_base, uint32_t data_size, - uint32_t data_id); +int event_log_measure(uintptr_t data_base, uint32_t data_size, + unsigned char hash_data[CRYPTO_MD_MAX_SIZE]); +void event_log_record(const uint8_t *hash, uint32_t event_type, + const event_log_metadata_t *metadata_ptr); +int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size, + uint32_t data_id, + const event_log_metadata_t *metadata_ptr); +size_t event_log_get_cur_size(uint8_t *event_log_start); + #endif /* EVENT_LOG_H */ diff --git a/include/drivers/measured_boot/tcg.h b/include/drivers/measured_boot/event_log/tcg.h index ab27a0844f..4ac2c2ff3b 100644 --- a/include/drivers/measured_boot/tcg.h +++ b/include/drivers/measured_boot/event_log/tcg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -98,7 +98,12 @@ enum { /* 8-15: Defined for use by the Static OS */ PCR_8, /* Debug */ - PCR_16 = 16 + PCR_16 = 16, + + /* D-CRTM-measurements by DRTM implementation */ + PCR_17 = 17, + /* DCE measurements by DRTM implementation */ + PCR_18 = 18 }; #pragma pack(push, 1) diff --git a/include/drivers/measured_boot/measured_boot.h b/include/drivers/measured_boot/measured_boot.h deleted file mode 100644 index f8769ab43c..0000000000 --- a/include/drivers/measured_boot/measured_boot.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef MEASURED_BOOT_H -#define MEASURED_BOOT_H - -#include <stdint.h> - -#include <drivers/measured_boot/event_log.h> - -/* Platform specific table of image IDs, names and PCRs */ -extern const image_data_t images_data[]; - -/* Functions' declarations */ -void measured_boot_init(void); -void measured_boot_finish(void); - -#endif /* MEASURED_BOOT_H */ diff --git a/include/drivers/measured_boot/metadata.h b/include/drivers/measured_boot/metadata.h new file mode 100644 index 0000000000..5e17a8350e --- /dev/null +++ b/include/drivers/measured_boot/metadata.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef METADATA_H +#define METADATA_H + +/* Minimum measurement value size that can be requested to store */ +#define MEASUREMENT_VALUE_MIN_SIZE 32U +/* Maximum measurement value size that can be requested to store */ +#define MEASUREMENT_VALUE_MAX_SIZE 64U +/* Minimum signer id size that can be requested to store */ +#define SIGNER_ID_MIN_SIZE MEASUREMENT_VALUE_MIN_SIZE +/* Maximum signer id size that can be requested to store */ +#define SIGNER_ID_MAX_SIZE MEASUREMENT_VALUE_MAX_SIZE +/* The theoretical maximum image version is: "255.255.65535\0" */ +#define VERSION_MAX_SIZE 14U +/* Example sw_type: "BL_2, BL_33, etc." */ +#define SW_TYPE_MAX_SIZE 32U + +/* + * Images, measured during the boot process, have some associated metadata. + * One of these types of metadata is the image identifier strings. These macros + * define these strings. They are used across the different measured boot + * backends. + * Note that these strings follow the standardization recommendations + * defined in the Arm Server Base Security Guide (a.k.a. SBSG, Arm DEN 0086), + * where applicable. They should not be changed in the code. + * Where the SBSG does not make recommendations, we are free to choose any + * naming convention. + * The key thing is to choose meaningful strings so that when the measured boot + * metadata is used in attestation, the different components can be identified. + */ +#define MBOOT_BL2_IMAGE_STRING "BL_2" +#define MBOOT_BL31_IMAGE_STRING "SECURE_RT_EL3" +#if defined(SPD_opteed) +#define MBOOT_BL32_IMAGE_STRING "SECURE_RT_EL1_OPTEE" +#elif defined(SPD_tspd) +#define MBOOT_BL32_IMAGE_STRING "SECURE_RT_EL1_TSPD" +#elif defined(SPD_tlkd) +#define MBOOT_BL32_IMAGE_STRING "SECURE_RT_EL1_TLKD" +#elif defined(SPD_trusty) +#define MBOOT_BL32_IMAGE_STRING "SECURE_RT_EL1_TRUSTY" +#elif defined(SPD_spmd) +#define MBOOT_BL32_IMAGE_STRING "SECURE_RT_EL1_SPMD" +#else +#define MBOOT_BL32_IMAGE_STRING "SECURE_RT_EL1_UNKNOWN" +#endif /* SPD_opteed */ +#define MBOOT_BL32_EXTRA1_IMAGE_STRING "SECURE_RT_EL1_OPTEE_EXTRA1" +#define MBOOT_BL32_EXTRA2_IMAGE_STRING "SECURE_RT_EL1_OPTEE_EXTRA2" +#define MBOOT_BL33_IMAGE_STRING "BL_33" +#define MBOOT_FW_CONFIG_STRING "FW_CONFIG" +#define MBOOT_HW_CONFIG_STRING "HW_CONFIG" +#define MBOOT_NT_FW_CONFIG_STRING "NT_FW_CONFIG" +#define MBOOT_SCP_BL2_IMAGE_STRING "SYS_CTRL_2" +#define MBOOT_SOC_FW_CONFIG_STRING "SOC_FW_CONFIG" +#define MBOOT_STM32_STRING "STM32" +#define MBOOT_TB_FW_CONFIG_STRING "TB_FW_CONFIG" +#define MBOOT_TOS_FW_CONFIG_STRING "TOS_FW_CONFIG" +#define MBOOT_RMM_IMAGE_STRING "RMM" +#define MBOOT_SP1_STRING "SP1" +#define MBOOT_SP2_STRING "SP2" +#define MBOOT_SP3_STRING "SP3" +#define MBOOT_SP4_STRING "SP4" +#define MBOOT_SP5_STRING "SP5" +#define MBOOT_SP6_STRING "SP6" +#define MBOOT_SP7_STRING "SP7" +#define MBOOT_SP8_STRING "SP8" + +#endif /* METADATA_H */ diff --git a/include/drivers/measured_boot/rss/dice_prot_env.h b/include/drivers/measured_boot/rss/dice_prot_env.h new file mode 100644 index 0000000000..6f754f548d --- /dev/null +++ b/include/drivers/measured_boot/rss/dice_prot_env.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DICE_PROT_ENV_H +#define DICE_PROT_ENV_H + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#include <drivers/measured_boot/metadata.h> + +#define DPE_INVALID_ID UINT32_MAX + +struct dpe_metadata { + unsigned int id; + uint32_t cert_id; + uint8_t signer_id[SIGNER_ID_MAX_SIZE]; + size_t signer_id_size; + uint8_t version[VERSION_MAX_SIZE]; + size_t version_size; + uint8_t sw_type[SW_TYPE_MAX_SIZE]; + size_t sw_type_size; + bool allow_new_context_to_derive; + bool retain_parent_context; + bool create_certificate; + void *pk_oid; +}; + +void dpe_init(struct dpe_metadata *metadata); + +/* Returns 0 in case of success otherwise -1. */ +int dpe_measure_and_record(struct dpe_metadata *metadata, + uintptr_t data_base, uint32_t data_size, + uint32_t data_id); + +int dpe_set_signer_id(struct dpe_metadata *metadata, + const void *pk_oid, const void *pk_ptr, size_t pk_len); + +/* Child components inherit their first valid context handle from their parents. + * How to share context handle is platform specific. + */ +void plat_dpe_share_context_handle(int *ctx_handle); +void plat_dpe_get_context_handle(int *ctx_handle); + +#endif /* DICE_PROT_ENV_H */ diff --git a/include/drivers/measured_boot/rss/rss_measured_boot.h b/include/drivers/measured_boot/rss/rss_measured_boot.h new file mode 100644 index 0000000000..38f7d4e346 --- /dev/null +++ b/include/drivers/measured_boot/rss/rss_measured_boot.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RSS_MEASURED_BOOT_H +#define RSS_MEASURED_BOOT_H + +#include <stdint.h> + +#include <common/debug.h> +#include <drivers/measured_boot/metadata.h> + +#define RSS_MBOOT_INVALID_ID UINT32_MAX + +struct rss_mboot_metadata { + unsigned int id; + uint8_t slot; + uint8_t signer_id[SIGNER_ID_MAX_SIZE]; + size_t signer_id_size; + uint8_t version[VERSION_MAX_SIZE]; + size_t version_size; + uint8_t sw_type[SW_TYPE_MAX_SIZE]; + size_t sw_type_size; + void *pk_oid; + bool lock_measurement; +}; + +/* Functions' declarations */ +void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr); +int rss_mboot_measure_and_record(struct rss_mboot_metadata *metadata_ptr, + uintptr_t data_base, uint32_t data_size, + uint32_t data_id); + +int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr, + const void *pk_oid, const void *pk_ptr, + size_t pk_len); + +#endif /* RSS_MEASURED_BOOT_H */ diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h index 834a80f4ac..e94693dd73 100644 --- a/include/drivers/mmc.h +++ b/include/drivers/mmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,10 +62,12 @@ #define CMD_EXTCSD_HS_TIMING 185 #define CMD_EXTCSD_PART_SWITCH_TIME 199 #define CMD_EXTCSD_SEC_CNT 212 +#define CMD_EXTCSD_BOOT_SIZE_MULT 226 #define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0) #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) #define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0) +#define PART_CFG_BOOT_PARTITION_NO_ACCESS U(0) #define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3) #define PART_CFG_BOOT_PART_EN_SHIFT 3 #define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \ @@ -110,6 +112,7 @@ #define MMC_STATE_SLP 10 #define MMC_FLAG_CMD23 (U(1) << 0) +#define MMC_FLAG_SD_CMD6 (U(1) << 1) #define CMD8_CHECK_PATTERN U(0xAA) #define VHS_2_7_3_6_V BIT(8) @@ -117,6 +120,10 @@ #define SD_SCR_BUS_WIDTH_1 BIT(8) #define SD_SCR_BUS_WIDTH_4 BIT(10) +#define SD_SWITCH_FUNC_CHECK 0U +#define SD_SWITCH_FUNC_SWITCH BIT(31) +#define SD_SWITCH_ALL_GROUPS_MASK GENMASK(23, 0) + struct mmc_cmd { unsigned int cmd_idx; unsigned int cmd_arg; @@ -216,6 +223,27 @@ struct mmc_csd_sd_v2 { unsigned int csd_structure: 2; }; +struct sd_switch_status { + unsigned short max_current; + unsigned short support_g6; + unsigned short support_g5; + unsigned short support_g4; + unsigned short support_g3; + unsigned short support_g2; + unsigned short support_g1; + unsigned char sel_g6_g5; + unsigned char sel_g4_g3; + unsigned char sel_g2_g1; + unsigned char data_struct_ver; + unsigned short busy_g6; + unsigned short busy_g5; + unsigned short busy_g4; + unsigned short busy_g3; + unsigned short busy_g2; + unsigned short busy_g1; + unsigned short reserved[17]; +}; + enum mmc_device_type { MMC_IS_EMMC, MMC_IS_SD, @@ -233,9 +261,9 @@ struct mmc_device_info { size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size); size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size); size_t mmc_erase_blocks(int lba, size_t size); -size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size); -size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size); -size_t mmc_rpmb_erase_blocks(int lba, size_t size); +int mmc_part_switch_current_boot(void); +int mmc_part_switch_user(void); +size_t mmc_boot_part_size(void); size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size); int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, unsigned int width, unsigned int flags, diff --git a/include/drivers/nand.h b/include/drivers/nand.h index 1dbb008f9c..5e5607c648 100644 --- a/include/drivers/nand.h +++ b/include/drivers/nand.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,6 +33,8 @@ struct nand_device { uintptr_t buffer); }; +void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size); + /* * Read bytes from NAND device * @@ -46,6 +48,16 @@ int nand_read(unsigned int offset, uintptr_t buffer, size_t length, size_t *length_read); /* + * Look for an extra offset to be added in case of bad blocks + * + * @base: Base address of the area + * @offset: Byte offset to read from in device + * @extra_offset: [out] Extra offset to be added if bad blocks are found + * Return: 0 on success, a negative errno on failure + */ +int nand_seek_bb(uintptr_t base, unsigned int offset, size_t *extra_offset); + +/* * Get NAND device instance * * Return: NAND device instance reference diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_clock.h b/include/drivers/nuvoton/npcm845x/npcm845x_clock.h new file mode 100644 index 0000000000..3c457d7a6d --- /dev/null +++ b/include/drivers/nuvoton/npcm845x/npcm845x_clock.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __ARBEL_CLOCK_H_ +#define __ARBEL_CLOCK_H_ + +struct clk_ctl { + unsigned int clken1; + unsigned int clksel; + unsigned int clkdiv1; + unsigned int pllcon0; + unsigned int pllcon1; + unsigned int swrstr; + unsigned char res1[0x8]; + unsigned int ipsrst1; + unsigned int ipsrst2; + unsigned int clken2; + unsigned int clkdiv2; + unsigned int clken3; + unsigned int ipsrst3; + unsigned int wd0rcr; + unsigned int wd1rcr; + unsigned int wd2rcr; + unsigned int swrstc1; + unsigned int swrstc2; + unsigned int swrstc3; + unsigned int tiprstc; + unsigned int pllcon2; + unsigned int clkdiv3; + unsigned int corstc; + unsigned int pllcong; + unsigned int ahbckfi; + unsigned int seccnt; + unsigned int cntr25m; + unsigned int clken4; + unsigned int ipsrst4; + unsigned int busto; + unsigned int clkdiv4; + unsigned int wd0rcrb; + unsigned int wd1rcrb; + unsigned int wd2rcrb; + unsigned int swrstc1b; + unsigned int swrstc2b; + unsigned int swrstc3b; + unsigned int tiprstcb; + unsigned int corstcb; + unsigned int ipsrstdis1; + unsigned int ipsrstdis2; + unsigned int ipsrstdis3; + unsigned int ipsrstdis4; + unsigned char res2[0x10]; + unsigned int thrtl_cnt; +}; + +#endif /* __ARBEL_CLOCK_H_ */ diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h b/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h new file mode 100644 index 0000000000..b9f3048cdf --- /dev/null +++ b/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2022-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __NPCM845x_GCR_H_ +#define __NPCM845x_GCR_H_ + +struct npcm845x_gcr { + unsigned int pdid; + unsigned int pwron; + unsigned int swstrps; + unsigned int rsvd1[2]; + unsigned int miscpe; + unsigned int spldcnt; + unsigned int rsvd2[1]; + unsigned int flockr2; + unsigned int flockr3; + unsigned int rsvd3[3]; + unsigned int a35_mode; + unsigned int spswc; + unsigned int intcr; + unsigned int intsr; + unsigned int obscr1; + unsigned int obsdr1; + unsigned int rsvd4[1]; + unsigned int hifcr; + unsigned int rsvd5[3]; + unsigned int intcr2; + unsigned int rsvd6[1]; + unsigned int srcnt; + unsigned int ressr; + unsigned int rlockr1; + unsigned int flockr1; + unsigned int dscnt; + unsigned int mdlr; + unsigned int scrpad_c; + unsigned int scrpad_b; + unsigned int rsvd7[4]; + unsigned int daclvlr; + unsigned int intcr3; + unsigned int pcirctl; + unsigned int rsvd8[2]; + unsigned int vsintr; + unsigned int rsvd9[1]; + unsigned int sd2sur1; + unsigned int sd2sur2; + unsigned int sd2irv3; + unsigned int intcr4; + unsigned int obscr2; + unsigned int obsdr2; + unsigned int rsvd10[5]; + unsigned int i2csegsel; + unsigned int i2csegctl; + unsigned int vsrcr; + unsigned int mlockr; + unsigned int rsvd11[8]; + unsigned int etsr; + unsigned int dft1r; + unsigned int dft2r; + unsigned int dft3r; + unsigned int edffsr; + unsigned int rsvd12[1]; + unsigned int intcrpce3; + unsigned int intcrpce2; + unsigned int intcrpce0; + unsigned int intcrpce1; + unsigned int dactest; + unsigned int scrpad; + unsigned int usb1phyctl; + unsigned int usb2phyctl; + unsigned int usb3phyctl; + unsigned int intsr2; + unsigned int intcrpce2b; + unsigned int intcrpce0b; + unsigned int intcrpce1b; + unsigned int intcrpce3b; + unsigned int rsvd13[4]; + unsigned int intcrpce2c; + unsigned int intcrpce0c; + unsigned int intcrpce1c; + unsigned int intcrpce3c; + unsigned int rsvd14[40]; + unsigned int sd2irv4; + unsigned int sd2irv5; + unsigned int sd2irv6; + unsigned int sd2irv7; + unsigned int sd2irv8; + unsigned int sd2irv9; + unsigned int sd2irv10; + unsigned int sd2irv11; + unsigned int rsvd15[8]; + unsigned int mfsel1; + unsigned int mfsel2; + unsigned int mfsel3; + unsigned int mfsel4; + unsigned int mfsel5; + unsigned int mfsel6; + unsigned int mfsel7; + unsigned int rsvd16[1]; + unsigned int mfsel_lk1; + unsigned int mfsel_lk2; + unsigned int mfsel_lk3; + unsigned int mfsel_lk4; + unsigned int mfsel_lk5; + unsigned int mfsel_lk6; + unsigned int mfsel_lk7; + unsigned int rsvd17[1]; + unsigned int mfsel_set1; + unsigned int mfsel_set2; + unsigned int mfsel_set3; + unsigned int mfsel_set4; + unsigned int mfsel_set5; + unsigned int mfsel_set6; + unsigned int mfsel_set7; + unsigned int rsvd18[1]; + unsigned int mfsel_clr1; + unsigned int mfsel_clr2; + unsigned int mfsel_clr3; + unsigned int mfsel_clr4; + unsigned int mfsel_clr5; + unsigned int mfsel_clr6; + unsigned int mfsel_clr7; +}; + +#endif diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h b/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h new file mode 100644 index 0000000000..8962b904bb --- /dev/null +++ b/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (C) 2022-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +#ifndef __ASSEMBLY__ + +struct npcmX50_uart { + union { + unsigned int rbr; + unsigned int thr; + unsigned int dll; + }; + union { + unsigned int ier; + unsigned int dlm; + }; + union { + unsigned int iir; + unsigned int fcr; + }; + unsigned int lcr; + unsigned int mcr; + unsigned int lsr; + unsigned int msr; + unsigned int tor; +}; + +typedef enum { + /* + * UART0 is a general UART block without modem-I/O-control + * connection to external signals. + */ + UART0_DEV = 0, + /* + * UART1-3 are each a general UART with modem-I/O-control + * connection to external signals. + */ + UART1_DEV, + UART2_DEV, + UART3_DEV, +} UART_DEV_T; + +typedef enum { + /* + * 0 0 0: Mode 1: + * HSP1 connected to SI2, + * HSP2 connected to UART2, + * UART1 snoops HSP1, + * UART3 snoops SI2 + */ + UART_MUX_MODE1 = 0, + /* + * 0 0 1: Mode 2: + * HSP1 connected to UART1, + * HSP2 connected to SI2, + * UART2 snoops HSP2, + * UART3 snoops SI2 + */ + UART_MUX_MODE2, + /* + * 0 1 0: Mode 3: + * HSP1 connected to UART1, + * HSP2 connected to UART2, + * UART3 connected to SI2 + */ + UART_MUX_MODE3, + /* + * 0 1 1: Mode 4: + * HSP1 connected to SI1, + * HSP2 connected to SI2, + * UART1 snoops SI1, + * UART3 snoops SI2, + * UART2 snoops HSP1 (default) + */ + UART_MUX_MODE4, + /* + * 1 0 0: Mode 5: + * HSP1 connected to SI1, + * HSP2 connected to UART2, + * UART1 snoops HSP1, + * UART3 snoops SI1 + */ + UART_MUX_MODE5, + /* + * 1 0 1: Mode 6: + * HSP1 connected to SI1, + * HSP2 connected to SI2, + * UART1 snoops SI1, + * UART3 snoops SI2, + * UART2 snoops HSP2 + */ + UART_MUX_MODE6, + /* + * 1 1 0: Mode 7: + * HSP1 connected to SI1, + * HSP2 connected to UART2, + * UART1 snoops HSP1, + * UART3 connected to SI2 + */ + UART_MUX_MODE7, + /* Skip UART mode configuration. */ + UART_MUX_RESERVED, + /* + * A SW option to allow config of UART + * without touching the UART mux. + */ + UART_MUX_SKIP_CONFIG +} UART_MUX_T; + +/*---------------------------------------------------------------------------*/ +/* Common baudrate definitions */ +/*---------------------------------------------------------------------------*/ +typedef enum { + UART_BAUDRATE_110 = 110, + UART_BAUDRATE_300 = 300, + UART_BAUDRATE_600 = 600, + UART_BAUDRATE_1200 = 1200, + UART_BAUDRATE_2400 = 2400, + UART_BAUDRATE_4800 = 4800, + UART_BAUDRATE_9600 = 9600, + UART_BAUDRATE_14400 = 14400, + UART_BAUDRATE_19200 = 19200, + UART_BAUDRATE_38400 = 38400, + UART_BAUDRATE_57600 = 57600, + UART_BAUDRATE_115200 = 115200, + UART_BAUDRATE_230400 = 230400, + UART_BAUDRATE_380400 = 380400, + UART_BAUDRATE_460800 = 460800, +} UART_BAUDRATE_T; + +/*---------------------------------------------------------------------------*/ +/* UART parity types */ +/*---------------------------------------------------------------------------*/ +typedef enum { + UART_PARITY_NONE = 0, + UART_PARITY_EVEN, + UART_PARITY_ODD, +} UART_PARITY_T; + +/*---------------------------------------------------------------------------*/ +/* Uart stop bits */ +/*---------------------------------------------------------------------------*/ +typedef enum { + UART_STOPBIT_1 = 0x00, + UART_STOPBIT_DYNAMIC, +} UART_STOPBIT_T; + +enum FCR_RFITL_TYPE { + FCR_RFITL_1B = 0x0, + FCR_RFITL_4B = 0x4, + FCR_RFITL_8B = 0x8, + FCR_RFITL_14B = 0xC, +}; + +enum LCR_WLS_TYPE { + LCR_WLS_5bit = 0x0, + LCR_WLS_6bit = 0x1, + LCR_WLS_7bit = 0x2, + LCR_WLS_8bit = 0x3, +}; + +#define IER_DBGACK (1 << 4) +#define IER_MSIE (1 << 3) +#define IER_RLSE (1 << 2) +#define IER_THREIE (1 << 1) +#define IER_RDAIE (1 << 0) + +#define IIR_FMES (1 << 7) +#define IIR_RFTLS (1 << 5) +#define IIR_DMS (1 << 4) +#define IIR_IID (1 << 1) +#define IIR_NIP (1 << 0) + +#define FCR_RFITL_1B (0 << 4) +#define FCR_RFITL_4B (4 << 4) +#define FCR_RFITL_8B (8 << 4) +#define FCR_RFITL_14B (12 << 4) +#define FCR_DMS (1 << 3) +#define FCR_TFR (1 << 2) +#define FCR_RFR (1 << 1) +#define FCR_FME (1 << 0) + +#define LCR_DLAB (1 << 7) +#define LCR_BCB (1 << 6) +#define LCR_SPE (1 << 5) +#define LCR_EPS (1 << 4) +#define LCR_PBE (1 << 3) +#define LCR_NSB (1 << 2) +#define LCR_WLS_8b (3 << 0) +#define LCR_WLS_7b (2 << 0) +#define LCR_WLS_6b (1 << 0) +#define LCR_WLS_5b (0 << 0) + +#define MCR_LBME (1 << 4) +#define MCR_OUT2 (1 << 3) +#define MCR_RTS (1 << 1) +#define MCR_DTR (1 << 0) + +#define LSR_ERR_RX (1 << 7) +#define LSR_TE (1 << 6) +#define LSR_THRE (1 << 5) +#define LSR_BII (1 << 4) +#define LSR_FEI (1 << 3) +#define LSR_PEI (1 << 2) +#define LSR_OEI (1 << 1) +#define LSR_RFDR (1 << 0) + +#define MSR_DCD (1 << 7) +#define MSR_RI (1 << 6) +#define MSR_DSR (1 << 5) +#define MSR_CTS (1 << 4) +#define MSR_DDCD (1 << 3) +#define MSR_DRI (1 << 2) +#define MSR_DDSR (1 << 1) +#define MSR_DCTS (1 << 0) + +#endif /* __ASSEMBLY__ */ + +uintptr_t npcm845x_get_base_uart(UART_DEV_T dev); +void CLK_ResetUART(void); +int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate); + +#endif /* __ASM_ARCH_UART_H_ */ diff --git a/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h b/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h new file mode 100644 index 0000000000..ae56d3b65a --- /dev/null +++ b/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h @@ -0,0 +1,155 @@ +/* + * Copyright 2017-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef CSF_HDR_H +#define CSF_HDR_H + +#include "caam.h" +#include "hash.h" +#include "rsa.h" + +/* Barker code size in bytes */ +#define CSF_BARKER_LEN 4 /* barker code length in ESBC uboot client */ + /* header */ + +#ifdef CSF_HDR_CH3 +struct csf_hdr { + uint8_t barker[CSF_BARKER_LEN]; /* 0x00 Barker code */ + uint32_t srk_tbl_off; /* 0x04 SRK Table Offset */ + + struct { + uint8_t num_srk; /* 0x08 No. of keys */ + uint8_t srk_sel; /* Key no. to be used */ + uint8_t reserve; /* 0x0a rseerved */ + } len_kr; + uint8_t ie_flag; + + uint32_t uid_flag; + + uint32_t psign; /* 0x10 signature offset */ + uint32_t sign_len; /* 0x14 length of signature */ + + union { + struct { + uint32_t sg_table_offset; /* 0x18 SG Table Offset */ + uint32_t sg_entries; /* 0x1c no of entries in SG */ + } sg_isbc; + uint64_t img_addr; /* 64 bit pointer to ESBC Image */ + }; + + union { + struct { + uint32_t img_size; /* ESBC client img size in bytes */ + uint32_t ie_key_sel; + } img; + uint64_t entry_point; /* 0x20-0x24 ESBC entry point */ + }; + + uint32_t fsl_uid_0; /* 0x28 Freescale unique id 0 */ + uint32_t fsl_uid_1; /* 0x2c Freescale unique id 1 */ + uint32_t oem_uid_0; /* 0x30 OEM unique id 0 */ + uint32_t oem_uid_1; /* 0x34 OEM unique id 1 */ + uint32_t oem_uid_2; /* 0x38 OEM unique id 2 */ + uint32_t oem_uid_3; /* 0x3c OEM unique id 3 */ + uint32_t oem_uid_4; /* 0x40 OEM unique id 4 */ + + uint32_t reserved[3]; /* 0x44 - 0x4f */ +}; + +/* Srk table and key revocation check */ +#define UNREVOCABLE_KEY 8 +#define REVOC_KEY_ALIGN 7 +#define MAX_KEY_ENTRIES 8 + +#else + +/* CSF header for Chassis 2 */ +struct csf_hdr { + uint8_t barker[CSF_BARKER_LEN]; /* barker code */ + union { + uint32_t pkey; /* public key offset */ + uint32_t srk_tbl_off; + }; + + union { + uint32_t key_len; /* pub key length in bytes */ + struct { + uint32_t srk_table_flag:8; + uint32_t srk_sel:8; + uint32_t num_srk:16; + } len_kr; + }; + + uint32_t psign; /* signature offset */ + uint32_t sign_len; /* length of the signature in bytes */ + + /* SG Table used by ISBC header */ + union { + struct { + uint32_t sg_table_offset; /* 0x14 SG Table Offset */ + uint32_t sg_entries; /* no of entries in SG table */ + } sg_isbc; + struct { + uint32_t reserved1; /* Reserved field */ + uint32_t img_size; /* ESBC img size in bytes */ + } img; + }; + + uint32_t entry_point; /* ESBC client entry point */ + uint32_t reserved2; /* Scatter gather flag */ + uint32_t uid_flag; + uint32_t fsl_uid_0; + uint32_t oem_uid_0; + uint32_t reserved3[2]; + uint32_t fsl_uid_1; + uint32_t oem_uid_1; + + /* The entries below aren't present in ISBC header */ + uint64_t img_addr; /* 64 bit pointer to ESBC Image */ + uint32_t ie_flag; + uint32_t ie_key_sel; +}; + +/* Srk table and key revocation check */ +#define UNREVOCABLE_KEY 4 +#define REVOC_KEY_ALIGN 3 +#define MAX_KEY_ENTRIES 4 + +#endif + +struct srk_table { + uint32_t key_len; + uint8_t pkey[2 * RSA_4K_KEY_SZ_BYTES]; +}; + +/* + * This struct contains the following fields + * length of the segment + * Destination Target ID + * source address + * destination address + */ +struct sg_table { + uint32_t len; /* Length of Image */ + uint32_t res1; + union { + uint64_t src_addr; /* SRC Address of Image */ + struct { + uint32_t src_addr; + uint32_t dst_addr; + } img; + }; +}; + +int validate_esbc_header(void *img_hdr, void **img_key, uint32_t *key_len, + void **img_sign, uint32_t *sign_len, + enum sig_alg *algo); + +int calc_img_hash(struct csf_hdr *hdr, void *img_addr, uint32_t img_size, + uint8_t *img_hash, uint32_t *hash_len); + +#endif diff --git a/include/drivers/nxp/console/plat_console.h b/include/drivers/nxp/console/plat_console.h new file mode 100644 index 0000000000..8b1b23a041 --- /dev/null +++ b/include/drivers/nxp/console/plat_console.h @@ -0,0 +1,38 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PLAT_CONSOLE_H +#define PLAT_CONSOLE_H + +#include <stdint.h> +#include <drivers/console.h> + +#if (NXP_CONSOLE == NS16550) +/* + * NXP specific UART - 16550 configuration + * + * Initialize a NXP 16550 console instance and register it with the console + * framework. The |console| pointer must point to storage that will be valid + * for the lifetime of the console, such as a global or static local variable. + * Its contents will be reinitialized from scratch. + * When |clock| has a value of 0, the UART will *not* be initialised. This + * means the UART should already be enabled and the baudrate and clock setup + * should have been done already, either by platform specific code or by + * previous firmware stages. The |baud| parameter will be ignored in this + * case as well. + */ +int nxp_console_16550_register(uintptr_t baseaddr, uint32_t clock, + uint32_t baud, console_t *console); +#endif +/* + * Function to initialize platform's console + * and register with console framework + */ +void plat_console_init(uintptr_t nxp_console_addr, uint32_t uart_clk_div, + uint32_t baud); + +#endif diff --git a/include/drivers/nxp/crypto/caam/caam.h b/include/drivers/nxp/crypto/caam/caam.h new file mode 100644 index 0000000000..6cc1f3dfd9 --- /dev/null +++ b/include/drivers/nxp/crypto/caam/caam.h @@ -0,0 +1,53 @@ +/* + * Copyright 2017-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef CAAM_H +#define CAAM_H + +#include "caam_io.h" +#include "sec_jr_driver.h" + + +/* Job ring 3 is reserved for usage by sec firmware */ +#define DEFAULT_JR 3 + +#if defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_2) +#define CAAM_JR0_OFFSET 0x10000 +#define CAAM_JR1_OFFSET 0x20000 +#define CAAM_JR2_OFFSET 0x30000 +#define CAAM_JR3_OFFSET 0x40000 +#endif + +enum sig_alg { + RSA, + ECC +}; + +/* This function does basic SEC Initialization */ +int sec_init(uintptr_t nxp_caam_addr); +int config_sec_block(void); +uintptr_t get_caam_addr(void); + +/* This function is used to submit jobs to JR */ +int run_descriptor_jr(struct job_descriptor *desc); + +/* This function is used to instatiate the HW RNG is already not instantiated */ +int hw_rng_instantiate(void); + +/* This function is used to return random bytes of byte_len from HW RNG */ +int get_rand_bytes_hw(uint8_t *bytes, int byte_len); + +/* This function is used to set the hw unique key from HW CAAM */ +int get_hw_unq_key_blob_hw(uint8_t *hw_key, int size); + +/* This function is used to fetch random number from + * CAAM of length either of 4 bytes or 8 bytes depending + * rngWidth value. + */ +unsigned long long get_random(int rngWidth); + +#endif /* CAAM_H */ diff --git a/include/drivers/nxp/crypto/caam/caam_io.h b/include/drivers/nxp/crypto/caam/caam_io.h new file mode 100644 index 0000000000..b68f836c92 --- /dev/null +++ b/include/drivers/nxp/crypto/caam/caam_io.h @@ -0,0 +1,56 @@ +/* + * Copyright 2018-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef CAAM_IO_H +#define CAAM_IO_H + +#include <endian.h> +#include <lib/mmio.h> + +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; + +/* Return higher 32 bits of physical address */ +#define PHYS_ADDR_HI(phys_addr) \ + (uint32_t)(((uint64_t)phys_addr) >> 32) + +/* Return lower 32 bits of physical address */ +#define PHYS_ADDR_LO(phys_addr) \ + (uint32_t)(((uint64_t)phys_addr) & 0xFFFFFFFF) + +#ifdef NXP_SEC_BE +#define sec_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define sec_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#define sec_in64(addr) ( \ + ((uint64_t)sec_in32((uintptr_t)(addr)) << 32) | \ + (sec_in32(((uintptr_t)(addr)) + 4))) +#define sec_out64(addr, val) ({ \ + sec_out32(((uintptr_t)(addr)), (uint32_t)((val) >> 32)); \ + sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)(val)); }) +#elif defined(NXP_SEC_LE) +#define sec_in32(a) mmio_read_32((uintptr_t)(a)) +#define sec_out32(a, v) mmio_write_32((uintptr_t)(a), (v)) +#define sec_in64(addr) ( \ + ((uint64_t)sec_in32((uintptr_t)(addr) + 4) << 32) | \ + (sec_in32((uintptr_t)(addr)))) +#define sec_out64(addr, val) ({ \ + sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)((val) >> 32)); \ + sec_out32(((uintptr_t)(addr)), (uint32_t)(val)); }) +#else +#error Please define CCSR SEC register endianness +#endif + +static inline void *ptov(phys_addr_t *ptr) +{ + return (void *)ptr; +} + +static inline phys_addr_t *vtop(void *ptr) +{ + return (phys_addr_t *)ptr; +} +#endif /* CAAM_IO_H */ diff --git a/include/drivers/nxp/crypto/caam/hash.h b/include/drivers/nxp/crypto/caam/hash.h new file mode 100644 index 0000000000..9136dca2d0 --- /dev/null +++ b/include/drivers/nxp/crypto/caam/hash.h @@ -0,0 +1,85 @@ +/* + * Copyright 2017-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __HASH_H__ +#define __HASH_H__ + +#include <stdbool.h> + +/* List of hash algorithms */ +enum hash_algo { + SHA1 = 0, + SHA256 +}; + +/* number of bytes in the SHA256-256 digest */ +#define SHA256_DIGEST_SIZE 32 + +/* + * number of words in the digest - Digest is kept internally + * as 8 32-bit words + */ +#define _SHA256_DIGEST_LENGTH 8 + +/* + * block length - A block, treated as a sequence of + * 32-bit words + */ +#define SHA256_BLOCK_LENGTH 16 + +/* number of bytes in the block */ +#define SHA256_DATA_SIZE 64 + +#define MAX_SG 12 + +struct sg_entry { +#if defined(NXP_SEC_LE) + uint32_t addr_lo; /* Memory Address - lo */ + uint32_t addr_hi; /* Memory Address of start of buffer - hi */ +#else + uint32_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_lo; /* Memory Address - lo */ +#endif + + uint32_t len_flag; /* Length of the data in the frame */ +#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF +#define SG_ENTRY_EXTENSION_BIT 0x80000000 +#define SG_ENTRY_FINAL_BIT 0x40000000 + uint32_t bpid_offset; +#define SG_ENTRY_BPID_MASK 0x00FF0000 +#define SG_ENTRY_BPID_SHIFT 16 +#define SG_ENTRY_OFFSET_MASK 0x00001FFF +#define SG_ENTRY_OFFSET_SHIFT 0 +}; + +/* + * SHA256-256 context + * contain the following fields + * State + * count low + * count high + * block data buffer + * index to the buffer + */ +struct hash_ctx { + struct sg_entry sg_tbl[MAX_SG]; + uint32_t hash_desc[64]; + uint8_t hash[SHA256_DIGEST_SIZE]; + uint32_t sg_num; + uint32_t len; + uint8_t *data; + enum hash_algo algo; + bool active; +}; + +int hash_init(enum hash_algo algo, void **ctx); +int hash_update(enum hash_algo algo, void *context, void *data_ptr, + unsigned int data_len); +int hash_final(enum hash_algo algo, void *context, void *hash_ptr, + unsigned int hash_len); + +#endif diff --git a/include/drivers/nxp/crypto/caam/jobdesc.h b/include/drivers/nxp/crypto/caam/jobdesc.h new file mode 100644 index 0000000000..efef228fb6 --- /dev/null +++ b/include/drivers/nxp/crypto/caam/jobdesc.h @@ -0,0 +1,56 @@ +/* + * Copyright 2017-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __JOBDESC_H +#define __JOBDESC_H + +#include <rsa.h> + +#define DESC_LEN_MASK 0x7f +#define DESC_START_SHIFT 16 + +#define KEY_BLOB_SIZE 32 +#define MAC_SIZE 16 + +#define KEY_IDNFR_SZ_BYTES 16 +#define CLASS_SHIFT 25 +#define CLASS_2 (0x02 << CLASS_SHIFT) + +#define CMD_SHIFT 27 +#define CMD_OPERATION (U(0x10) << CMD_SHIFT) + +#define OP_TYPE_SHIFT 24 +#define OP_TYPE_ENCAP_PROTOCOL (0x07 << OP_TYPE_SHIFT) + +/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */ +#define OP_PCLID_SHIFT 16 +#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT) + +#define BLOB_PROTO_INFO 0x00000002 + +uint32_t desc_length(uint32_t *desc); + +int cnstr_rng_jobdesc(uint32_t *desc, uint32_t state_handle, + uint32_t *add_inp, uint32_t add_ip_len, + uint8_t *out_data, uint32_t len); + +int cnstr_rng_instantiate_jobdesc(uint32_t *desc); + +/* Construct descriptor to generate hw key blob */ +int cnstr_hw_encap_blob_jobdesc(uint32_t *desc, + uint8_t *key_idnfr, uint32_t key_sz, + uint32_t key_class, uint8_t *plain_txt, + uint32_t in_sz, uint8_t *enc_blob, + uint32_t out_sz, uint32_t operation); + +void cnstr_hash_jobdesc(uint32_t *desc, uint8_t *msg, uint32_t msgsz, + uint8_t *digest); + +void cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, + struct pk_in_params *pkin, uint8_t *out, + uint32_t out_siz); +#endif diff --git a/include/drivers/nxp/crypto/caam/jr_driver_config.h b/include/drivers/nxp/crypto/caam/jr_driver_config.h new file mode 100644 index 0000000000..1b3c447ae5 --- /dev/null +++ b/include/drivers/nxp/crypto/caam/jr_driver_config.h @@ -0,0 +1,205 @@ +/* + * Copyright 2017-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _JR_DRIVER_CONFIG_H_ +#define _JR_DRIVER_CONFIG_H_ + +/* Helper defines */ + + /* Define used for setting a flag on */ +#define ON 1 + /* Define used for setting a flag off */ +#define OFF 0 + + /* SEC is configured to start work in polling mode, */ +#define SEC_STARTUP_POLLING_MODE 0 +/* + * SEC is configured to start work in interrupt mode, + * when configured for NAPI notification style. + */ +#define SEC_STARTUP_INTERRUPT_MODE 1 + +/* + * SEC driver will use ONLY interrupts to receive notifications + * for processed packets from SEC engine hardware. + */ +#define SEC_NOTIFICATION_TYPE_IRQ 1 +/* + * SEC driver will use ONLY polling to receive notifications + * for processed packets from SEC engine hardware. + */ +#define SEC_NOTIFICATION_TYPE_POLL 2 + +/* + * Determines how SEC user space driver will receive notifications + * for processed packets from SEC engine. + * Valid values are: #SEC_NOTIFICATION_TYPE_POLL, #SEC_NOTIFICATION_TYPE_IRQ + */ +#define SEC_NOTIFICATION_TYPE SEC_NOTIFICATION_TYPE_POLL + + /* Maximum number of job rings supported by SEC hardware */ +#define MAX_SEC_JOB_RINGS 1 + +/* + * Size of cryptographic context that is used directly in communicating + * with SEC device. + * SEC device works only with physical addresses. This is the maximum size + * for a SEC descriptor ( = 64 words). + */ + +#define SEC_CRYPTO_DESCRIPTOR_SIZE 256 + +/* + * Size of job descriptor submitted to SEC device for each packet to be + * processed. + * Job descriptor contains 3 DMA address pointers: + * - to shared descriptor, to input buffer and to output buffer. + * The job descriptor contains other SEC specific commands as well: + * - HEADER command, SEQ IN PTR command SEQ OUT PTR command and opaque + * data, each measuring 4 bytes. + * Job descriptor size, depending on physical address representation: + * - 32 bit - size is 28 bytes - cacheline-aligned size is 64 bytes + * - 36 bit - size is 40 bytes - cacheline-aligned size is 64 bytes + * @note: Job descriptor must be cacheline-aligned to ensure efficient memory + * access. + * @note: If other format is used for job descriptor, then the size must be + * revised. + */ + +#define SEC_JOB_DESCRIPTOR_SIZE 64 + +/* + * Size of one entry in the input ring of a job ring. + * Input ring contains pointers to job descriptors. + * The memory used for an input ring and output ring must be physically + * contiguous. + */ + +#define SEC_JOB_INPUT_RING_ENTRY_SIZE sizeof(phys_addr_t) + +/* + * Size of one entry in the output ring of a job ring. + * Output ring entry is a pointer to a job descriptor followed by a 4 byte + * status word. + * The memory used for an input ring and output ring must be physically + * contiguous. + * @note If desired to use also the optional SEQ OUT indication in output + * ring entries, then 4 more bytes must be added to the size. + */ + +#define SEC_JOB_OUTPUT_RING_ENTRY_SIZE (SEC_JOB_INPUT_RING_ENTRY_SIZE + 4) + + /* DMA memory required for an input ring of a job ring. */ +#define SEC_DMA_MEM_INPUT_RING_SIZE \ + ((SEC_JOB_INPUT_RING_ENTRY_SIZE) * (SEC_JOB_RING_SIZE)) + +/* + * DMA memory required for an output ring of a job ring. + * Required extra 4 byte for status word per each entry. + */ +#define SEC_DMA_MEM_OUTPUT_RING_SIZE \ + ((SEC_JOB_OUTPUT_RING_ENTRY_SIZE) * (SEC_JOB_RING_SIZE)) + + /* DMA memory required for descriptors of a job ring. */ +#define SEC_DMA_MEM_DESCRIPTORS \ + ((SEC_CRYPTO_DESCRIPTOR_SIZE)*(SEC_JOB_RING_SIZE)) + + /* DMA memory required for a job ring, including both input output rings. */ +#define SEC_DMA_MEM_JOB_RING_SIZE \ + ((SEC_DMA_MEM_INPUT_RING_SIZE) + \ + (SEC_DMA_MEM_OUTPUT_RING_SIZE)) + +/* + * When calling sec_init() UA will provide an area of virtual memory + * of size #SEC_DMA_MEMORY_SIZE to be used internally by the driver + * to allocate data (like SEC descriptors) that needs to be passed to + * SEC device in physical addressing and later on retrieved from SEC device. + * At initialization the UA provides specialized ptov/vtop functions/macros to + * translate addresses allocated from this memory area. + */ +#define SEC_DMA_MEMORY_SIZE \ + ((SEC_DMA_MEM_JOB_RING_SIZE) * (MAX_SEC_JOB_RINGS)) + +/* + * SEC DEVICE related configuration. + + * Enable/Disable logging support at compile time. + * Valid values: + * ON - enable logging + * OFF - disable logging + * The messages are logged at stdout. + */ + +#define SEC_DRIVER_LOGGING OFF + +/* + * Configure logging level at compile time. + * Valid values: + * SEC_DRIVER_LOG_ERROR - log only errors + * SEC_DRIVER_LOG_INFO - log errors and info messages + * SEC_DRIVER_LOG_DEBUG - log errors, info and debug messages + */ + +#define SEC_DRIVER_LOGGING_LEVEL SEC_DRIVER_LOG_DEBUG + +/* + * SEC JOB RING related configuration. + + * Configure the size of the JOB RING. + * The maximum size of the ring is hardware limited to 1024. + * However the number of packets in flight in a time interval of + * 1ms can be calculated + * from the traffic rate (Mbps) and packet size. + * Here it was considered a packet size of 40 bytes. + * @note Round up to nearest power of 2 for optimized update + * of producer/consumer indexes of each job ring + * \todo Should set to 750, according to the calculation above, but + * the JR size must be power of 2, thus the next closest value must + * be chosen (i.e. 512 since 1024 is not available) + * For firmware choose this to be 16 + */ + +#define SEC_JOB_RING_SIZE 16 + +/* + * Interrupt coalescing related configuration. + * NOTE: SEC hardware enabled interrupt + * coalescing is not supported on SEC version 3.1! + * SEC version 4.4 has support for interrupt + * coalescing. + */ + +#if SEC_NOTIFICATION_TYPE != SEC_NOTIFICATION_TYPE_POLL + +#define SEC_INT_COALESCING_ENABLE ON +/* + * Interrupt Coalescing Descriptor Count Threshold. + * While interrupt coalescing is enabled (ICEN=1), this value determines + * how many Descriptors are completed before raising an interrupt. + * Valid values for this field are from 0 to 255. + * Note that a value of 1 functionally defeats the advantages of interrupt + * coalescing since the threshold value is reached each time that a + * Job Descriptor is completed. A value of 0 is treated in the same + * manner as a value of 1. + * + */ +#define SEC_INTERRUPT_COALESCING_DESCRIPTOR_COUNT_THRESH 10 + +/* + * Interrupt Coalescing Timer Threshold. + * While interrupt coalescing is enabled (ICEN=1), this value determines the + * maximum amount of time after processing a Descriptor before raising an + * interrupt. + * The threshold value is represented in units equal to 64 CAAM interface + * clocks. Valid values for this field are from 1 to 65535. + * A value of 0 results in behavior identical to that when interrupt + * coalescing is disabled. + */ +#define SEC_INTERRUPT_COALESCING_TIMER_THRESH 100 +#endif /* SEC_NOTIFICATION_TYPE_POLL */ + +#endif /* _JR_DRIVER_CONFIG_H_ */ diff --git a/include/drivers/nxp/crypto/caam/rsa.h b/include/drivers/nxp/crypto/caam/rsa.h new file mode 100644 index 0000000000..dd9ecdc98c --- /dev/null +++ b/include/drivers/nxp/crypto/caam/rsa.h @@ -0,0 +1,40 @@ +/* + * Copyright 2017-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RSA_H__ +#define _RSA_H__ + +/* RSA key size defines */ +#define RSA_4K_KEY_SZ 4096 +#define RSA_4K_KEY_SZ_BYTES (RSA_4K_KEY_SZ/8) +#define RSA_2K_KEY_SZ 2048 +#define RSA_2K_KEY_SZ_BYTES (RSA_2K_KEY_SZ/8) +#define RSA_1K_KEY_SZ 1024 +#define RSA_1K_KEY_SZ_BYTES (RSA_1K_KEY_SZ/8) + +#define SHA256_BYTES (256/8) + +struct pk_in_params { + uint8_t *e; + uint32_t e_siz; + uint8_t *n; + uint32_t n_siz; + uint8_t *a; + uint32_t a_siz; + uint8_t *b; + uint32_t b_siz; +}; + +struct rsa_context { + struct pk_in_params pkin; +}; + +int rsa_verify_signature(void *hash_ptr, unsigned int hash_len, + void *sig_ptr, unsigned int sig_len, + void *pk_ptr, unsigned int pk_len); + +#endif diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h new file mode 100644 index 0000000000..bc11aca1ee --- /dev/null +++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h @@ -0,0 +1,503 @@ +/* + * Copyright 2017-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _SEC_HW_SPECIFIC_H_ +#define _SEC_HW_SPECIFIC_H_ + +#include "caam.h" +#include "sec_jr_driver.h" + + /* DEFINES AND MACROS */ + +/* Used to retry resetting a job ring in SEC hardware. */ +#define SEC_TIMEOUT 100000 + +/* + * Offset to the registers of a job ring. + *Is different for each job ring. + */ +#define CHAN_BASE(jr) ((phys_addr_t)(jr)->register_base_addr) + +#define unlikely(x) __builtin_expect(!!(x), 0) + +#define SEC_JOB_RING_IS_FULL(pi, ci, ring_max_size, ring_threshold) \ + ((((pi) + 1 + ((ring_max_size) - (ring_threshold))) & \ + (ring_max_size - 1)) == ((ci))) + +#define SEC_CIRCULAR_COUNTER(x, max) (((x) + 1) & (max - 1)) + + /* Struct representing various job ring registers */ +struct jobring_regs { +#ifdef NXP_SEC_BE + unsigned int irba_h; + unsigned int irba_l; +#else + unsigned int irba_l; + unsigned int irba_h; +#endif + unsigned int rsvd1; + unsigned int irs; + unsigned int rsvd2; + unsigned int irsa; + unsigned int rsvd3; + unsigned int irja; +#ifdef NXP_SEC_BE + unsigned int orba_h; + unsigned int orba_l; +#else + unsigned int orba_l; + unsigned int orba_h; +#endif + unsigned int rsvd4; + unsigned int ors; + unsigned int rsvd5; + unsigned int orjr; + unsigned int rsvd6; + unsigned int orsf; + unsigned int rsvd7; + unsigned int jrsta; + unsigned int rsvd8; + unsigned int jrint; + unsigned int jrcfg0; + unsigned int jrcfg1; + unsigned int rsvd9; + unsigned int irri; + unsigned int rsvd10; + unsigned int orwi; + unsigned int rsvd11; + unsigned int jrcr; +}; + + /* Offsets representing common SEC Registers */ +#define SEC_REG_MCFGR_OFFSET 0x0004 +#define SEC_REG_SCFGR_OFFSET 0x000C +#define SEC_REG_JR0ICIDR_MS_OFFSET 0x0010 +#define SEC_REG_JR0ICIDR_LS_OFFSET 0x0014 +#define SEC_REG_JR1ICIDR_MS_OFFSET 0x0018 +#define SEC_REG_JR1ICIDR_LS_OFFSET 0x001C +#define SEC_REG_JR2ICIDR_MS_OFFSET 0x0020 +#define SEC_REG_JR2ICIDR_LS_OFFSET 0x0024 +#define SEC_REG_JR3ICIDR_MS_OFFSET 0x0028 +#define SEC_REG_JR3ICIDR_LS_OFFSET 0x002C +#define SEC_REG_JRSTARTR_OFFSET 0x005C +#define SEC_REG_CTPR_MS_OFFSET 0x0FA8 + + /* Offsets representing various RNG registers */ +#define RNG_REG_RTMCTL_OFFSET 0x0600 +#define RNG_REG_RTSDCTL_OFFSET 0x0610 +#define RNG_REG_RTFRQMIN_OFFSET 0x0618 +#define RNG_REG_RTFRQMAX_OFFSET 0x061C +#define RNG_REG_RDSTA_OFFSET 0x06C0 +#define ALG_AAI_SH_SHIFT 4 + + /* SEC Registers Bitmasks */ +#define MCFGR_PS_SHIFT 16 +#define MCFGR_AWCACHE_SHIFT 8 +#define MCFGR_AWCACHE_MASK (0xF << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT 12 +#define MCFGR_ARCACHE_MASK (0xF << MCFGR_ARCACHE_SHIFT) + +#define SCFGR_RNGSH0 0x00000200 +#define SCFGR_VIRT_EN 0x00008000 + +#define JRICID_MS_LICID 0x80000000 +#define JRICID_MS_LAMTD 0x00020000 +#define JRICID_MS_AMTDT 0x00010000 +#define JRICID_MS_TZ 0x00008000 +#define JRICID_LS_SDID_MASK 0x00000FFF +#define JRICID_LS_NSEQID_MASK 0x0FFF0000 +#define JRICID_LS_NSEQID_SHIFT 16 +#define JRICID_LS_SEQID_MASK 0x00000FFF + +#define JRSTARTR_STARTJR0 0x00000001 +#define JRSTARTR_STARTJR1 0x00000002 +#define JRSTARTR_STARTJR2 0x00000004 +#define JRSTARTR_STARTJR3 0x00000008 + +#define CTPR_VIRT_EN_POR 0x00000002 +#define CTPR_VIRT_EN_INC 0x00000001 + + /* RNG RDSTA bitmask */ +#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001 +#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ + /* use von Neumann data in both entropy shifter and statistical checker */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 + /* use raw data in both entropy shifter and statistical checker */ +#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 + /* use von Neumann data in entropy shifter, raw data in statistical checker */ +#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 + /* invalid combination */ +#define RTMCTL_SAMP_MODE_INVALID 3 +#define RTSDCTL_ENT_DLY_MIN 3200 +#define RTSDCTL_ENT_DLY_MAX 12800 +#define RTSDCTL_ENT_DLY_SHIFT 16 +#define RTSDCTL_ENT_DLY_MASK (U(0xffff) << RTSDCTL_ENT_DLY_SHIFT) +#define RTFRQMAX_DISABLE (1 << 20) + + /* Constants for error handling on job ring */ +#define JR_REG_JRINT_ERR_TYPE_SHIFT 8 +#define JR_REG_JRINT_ERR_ORWI_SHIFT 16 +#define JR_REG_JRINIT_JRE_SHIFT 1 + +#define JRINT_JRE (1 << JR_REG_JRINIT_JRE_SHIFT) +#define JRINT_ERR_WRITE_STATUS (1 << JR_REG_JRINT_ERR_TYPE_SHIFT) +#define JRINT_ERR_BAD_INPUT_BASE (3 << JR_REG_JRINT_ERR_TYPE_SHIFT) +#define JRINT_ERR_BAD_OUTPUT_BASE (4 << JR_REG_JRINT_ERR_TYPE_SHIFT) +#define JRINT_ERR_WRITE_2_IRBA (5 << JR_REG_JRINT_ERR_TYPE_SHIFT) +#define JRINT_ERR_WRITE_2_ORBA (6 << JR_REG_JRINT_ERR_TYPE_SHIFT) +#define JRINT_ERR_RES_B4_HALT (7 << JR_REG_JRINT_ERR_TYPE_SHIFT) +#define JRINT_ERR_REM_TOO_MANY (8 << JR_REG_JRINT_ERR_TYPE_SHIFT) +#define JRINT_ERR_ADD_TOO_MANY (9 << JR_REG_JRINT_ERR_TYPE_SHIFT) +#define JRINT_ERR_HALT_MASK 0x0C +#define JRINT_ERR_HALT_INPROGRESS 0x04 +#define JRINT_ERR_HALT_COMPLETE 0x08 + +#define JR_REG_JRCR_VAL_RESET 0x00000001 + +#define JR_REG_JRCFG_LO_ICTT_SHIFT 0x10 +#define JR_REG_JRCFG_LO_ICDCT_SHIFT 0x08 +#define JR_REG_JRCFG_LO_ICEN_EN 0x02 +#define JR_REG_JRCFG_LO_IMSK_EN 0x01 + + /* Constants for Descriptor Processing errors */ +#define SEC_HW_ERR_SSRC_NO_SRC 0x00 +#define SEC_HW_ERR_SSRC_CCB_ERR 0x02 +#define SEC_HW_ERR_SSRC_JMP_HALT_U 0x03 +#define SEC_HW_ERR_SSRC_DECO 0x04 +#define SEC_HW_ERR_SSRC_JR 0x06 +#define SEC_HW_ERR_SSRC_JMP_HALT_COND 0x07 + +#define SEC_HW_ERR_DECO_HFN_THRESHOLD 0xF1 +#define SEC_HW_ERR_CCB_ICV_CHECK_FAIL 0x0A + + /* Macros for extracting error codes for the job ring */ + +#define JR_REG_JRINT_ERR_TYPE_EXTRACT(value) \ + ((value) & 0x00000F00) + +#define JR_REG_JRINT_ERR_ORWI_EXTRACT(value) \ + (((value) & 0x3FFF0000) >> \ + JR_REG_JRINT_ERR_ORWI_SHIFT) + +#define JR_REG_JRINT_JRE_EXTRACT(value) \ + ((value) & JRINT_JRE) + + /* Macros for manipulating JR registers */ +typedef struct { +#ifdef NXP_SEC_BE + uint32_t high; + uint32_t low; +#else + uint32_t low; + uint32_t high; +#endif +} ptr_addr_t; + +#if defined(CONFIG_PHYS_64BIT) +#define sec_read_addr(a) sec_in64((a)) +#define sec_write_addr(a, v) sec_out64((a), (v)) +#else +#define sec_read_addr(a) sec_in32((a)) +#define sec_write_addr(a, v) sec_out32((a), (v)) +#endif + +#define JR_REG(name, jr) (CHAN_BASE(jr) + JR_REG_##name##_OFFSET) +#define JR_REG_LO(name, jr) (CHAN_BASE(jr) + JR_REG_##name##_OFFSET_LO) + +#define GET_JR_REG(name, jr) (sec_in32(JR_REG(name, (jr)))) +#define GET_JR_REG_LO(name, jr) (sec_in32(JR_REG_LO(name, (jr)))) + +#define SET_JR_REG(name, jr, val) \ + (sec_out32(JR_REG(name, (jr)), (val))) + +#define SET_JR_REG_LO(name, jr, val) \ + (sec_out32(JR_REG_LO(name, (jr)), (val))) + + /* STRUCTURES AND OTHER TYPEDEFS */ + /* Lists the possible states for a job ring. */ +typedef enum sec_job_ring_state_e { + SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */ + SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progress */ +} sec_job_ring_state_t; + +struct sec_job_ring_t { + /* + * Consumer index for job ring (jobs array). + * @note: cidx and pidx are accessed from + * different threads. + * Place the cidx and pidx inside the structure + * so that they lay on different cachelines, to + * avoid false sharing between threads when the + * threads run on different cores! + */ + uint32_t cidx; + + /* Producer index for job ring (jobs array) */ + uint32_t pidx; + + /* Ring of input descriptors. Size of array is power of 2 to allow + * fast update of producer/consumer indexes with bitwise operations. + */ + phys_addr_t *input_ring; + + /* Ring of output descriptors. */ + struct sec_outring_entry *output_ring; + + /* The file descriptor used for polling for interrupts notifications */ + uint32_t irq_fd; + + /* Model used by SEC Driver to receive notifications from SEC. + * Can be either of the three: + * #SEC_NOTIFICATION_TYPE_IRQ or + * #SEC_NOTIFICATION_TYPE_POLL + */ + uint32_t jr_mode; + /* Base address for SEC's register memory for this job ring. */ + void *register_base_addr; + /* notifies if coelescing is enabled for the job ring */ + uint8_t coalescing_en; + /* The state of this job ring */ + sec_job_ring_state_t jr_state; +}; + + /* Forward structure declaration */ +typedef struct sec_job_ring_t sec_job_ring_t; + +struct sec_outring_entry { + phys_addr_t desc; /* Pointer to completed descriptor */ + uint32_t status; /* Status for completed descriptor */ +} __packed; + + /* Lists the states possible for the SEC user space driver. */ +typedef enum sec_driver_state_e { + SEC_DRIVER_STATE_IDLE, /*< Driver not initialized */ + SEC_DRIVER_STATE_STARTED, /*< Driver initialized and */ + SEC_DRIVER_STATE_RELEASE, /*< Driver release is in progress */ +} sec_driver_state_t; + + /* Union describing the possible error codes that */ + /* can be set in the descriptor status word */ + +union hw_error_code { + uint32_t error; + union { + struct { + uint32_t ssrc:4; + uint32_t ssed_val:28; + } __packed value; + struct { + uint32_t ssrc:4; + uint32_t res:28; + } __packed no_status_src; + struct { + uint32_t ssrc:4; + uint32_t jmp:1; + uint32_t res:11; + uint32_t desc_idx:8; + uint32_t cha_id:4; + uint32_t err_id:4; + } __packed ccb_status_src; + struct { + uint32_t ssrc:4; + uint32_t jmp:1; + uint32_t res:11; + uint32_t desc_idx:8; + uint32_t offset:8; + } __packed jmp_halt_user_src; + struct { + uint32_t ssrc:4; + uint32_t jmp:1; + uint32_t res:11; + uint32_t desc_idx:8; + uint32_t desc_err:8; + } __packed deco_src; + struct { + uint32_t ssrc:4; + uint32_t res:17; + uint32_t naddr:3; + uint32_t desc_err:8; + } __packed jr_src; + struct { + uint32_t ssrc:4; + uint32_t jmp:1; + uint32_t res:11; + uint32_t desc_idx:8; + uint32_t cond:8; + } __packed jmp_halt_cond_src; + } __packed error_desc; +} __packed; + + /* FUNCTION PROTOTYPES */ + +/* + * @brief Initialize a job ring/channel in SEC device. + * Write configuration register/s to properly initialize a job ring. + * + * @param [in] job_ring The job ring + * + * @retval 0 for success + * @retval other for error + */ +int hw_reset_job_ring(sec_job_ring_t *job_ring); + +/* + * @brief Reset a job ring/channel in SEC device. + * Write configuration register/s to reset a job ring. + * + * @param [in] job_ring The job ring + * + * @retval 0 for success + * @retval -1 in case job ring reset failed + */ +int hw_shutdown_job_ring(sec_job_ring_t *job_ring); + +/* + * @brief Handle a job ring/channel error in SEC device. + * Identify the error type and clear error bits if required. + * + * @param [in] job_ring The job ring + * @param [in] sec_error_code error code as first read from SEC engine + */ + +void hw_handle_job_ring_error(sec_job_ring_t *job_ring, + uint32_t sec_error_code); +/* + * @brief Handle a job ring error in the device. + * Identify the error type and printout a explanatory + * messages. + * + * @param [in] job_ring The job ring + * + */ + +int hw_job_ring_error(sec_job_ring_t *job_ring); + +/* @brief Set interrupt coalescing parameters on the Job Ring. + * @param [in] job_ring The job ring + * @param [in] irq_coalesing_timer + * Interrupt coalescing timer threshold. + * This value determines the maximum + * amount of time after processing a descriptor + * before raising an interrupt. + * @param [in] irq_coalescing_count + * Interrupt coalescing count threshold. + * This value determines how many descriptors + * are completed before raising an interrupt. + */ + +int hw_job_ring_set_coalescing_param(sec_job_ring_t *job_ring, + uint16_t irq_coalescing_timer, + uint8_t irq_coalescing_count); + +/* @brief Enable interrupt coalescing on a job ring + * @param [in] job_ring The job ring + */ + +int hw_job_ring_enable_coalescing(sec_job_ring_t *job_ring); + +/* + * @brief Disable interrupt coalescing on a job ring + * @param [in] job_ring The job ring + */ + +int hw_job_ring_disable_coalescing(sec_job_ring_t *job_ring); + +/* + * @brief Poll the HW for already processed jobs in the JR + * and notify the available jobs to UA. + * + * @param [in] job_ring The job ring to poll. + * @param [in] limit The maximum number of jobs to notify. + * If set to negative value, all available + * jobs are notified. + * + * @retval >=0 for No of jobs notified to UA. + * @retval -1 for error + */ + +int hw_poll_job_ring(struct sec_job_ring_t *job_ring, int32_t limit); + +/* @brief Poll the HW for already processed jobs in the JR + * and silently discard the available jobs or notify them to UA + * with indicated error code. + + * @param [in,out] job_ring The job ring to poll. + * @param [in] do_notify Can be #TRUE or #FALSE. + * Indicates if descriptors to be discarded + * or notified to UA with given error_code. + * @param [in] error_code The detailed SEC error code. + * @param [out] notified_descs Number of notified descriptors. + * Can be NULL if do_notify is #FALSE + */ +void hw_flush_job_ring(struct sec_job_ring_t *job_ring, + uint32_t do_notify, + uint32_t error_code, uint32_t *notified_descs); + +/* + * @brief Flush job rings of any processed descs. + * The processed descs are silently dropped, + * WITHOUT being notified to UA. + */ +void flush_job_rings(void); + +/* + * @brief Handle desc that generated error in SEC engine. + * Identify the exact type of error and handle the error. + * Depending on the error type, the job ring could be reset. + * All descs that are submitted for processing on this job ring + * are notified to User Application with error status and detailed error code. + + * @param [in] job_ring Job ring + * @param [in] sec_error_code Error code read from job ring's Channel + * Status Register + * @param [out] notified_descs Number of notified descs. Can be NULL if + * do_notify is #FALSE + * @param [out] do_driver_shutdown If set to #TRUE, then UA is returned code + * #SEC_PROCESSING_ERROR + * which is indication that UA must call + * sec_release() after this. + */ +void sec_handle_desc_error(struct sec_job_ring_t *job_ring, + uint32_t sec_error_code, + uint32_t *notified_descs, + uint32_t *do_driver_shutdown); + +/* + * @brief Release the software and hardware resources tied to a job ring. + * @param [in] job_ring The job ring + * @retval 0 for success + * @retval -1 for error + */ +int shutdown_job_ring(struct sec_job_ring_t *job_ring); + +/* + * @brief Enable irqs on associated job ring. + * @param [in] job_ring The job ring + * @retval 0 for success + * @retval -1 for error + */ +int jr_enable_irqs(struct sec_job_ring_t *job_ring); + +/* + * @brief Disable irqs on associated job ring. + * @param [in] job_ring The job ring + * @retval 0 for success + * @retval -1 for error + */ +int jr_disable_irqs(struct sec_job_ring_t *job_ring); + + /* + * IRJA - Input Ring Jobs Added Register shows + * how many new jobs were added to the Input Ring. + */ +static inline void hw_enqueue_desc_on_job_ring(struct jobring_regs *regs, + int num) +{ + sec_out32(®s->irja, num); +} + +#endif /* _SEC_HW_SPECIFIC_H_ */ diff --git a/include/drivers/nxp/crypto/caam/sec_jr_driver.h b/include/drivers/nxp/crypto/caam/sec_jr_driver.h new file mode 100644 index 0000000000..a6570d8bf6 --- /dev/null +++ b/include/drivers/nxp/crypto/caam/sec_jr_driver.h @@ -0,0 +1,178 @@ +/* + * Copyright 2017-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _JR_DRIVER_H_ +#define _JR_DRIVER_H_ + +#include "jr_driver_config.h" + +/* The maximum size of a SEC descriptor, in WORDs (32 bits). */ +#define MAX_DESC_SIZE_WORDS 64 + +#define CAAM_TIMEOUT 200000 /* ms */ + +/* Return codes for JR user space driver APIs */ +typedef enum sec_return_code_e { + SEC_SUCCESS = 0, + SEC_INVALID_INPUT_PARAM, + SEC_OUT_OF_MEMORY, + SEC_DESCRIPTOR_IN_FLIGHT, + SEC_LAST_DESCRIPTOR_IN_FLIGHT, + SEC_PROCESSING_ERROR, + SEC_DESC_PROCESSING_ERROR, + SEC_JR_IS_FULL, + SEC_DRIVER_RELEASE_IN_PROGRESS, + SEC_DRIVER_ALREADY_INITIALIZED, + SEC_DRIVER_NOT_INITIALIZED, + SEC_JOB_RING_RESET_IN_PROGRESS, + SEC_RESET_ENGINE_FAILED, + SEC_ENABLE_IRQS_FAILED, + SEC_DISABLE_IRQS_FAILED, + SEC_RETURN_CODE_MAX_VALUE, +} sec_return_code_t; + +/* STRUCTURES AND OTHER TYPEDEFS */ + +/* + * @brief Function called by JR User Space driver to notify every processed + * descriptor. + * + * Callback provided by the User Application. + * Callback is invoked by JR User Space driver for each descriptor processed by + * SEC + * @param [in] status Status word indicating processing result for + * this descriptor. + * @param [in] arg Opaque data passed by User Application + * It is opaque from JR driver's point of view. + * @param [in] job_ring The job ring handle on which the processed + * descriptor word was enqueued + */ +typedef void (*user_callback) (uint32_t *desc, uint32_t status, + void *arg, void *job_ring); + +/* + * Structure encompassing a job descriptor which is to be processed + * by SEC. User should also initialise this structure with the callback + * function pointer which will be called by driver after receiving proccessed + * descriptor from SEC. User data is also passed in this data structure which + * will be sent as an argument to the user callback function. + */ +struct job_descriptor { + uint32_t desc[MAX_DESC_SIZE_WORDS]; + void *arg; + user_callback callback; +}; + +/* + * @brief Initialize the JR User Space driver. + * This function will handle initialization of sec library + * along with registering platform specific callbacks, + * as well as local data initialization. + * Call once during application startup. + * @note Global SEC initialization is done in SEC kernel driver. + * @note The hardware IDs of the initialized Job Rings are opaque to the UA. + * The exact Job Rings used by this library are decided between SEC user + * space driver and SEC kernel driver. A static partitioning of Job Rings is + * assumed, configured in DTS(device tree specification) file. + * @param [in] platform_cb Registering the platform specific + * callbacks with driver + * @retval ::0 for successful execution + * @retval ::-1 failure + */ +int sec_jr_lib_init(void); + +/* + * @brief Initialize the software and hardware resources tied to a job ring. + * @param [in] jr_mode; Model to be used by SEC Driver to receive + * notifications from SEC. Can be either + * SEC_NOTIFICATION_TYPE_IRQ or + * SEC_NOTIFICATION_TYPE_POLL + * @param [in] irq_coalescing_timer This value determines the maximum + * amount of time after processing a + * descriptor before raising an interrupt. + * @param [in] irq_coalescing_count This value determines how many + * descriptors are completed before + * raising an interrupt. + * @param [in] reg_base_addr The job ring base address register + * @param [in] irq_id The job ring interrupt identification number. + * @retval job_ring_handle for successful job ring configuration + * @retval NULL on error + */ +void *init_job_ring(uint8_t jr_mode, + uint16_t irq_coalescing_timer, + uint8_t irq_coalescing_count, + void *reg_base_addr, uint32_t irq_id); + +/* + * @brief Release the resources used by the JR User Space driver. + * Reset and release SEC's job rings indicated by the User Application at + * init_job_ring() and free any memory allocated internally. + * Call once during application tear down. + * @note In case there are any descriptors in-flight (descriptors received by + * JR driver for processing and for which no response was yet provided to UA), + * the descriptors are discarded without any notifications to User Application. + * @retval ::0 is returned for a successful execution + * @retval ::-1 is returned if JR driver release is in progress + */ +int sec_release(void); + +/* + * @brief Submit a descriptor for SEC processing. + * This function creates a "job" which is meant to instruct SEC HW + * to perform the processing on the input buffer. The "job" is enqueued + * in the Job Ring associated. The function will return after the "job" + * enqueue is finished. The function will not wait for SEC to + * start or/and finish the "job" processing. + * After the processing is finished the SEC HW writes the processing result + * to the provided output buffer. + * The Caller must poll JR driver using jr_dequeue() + * to receive notifications of the processing completion + * status. The notifications are received by caller by means of callback + * (see ::user_callback). + * @param [in] job_ring_handle The handle of the job ring on which + * descriptor is to be enqueued + * @param [in] job_descriptor The job descriptor structure of type + * struct job_descriptor. This structure + * should be filled with job descriptor along + * with callback function to be called after + * processing of descriptor and some + * opaque data passed to be passed to the + * callback function + * + * @retval ::0 is returned for successful execution + * @retval ::-1 is returned if there is some enqueue failure + */ +int enq_jr_desc(void *job_ring_handle, struct job_descriptor *jobdescr); + +/* + * @brief Polls for available descriptors processed by SEC on a specific + * Job Ring + * This function polls the SEC Job Rings and delivers processed descriptors + * Each processed descriptor has a user_callback registered. + * This user_callback is invoked for each processed descriptor. + * The polling is stopped when "limit" descriptors are notified or when + * there are no more descriptors to notify. + * @note The dequeue_jr() API cannot be called from within a user_callback + * function + * @param [in] job_ring_handle The Job Ring handle. + * @param [in] limit This value represents the maximum number + * of processed descriptors that can be + * notified API call on this Job Ring. + * Note that fewer descriptors may be notified + * if enough processed descriptors are not + * available. + * If limit has a negative value, then all + * ready descriptors will be notified. + * + * @retval :: >=0 is returned where retval is the total + * Number of descriptors notified + * during this function call. + * @retval :: -1 is returned in case of some error + */ +int dequeue_jr(void *job_ring_handle, int32_t limit); + +#endif /* _JR_DRIVER_H_ */ diff --git a/include/drivers/nxp/csu/csu.h b/include/drivers/nxp/csu/csu.h new file mode 100644 index 0000000000..83f18345d4 --- /dev/null +++ b/include/drivers/nxp/csu/csu.h @@ -0,0 +1,42 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef CSU_H +#define CSU_H + +#define CSU_SEC_ACCESS_REG_OFFSET (0x0021CU) +/* Bit mask */ +#define TZASC_BYPASS_MUX_DISABLE (0x4U) + +/* Macros defining access permissions to configure + * the regions controlled by Central Security Unit. + */ +enum csu_cslx_access { + CSU_NS_SUP_R = (0x8U), + CSU_NS_SUP_W = (0x80U), + CSU_NS_SUP_RW = (0x88U), + CSU_NS_USER_R = (0x4U), + CSU_NS_USER_W = (0x40U), + CSU_NS_USER_RW = (0x44U), + CSU_S_SUP_R = (0x2U), + CSU_S_SUP_W = (0x20U), + CSU_S_SUP_RW = (0x22U), + CSU_S_USER_R = (0x1U), + CSU_S_USER_W = (0x10U), + CSU_S_USER_RW = (0x11U), + CSU_ALL_RW = (0xffU), +}; + +struct csu_ns_dev_st { + uintptr_t ind; + uint32_t val; +}; + +void enable_layerscape_ns_access(struct csu_ns_dev_st *csu_ns_dev, + uint32_t num, uintptr_t nxp_csu_addr); + +#endif diff --git a/include/drivers/nxp/dcfg/dcfg.h b/include/drivers/nxp/dcfg/dcfg.h new file mode 100644 index 0000000000..ee8f866c53 --- /dev/null +++ b/include/drivers/nxp/dcfg/dcfg.h @@ -0,0 +1,103 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DCFG_H +#define DCFG_H + +#include <endian.h> + +#if defined(CONFIG_CHASSIS_2) +#include <dcfg_lsch2.h> +#elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3) +#include <dcfg_lsch3.h> +#endif + +#ifdef NXP_GUR_BE +#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#elif defined(NXP_GUR_LE) +#define gur_in32(a) mmio_read_32((uintptr_t)(a)) +#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v) +#else +#error Please define CCSR GUR register endianness +#endif + +typedef struct { + union { + uint32_t val; + struct { + uint32_t min_ver:4; + uint32_t maj_ver:4; +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) + uint32_t personality:6; + uint32_t rsv1:2; +#elif defined(CONFIG_CHASSIS_2) + uint32_t personality:8; + +#endif +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) + uint32_t dev_id:6; + uint32_t rsv2:2; + uint32_t family:4; +#elif defined(CONFIG_CHASSIS_2) + uint32_t dev_id:12; +#endif + uint32_t mfr_id; + } __packed bf; + struct { + uint32_t maj_min:8; + uint32_t version; /* SoC version without major and minor info */ + } __packed bf_ver; + } __packed svr_reg; + bool sec_enabled; + bool is_populated; +} soc_info_t; + +typedef struct { + bool is_populated; + uint8_t ocram_present; + uint8_t ddrc1_present; +#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) + uint8_t ddrc2_present; +#endif +} devdisr5_info_t; + +typedef struct { + uint32_t porsr1; + uintptr_t g_nxp_dcfg_addr; + unsigned long nxp_sysclk_freq; + unsigned long nxp_ddrclk_freq; + unsigned int nxp_plat_clk_divider; +} dcfg_init_info_t; + + +struct sysinfo { + unsigned long freq_platform; + unsigned long freq_ddr_pll0; + unsigned long freq_ddr_pll1; +}; + +int get_clocks(struct sysinfo *sys); + +/* Read the PORSR1 register */ +uint32_t read_reg_porsr1(void); + +/******************************************************************************* + * Returns true if secur eboot is enabled on board + * mode = 0 (development mode - sb_en = 1) + * mode = 1 (production mode - ITS = 1) + ******************************************************************************/ +bool check_boot_mode_secure(uint32_t *mode); + +const soc_info_t *get_soc_info(void); +const devdisr5_info_t *get_devdisr5_info(void); + +void dcfg_init(dcfg_init_info_t *dcfg_init_data); +bool is_sec_enabled(void); + +void error_handler(int error_code); +#endif /* DCFG_H */ diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h new file mode 100644 index 0000000000..bdef6deba3 --- /dev/null +++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h @@ -0,0 +1,85 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DCFG_LSCH2_H +#define DCFG_LSCH2_H + +/* dcfg block register offsets and bitfields */ +#define DCFG_PORSR1_OFFSET 0x00 +#define DCFG_DEVDISR1_OFFSET 0x070 +#define DCFG_DEVDISR2_OFFSET 0x074 +#define DCFG_DEVDISR3_OFFSET 0x078 +#define DCFG_DEVDISR4_OFFSET 0x07C +#define DCFG_DEVDISR5_OFFSET 0x080 +#define DCFG_COREDISR_OFFSET 0x094 +#define RCWSR0_OFFSET 0x100 +#define RCWSR5_OFFSET 0x118 +#define DCFG_BOOTLOCPTRL_OFFSET 0x400 +#define DCFG_BOOTLOCPTRH_OFFSET 0x404 +#define DCFG_COREDISABLEDSR_OFFSET 0x990 +#define DCFG_SCRATCH4_OFFSET 0x20C +#define DCFG_SVR_OFFSET 0x0A4 +#define DCFG_BRR_OFFSET 0x0E4 + +#define DCFG_RSTCR_OFFSET 0x0B0 +#define RSTCR_RESET_REQ 0x2 + +#define DCFG_RSTRQSR1_OFFSET 0x0C8 +#define DCFG_RSTRQMR1_OFFSET 0x0C0 + +/* PORSR1 bit mask */ +#define PORSR1_RCW_MASK 0xff800000 +#define PORSR1_RCW_SHIFT 23 + +/* DCFG DCSR Macros */ +#define DCFG_DCSR_PORCR1_OFFSET 0x0 + +#define SVR_MFR_ID_MASK 0xF0000000 +#define SVR_MFR_ID_SHIFT 28 +#define SVR_DEV_ID_MASK 0xFFF0000 +#define SVR_DEV_ID_SHIFT 16 +#define SVR_PERSONALITY_MASK 0xFF00 +#define SVR_PERSONALITY_SHIFT 8 +#define SVR_SEC_MASK 0x100 +#define SVR_SEC_SHIFT 8 +#define SVR_MAJ_VER_MASK 0xF0 +#define SVR_MAJ_VER_SHIFT 4 +#define SVR_MIN_VER_MASK 0xF +#define SVR_MINOR_VER_0 0x00 +#define SVR_MINOR_VER_1 0x01 + +#define DISR5_DDRC1_MASK 0x1 +#define DISR5_OCRAM_MASK 0x40 + +/* DCFG registers bit masks */ +#define RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET +#define RCWSR_SBEN_MASK 0x1 +#define RCWSR_SBEN_SHIFT 21 + +/* RCW SRC NAND */ +#define RCW_SRC_NAND_MASK (0x100) +#define RCW_SRC_NAND_VAL (0x100) +#define NAND_RESERVED_MASK (0xFC) +#define NAND_RESERVED_1 (0x0) +#define NAND_RESERVED_2 (0x80) + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_MASK (0x1F0) +#define NOR_8B_VAL (0x10) +#define NOR_16B_VAL (0x20) +#define SD_VAL (0x40) +#define QSPI_VAL1 (0x44) +#define QSPI_VAL2 (0x45) + +#endif /* DCFG_LSCH2_H */ diff --git a/include/drivers/nxp/dcfg/dcfg_lsch3.h b/include/drivers/nxp/dcfg/dcfg_lsch3.h new file mode 100644 index 0000000000..cde86fe19b --- /dev/null +++ b/include/drivers/nxp/dcfg/dcfg_lsch3.h @@ -0,0 +1,80 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DCFG_LSCH3_H +#define DCFG_LSCH3_H + +/* dcfg block register offsets and bitfields */ +#define DCFG_PORSR1_OFFSET 0x00 + +#define DCFG_DEVDISR1_OFFSET 0x70 +#define DCFG_DEVDISR1_SEC (1 << 22) + +#define DCFG_DEVDISR2_OFFSET 0x74 + +#define DCFG_DEVDISR3_OFFSET 0x78 +#define DCFG_DEVDISR3_QBMAIN (1 << 12) + +#define DCFG_DEVDISR4_OFFSET 0x7C +#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5) + +#define DCFG_DEVDISR5_OFFSET 0x80 +#define DISR5_DDRC1_MASK 0x1 +#define DISR5_DDRC2_MASK 0x2 +#define DISR5_OCRAM_MASK 0x1000 +#define DEVDISR5_MASK_ALL_MEM 0x00001003 +#define DEVDISR5_MASK_DDR 0x00000003 +#define DEVDISR5_MASK_DBG 0x00000400 + +#define DCFG_DEVDISR6_OFFSET 0x84 +//#define DEVDISR6_MASK 0x00000001 + +#define DCFG_COREDISR_OFFSET 0x94 + +#define DCFG_SVR_OFFSET 0x0A4 +#define SVR_MFR_ID_MASK 0xF0000000 +#define SVR_MFR_ID_SHIFT 28 +#define SVR_FAMILY_MASK 0xF000000 +#define SVR_FAMILY_SHIFT 24 +#define SVR_DEV_ID_MASK 0x3F0000 +#define SVR_DEV_ID_SHIFT 16 +#define SVR_PERSONALITY_MASK 0x3E00 +#define SVR_PERSONALITY_SHIFT 9 +#define SVR_SEC_MASK 0x100 +#define SVR_SEC_SHIFT 8 +#define SVR_MAJ_VER_MASK 0xF0 +#define SVR_MAJ_VER_SHIFT 4 +#define SVR_MIN_VER_MASK 0xF + +#define RCWSR0_OFFSET 0x100 +#define RCWSR0_SYS_PLL_RAT_SHIFT 2 +#define RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define RCWSR0_MEM_PLL_RAT_SHIFT 10 +#define RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#define RCWSR5_OFFSET 0x110 +#define RCWSR9_OFFSET 0x120 +#define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET +#define RCWSR_SBEN_MASK 0x1 +#define RCWSR_SBEN_SHIFT 10 + +#define RCW_SR27_OFFSET 0x168 +/* DCFG register to dump error code */ +#define DCFG_SCRATCH4_OFFSET 0x20C +#define DCFG_SCRATCHRW5_OFFSET 0x210 +#define DCFG_SCRATCHRW6_OFFSET 0x214 +#define DCFG_SCRATCHRW7_OFFSET 0x218 +#define DCFG_BOOTLOCPTRL_OFFSET 0x400 +#define DCFG_BOOTLOCPTRH_OFFSET 0x404 +#define DCFG_COREDISABLEDSR_OFFSET 0x990 + +/* Reset module bit field */ +#define RSTCR_RESET_REQ 0x2 + +#endif /* DCFG_LSCH3_H */ diff --git a/include/drivers/nxp/dcfg/scfg.h b/include/drivers/nxp/dcfg/scfg.h new file mode 100644 index 0000000000..8067de10ac --- /dev/null +++ b/include/drivers/nxp/dcfg/scfg.h @@ -0,0 +1,65 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef SCFG_H +#define SCFG_H + +#ifdef CONFIG_CHASSIS_2 + +/* SCFG register offsets */ +#define SCFG_CORE0_SFT_RST_OFFSET 0x0130 +#define SCFG_SNPCNFGCR_OFFSET 0x01A4 +#define SCFG_CORESRENCR_OFFSET 0x0204 +#define SCFG_RVBAR0_0_OFFSET 0x0220 +#define SCFG_RVBAR0_1_OFFSET 0x0224 +#define SCFG_COREBCR_OFFSET 0x0680 +#define SCFG_RETREQCR_OFFSET 0x0424 + +#define SCFG_COREPMCR_OFFSET 0x042C +#define COREPMCR_WFIL2 0x1 + +#define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188 +#define SCFG_BOOTLOCPTRH_OFFSET 0x0600 +#define SCFG_BOOTLOCPTRL_OFFSET 0x0604 +#define SCFG_SCRATCHRW2_OFFSET 0x0608 +#define SCFG_SCRATCHRW3_OFFSET 0x060C + +/* SCFG bit fields */ +#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 +#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 + +/* GIC Address Align Register */ +#define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK 0x80000000 +#define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN 0x80000000 +#define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS 0x0 + +#endif /* CONFIG_CHASSIS_2 */ + +#ifndef __ASSEMBLER__ +#include <endian.h> +#include <lib/mmio.h> + +#ifdef NXP_SCFG_BE +#define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) +#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) +#define scfg_clrsetbits32(a, clear, set) \ + mmio_clrsetbits_32((uintptr_t)(a), clear, set) +#elif defined(NXP_SCFG_LE) +#define scfg_in32(a) mmio_read_32((uintptr_t)(a)) +#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v) +#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) +#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) +#define scfg_clrsetbits32(a, clear, set) \ + mmio_clrsetbits_32((uintptr_t)(a), clear, set) +#else +#error Please define CCSR SCFG register endianness +#endif +#endif /* __ASSEMBLER__ */ + +#endif /* SCFG_H */ diff --git a/include/drivers/nxp/ddr/ddr.h b/include/drivers/nxp/ddr/ddr.h new file mode 100644 index 0000000000..0ef28706fb --- /dev/null +++ b/include/drivers/nxp/ddr/ddr.h @@ -0,0 +1,151 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DDR_H +#define DDR_H + +#include "ddr_io.h" +#include "dimm.h" +#include "immap.h" + +#ifndef DDRC_NUM_CS +#define DDRC_NUM_CS 4 +#endif + +/* + * This is irrespective of what is the number of DDR controller, + * number of DIMM used. This is set to maximum + * Max controllers = 2 + * Max num of DIMM per controlle = 2 + * MAX NUM CS = 4 + * Not to be changed. + */ +#define MAX_DDRC_NUM 2 +#define MAX_DIMM_NUM 2 +#define MAX_CS_NUM 4 + +#include "opts.h" +#include "regs.h" +#include "utility.h" + +#ifdef DDR_DEBUG +#define debug(...) INFO(__VA_ARGS__) +#else +#define debug(...) VERBOSE(__VA_ARGS__) +#endif + +#ifndef DDRC_NUM_DIMM +#define DDRC_NUM_DIMM 1 +#endif + +#define CONFIG_CS_PER_SLOT \ + (DDRC_NUM_CS / DDRC_NUM_DIMM) + +/* Record of register values computed */ +struct ddr_cfg_regs { + struct { + unsigned int bnds; + unsigned int config; + unsigned int config_2; + } cs[MAX_CS_NUM]; + unsigned int dec[10]; + unsigned int timing_cfg[10]; + unsigned int sdram_cfg[3]; + unsigned int sdram_mode[16]; + unsigned int md_cntl; + unsigned int interval; + unsigned int data_init; + unsigned int clk_cntl; + unsigned int init_addr; + unsigned int init_ext_addr; + unsigned int zq_cntl; + unsigned int wrlvl_cntl[3]; + unsigned int ddr_sr_cntr; + unsigned int sdram_rcw[6]; + unsigned int dq_map[4]; + unsigned int eor; + unsigned int cdr[2]; + unsigned int err_disable; + unsigned int err_int_en; + unsigned int tx_cfg[4]; + unsigned int debug[64]; +}; + +struct ddr_conf { + int dimm_in_use[MAX_DIMM_NUM]; + int cs_in_use; /* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */ + int cs_on_dimm[MAX_DIMM_NUM]; /* bitmask */ + unsigned long long cs_base_addr[MAX_CS_NUM]; + unsigned long long cs_size[MAX_CS_NUM]; + unsigned long long base_addr; + unsigned long long total_mem; +}; + +struct ddr_info { + unsigned long clk; + unsigned long long mem_base; + unsigned int num_ctlrs; + unsigned int dimm_on_ctlr; + struct dimm_params dimm; + struct memctl_opt opt; + struct ddr_conf conf; + struct ddr_cfg_regs ddr_reg; + struct ccsr_ddr *ddr[MAX_DDRC_NUM]; + uint16_t *phy[MAX_DDRC_NUM]; + int *spd_addr; + unsigned int ip_rev; + uintptr_t phy_gen2_fw_img_buf; + void *img_loadr; + int warm_boot_flag; +}; + +struct rc_timing { + unsigned int speed_bin; + unsigned int clk_adj; + unsigned int wrlvl; +}; + +struct board_timing { + unsigned int rc; + struct rc_timing const *p; + unsigned int add1; + unsigned int add2; +}; + +enum warm_boot { + DDR_COLD_BOOT = 0, + DDR_WARM_BOOT = 1, + DDR_WRM_BOOT_NT_SUPPORTED = -1, +}; + +int disable_unused_ddrc(struct ddr_info *priv, int mask, + uintptr_t nxp_ccn_hn_f0_addr); +int ddr_board_options(struct ddr_info *priv); +int compute_ddrc(const unsigned long clk, + const struct memctl_opt *popts, + const struct ddr_conf *conf, + struct ddr_cfg_regs *ddr, + const struct dimm_params *dimm_params, + const unsigned int ip_rev); +int compute_ddr_phy(struct ddr_info *priv); +int ddrc_set_regs(const unsigned long clk, + const struct ddr_cfg_regs *regs, + const struct ccsr_ddr *ddr, + int twopass); +int cal_board_params(struct ddr_info *priv, + const struct board_timing *dimm, + int len); +/* return bit mask of used DIMM(s) */ +int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf); +long long dram_init(struct ddr_info *priv +#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508) + , uintptr_t nxp_ccn_hn_f0_addr +#endif + ); +long long board_static_ddr(struct ddr_info *info); + +#endif /* DDR_H */ diff --git a/include/drivers/nxp/ddr/ddr_io.h b/include/drivers/nxp/ddr/ddr_io.h new file mode 100644 index 0000000000..fbd7e974d5 --- /dev/null +++ b/include/drivers/nxp/ddr/ddr_io.h @@ -0,0 +1,38 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DDR_IO_H +#define DDR_IO_H + +#include <endian.h> + +#include <lib/mmio.h> + +#define min(a, b) (((a) > (b)) ? (b) : (a)) + +#define max(a, b) (((a) > (b)) ? (a) : (b)) + +/* macro for memory barrier */ +#define mb() asm volatile("dsb sy" : : : "memory") + +#ifdef NXP_DDR_BE +#define ddr_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a),\ + bswap32(v)) +#elif defined(NXP_DDR_LE) +#define ddr_in32(a) mmio_read_32((uintptr_t)(a)) +#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a), v) +#else +#error Please define CCSR DDR register endianness +#endif + +#define ddr_setbits32(a, v) ddr_out32((a), ddr_in32(a) | (v)) +#define ddr_clrbits32(a, v) ddr_out32((a), ddr_in32(a) & ~(v)) +#define ddr_clrsetbits32(a, c, s) ddr_out32((a), (ddr_in32(a) & ~(c)) \ + | (s)) + +#endif /* DDR_IO_H */ diff --git a/include/drivers/nxp/ddr/dimm.h b/include/drivers/nxp/ddr/dimm.h new file mode 100644 index 0000000000..fcae179845 --- /dev/null +++ b/include/drivers/nxp/ddr/dimm.h @@ -0,0 +1,330 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DIMM_H +#define DIMM_H + +#define SPD_MEMTYPE_DDR4 0x0C + +#define DDR4_SPD_MODULETYPE_MASK 0x0f +#define DDR4_SPD_MODULETYPE_EXT 0x00 +#define DDR4_SPD_RDIMM 0x01 +#define DDR4_SPD_UDIMM 0x02 +#define DDR4_SPD_SO_DIMM 0x03 +#define DDR4_SPD_LRDIMM 0x04 +#define DDR4_SPD_MINI_RDIMM 0x05 +#define DDR4_SPD_MINI_UDIMM 0x06 +#define DDR4_SPD_72B_SO_RDIMM 0x08 +#define DDR4_SPD_72B_SO_UDIMM 0x09 +#define DDR4_SPD_16B_SO_DIMM 0x0c +#define DDR4_SPD_32B_SO_DIMM 0x0d + +#define SPD_SPA0_ADDRESS 0x36 +#define SPD_SPA1_ADDRESS 0x37 + +#define spd_to_ps(mtb, ftb) \ + ((mtb) * pdimm->mtb_ps + ((ftb) * pdimm->ftb_10th_ps) / 10) + +#ifdef DDR_DEBUG +#define dump_spd(spd, len) { \ + register int i; \ + register unsigned char *buf = (void *)(spd); \ + \ + for (i = 0; i < (len); i++) { \ + print_uint(i); \ + puts("\t: 0x"); \ + print_hex(buf[i]); \ + puts("\n"); \ + } \ +} +#else +#define dump_spd(spd, len) {} +#endif + +/* From JEEC Standard No. 21-C release 23A */ +struct ddr4_spd { + /* General Section: Bytes 0-127 */ + unsigned char info_size_crc; /* 0 # bytes */ + unsigned char spd_rev; /* 1 Total # bytes of SPD */ + unsigned char mem_type; /* 2 Key Byte / mem type */ + unsigned char module_type; /* 3 Key Byte / Module Type */ + unsigned char density_banks; /* 4 Density and Banks */ + unsigned char addressing; /* 5 Addressing */ + unsigned char package_type; /* 6 Package type */ + unsigned char opt_feature; /* 7 Optional features */ + unsigned char thermal_ref; /* 8 Thermal and refresh */ + unsigned char oth_opt_features; /* 9 Other optional features */ + unsigned char res_10; /* 10 Reserved */ + unsigned char module_vdd; /* 11 Module nominal voltage */ + unsigned char organization; /* 12 Module Organization */ + unsigned char bus_width; /* 13 Module Memory Bus Width */ + unsigned char therm_sensor; /* 14 Module Thermal Sensor */ + unsigned char ext_type; /* 15 Extended module type */ + unsigned char res_16; + unsigned char timebases; /* 17 MTb and FTB */ + unsigned char tck_min; /* 18 tCKAVGmin */ + unsigned char tck_max; /* 19 TCKAVGmax */ + unsigned char caslat_b1; /* 20 CAS latencies, 1st byte */ + unsigned char caslat_b2; /* 21 CAS latencies, 2nd byte */ + unsigned char caslat_b3; /* 22 CAS latencies, 3rd byte */ + unsigned char caslat_b4; /* 23 CAS latencies, 4th byte */ + unsigned char taa_min; /* 24 Min CAS Latency Time */ + unsigned char trcd_min; /* 25 Min RAS# to CAS# Delay Time */ + unsigned char trp_min; /* 26 Min Row Precharge Delay Time */ + unsigned char tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ + unsigned char tras_min_lsb; /* 28 tRASmin, lsb */ + unsigned char trc_min_lsb; /* 29 tRCmin, lsb */ + unsigned char trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ + unsigned char trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ + unsigned char trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ + unsigned char trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ + unsigned char trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ + unsigned char trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ + unsigned char tfaw_msb; /* 36 Upper Nibble for tFAW */ + unsigned char tfaw_min; /* 37 tFAW, lsb */ + unsigned char trrds_min; /* 38 tRRD_Smin, MTB */ + unsigned char trrdl_min; /* 39 tRRD_Lmin, MTB */ + unsigned char tccdl_min; /* 40 tCCS_Lmin, MTB */ + unsigned char res_41[60-41]; /* 41 Rserved */ + unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ + unsigned char res_78[117-78]; /* 78~116, Reserved */ + signed char fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ + signed char fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ + signed char fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ + signed char fine_trc_min; /* 120 Fine offset for tRCmin */ + signed char fine_trp_min; /* 121 Fine offset for tRPmin */ + signed char fine_trcd_min; /* 122 Fine offset for tRCDmin */ + signed char fine_taa_min; /* 123 Fine offset for tAAmin */ + signed char fine_tck_max; /* 124 Fine offset for tCKAVGmax */ + signed char fine_tck_min; /* 125 Fine offset for tCKAVGmin */ + /* CRC: Bytes 126-127 */ + unsigned char crc[2]; /* 126-127 SPD CRC */ + + /* Module-Specific Section: Bytes 128-255 */ + union { + struct { + /* 128 (Unbuffered) Module Nominal Height */ + unsigned char mod_height; + /* 129 (Unbuffered) Module Maximum Thickness */ + unsigned char mod_thickness; + /* 130 (Unbuffered) Reference Raw Card Used */ + unsigned char ref_raw_card; + /* 131 (Unbuffered) Address Mapping from + * Edge Connector to DRAM + */ + unsigned char addr_mapping; + /* 132~253 (Unbuffered) Reserved */ + unsigned char res_132[254-132]; + /* 254~255 CRC */ + unsigned char crc[2]; + } unbuffered; + struct { + /* 128 (Registered) Module Nominal Height */ + unsigned char mod_height; + /* 129 (Registered) Module Maximum Thickness */ + unsigned char mod_thickness; + /* 130 (Registered) Reference Raw Card Used */ + unsigned char ref_raw_card; + /* 131 DIMM Module Attributes */ + unsigned char modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + unsigned char thermal; + /* 133 Register Manufacturer ID Code, LSB */ + unsigned char reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + unsigned char reg_id_hi; + /* 135 Register Revision Number */ + unsigned char reg_rev; + /* 136 Address mapping from register to DRAM */ + unsigned char reg_map; + unsigned char ca_stren; + unsigned char clk_stren; + /* 139~253 Reserved */ + unsigned char res_139[254-139]; + /* 254~255 CRC */ + unsigned char crc[2]; + } registered; + struct { + /* 128 (Loadreduced) Module Nominal Height */ + unsigned char mod_height; + /* 129 (Loadreduced) Module Maximum Thickness */ + unsigned char mod_thickness; + /* 130 (Loadreduced) Reference Raw Card Used */ + unsigned char ref_raw_card; + /* 131 DIMM Module Attributes */ + unsigned char modu_attr; + /* 132 RDIMM Thermal Heat Spreader Solution */ + unsigned char thermal; + /* 133 Register Manufacturer ID Code, LSB */ + unsigned char reg_id_lo; + /* 134 Register Manufacturer ID Code, MSB */ + unsigned char reg_id_hi; + /* 135 Register Revision Number */ + unsigned char reg_rev; + /* 136 Address mapping from register to DRAM */ + unsigned char reg_map; + /* 137 Register Output Drive Strength for CMD/Add*/ + unsigned char reg_drv; + /* 138 Register Output Drive Strength for CK */ + unsigned char reg_drv_ck; + /* 139 Data Buffer Revision Number */ + unsigned char data_buf_rev; + /* 140 DRAM VrefDQ for Package Rank 0 */ + unsigned char vrefqe_r0; + /* 141 DRAM VrefDQ for Package Rank 1 */ + unsigned char vrefqe_r1; + /* 142 DRAM VrefDQ for Package Rank 2 */ + unsigned char vrefqe_r2; + /* 143 DRAM VrefDQ for Package Rank 3 */ + unsigned char vrefqe_r3; + /* 144 Data Buffer VrefDQ for DRAM Interface */ + unsigned char data_intf; + /* + * 145 Data Buffer MDQ Drive Strength and RTT + * for data rate <= 1866 + */ + unsigned char data_drv_1866; + /* + * 146 Data Buffer MDQ Drive Strength and RTT + * for 1866 < data rate <= 2400 + */ + unsigned char data_drv_2400; + /* + * 147 Data Buffer MDQ Drive Strength and RTT + * for 2400 < data rate <= 3200 + */ + unsigned char data_drv_3200; + /* 148 DRAM Drive Strength */ + unsigned char dram_drv; + /* + * 149 DRAM ODT (RTT_WR, RTT_NOM) + * for data rate <= 1866 + */ + unsigned char dram_odt_1866; + /* + * 150 DRAM ODT (RTT_WR, RTT_NOM) + * for 1866 < data rate <= 2400 + */ + unsigned char dram_odt_2400; + /* + * 151 DRAM ODT (RTT_WR, RTT_NOM) + * for 2400 < data rate <= 3200 + */ + unsigned char dram_odt_3200; + /* + * 152 DRAM ODT (RTT_PARK) + * for data rate <= 1866 + */ + unsigned char dram_odt_park_1866; + /* + * 153 DRAM ODT (RTT_PARK) + * for 1866 < data rate <= 2400 + */ + unsigned char dram_odt_park_2400; + /* + * 154 DRAM ODT (RTT_PARK) + * for 2400 < data rate <= 3200 + */ + unsigned char dram_odt_park_3200; + unsigned char res_155[254-155]; /* Reserved */ + /* 254~255 CRC */ + unsigned char crc[2]; + } loadreduced; + unsigned char uc[128]; /* 128-255 Module-Specific Section */ + } mod_section; + + unsigned char res_256[320-256]; /* 256~319 Reserved */ + + /* Module supplier's data: Byte 320~383 */ + unsigned char mmid_lsb; /* 320 Module MfgID Code LSB */ + unsigned char mmid_msb; /* 321 Module MfgID Code MSB */ + unsigned char mloc; /* 322 Mfg Location */ + unsigned char mdate[2]; /* 323~324 Mfg Date */ + unsigned char sernum[4]; /* 325~328 Module Serial Number */ + unsigned char mpart[20]; /* 329~348 Mfg's Module Part Number */ + unsigned char mrev; /* 349 Module Revision Code */ + unsigned char dmid_lsb; /* 350 DRAM MfgID Code LSB */ + unsigned char dmid_msb; /* 351 DRAM MfgID Code MSB */ + unsigned char stepping; /* 352 DRAM stepping */ + unsigned char msd[29]; /* 353~381 Mfg's Specific Data */ + unsigned char res_382[2]; /* 382~383 Reserved */ +}; + +/* Parameters for a DDR dimm computed from the SPD */ +struct dimm_params { + /* DIMM organization parameters */ + char mpart[19]; /* guaranteed null terminated */ + + unsigned int n_ranks; + unsigned int die_density; + unsigned long long rank_density; + unsigned long long capacity; + unsigned int primary_sdram_width; + unsigned int ec_sdram_width; + unsigned int rdimm; + unsigned int package_3ds; /* number of dies in 3DS */ + unsigned int device_width; /* x4, x8, x16 components */ + unsigned int rc; + + /* SDRAM device parameters */ + unsigned int n_row_addr; + unsigned int n_col_addr; + unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ + unsigned int bank_addr_bits; + unsigned int bank_group_bits; + unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ + + /* mirrored DIMMs */ + unsigned int mirrored_dimm; /* only for ddr3 */ + + /* DIMM timing parameters */ + + int mtb_ps; /* medium timebase ps */ + int ftb_10th_ps; /* fine timebase, in 1/10 ps */ + int taa_ps; /* minimum CAS latency time */ + int tfaw_ps; /* four active window delay */ + + /* + * SDRAM clock periods + * The range for these are 1000-10000 so a short should be sufficient + */ + int tckmin_x_ps; + int tckmax_ps; + + /* SPD-defined CAS latencies */ + unsigned int caslat_x; + + /* basic timing parameters */ + int trcd_ps; + int trp_ps; + int tras_ps; + + int trfc1_ps; + int trfc2_ps; + int trfc4_ps; + int trrds_ps; + int trrdl_ps; + int tccdl_ps; + int trfc_slr_ps; + + int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + int twr_ps; /* 15ns for all speed bins */ + + unsigned int refresh_rate_ps; + unsigned int extended_op_srt; + + /* RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ + unsigned int dq_mapping[18]; + unsigned int dq_mapping_ors; +}; + +int read_spd(unsigned char chip, void *buf, int len); +int crc16(unsigned char *ptr, int count); +int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm); + +#endif /* DIMM_H */ diff --git a/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h b/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h new file mode 100644 index 0000000000..31db55230e --- /dev/null +++ b/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h @@ -0,0 +1,173 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_MMDC_H +#define FSL_MMDC_H + +/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */ +#define MPWLGCR_HW_WL_EN (1 << 0) + +/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ +#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0) + + +/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ +#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28) + +/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ +#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4) + +/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */ +#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067 + +/* MMDC Core Refresh Control Register (MMDC_MDREF) */ +#define MDREF_START_REFRESH (1 << 0) + +/* MMDC Core Special Command Register (MDSCR) */ +#define CMD_ADDR_MSB_MR_OP(x) (x << 24) +#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) +#define MDSCR_DISABLE_CFG_REQ (0 << 15) +#define MDSCR_ENABLE_CON_REQ (1 << 15) +#define MDSCR_CON_ACK (1 << 14) +#define MDSCR_WL_EN (1 << 9) +#define CMD_NORMAL (0 << 4) +#define CMD_PRECHARGE (1 << 4) +#define CMD_AUTO_REFRESH (2 << 4) +#define CMD_LOAD_MODE_REG (3 << 4) +#define CMD_ZQ_CALIBRATION (4 << 4) +#define CMD_PRECHARGE_BANK_OPEN (5 << 4) +#define CMD_MRR (6 << 4) +#define CMD_BANK_ADDR_0 0x0 +#define CMD_BANK_ADDR_1 0x1 +#define CMD_BANK_ADDR_2 0x2 +#define CMD_BANK_ADDR_3 0x3 +#define CMD_BANK_ADDR_4 0x4 +#define CMD_BANK_ADDR_5 0x5 +#define CMD_BANK_ADDR_6 0x6 +#define CMD_BANK_ADDR_7 0x7 + +/* MMDC Core Control Register (MDCTL) */ +#define MDCTL_SDE0 (U(1) << 31) +#define MDCTL_SDE1 (1 << 30) + +/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */ +#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16) + +/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */ +#define MMDC_MPMUR0_FRC_MSR (1 << 11) + +/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */ +/* default 64 for a quarter cycle delay */ +#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040 + +/* MMDC Registers */ +struct mmdc_regs { + unsigned int mdctl; + unsigned int mdpdc; + unsigned int mdotc; + unsigned int mdcfg0; + unsigned int mdcfg1; + unsigned int mdcfg2; + unsigned int mdmisc; + unsigned int mdscr; + unsigned int mdref; + unsigned int res1[2]; + unsigned int mdrwd; + unsigned int mdor; + unsigned int mdmrr; + unsigned int mdcfg3lp; + unsigned int mdmr4; + unsigned int mdasp; + unsigned int res2[239]; + unsigned int maarcr; + unsigned int mapsr; + unsigned int maexidr0; + unsigned int maexidr1; + unsigned int madpcr0; + unsigned int madpcr1; + unsigned int madpsr0; + unsigned int madpsr1; + unsigned int madpsr2; + unsigned int madpsr3; + unsigned int madpsr4; + unsigned int madpsr5; + unsigned int masbs0; + unsigned int masbs1; + unsigned int res3[2]; + unsigned int magenp; + unsigned int res4[239]; + unsigned int mpzqhwctrl; + unsigned int mpzqswctrl; + unsigned int mpwlgcr; + unsigned int mpwldectrl0; + unsigned int mpwldectrl1; + unsigned int mpwldlst; + unsigned int mpodtctrl; + unsigned int mprddqby0dl; + unsigned int mprddqby1dl; + unsigned int mprddqby2dl; + unsigned int mprddqby3dl; + unsigned int mpwrdqby0dl; + unsigned int mpwrdqby1dl; + unsigned int mpwrdqby2dl; + unsigned int mpwrdqby3dl; + unsigned int mpdgctrl0; + unsigned int mpdgctrl1; + unsigned int mpdgdlst0; + unsigned int mprddlctl; + unsigned int mprddlst; + unsigned int mpwrdlctl; + unsigned int mpwrdlst; + unsigned int mpsdctrl; + unsigned int mpzqlp2ctl; + unsigned int mprddlhwctl; + unsigned int mpwrdlhwctl; + unsigned int mprddlhwst0; + unsigned int mprddlhwst1; + unsigned int mpwrdlhwst0; + unsigned int mpwrdlhwst1; + unsigned int mpwlhwerr; + unsigned int mpdghwst0; + unsigned int mpdghwst1; + unsigned int mpdghwst2; + unsigned int mpdghwst3; + unsigned int mppdcmpr1; + unsigned int mppdcmpr2; + unsigned int mpswdar0; + unsigned int mpswdrdr0; + unsigned int mpswdrdr1; + unsigned int mpswdrdr2; + unsigned int mpswdrdr3; + unsigned int mpswdrdr4; + unsigned int mpswdrdr5; + unsigned int mpswdrdr6; + unsigned int mpswdrdr7; + unsigned int mpmur0; + unsigned int mpwrcadl; + unsigned int mpdccr; +}; + +struct fsl_mmdc_info { + unsigned int mdctl; + unsigned int mdpdc; + unsigned int mdotc; + unsigned int mdcfg0; + unsigned int mdcfg1; + unsigned int mdcfg2; + unsigned int mdmisc; + unsigned int mdref; + unsigned int mdrwd; + unsigned int mdor; + unsigned int mdasp; + unsigned int mpodtctrl; + unsigned int mpzqhwctrl; + unsigned int mprddlctl; +}; + +void mmdc_init(const struct fsl_mmdc_info *priv, uintptr_t nxp_ddr_addr); + +#endif /* FSL_MMDC_H */ diff --git a/include/drivers/nxp/ddr/immap.h b/include/drivers/nxp/ddr/immap.h new file mode 100644 index 0000000000..83b4de6ef7 --- /dev/null +++ b/include/drivers/nxp/ddr/immap.h @@ -0,0 +1,125 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DDR_IMMAP_H +#define DDR_IMMAP_H + +#define DDR_DBUS_64 0 +#define DDR_DBUS_32 1 +#define DDR_DBUS_16 2 + +/* + * DDRC register file for DDRC 5.0 and above + */ +struct ccsr_ddr { + struct { + unsigned int a; /* 0x0, 0x8, 0x10, 0x18 */ + unsigned int res; /* 0x4, 0xc, 0x14, 0x1c */ + } bnds[4]; + unsigned char res_20[0x40 - 0x20]; + unsigned int dec[10]; /* 0x40 */ + unsigned char res_68[0x80 - 0x68]; + unsigned int csn_cfg[4]; /* 0x80, 0x84, 0x88, 0x8c */ + unsigned char res_90[48]; + unsigned int csn_cfg_2[4]; /* 0xc0, 0xc4, 0xc8, 0xcc */ + unsigned char res_d0[48]; + unsigned int timing_cfg_3; /* SDRAM Timing Configuration 3 */ + unsigned int timing_cfg_0; /* SDRAM Timing Configuration 0 */ + unsigned int timing_cfg_1; /* SDRAM Timing Configuration 1 */ + unsigned int timing_cfg_2; /* SDRAM Timing Configuration 2 */ + unsigned int sdram_cfg; /* SDRAM Control Configuration */ + unsigned int sdram_cfg_2; /* SDRAM Control Configuration 2 */ + unsigned int sdram_mode; /* SDRAM Mode Configuration */ + unsigned int sdram_mode_2; /* SDRAM Mode Configuration 2 */ + unsigned int sdram_md_cntl; /* SDRAM Mode Control */ + unsigned int sdram_interval; /* SDRAM Interval Configuration */ + unsigned int sdram_data_init; /* SDRAM Data initialization */ + unsigned char res_12c[4]; + unsigned int sdram_clk_cntl; /* SDRAM Clock Control */ + unsigned char res_134[20]; + unsigned int init_addr; /* training init addr */ + unsigned int init_ext_addr; /* training init extended addr */ + unsigned char res_150[16]; + unsigned int timing_cfg_4; /* SDRAM Timing Configuration 4 */ + unsigned int timing_cfg_5; /* SDRAM Timing Configuration 5 */ + unsigned int timing_cfg_6; /* SDRAM Timing Configuration 6 */ + unsigned int timing_cfg_7; /* SDRAM Timing Configuration 7 */ + unsigned int zq_cntl; /* ZQ calibration control*/ + unsigned int wrlvl_cntl; /* write leveling control*/ + unsigned char reg_178[4]; + unsigned int ddr_sr_cntr; /* self refresh counter */ + unsigned int ddr_sdram_rcw_1; /* Control Words 1 */ + unsigned int ddr_sdram_rcw_2; /* Control Words 2 */ + unsigned char reg_188[8]; + unsigned int ddr_wrlvl_cntl_2; /* write leveling control 2 */ + unsigned int ddr_wrlvl_cntl_3; /* write leveling control 3 */ + unsigned char res_198[0x1a0-0x198]; + unsigned int ddr_sdram_rcw_3; + unsigned int ddr_sdram_rcw_4; + unsigned int ddr_sdram_rcw_5; + unsigned int ddr_sdram_rcw_6; + unsigned char res_1b0[0x200-0x1b0]; + unsigned int sdram_mode_3; /* SDRAM Mode Configuration 3 */ + unsigned int sdram_mode_4; /* SDRAM Mode Configuration 4 */ + unsigned int sdram_mode_5; /* SDRAM Mode Configuration 5 */ + unsigned int sdram_mode_6; /* SDRAM Mode Configuration 6 */ + unsigned int sdram_mode_7; /* SDRAM Mode Configuration 7 */ + unsigned int sdram_mode_8; /* SDRAM Mode Configuration 8 */ + unsigned char res_218[0x220-0x218]; + unsigned int sdram_mode_9; /* SDRAM Mode Configuration 9 */ + unsigned int sdram_mode_10; /* SDRAM Mode Configuration 10 */ + unsigned int sdram_mode_11; /* SDRAM Mode Configuration 11 */ + unsigned int sdram_mode_12; /* SDRAM Mode Configuration 12 */ + unsigned int sdram_mode_13; /* SDRAM Mode Configuration 13 */ + unsigned int sdram_mode_14; /* SDRAM Mode Configuration 14 */ + unsigned int sdram_mode_15; /* SDRAM Mode Configuration 15 */ + unsigned int sdram_mode_16; /* SDRAM Mode Configuration 16 */ + unsigned char res_240[0x250-0x240]; + unsigned int timing_cfg_8; /* SDRAM Timing Configuration 8 */ + unsigned int timing_cfg_9; /* SDRAM Timing Configuration 9 */ + unsigned int timing_cfg_10; /* SDRAM Timing COnfigurtion 10 */ + unsigned char res_258[0x260-0x25c]; + unsigned int sdram_cfg_3; + unsigned char res_264[0x270-0x264]; + unsigned int sdram_md_cntl_2; + unsigned char res_274[0x400-0x274]; + unsigned int dq_map[4]; + unsigned char res_410[0x800-0x410]; + unsigned int tx_cfg[4]; + unsigned char res_810[0xb20-0x810]; + unsigned int ddr_dsr1; /* Debug Status 1 */ + unsigned int ddr_dsr2; /* Debug Status 2 */ + unsigned int ddr_cdr1; /* Control Driver 1 */ + unsigned int ddr_cdr2; /* Control Driver 2 */ + unsigned char res_b30[200]; + unsigned int ip_rev1; /* IP Block Revision 1 */ + unsigned int ip_rev2; /* IP Block Revision 2 */ + unsigned int eor; /* Enhanced Optimization Register */ + unsigned char res_c04[252]; + unsigned int mtcr; /* Memory Test Control Register */ + unsigned char res_d04[28]; + unsigned int mtp[10]; /* Memory Test Patterns */ + unsigned char res_d48[184]; + unsigned int data_err_inject_hi; /* Data Path Err Injection Mask Hi*/ + unsigned int data_err_inject_lo;/* Data Path Err Injection Mask Lo*/ + unsigned int ecc_err_inject; /* Data Path Err Injection Mask ECC */ + unsigned char res_e0c[20]; + unsigned int capture_data_hi; /* Data Path Read Capture High */ + unsigned int capture_data_lo; /* Data Path Read Capture Low */ + unsigned int capture_ecc; /* Data Path Read Capture ECC */ + unsigned char res_e2c[20]; + unsigned int err_detect; /* Error Detect */ + unsigned int err_disable; /* Error Disable */ + unsigned int err_int_en; + unsigned int capture_attributes; /* Error Attrs Capture */ + unsigned int capture_address; /* Error Addr Capture */ + unsigned int capture_ext_address; /* Error Extended Addr Capture */ + unsigned int err_sbe; /* Single-Bit ECC Error Management */ + unsigned char res_e5c[164]; + unsigned int debug[64]; /* debug_1 to debug_64 */ +}; +#endif /* DDR_IMMAP_H */ diff --git a/include/drivers/nxp/ddr/opts.h b/include/drivers/nxp/ddr/opts.h new file mode 100644 index 0000000000..f32891bc85 --- /dev/null +++ b/include/drivers/nxp/ddr/opts.h @@ -0,0 +1,119 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DDR_OPTS_H +#define DDR_OPTS_H + +#define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */ + +#define DDR_BC4 4 /* burst chop */ +#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ +#define DDR_BL8 8 /* burst length 8 */ + +#define DDR4_RTT_OFF 0 +#define DDR4_RTT_60_OHM 1 /* RZQ/4 */ +#define DDR4_RTT_120_OHM 2 /* RZQ/2 */ +#define DDR4_RTT_40_OHM 3 /* RZQ/6 */ +#define DDR4_RTT_240_OHM 4 /* RZQ/1 */ +#define DDR4_RTT_48_OHM 5 /* RZQ/5 */ +#define DDR4_RTT_80_OHM 6 /* RZQ/3 */ +#define DDR4_RTT_34_OHM 7 /* RZQ/7 */ +#define DDR4_RTT_WR_OFF 0 +#define DDR4_RTT_WR_120_OHM 1 +#define DDR4_RTT_WR_240_OHM 2 +#define DDR4_RTT_WR_HZ 3 +#define DDR4_RTT_WR_80_OHM 4 +#define DDR_ODT_NEVER 0x0 +#define DDR_ODT_CS 0x1 +#define DDR_ODT_ALL_OTHER_CS 0x2 +#define DDR_ODT_OTHER_DIMM 0x3 +#define DDR_ODT_ALL 0x4 +#define DDR_ODT_SAME_DIMM 0x5 +#define DDR_ODT_CS_AND_OTHER_DIMM 0x6 +#define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 +#define DDR_BA_INTLV_CS01 0x40 +#define DDR_BA_INTLV_CS0123 0x64 +#define DDR_BA_NONE 0 +#define DDR_256B_INTLV 0x8 + +struct memctl_opt { + int rdimm; + unsigned int dbw_cap_shift; + struct local_opts_s { + unsigned int auto_precharge; + unsigned int odt_rd_cfg; + unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; + } cs_odt[DDRC_NUM_CS]; + int ctlr_intlv; + unsigned int ctlr_intlv_mode; + unsigned int ba_intlv; + int addr_hash; + int ecc_mode; + int ctlr_init_ecc; + int self_refresh_in_sleep; + int self_refresh_irq_en; + int dynamic_power; + /* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ + unsigned int data_bus_dimm; + unsigned int data_bus_used; /* on individual board */ + unsigned int burst_length; /* BC4, OTF and BL8 */ + int otf_burst_chop_en; + int mirrored_dimm; + int quad_rank_present; + int output_driver_impedance; + int ap_en; + int x4_en; + + int caslat_override; + unsigned int caslat_override_value; + int addt_lat_override; + unsigned int addt_lat_override_value; + + unsigned int clk_adj; + unsigned int cpo_sample; + unsigned int wr_data_delay; + + unsigned int cswl_override; + unsigned int wrlvl_override; + unsigned int wrlvl_sample; + unsigned int wrlvl_start; + unsigned int wrlvl_ctl_2; + unsigned int wrlvl_ctl_3; + + int half_strength_drive_en; + int twot_en; + int threet_en; + unsigned int bstopre; + unsigned int tfaw_ps; + + int rtt_override; + unsigned int rtt_override_value; + unsigned int rtt_wr_override_value; + unsigned int rtt_park; + + int auto_self_refresh_en; + unsigned int sr_it; + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + + unsigned int trwt_override; + unsigned int trwt; + unsigned int twrt; + unsigned int trrt; + unsigned int twwt; + + unsigned int vref_phy; + unsigned int vref_dimm; + unsigned int odt; + unsigned int phy_tx_impedance; + unsigned int phy_atx_impedance; + unsigned int skip2d; +}; + +#endif /* DDR_OPTS_H */ diff --git a/include/drivers/nxp/ddr/regs.h b/include/drivers/nxp/ddr/regs.h new file mode 100644 index 0000000000..e85fd8fa85 --- /dev/null +++ b/include/drivers/nxp/ddr/regs.h @@ -0,0 +1,109 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DDR_REG_H +#define DDR_REG_H + +#define SDRAM_CS_CONFIG_EN 0x80000000 + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_SHIFT 19 +#define SDRAM_CFG_32_BW 0x00080000 +#define SDRAM_CFG_16_BW 0x00100000 +#define SDRAM_CFG_8_BW 0x00180000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_MEM_HLT 0x00000002 +#define SDRAM_CFG_BI 0x00000001 + +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG2_FRC_SR_CLEAR ~(SDRAM_CFG2_FRC_SR) +#define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_AP_EN 0x00000020 +#define SDRAM_CFG2_ODT_ONLY_READ 2 + +#define SDRAM_CFG3_DDRC_RST 0x80000000 + +#define SDRAM_INTERVAL_REFINT 0xFFFF0000 +#define SDRAM_INTERVAL_REFINT_CLEAR ~(SDRAM_INTERVAL_REFINT) +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF + +/* DDR_MD_CNTL */ +#define MD_CNTL_MD_EN 0x80000000 +#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) +#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) +#define MD_CNTL_CKE(x) (((x) & 0x3) << 20) + +/* DDR_CDR1 */ +#define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_ODT_SHIFT 17 +#define DDR_CDR1_ODT_MASK 0x6 +#define DDR_CDR2_ODT_MASK 0x1 +#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) +#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) +#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define DDR_CDR2_VREF_RANGE_2 0x00000040 +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_100ohm 0x1 +#define DDR_CDR_ODT_120OHM 0x2 +#define DDR_CDR_ODT_80ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x4 +#define DDR_CDR_ODT_40ohm 0x5 +#define DDR_CDR_ODT_50ohm 0x6 +#define DDR_CDR_ODT_30ohm 0x7 + + +/* DDR ERR_DISABLE */ +#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ +#define DDR_ERR_DISABLE_SBED (1 << 2) /* Address parity error disable */ +#define DDR_ERR_DISABLE_MBED (1 << 3) /* Address parity error disable */ + +/* Mode Registers */ +#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ +#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ + +/* DDR DSR2 register */ +#define DDR_DSR_2_PHY_INIT_CMPLT 0x4 + +/* SDRAM TIMING_CFG_10 register */ +#define DDR_TIMING_CFG_10_T_STAB 0x7FFF + +/* DEBUG 2 register */ +#define DDR_DBG_2_MEM_IDLE 0x00000002 + +/* DEBUG 26 register */ +#define DDR_DEBUG_26_BIT_6 (0x1 << 6) +#define DDR_DEBUG_26_BIT_7 (0x1 << 7) +#define DDR_DEBUG_26_BIT_12 (0x1 << 12) +#define DDR_DEBUG_26_BIT_13 (0x1 << 13) +#define DDR_DEBUG_26_BIT_14 (0x1 << 14) +#define DDR_DEBUG_26_BIT_15 (0x1 << 15) +#define DDR_DEBUG_26_BIT_16 (0x1 << 16) +#define DDR_DEBUG_26_BIT_17 (0x1 << 17) +#define DDR_DEBUG_26_BIT_18 (0x1 << 18) +#define DDR_DEBUG_26_BIT_19 (0x1 << 19) +#define DDR_DEBUG_26_BIT_24 (0x1 << 24) +#define DDR_DEBUG_26_BIT_25 (0x1 << 25) + +#define DDR_DEBUG_26_BIT_24_CLEAR ~(DDR_DEBUG_26_BIT_24) + +/* DEBUG_29 register */ +#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ + +#define DDR_INIT_ADDR_EXT_UIA (1 << 31) + +#endif /* DDR_REG_H */ diff --git a/include/drivers/nxp/ddr/utility.h b/include/drivers/nxp/ddr/utility.h new file mode 100644 index 0000000000..2e22ad5c36 --- /dev/null +++ b/include/drivers/nxp/ddr/utility.h @@ -0,0 +1,24 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef UTILITY_H +#define UTILITY_H + +#include <dcfg.h> + +#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508) +#define CCN_HN_F_SAM_CTL 0x8 +#define CCN_HN_F_REGION_SIZE 0x10000 +#endif + +unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num); +unsigned int get_memory_clk_ps(unsigned long clk); +unsigned int picos_to_mclk(unsigned long data_rate, unsigned int picos); +unsigned int get_ddrc_version(const struct ccsr_ddr *ddr); +void print_ddr_info(struct ccsr_ddr *ddr); + +#endif diff --git a/include/drivers/nxp/flexspi/flash_info.h b/include/drivers/nxp/flexspi/flash_info.h index 6df79c9613..d0ffc86b4f 100644 --- a/include/drivers/nxp/flexspi/flash_info.h +++ b/include/drivers/nxp/flexspi/flash_info.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ /** @@ -12,6 +12,7 @@ #define SZ_16M_BYTES 0x1000000U +/* Start of "if defined(CONFIG_MT25QU512A)" */ #if defined(CONFIG_MT25QU512A) #define F_SECTOR_64K 0x10000U #define F_PAGE_256 0x100U @@ -22,6 +23,9 @@ #define F_SECTOR_ERASE_SZ F_SECTOR_4K #endif +/* End of "if defined(CONFIG_MT25QU512A)" */ + +/* Start of "if defined(CONFIG_MX25U25645G)" */ #elif defined(CONFIG_MX25U25645G) #define F_SECTOR_64K 0x10000U #define F_PAGE_256 0x100U @@ -32,6 +36,9 @@ #define F_SECTOR_ERASE_SZ F_SECTOR_4K #endif +/* End of "if defined(CONFIG_MX25U25645G)" */ + +/* Start of "if defined(CONFIG_MX25U51245G)" */ #elif defined(CONFIG_MX25U51245G) #define F_SECTOR_64K 0x10000U #define F_PAGE_256 0x100U @@ -42,6 +49,9 @@ #define F_SECTOR_ERASE_SZ F_SECTOR_4K #endif +/* End of "if defined(CONFIG_MX25U51245G)" */ + +/* Start of "if defined(CONFIG_MT35XU512A)" */ #elif defined(CONFIG_MT35XU512A) #define F_SECTOR_128K 0x20000U #define F_SECTOR_32K 0x8000U @@ -52,10 +62,28 @@ #ifdef CONFIG_FSPI_4K_ERASE #define F_SECTOR_ERASE_SZ F_SECTOR_4K #endif - +/* If Warm boot is enabled for the platform, + * count of arm instruction N-OP(s) to mark + * the completion of write operation to flash; + * varies from one flash to other. + */ #ifdef NXP_WARM_BOOT #define FLASH_WR_COMP_WAIT_BY_NOP_COUNT 0x20000 #endif +/* End of "if defined(CONFIG_MT35XU512A)" */ + +/* Start of #elif defined(CONFIG_MT35XU02G) */ +#elif defined(CONFIG_MT35XU02G) +#define F_SECTOR_128K 0x20000U +#define F_PAGE_256 0x100U +#define F_SECTOR_4K 0x1000U +#define F_FLASH_SIZE_BYTES 0x10000000U +#define F_SECTOR_ERASE_SZ F_SECTOR_128K +#ifdef CONFIG_FSPI_4K_ERASE +#define F_SECTOR_ERASE_SZ F_SECTOR_4K #endif + +#endif /* End of #elif defined(CONFIG_MT35XU02G) */ + #endif /* FLASH_INFO_H */ diff --git a/include/drivers/nxp/gic/gicv2/plat_gic.h b/include/drivers/nxp/gic/gicv2/plat_gic.h new file mode 100644 index 0000000000..ff347440d6 --- /dev/null +++ b/include/drivers/nxp/gic/gicv2/plat_gic.h @@ -0,0 +1,72 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PLAT_GICV2_H +#define PLAT_GICV2_H + +#include <drivers/arm/gicv2.h> + + /* register offsets */ +#define GICD_CTLR_OFFSET 0x0 +#define GICD_CPENDSGIR3_OFFSET 0xF1C +#define GICD_SPENDSGIR3_OFFSET 0xF2C +#define GICD_SGIR_OFFSET 0xF00 +#define GICD_IGROUPR0_OFFSET 0x080 +#define GICD_TYPER_OFFSET 0x0004 +#define GICD_ISENABLER0_OFFSET 0x0100 +#define GICD_ICENABLER0_OFFSET 0x0180 +#define GICD_IPRIORITYR3_OFFSET 0x040C +#define GICD_ISENABLERn_OFFSET 0x0100 +#define GICD_ISACTIVER0_OFFSET 0x300 + +#define GICC_CTLR_OFFSET 0x0 +#define GICC_PMR_OFFSET 0x0004 +#define GICC_IAR_OFFSET 0x000C +#define GICC_DIR_OFFSET 0x1000 +#define GICC_EOIR_OFFSET 0x0010 + + /* bitfield masks */ +#define GICC_CTLR_EN_GRP0 0x1 +#define GICC_CTLR_EN_GRP1 0x2 +#define GICC_CTLR_EOImodeS_MASK 0x200 +#define GICC_CTLR_DIS_BYPASS 0x60 +#define GICC_CTLR_CBPR_MASK 0x10 +#define GICC_CTLR_FIQ_EN_MASK 0x8 +#define GICC_CTLR_ACKCTL_MASK 0x4 +#define GICC_PMR_FILTER 0xFF + +#define GICD_CTLR_EN_GRP0 0x1 +#define GICD_CTLR_EN_GRP1 0x2 +#define GICD_IGROUP0_SGI15 0x8000 +#define GICD_ISENABLE0_SGI15 0x8000 +#define GICD_ICENABLE0_SGI15 0x8000 +#define GICD_ISACTIVER0_SGI15 0x8000 +#define GICD_CPENDSGIR_CLR_MASK 0xFF000000 +#define GICD_IPRIORITY_SGI15_MASK 0xFF000000 +#define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000 +#define GICD_SPENDSGIR3_SGI15_OFFSET 0x18 + +#ifndef __ASSEMBLER__ + +/* GIC common API's */ +void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr, + const uintptr_t nxp_gicc_addr, + uint8_t plat_core_count, + interrupt_prop_t *ls_interrupt_props, + uint8_t ls_interrupt_prop_count, + uint32_t *target_mask_array); +void plat_ls_gic_init(void); +void plat_ls_gic_cpuif_enable(void); +void plat_ls_gic_cpuif_disable(void); +void plat_ls_gic_redistif_on(void); +void plat_ls_gic_redistif_off(void); +void plat_gic_pcpu_init(void); +/* GIC utility functions */ +void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base); +#endif + +#endif /* PLAT_GICV2_H */ diff --git a/include/drivers/nxp/gic/gicv3/plat_gic.h b/include/drivers/nxp/gic/gicv3/plat_gic.h new file mode 100644 index 0000000000..794b06b61c --- /dev/null +++ b/include/drivers/nxp/gic/gicv3/plat_gic.h @@ -0,0 +1,120 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PLAT_GICV3_H +#define PLAT_GICV3_H + +#include <drivers/arm/gicv3.h> + + /* offset between redistributors */ +#define GIC_RD_OFFSET 0x00020000 + /* offset between SGI's */ +#define GIC_SGI_OFFSET 0x00020000 + /* offset from rd base to sgi base */ +#define GIC_RD_2_SGI_OFFSET 0x00010000 + + /* register offsets */ +#define GICD_CTLR_OFFSET 0x0 +#define GICD_CLR_SPI_SR 0x58 +#define GICD_IGROUPR_2 0x88 +#define GICD_ISENABLER_1 0x104 +#define GICD_ICENABLER_1 0x184 +#define GICD_ISENABLER_2 0x108 +#define GICD_ICENABLER_2 0x188 +#define GICD_ISENABLER_3 0x10c +#define GICD_ICENABLER_3 0x18c +#define GICD_ICPENDR_2 0x288 +#define GICD_ICACTIVER_2 0x388 +#define GICD_IPRIORITYR_22 0x458 +#define GICD_ICFGR_5 0xC14 +#define GICD_IGRPMODR_2 0xD08 + +#define GICD_IROUTER60_OFFSET 0x61e0 +#define GICD_IROUTER76_OFFSET 0x6260 +#define GICD_IROUTER89_OFFSET 0x62C8 +#define GICD_IROUTER112_OFFSET 0x6380 +#define GICD_IROUTER113_OFFSET 0x6388 + +#define GICR_ICENABLER0_OFFSET 0x180 +#define GICR_CTLR_OFFSET 0x0 +#define GICR_IGROUPR0_OFFSET 0x80 +#define GICR_IGRPMODR0_OFFSET 0xD00 +#define GICR_IPRIORITYR3_OFFSET 0x40C +#define GICR_ICPENDR0_OFFSET 0x280 +#define GICR_ISENABLER0_OFFSET 0x100 +#define GICR_TYPER_OFFSET 0x8 +#define GICR_WAKER_OFFSET 0x14 +#define GICR_ICACTIVER0_OFFSET 0x380 +#define GICR_ICFGR0_OFFSET 0xC00 + + /* bitfield masks */ +#define GICD_CTLR_EN_GRP_MASK 0x7 +#define GICD_CTLR_EN_GRP_1NS 0x2 +#define GICD_CTLR_EN_GRP_1S 0x4 +#define GICD_CTLR_EN_GRP_0 0x1 +#define GICD_CTLR_ARE_S_MASK 0x10 +#define GICD_CTLR_RWP 0x80000000 + +#define GICR_ICENABLER0_SGI15 0x00008000 +#define GICR_CTLR_RWP 0x8 +#define GICR_IGROUPR0_SGI15 0x00008000 +#define GICR_IGRPMODR0_SGI15 0x00008000 +#define GICR_ISENABLER0_SGI15 0x00008000 +#define GICR_IPRIORITYR3_SGI15_MASK 0xFF000000 +#define GICR_ICPENDR0_SGI15 0x8000 + +#define GIC_SPI_89_MASK 0x02000000 +#define GIC_SPI89_PRIORITY_MASK 0xFF00 +#define GIC_IRM_SPI89 0x80000000 + +#define GICD_IROUTER_VALUE 0x100 +#define GICD_ISENABLER_1_VALUE 0x10000000 +#define GICD_ISENABLER_2_VALUE 0x100 +#define GICD_ISENABLER_3_VALUE 0x20100 +#define GICR_WAKER_SLEEP_BIT 0x2 +#define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1) + +#define ICC_SRE_EL3_SRE 0x1 +#define ICC_IGRPEN0_EL1_EN 0x1 +#define ICC_CTLR_EL3_CBPR_EL1S 0x1 +#define ICC_CTLR_EL3_RM 0x20 +#define ICC_CTLR_EL3_EOIMODE_EL3 0x4 +#define ICC_CTLR_EL3_PMHE 0x40 +#define ICC_PMR_EL1_P_FILTER 0xFF +#define ICC_IAR0_EL1_SGI15 0xF +#define ICC_SGI0R_EL1_INTID 0x0F000000 +#define ICC_IAR0_INTID_SPI_89 0x59 + +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 + +#ifndef __ASSEMBLER__ + +/* GIC common API's */ +typedef unsigned int (*my_core_pos_fn)(void); + +void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr, + const uintptr_t nxp_gicr_addr, + uint8_t plat_core_count, + interrupt_prop_t *ls_interrupt_props, + uint8_t ls_interrupt_prop_count, + uintptr_t *target_mask_array, + mpidr_hash_fn mpidr_to_core_pos); +//void plat_ls_gic_driver_init(void); +void plat_ls_gic_init(void); +void plat_ls_gic_cpuif_enable(void); +void plat_ls_gic_cpuif_disable(void); +void plat_ls_gic_redistif_on(void); +void plat_ls_gic_redistif_off(void); +void plat_gic_pcpu_init(void); +#endif + +#endif /* PLAT_GICV3_H */ diff --git a/include/drivers/nxp/gpio/nxp_gpio.h b/include/drivers/nxp/gpio/nxp_gpio.h new file mode 100644 index 0000000000..df758404ca --- /dev/null +++ b/include/drivers/nxp/gpio/nxp_gpio.h @@ -0,0 +1,53 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PLAT_GPIO_H +#define PLAT_GPIO_H + +#include <endian.h> +#include <lib/mmio.h> + +/* GPIO Register offset */ +#define GPIO_SEL_MASK 0x7F +#define GPIO_BIT_MASK 0x1F +#define GPDIR_REG_OFFSET 0x0 +#define GPDAT_REG_OFFSET 0x8 + +#define GPIO_ID_BASE_ADDR_SHIFT 5U +#define GPIO_BITS_PER_BASE_REG 32U + +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 + +#define GPIO_SUCCESS 0x0 +#define GPIO_FAILURE 0x1 + +#ifdef NXP_GPIO_BE +#define gpio_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define gpio_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#elif defined(NXP_GPIO_LE) +#define gpio_read32(a) mmio_read_32((uintptr_t)(a)) +#define gpio_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) +#else +#error Please define GPIO register endianness +#endif + +typedef struct { + uintptr_t gpio1_base_addr; + uintptr_t gpio2_base_addr; + uintptr_t gpio3_base_addr; + uintptr_t gpio4_base_addr; +} gpio_init_info_t; + +void gpio_init(gpio_init_info_t *gpio_init_data); +uint32_t *select_gpio_n_bitnum(uint32_t povdd_gpio, uint32_t *bit_num); +int clr_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num); +int set_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num); + +#endif /* PLAT_GPIO_H */ diff --git a/include/drivers/nxp/i2c/i2c.h b/include/drivers/nxp/i2c/i2c.h new file mode 100644 index 0000000000..85e6eb4cf7 --- /dev/null +++ b/include/drivers/nxp/i2c/i2c.h @@ -0,0 +1,52 @@ +/* + * Copyright 2016-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef I2C_H +#define I2C_H + +#include <lib/mmio.h> + +#define I2C_TIMEOUT 1000 /* ms */ + +#define I2C_FD_CONSERV 0x7e +#define I2C_CR_DIS (1 << 7) +#define I2C_CR_EN (0 << 7) +#define I2C_CR_MA (1 << 5) +#define I2C_CR_TX (1 << 4) +#define I2C_CR_TX_NAK (1 << 3) +#define I2C_CR_RSTA (1 << 2) +#define I2C_SR_BB (1 << 5) +#define I2C_SR_IDLE (0 << 5) +#define I2C_SR_AL (1 << 4) +#define I2C_SR_IF (1 << 1) +#define I2C_SR_RX_NAK (1 << 0) +#define I2C_SR_RST (I2C_SR_AL | I2C_SR_IF) + +#define I2C_GLITCH_EN 0x8 + +#define i2c_in(a) mmio_read_8((uintptr_t)(a)) +#define i2c_out(a, v) mmio_write_8((uintptr_t)(a), (v)) + +struct ls_i2c { + unsigned char ad; /* I2c Bus Address Register */ + unsigned char fd; /* I2c Bus Frequency Dividor Register */ + unsigned char cr; /* I2c Bus Control Register */ + unsigned char sr; /* I2c Bus Status Register */ + unsigned char dr; /* I2C Bus Data I/O Register */ + unsigned char ic; /* I2C Bus Interrupt Config Register */ + unsigned char dbg; /* I2C Bus Debug Register */ +}; + +void i2c_init(uintptr_t nxp_i2c_addr); +int i2c_read(unsigned char chip, int addr, int alen, + unsigned char *buf, int len); +int i2c_write(unsigned char chip, int addr, int alen, + const unsigned char *buf, int len); +int i2c_probe_chip(unsigned char chip); + +#endif /* I2C_H */ diff --git a/include/drivers/nxp/ifc/ifc_nand.h b/include/drivers/nxp/ifc/ifc_nand.h new file mode 100644 index 0000000000..dbcd762ce1 --- /dev/null +++ b/include/drivers/nxp/ifc/ifc_nand.h @@ -0,0 +1,19 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IFC_NAND_H +#define IFC_NAND_H + +#define NXP_IFC_SRAM_BUFFER_SIZE UL(0x100000) /* 1M */ + +int ifc_nand_init(uintptr_t *block_dev_spec, + uintptr_t ifc_region_addr, + uintptr_t ifc_register_addr, + size_t ifc_sram_size, + uintptr_t ifc_nand_blk_offset, + size_t ifc_nand_blk_size); + +#endif /*IFC_NAND_H*/ diff --git a/include/drivers/nxp/ifc/ifc_nor.h b/include/drivers/nxp/ifc/ifc_nor.h new file mode 100644 index 0000000000..ee1446069e --- /dev/null +++ b/include/drivers/nxp/ifc/ifc_nor.h @@ -0,0 +1,14 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef IFC_NOR_H +#define IFC_NOR_H + + +int ifc_nor_init(uintptr_t flash_addr, size_t flash_size); + +#endif /*IFC_NOR_H*/ diff --git a/include/drivers/nxp/interconnect/ls_interconnect.h b/include/drivers/nxp/interconnect/ls_interconnect.h new file mode 100644 index 0000000000..777089c80f --- /dev/null +++ b/include/drivers/nxp/interconnect/ls_interconnect.h @@ -0,0 +1,19 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef LS_INTERCONNECT_H +#define LS_INTERCONNECT_H + +#if (INTERCONNECT == CCI400) +#define CCI_TERMINATE_BARRIER_TX 0x8 +#endif + +/* Interconnect CCI/CCN functions */ +void plat_ls_interconnect_enter_coherency(unsigned int num_clusters); +void plat_ls_interconnect_exit_coherency(void); + +#endif diff --git a/include/drivers/nxp/pmu/pmu.h b/include/drivers/nxp/pmu/pmu.h new file mode 100644 index 0000000000..28199e852b --- /dev/null +++ b/include/drivers/nxp/pmu/pmu.h @@ -0,0 +1,75 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PMU_H +#define PMU_H + +/* PMU Registers' OFFSET */ +#define PMU_PCPW20SR_OFFSET 0x830 +#define PMU_CLL2FLUSHSETR_OFFSET 0x1110 +#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114 +#define PMU_CLL2FLUSHSR_OFFSET 0x1118 +#define PMU_POWMGTCSR_VAL (1 << 20) + +/* PMU Registers */ +#define CORE_TIMEBASE_ENBL_OFFSET 0x8A0 +#define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0 + +#define PMU_IDLE_CLUSTER_MASK 0x2 +#define PMU_FLUSH_CLUSTER_MASK 0x2 +#define PMU_IDLE_CORE_MASK 0xfe + +/* pmu register offsets and bitmaps */ +#define PMU_POWMGTDCR0_OFFSET 0xC20 +#define PMU_POWMGTCSR_OFFSET 0x4000 +#define PMU_CLAINACTSETR_OFFSET 0x1100 +#define PMU_CLAINACTCLRR_OFFSET 0x1104 +#define PMU_CLSINACTSETR_OFFSET 0x1108 +#define PMU_CLSINACTCLRR_OFFSET 0x110C +#define PMU_CLL2FLUSHSETR_OFFSET 0x1110 +#define PMU_CLL2FLUSHCLRR_OFFSET 0x1114 +#define PMU_IPPDEXPCR0_OFFSET 0x4040 +#define PMU_IPPDEXPCR1_OFFSET 0x4044 +#define PMU_IPPDEXPCR2_OFFSET 0x4048 +#define PMU_IPPDEXPCR3_OFFSET 0x404C +#define PMU_IPPDEXPCR4_OFFSET 0x4050 +#define PMU_IPPDEXPCR5_OFFSET 0x4054 +#define PMU_IPPDEXPCR6_OFFSET 0x4058 +#define PMU_IPSTPCR0_OFFSET 0x4120 +#define PMU_IPSTPCR1_OFFSET 0x4124 +#define PMU_IPSTPCR2_OFFSET 0x4128 +#define PMU_IPSTPCR3_OFFSET 0x412C +#define PMU_IPSTPCR4_OFFSET 0x4130 +#define PMU_IPSTPCR5_OFFSET 0x4134 +#define PMU_IPSTPCR6_OFFSET 0x4138 +#define PMU_IPSTPACKSR0_OFFSET 0x4140 +#define PMU_IPSTPACKSR1_OFFSET 0x4144 +#define PMU_IPSTPACKSR2_OFFSET 0x4148 +#define PMU_IPSTPACKSR3_OFFSET 0x414C +#define PMU_IPSTPACKSR4_OFFSET 0x4150 +#define PMU_IPSTPACKSR5_OFFSET 0x4154 +#define PMU_IPSTPACKSR6_OFFSET 0x4158 + +#define CLAINACT_DISABLE_ACP 0xFF +#define CLSINACT_DISABLE_SKY 0xFF +#define POWMGTDCR_STP_OV_EN 0x1 +#define POWMGTCSR_LPM20_REQ 0x00100000 + +/* Used by PMU */ +#define DEVDISR1_MASK 0x024F3504 +#define DEVDISR2_MASK 0x0003FFFF +#define DEVDISR3_MASK 0x0000303F +#define DEVDISR4_MASK 0x0000FFFF +#define DEVDISR5_MASK 0x00F07603 +#define DEVDISR6_MASK 0x00000001 + +#ifndef __ASSEMBLER__ +void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr); +void enable_core_tb(uintptr_t nxp_pmu_addr); +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/include/drivers/nxp/qspi/qspi.h b/include/drivers/nxp/qspi/qspi.h new file mode 100644 index 0000000000..db11c3bc69 --- /dev/null +++ b/include/drivers/nxp/qspi/qspi.h @@ -0,0 +1,30 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef QSPI_H +#define QSPI_H + +#include <endian.h> +#include <lib/mmio.h> + +#define CHS_QSPI_MCR 0x01550000 +#define CHS_QSPI_64LE 0xC + +#ifdef NXP_QSPI_BE +#define qspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#elif defined(NXP_QSPI_LE) +#define qspi_in32(a) mmio_read_32((uintptr_t)(a)) +#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), (v)) +#else +#error Please define CCSR QSPI register endianness +#endif + +int qspi_io_setup(uintptr_t nxp_qspi_flash_addr, + size_t nxp_qspi_flash_size, + uintptr_t fip_offset); +#endif /* __QSPI_H__ */ diff --git a/include/drivers/nxp/sd/sd_mmc.h b/include/drivers/nxp/sd/sd_mmc.h new file mode 100644 index 0000000000..32b41f1374 --- /dev/null +++ b/include/drivers/nxp/sd/sd_mmc.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2015, 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef SD_MMC_H +#define SD_MMC_H + +#include <lib/mmio.h> + +/* operating freq */ +#define CARD_IDENTIFICATION_FREQ 400000 +#define SD_SS_25MHZ 20000000 +#define SD_HS_50MHZ 40000000 +#define MMC_SS_20MHZ 15000000 +#define MMC_HS_26MHZ 20000000 +#define MMC_HS_52MHZ 40000000 + +/* Need to check this value ? */ +#define MAX_PLATFORM_CLOCK 800000000 + +/* eSDHC system control register defines */ +#define ESDHC_SYSCTL_DTOCV(t) (((t) & 0xF) << 16) +#define ESDHC_SYSCTL_SDCLKFS(f) (((f) & 0xFF) << 8) +#define ESDHC_SYSCTL_DVS(d) (((d) & 0xF) << 4) +#define ESDHC_SYSCTL_SDCLKEN (0x00000008) +#define ESDHC_SYSCTL_RSTA (0x01000000) + +/* Data timeout counter value. SDHC_CLK x 227 */ +#define TIMEOUT_COUNTER_SDCLK_2_27 0xE +#define ESDHC_SYSCTL_INITA 0x08000000 + +/* eSDHC interrupt status enable register defines */ +#define ESDHC_IRQSTATEN_CINS 0x00000040 +#define ESDHC_IRQSTATEN_BWR 0x00000010 + +/* eSDHC interrupt status register defines */ +#define ESDHC_IRQSTAT_DMAE (0x10000000) +#define ESDHC_IRQSTAT_AC12E (0x01000000) +#define ESDHC_IRQSTAT_DEBE (0x00400000) +#define ESDHC_IRQSTAT_DCE (0x00200000) +#define ESDHC_IRQSTAT_DTOE (0x00100000) +#define ESDHC_IRQSTAT_CIE (0x00080000) +#define ESDHC_IRQSTAT_CEBE (0x00040000) +#define ESDHC_IRQSTAT_CCE (0x00020000) +#define ESDHC_IRQSTAT_CTOE (0x00010000) +#define ESDHC_IRQSTAT_CINT (0x00000100) +#define ESDHC_IRQSTAT_CRM (0x00000080) +#define ESDHC_IRQSTAT_CINS (0x00000040) +#define ESDHC_IRQSTAT_BRR (0x00000020) +#define ESDHC_IRQSTAT_BWR (0x00000010) +#define ESDHC_IRQSTAT_DINT (0x00000008) +#define ESDHC_IRQSTAT_BGE (0x00000004) +#define ESDHC_IRQSTAT_TC (0x00000002) +#define ESDHC_IRQSTAT_CC (0x00000001) +#define ESDHC_IRQSTAT_CMD_ERR (ESDHC_IRQSTAT_CIE |\ + ESDHC_IRQSTAT_CEBE |\ + ESDHC_IRQSTAT_CCE) +#define ESDHC_IRQSTAT_DATA_ERR (ESDHC_IRQSTAT_DEBE |\ + ESDHC_IRQSTAT_DCE |\ + ESDHC_IRQSTAT_DTOE) +#define ESDHC_IRQSTAT_CLEAR_ALL (0xFFFFFFFF) + +/* eSDHC present state register defines */ +#define ESDHC_PRSSTAT_CLSL 0x00800000 +#define ESDHC_PRSSTAT_WPSPL 0x00080000 +#define ESDHC_PRSSTAT_CDPL 0x00040000 +#define ESDHC_PRSSTAT_CINS 0x00010000 +#define ESDHC_PRSSTAT_BREN 0x00000800 +#define ESDHC_PRSSTAT_BWEN 0x00000400 +#define ESDHC_PRSSTAT_RTA 0x00000200 +#define ESDHC_PRSSTAT_WTA 0x00000100 +#define ESDHC_PRSSTAT_SDOFF 0x00000080 +#define ESDHC_PRSSTAT_PEROFF 0x00000040 +#define ESDHC_PRSSTAT_HCKOFF 0x00000020 +#define ESDHC_PRSSTAT_IPGOFF 0x00000010 +#define ESDHC_PRSSTAT_DLA 0x00000004 +#define ESDHC_PRSSTAT_CDIHB 0x00000002 +#define ESDHC_PRSSTAT_CIHB 0x00000001 + +/* eSDHC protocol control register defines */ +#define ESDHC_PROCTL_EMODE_LE 0x00000020 +#define ESDHC_PROCTL_DTW_1BIT 0x00000000 +#define ESDHC_PROCTL_DTW_4BIT 0x00000002 +#define ESDHC_PROCTL_DTW_8BIT 0x00000004 + +/* Watermark Level Register (WML) */ +#define ESDHC_WML_RD_WML(w) ((w) & 0x7F) +#define ESDHC_WML_WR_WML(w) (((w) & 0x7F) << 16) +#define ESDHC_WML_RD_BRST(w) (((w) & 0xF) << 8) +#define ESDHC_WML_WR_BRST(w) (((w) & 0xF) << 24) +#define ESDHC_WML_WR_BRST_MASK (0x0F000000) +#define ESDHC_WML_RD_BRST_MASK (0x00000F00) +#define ESDHC_WML_RD_WML_MASK (0x0000007F) +#define ESDHC_WML_WR_WML_MASK (0x007F0000) +#define WML_512_BYTES (0x0) +#define BURST_128_BYTES (0x0) + +/* eSDHC control register define */ +#define ESDHC_DCR_SNOOP 0x00000040 + +/* ESDHC Block attributes register */ +#define ESDHC_BLKATTR_BLKCNT(c) (((c) & 0xffff) << 16) +#define ESDHC_BLKATTR_BLKSZE(s) ((s) & 0xfff) + +/* Transfer Type Register */ +#define ESDHC_XFERTYP_CMD(c) (((c) & 0x3F) << 24) +#define ESDHC_XFERTYP_CMDTYP_NORMAL (0x0) +#define ESDHC_XFERTYP_CMDTYP_SUSPEND (0x00400000) +#define ESDHC_XFERTYP_CMDTYP_RESUME (0x00800000) +#define ESDHC_XFERTYP_CMDTYP_ABORT (0x00C00000) +#define ESDHC_XFERTYP_DPSEL (0x00200000) +#define ESDHC_XFERTYP_CICEN (0x00100000) +#define ESDHC_XFERTYP_CCCEN (0x00080000) +#define ESDHC_XFERTYP_RSPTYP_NONE (0x0) +#define ESDHC_XFERTYP_RSPTYP_136 (0x00010000) +#define ESDHC_XFERTYP_RSPTYP_48 (0x00020000) +#define ESDHC_XFERTYP_RSPTYP_48_BUSY (0x00030000) +#define ESDHC_XFERTYP_MSBSEL (0x00000020) +#define ESDHC_XFERTYP_DTDSEL (0x00000010) +#define ESDHC_XFERTYP_AC12EN (0x00000004) +#define ESDHC_XFERTYP_BCEN (0x00000002) +#define ESDHC_XFERTYP_DMAEN (0x00000001) + +#define MMC_VDD_HIGH_VOLTAGE 0x00000100 + +/* command index */ +#define CMD0 0 +#define CMD1 1 +#define CMD2 2 +#define CMD3 3 +#define CMD5 5 +#define CMD6 6 +#define CMD7 7 +#define CMD8 8 +#define CMD9 9 +#define CMD12 12 +#define CMD13 13 +#define CMD14 14 +#define CMD16 16 +#define CMD17 17 +#define CMD18 18 +#define CMD19 19 +#define CMD24 24 +#define CMD41 41 +#define CMD42 42 +#define CMD51 51 +#define CMD55 55 +#define CMD56 56 +#define ACMD6 CMD6 +#define ACMD13 CMD13 +#define ACMD41 CMD41 +#define ACMD42 CMD42 +#define ACMD51 CMD51 + +/* commands abbreviations */ +#define CMD_GO_IDLE_STATE CMD0 +#define CMD_MMC_SEND_OP_COND CMD1 +#define CMD_ALL_SEND_CID CMD2 +#define CMD_SEND_RELATIVE_ADDR CMD3 +#define CMD_SET_DSR CMD4 +#define CMD_SWITCH_FUNC CMD6 +#define CMD_SELECT_CARD CMD7 +#define CMD_DESELECT_CARD CMD7 +#define CMD_SEND_IF_COND CMD8 +#define CMD_MMC_SEND_EXT_CSD CMD8 +#define CMD_SEND_CSD CMD9 +#define CMD_SEND_CID CMD10 +#define CMD_STOP_TRANSMISSION CMD12 +#define CMD_SEND_STATUS CMD13 +#define CMD_BUS_TEST_R CMD14 +#define CMD_GO_INACTIVE_STATE CMD15 +#define CMD_SET_BLOCKLEN CMD16 +#define CMD_READ_SINGLE_BLOCK CMD17 +#define CMD_READ_MULTIPLE_BLOCK CMD18 +#define CMD_WRITE_SINGLE_BLOCK CMD24 +#define CMD_BUS_TEST_W CMD19 +#define CMD_APP_CMD CMD55 +#define CMD_GEN_CMD CMD56 +#define CMD_SET_BUS_WIDTH ACMD6 +#define CMD_SD_STATUS ACMD13 +#define CMD_SD_SEND_OP_COND ACMD41 +#define CMD_SET_CLR_CARD_DETECT ACMD42 +#define CMD_SEND_SCR ACMD51 + +/* MMC card spec version */ +#define MMC_CARD_VERSION_1_2 0 +#define MMC_CARD_VERSION_1_4 1 +#define MMC_CARD_VERSION_2_X 2 +#define MMC_CARD_VERSION_3_X 3 +#define MMC_CARD_VERSION_4_X 4 + +/* SD Card Spec Version */ +/* May need to add version 3 here? */ +#define SD_CARD_VERSION_1_0 0 +#define SD_CARD_VERSION_1_10 1 +#define SD_CARD_VERSION_2_0 2 + +/* card types */ +#define MMC_CARD 0 +#define SD_CARD 1 +#define NOT_SD_CARD MMC_CARD + +/* Card rca */ +#define SD_MMC_CARD_RCA 0x1 +#define BLOCK_LEN_512 512 + +/* card state */ +#define STATE_IDLE 0 +#define STATE_READY 1 +#define STATE_IDENT 2 +#define STATE_STBY 3 +#define STATE_TRAN 4 +#define STATE_DATA 5 +#define STATE_RCV 6 +#define STATE_PRG 7 +#define STATE_DIS 8 + +/* Card OCR register */ +/* VDD voltage window 1,65 to 1.95 */ +#define MMC_OCR_VDD_165_195 0x00000080 +/* VDD voltage window 2.7-2.8 */ +#define MMC_OCR_VDD_FF8 0x00FF8000 +#define MMC_OCR_CCS 0x40000000/* Card Capacity */ +#define MMC_OCR_BUSY 0x80000000/* busy bit */ +#define SD_OCR_HCS 0x40000000/* High capacity host */ +#define MMC_OCR_SECTOR_MODE 0x40000000/* Access Mode as Sector */ + +/* mmc Switch function */ +#define SET_EXT_CSD_HS_TIMING 0x03B90100/* set High speed */ + +/* check supports switching or not */ +#define SD_SWITCH_FUNC_CHECK_MODE 0x00FFFFF1 +#define SD_SWITCH_FUNC_SWITCH_MODE 0x80FFFFF1/* switch */ +#define SD_SWITCH_FUNC_HIGH_SPEED 0x02/* HIGH SPEED FUNC */ +#define SWITCH_ERROR 0x00000080 + +/* errors in sending commands */ +#define RESP_TIMEOUT 0x1 +#define COMMAND_ERROR 0x2 +/* error in response */ +#define R1_ERROR (1 << 19) +#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) + +/* Host Controller Capabilities */ +#define ESDHC_HOSTCAPBLT_DMAS (0x00400000) + + +/* SD/MMC memory map */ +struct esdhc_regs { + uint32_t dsaddr; /* dma system address */ + uint32_t blkattr; /* Block attributes */ + uint32_t cmdarg; /* Command argument */ + uint32_t xfertyp; /* Command transfer type */ + uint32_t cmdrsp[4]; /* Command response0,1,2,3 */ + uint32_t datport; /* Data buffer access port */ + uint32_t prsstat; /* Present state */ + uint32_t proctl; /* Protocol control */ + uint32_t sysctl; /* System control */ + uint32_t irqstat; /* Interrupt status */ + uint32_t irqstaten; /* Interrupt status enable */ + uint32_t irqsigen; /* Interrupt signal enable */ + uint32_t autoc12err; /* Auto CMD12 status */ + uint32_t hostcapblt; /* Host controller capabilities */ + uint32_t wml; /* Watermark level */ + uint32_t res1[2]; + uint32_t fevt; /* Force event */ + uint32_t res2; + uint32_t adsaddrl; + uint32_t adsaddrh; + uint32_t res3[39]; + uint32_t hostver; /* Host controller version */ + uint32_t res4; + uint32_t dmaerr; /* DMA error address */ + uint32_t dmaerrh; /* DMA error address high */ + uint32_t dmaerrattr; /* DMA error atrribute */ + uint32_t res5; + uint32_t hostcapblt2;/* Host controller capabilities2 */ + uint32_t res6[2]; + uint32_t tcr; /* Tuning control */ + uint32_t res7[7]; + uint32_t dirctrl; /* Direction control */ + uint32_t ccr; /* Clock control */ + uint32_t res8[177]; + uint32_t ctl; /* Control register */ +}; + +/* SD/MMC card attributes */ +struct card_attributes { + uint32_t type; /* sd or mmc card */ + uint32_t version; /* version */ + uint32_t block_len; /* block length */ + uint32_t bus_freq; /* sdhc bus frequency */ + uint16_t rca; /* relative card address */ + uint8_t is_high_capacity; /* high capacity */ +}; + +struct mmc { + struct esdhc_regs *esdhc_regs; + struct card_attributes card; + + uint32_t block_len; + uint32_t voltages_caps; /* supported voltaes */ + uint32_t dma_support; /* DMA support */ +}; + +enum cntrl_num { + SDHC1 = 0, + SDHC2 +}; + +int sd_emmc_init(uintptr_t *block_dev_spec, + uintptr_t nxp_esdhc_addr, + size_t nxp_sd_block_offset, + size_t nxp_sd_block_size, + bool card_detect); + +int esdhc_emmc_init(struct mmc *mmc, bool card_detect); +int esdhc_read(struct mmc *mmc, uint32_t src_offset, uintptr_t dst, + size_t size); +int esdhc_write(struct mmc *mmc, uintptr_t src, uint32_t dst_offset, + size_t size); + +#ifdef NXP_ESDHC_BE +#define esdhc_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#elif defined(NXP_ESDHC_LE) +#define esdhc_in32(a) mmio_read_32((uintptr_t)(a)) +#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), (v)) +#else +#error Please define CCSR ESDHC register endianness +#endif + +#endif /*SD_MMC_H*/ diff --git a/include/drivers/nxp/sec_mon/snvs.h b/include/drivers/nxp/sec_mon/snvs.h new file mode 100644 index 0000000000..4455383e3a --- /dev/null +++ b/include/drivers/nxp/sec_mon/snvs.h @@ -0,0 +1,86 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef SNVS_H +#define SNVS_H + + +#ifndef __ASSEMBLER__ + +#include <endian.h> +#include <stdbool.h> + +#include <lib/mmio.h> + +struct snvs_regs { + uint32_t reserved1; + uint32_t hp_com; /* 0x04 SNVS_HP Command Register */ + uint32_t reserved2[3]; + uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */ +}; + +#ifdef NXP_SNVS_BE +#define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v))) +#elif defined(NXP_SNVS_LE) +#define snvs_read32(a) mmio_read_32((uintptr_t)(a)) +#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) +#else +#error Please define CCSR SNVS register endianness +#endif + +void snvs_init(uintptr_t nxp_snvs_addr); +uint32_t get_snvs_state(void); +void transition_snvs_non_secure(void); +void transition_snvs_soft_fail(void); +uint32_t transition_snvs_trusted(void); +uint32_t transition_snvs_secure(void); + +uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos); +void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val); + +void snvs_disable_zeroize_lp_gpr(void); + +#if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB) +uint32_t snvs_read_app_data(void); +uint32_t snvs_read_app_data_bit(uint32_t bit_pos); +void snvs_clear_app_data(void); +void snvs_write_app_data_bit(uint32_t bit_pos); +#endif + +#endif /* __ASSEMBLER__ */ + +/* SSM_ST field in SNVS status reg */ +#define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */ +#define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */ +#define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */ +#define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */ +#define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */ +#define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */ + +/* SNVS register bits */ +#define HPCOM_SW_SV 0x100 /* Security Violation bit */ +#define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */ +#define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */ +#define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ +#define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ + +#define NXP_LP_GPR0_OFFSET 0x90 +#define NXP_LPCR_OFFSET 0x38 +#define NXP_GPR_Z_DIS_BIT 24 + +#ifdef NXP_COINED_BB + +#ifndef NXP_APP_DATA_LP_GPR_OFFSET +#define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET +#endif + +#define NXP_LPGPR_ZEROTH_BIT 0 + +#endif /* NXP_COINED_BB */ + +#endif /* SNVS_H */ diff --git a/include/drivers/nxp/sfp/fuse_prov.h b/include/drivers/nxp/sfp/fuse_prov.h new file mode 100644 index 0000000000..e015318daa --- /dev/null +++ b/include/drivers/nxp/sfp/fuse_prov.h @@ -0,0 +1,83 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#if !defined(FUSE_PROV_H) && defined(POLICY_FUSE_PROVISION) +#define FUSE_PROV_H + +#include <endian.h> +#include <lib/mmio.h> + +#define MASK_NONE U(0xFFFFFFFF) +#define ERROR_WRITE U(0xA) +#define ERROR_ALREADY_BLOWN U(0xB) + +/* Flag bit shifts */ +#define FLAG_POVDD_SHIFT U(0) +#define FLAG_SYSCFG_SHIFT U(1) +#define FLAG_SRKH_SHIFT U(2) +#define FLAG_MC_SHIFT U(3) +#define FLAG_DCV0_SHIFT U(4) +#define FLAG_DCV1_SHIFT U(5) +#define FLAG_DRV0_SHIFT U(6) +#define FLAG_DRV1_SHIFT U(7) +#define FLAG_OUID0_SHIFT U(8) +#define FLAG_OUID1_SHIFT U(9) +#define FLAG_OUID2_SHIFT U(10) +#define FLAG_OUID3_SHIFT U(11) +#define FLAG_OUID4_SHIFT U(12) +#define FLAG_DBG_LVL_SHIFT U(13) +#define FLAG_OTPMK_SHIFT U(16) +#define FLAG_OUID_MASK U(0x1F) +#define FLAG_DEBUG_MASK U(0xF) +#define FLAG_OTPMK_MASK U(0xF) + +/* OTPMK flag values */ +#define PROG_OTPMK_MIN U(0x0) +#define PROG_OTPMK_RANDOM U(0x1) +#define PROG_OTPMK_USER U(0x2) +#define PROG_OTPMK_RANDOM_MIN U(0x5) +#define PROG_OTPMK_USER_MIN U(0x6) +#define PROG_NO_OTPMK U(0x8) + +#define OTPMK_MIM_BITS_MASK U(0xF0000000) + +/* System configuration bit shifts */ +#define SCB_WP_SHIFT U(0) +#define SCB_ITS_SHIFT U(2) +#define SCB_NSEC_SHIFT U(4) +#define SCB_ZD_SHIFT U(5) +#define SCB_K0_SHIFT U(15) +#define SCB_K1_SHIFT U(14) +#define SCB_K2_SHIFT U(13) +#define SCB_K3_SHIFT U(12) +#define SCB_K4_SHIFT U(11) +#define SCB_K5_SHIFT U(10) +#define SCB_K6_SHIFT U(9) +#define SCB_FR0_SHIFT U(30) +#define SCB_FR1_SHIFT U(31) + +/* Fuse Header Structure */ +struct fuse_hdr_t { + uint8_t barker[4]; /* 0x00 Barker code */ + uint32_t flags; /* 0x04 Script flags */ + uint32_t povdd_gpio; /* 0x08 GPIO for POVDD */ + uint32_t otpmk[8]; /* 0x0C-0x2B OTPMK */ + uint32_t srkh[8]; /* 0x2C-0x4B SRKH */ + uint32_t oem_uid[5]; /* 0x4C-0x5F OEM unique id's */ + uint32_t dcv[2]; /* 0x60-0x67 Debug Challenge */ + uint32_t drv[2]; /* 0x68-0x6F Debug Response */ + uint32_t ospr1; /* 0x70 OSPR1 */ + uint32_t sc; /* 0x74 OSPR0 (System Configuration) */ + uint32_t reserved[2]; /* 0x78-0x7F Reserved */ +}; + +/* Function to do fuse provisioning */ +int provision_fuses(unsigned long long fuse_scr_addr, + bool en_povdd_status); + +#define EFUSE_POWERUP_DELAY_mSec U(25) +#endif /* FUSE_PROV_H */ diff --git a/include/drivers/nxp/sfp/sfp.h b/include/drivers/nxp/sfp/sfp.h new file mode 100644 index 0000000000..2cb4c7db51 --- /dev/null +++ b/include/drivers/nxp/sfp/sfp.h @@ -0,0 +1,100 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef SFP_H +#define SFP_H + +#include <endian.h> +#include <lib/mmio.h> + +/* SFP Configuration Register Offsets */ +#define SFP_INGR_OFFSET U(0x20) +#define SFP_SVHESR_OFFSET U(0x24) +#define SFP_SFPCR_OFFSET U(0x28) +#define SFP_VER_OFFSET U(0x38) + +/* SFP Hamming register masks for OTPMK and DRV */ +#define SFP_SVHESR_DRV_MASK U(0x7F) +#define SFP_SVHESR_OTPMK_MASK U(0x7FC00) + +/* SFP commands */ +#define SFP_INGR_READFB_CMD U(0x1) +#define SFP_INGR_PROGFB_CMD U(0x2) +#define SFP_INGR_ERROR_MASK U(0x100) + +/* SFPCR Masks */ +#define SFP_SFPCR_WD U(0x80000000) +#define SFP_SFPCR_WDL U(0x40000000) + +/* SFPCR Masks */ +#define SFP_SFPCR_WD U(0x80000000) +#define SFP_SFPCR_WDL U(0x40000000) + +#define SFP_FUSE_REGS_OFFSET U(0x200) + +#ifdef NXP_SFP_VER_3_4 +#define OSPR0_SC_MASK U(0xC000FE35) +#elif defined(NXP_SFP_VER_3_2) +#define OSPR0_SC_MASK U(0x0000E035) +#endif + +#if defined(NXP_SFP_VER_3_4) +#define OSPR_KEY_REVOC_SHIFT U(9) +#define OSPR_KEY_REVOC_MASK U(0x0000fe00) +#elif defined(NXP_SFP_VER_3_2) +#define OSPR_KEY_REVOC_SHIFT U(13) +#define OSPR_KEY_REVOC_MASK U(0x0000e000) +#endif /* NXP_SFP_VER_3_4 */ + +#define OSPR1_MC_MASK U(0xFFFF0000) +#define OSPR1_DBG_LVL_MASK U(0x00000007) + +#define OSPR_ITS_MASK U(0x00000004) +#define OSPR_WP_MASK U(0x00000001) + +#define MAX_OEM_UID U(5) +#define SRK_HASH_SIZE U(32) + +/* SFP CCSR Register Map */ +struct sfp_ccsr_regs_t { + uint32_t ospr; /* 0x200 OSPR0 */ + uint32_t ospr1; /* 0x204 OSPR1 */ + uint32_t dcv[2]; /* 0x208 Debug Challenge Value */ + uint32_t drv[2]; /* 0x210 Debug Response Value */ + uint32_t fswpr; /* 0x218 FSL Section Write Protect */ + uint32_t fsl_uid[2]; /* 0x21c FSL UID 0 */ + uint32_t isbcr; /* 0x224 ISBC Configuration */ + uint32_t fsspr[3]; /* 0x228 FSL Scratch Pad */ + uint32_t otpmk[8]; /* 0x234 OTPMK */ + uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)]; + /* 0x254 Super Root Key Hash */ + uint32_t oem_uid[MAX_OEM_UID]; /* 0x274 OEM UID 0 */ +}; + +uintptr_t get_sfp_addr(void); +void sfp_init(uintptr_t nxp_sfp_addr); +uint32_t *get_sfp_srk_hash(void); +int sfp_check_its(void); +int sfp_check_oem_wp(void); +uint32_t get_key_revoc(void); +void set_sfp_wr_disable(void); +int sfp_program_fuses(void); + +uint32_t sfp_read_oem_uid(uint8_t oem_uid); +uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val); + +#ifdef NXP_SFP_BE +#define sfp_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) +#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) +#elif defined(NXP_SFP_LE) +#define sfp_read32(a) mmio_read_32((uintptr_t)(a)) +#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) +#else +#error Please define CCSR SFP register endianness +#endif + +#endif/* SFP_H */ diff --git a/include/drivers/nxp/sfp/sfp_error_codes.h b/include/drivers/nxp/sfp/sfp_error_codes.h new file mode 100644 index 0000000000..7be7a274de --- /dev/null +++ b/include/drivers/nxp/sfp/sfp_error_codes.h @@ -0,0 +1,40 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef SFP_ERROR_CODES_H +#define SFP_ERROR_CODES_H + + /* Error codes */ +#define ERROR_FUSE_BARKER 0x1 +#define ERROR_READFB_CMD 0x2 +#define ERROR_PROGFB_CMD 0x3 +#define ERROR_SRKH_ALREADY_BLOWN 0x4 +#define ERROR_SRKH_WRITE 0x5 +#define ERROR_OEMUID_ALREADY_BLOWN 0x6 +#define ERROR_OEMUID_WRITE 0x7 +#define ERROR_DCV_ALREADY_BLOWN 0x8 +#define ERROR_DCV_WRITE 0x9 +#define ERROR_DRV_ALREADY_BLOWN 0xa +#define ERROR_DRV_HAMMING_ERROR 0xb +#define ERROR_DRV_WRITE 0x18 +#define ERROR_OTPMK_ALREADY_BLOWN 0xc +#define ERROR_OTPMK_HAMMING_ERROR 0xd +#define ERROR_OTPMK_USER_MIN 0xe +#define ERROR_OSPR1_ALREADY_BLOWN 0xf +#define ERROR_OSPR1_WRITE 0x10 +#define ERROR_SC_ALREADY_BLOWN 0x11 +#define ERROR_SC_WRITE 0x12 +#define ERROR_POVDD_GPIO_FAIL 0x13 +#define ERROR_GPIO_SET_FAIL 0x14 +#define ERROR_GPIO_RESET_FAIL 0x15 +#define ERROR_OTPMK_SEC_DISABLED 0x16 +#define ERROR_OTPMK_SEC_ERROR 0x17 +#define ERROR_OTPMK_WRITE 0x19 +#define PLAT_ERROR_ENABLE_POVDD 0x20 +#define PLAT_ERROR_DISABLE_POVDD 0x21 + +#endif /* SFP_ERROR_CODES_H */ diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h index d64c33b206..bc17703dc8 100644 --- a/include/drivers/nxp/smmu/nxp_smmu.h +++ b/include/drivers/nxp/smmu/nxp_smmu.h @@ -10,10 +10,13 @@ #define SMMU_SCR0 (0x0) #define SMMU_NSCR0 (0x400) +#define SMMU_SACR (0x10) #define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_USFCFG_MASK 0x00000400 +#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U) + static inline void bypass_smmu(uintptr_t smmu_base_addr) { uint32_t val; @@ -27,4 +30,13 @@ static inline void bypass_smmu(uintptr_t smmu_base_addr) mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); } +static inline void smmu_cache_unlock(uintptr_t smmu_base_addr) +{ + uint32_t val; + + val = mmio_read_32((smmu_base_addr + SMMU_SACR)); + val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT; + mmio_write_32((smmu_base_addr + SMMU_SACR), val); +} + #endif diff --git a/include/drivers/nxp/timer/nxp_timer.h b/include/drivers/nxp/timer/nxp_timer.h new file mode 100644 index 0000000000..280e5b27fc --- /dev/null +++ b/include/drivers/nxp/timer/nxp_timer.h @@ -0,0 +1,35 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +# +#ifndef NXP_TIMER_H +#define NXP_TIMER_H + + /* System Counter Offset and Bit Mask */ +#define SYS_COUNTER_CNTCR_OFFSET 0x0 +#define SYS_COUNTER_CNTCR_EN 0x00000001 +#define CNTCR_EN_MASK 0x1 + +#ifndef __ASSEMBLER__ +uint64_t get_timer_val(uint64_t start); + +#ifdef IMAGE_BL31 +void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base, + uint8_t ls_config_cntacr, + uint8_t plat_ls_ns_timer_frame_id); +void enable_init_timer(void); +#endif + +/* + * Initialise the nxp on-chip free rolling usec counter as the delay + * timer. + */ +void delay_timer_init(uintptr_t nxp_timer_addr); +void ls_bl31_timer_init(uintptr_t nxp_timer_addr); +#endif /* __ASSEMBLER__ */ + +#endif /* NXP_TIMER_H */ diff --git a/include/drivers/nxp/trdc/imx_trdc.h b/include/drivers/nxp/trdc/imx_trdc.h new file mode 100644 index 0000000000..0b41fcf451 --- /dev/null +++ b/include/drivers/nxp/trdc/imx_trdc.h @@ -0,0 +1,172 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX_TRDC_H +#define IMX_XRDC_H + +#define MBC_BLK_ALL U(255) +#define MRC_REG_ALL U(16) +#define GLBAC_NUM U(8) + +#define DID_NUM U(16) +#define MBC_MAX_NUM U(4) +#define MRC_MAX_NUM U(2) +#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF) +#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F) + +#define MBC_BLK_NUM(GLBCFG) ((GLBCFG) & 0x3FF) +#define MRC_RGN_NUM(GLBCFG) ((GLBCFG) & 0x1F) + +#define MDAC_W_X(m, r) (0x800 + (m) * 0x20 + (r) * 0x4) + +/* CPU/non-CPU domain common bits */ +#define MDA_VLD BIT(31) +#define MDA_LK1 BIT(30) +#define MDA_DFMT BIT(29) + +/* CPU domain bits */ +#define MDA_DFMT0_DID(x) ((x) & 0xF) +#define MDA_DFMT0_DIDS(x) (((x) & 0x3) << 4) +#define MDA_DFMT0_PE(x) (((x) & 0x3) << 6) +#define MDA_DFMT0_PIDM(x) (((x) & 0x3F) << 8) +#define MDA_DFMT0_SA(x) (((x) & 0x3) << 14) +#define MDA_DFMT0_PID(x) (((x) & 0x3F) << 16) + +/* non-CPU domain bits */ +#define MDA_DFMT1_DID(x) ((x) & 0xF) +#define MDA_DFMT1_PA(x) (((x) & 0x3) << 4) +#define MDA_DFMT1_SA(x) (((x) & 0x3) << 6) +#define MDA_DFMT1_DIDB(x) ((x) << 8) + +#define SP(X) ((X) << 12) +#define SU(X) ((X) << 8) +#define NP(X) ((X) << 4) +#define NU(X) ((X) << 0) + +#define RWX U(7) +#define RW U(6) +#define RX U(5) +#define R U(4) +#define X U(1) + +struct mbc_mem_dom { + uint32_t mem_glbcfg[4]; + uint32_t nse_blk_index; + uint32_t nse_blk_set; + uint32_t nse_blk_clr; + uint32_t nsr_blk_clr_all; + uint32_t memn_glbac[8]; + /* The upper only existed in the beginning of each MBC */ + uint32_t mem0_blk_cfg_w[64]; + uint32_t mem0_blk_nse_w[16]; + uint32_t mem1_blk_cfg_w[8]; + uint32_t mem1_blk_nse_w[2]; + uint32_t mem2_blk_cfg_w[8]; + uint32_t mem2_blk_nse_w[2]; + uint32_t mem3_blk_cfg_w[8]; + uint32_t mem3_blk_nse_w[2]; /*0x1F0, 0x1F4 */ + uint32_t reserved[2]; +}; + +struct mrc_rgn_dom { + uint32_t mrc_glbcfg[4]; + uint32_t nse_rgn_indirect; + uint32_t nse_rgn_set; + uint32_t nse_rgn_clr; + uint32_t nse_rgn_clr_all; + uint32_t memn_glbac[8]; + /* The upper only existed in the beginning of each MRC */ + uint32_t rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */ + uint32_t rgn_nse; + uint32_t reserved2[15]; +}; + +struct mda_inst { + uint32_t mda_w[8]; +}; + +struct trdc_mgr { + uint32_t trdc_cr; + uint32_t res0[59]; + uint32_t trdc_hwcfg0; + uint32_t trdc_hwcfg1; + uint32_t res1[450]; + struct mda_inst mda[128]; +}; + +struct trdc_mbc { + struct mbc_mem_dom mem_dom[DID_NUM]; +}; + +struct trdc_mrc { + struct mrc_rgn_dom mrc_dom[DID_NUM]; +}; + +/*************************************************************** + * Below structs used fro provding the TRDC configuration info + * that will be used to init the TRDC based on use case. + ***************************************************************/ +struct trdc_glbac_config { + uint8_t mbc_mrc_id; + uint8_t glbac_id; + uint32_t glbac_val; +}; + +struct trdc_mbc_config { + uint8_t mbc_id; + uint8_t dom_id; + uint8_t mem_id; + uint8_t blk_id; + uint8_t glbac_id; + bool secure; +}; + +struct trdc_mrc_config { + uint8_t mrc_id; + uint8_t dom_id; + uint8_t region_id; + uint32_t region_start; + uint32_t region_size; + uint8_t glbac_id; + bool secure; +}; + +struct trdc_mgr_info { + uintptr_t trdc_base; + uint8_t mbc_id; + uint8_t mbc_mem_id; + uint8_t blk_mgr; + uint8_t blk_mc; +}; + +struct trdc_config_info { + uintptr_t trdc_base; + struct trdc_glbac_config *mbc_glbac; + uint32_t num_mbc_glbac; + struct trdc_mbc_config *mbc_cfg; + uint32_t num_mbc_cfg; + struct trdc_glbac_config *mrc_glbac; + uint32_t num_mrc_glbac; + struct trdc_mrc_config *mrc_cfg; + uint32_t num_mrc_cfg; +}; + +extern struct trdc_mgr_info trdc_mgr_blks[]; +extern unsigned int trdc_mgr_num; +/* APIs to apply and enable TRDC */ +int trdc_mda_set_cpu(uintptr_t trdc_base, uint32_t mda_inst, + uint32_t mda_reg, uint8_t sa, uint8_t dids, + uint8_t did, uint8_t pe, uint8_t pidm, uint8_t pid); + +int trdc_mda_set_noncpu(uintptr_t trdc_base, uint32_t mda_inst, + bool did_bypass, uint8_t sa, uint8_t pa, + uint8_t did); + +void trdc_mgr_mbc_setup(struct trdc_mgr_info *mgr); +void trdc_setup(struct trdc_config_info *cfg); +void trdc_config(void); + +#endif /* IMX_TRDC_H */ diff --git a/include/drivers/nxp/tzc/plat_tzc380.h b/include/drivers/nxp/tzc/plat_tzc380.h new file mode 100644 index 0000000000..08d2148da9 --- /dev/null +++ b/include/drivers/nxp/tzc/plat_tzc380.h @@ -0,0 +1,47 @@ +/* + * Copyright 2018-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2) +#define PLAT_TZC380_H + +#include <tzc380.h> + +/* Number of DRAM regions to be configured + * for the platform can be over-written. + * + * Array tzc400_reg_list too, needs be over-written + * if there is any changes to default DRAM region + * configuration. + */ +#ifndef MAX_NUM_TZC_REGION +/* 3 regions: + * Region 0(default), + * Region 1 (DRAM0, Secure Memory), + * Region 2 (DRAM0, Shared memory) + */ +#define MAX_NUM_TZC_REGION 3 +#define DEFAULT_TZASC_CONFIG 1 +#endif + +struct tzc380_reg { + unsigned int secure; + unsigned int enabled; + uint64_t addr; + uint64_t size; + unsigned int sub_mask; +}; + +void mem_access_setup(uintptr_t base, uint32_t total_regions, + struct tzc380_reg *tzc380_reg_list); + +int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, + int dram_idx, int list_idx, + uint64_t dram_start_addr, + uint64_t dram_size, + uint32_t secure_dram_sz, + uint32_t shrd_dram_sz); + +#endif /* PLAT_TZC380_H */ diff --git a/include/drivers/nxp/tzc/plat_tzc400.h b/include/drivers/nxp/tzc/plat_tzc400.h new file mode 100644 index 0000000000..1b8e3a4da1 --- /dev/null +++ b/include/drivers/nxp/tzc/plat_tzc400.h @@ -0,0 +1,55 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2) +#define PLAT_TZC400_H + +#include <tzc400.h> + +/* Structure to configure TZC Regions' boundaries and attributes. */ +struct tzc400_reg { + uint8_t reg_filter_en; + unsigned long long start_addr; + unsigned long long end_addr; + unsigned int sec_attr; + unsigned int nsaid_permissions; +}; + +#define TZC_REGION_NS_NONE 0x00000000U + +/* NXP Platforms do not support NS Access ID (NSAID) based non-secure access. + * Supports only non secure through generic NS ACCESS ID + */ +#define TZC_NS_ACCESS_ID 0xFFFFFFFFU + +/* Number of DRAM regions to be configured + * for the platform can be over-written. + * + * Array tzc400_reg_list too, needs be over-written + * if there is any changes to default DRAM region + * configuration. + */ +#ifndef MAX_NUM_TZC_REGION +/* 3 regions: + * Region 0(default), + * Region 1 (DRAM0, Secure Memory), + * Region 2 (DRAM0, Shared memory) + */ +#define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3 +#define DEFAULT_TZASC_CONFIG 1 +#endif + +void mem_access_setup(uintptr_t base, uint32_t total_regions, + struct tzc400_reg *tzc400_reg_list); +int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list, + int dram_idx, int list_idx, + uint64_t dram_start_addr, + uint64_t dram_size, + uint32_t secure_dram_sz, + uint32_t shrd_dram_sz); + +#endif /* PLAT_TZC400_H */ diff --git a/include/drivers/partition/efi.h b/include/drivers/partition/efi.h new file mode 100644 index 0000000000..96c2857379 --- /dev/null +++ b/include/drivers/partition/efi.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021, Linaro Limited + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRIVERS_PARTITION_EFI_H +#define DRIVERS_PARTITION_EFI_H + +#include <string.h> + +#include <tools_share/uuid.h> + +#define EFI_NAMELEN 36 + +static inline int guidcmp(const void *g1, const void *g2) +{ + return memcmp(g1, g2, sizeof(struct efi_guid)); +} + +static inline void *guidcpy(void *dst, const void *src) +{ + return memcpy(dst, src, sizeof(struct efi_guid)); +} + +#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ + { (a) & 0xffffffffU, \ + (b) & 0xffffU, \ + (c) & 0xffffU, \ + { (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } + +#define NULL_GUID \ + EFI_GUID(0x00000000U, 0x0000U, 0x0000U, 0x00U, 0x00U, \ + 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U) + +#endif /* DRIVERS_PARTITION_EFI_H */ diff --git a/include/drivers/partition/gpt.h b/include/drivers/partition/gpt.h index d923e9535f..383c17de65 100644 --- a/include/drivers/partition/gpt.h +++ b/include/drivers/partition/gpt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,19 +7,16 @@ #ifndef GPT_H #define GPT_H +#include <drivers/partition/efi.h> #include <drivers/partition/partition.h> +#include <tools_share/uuid.h> #define PARTITION_TYPE_GPT 0xee -#define GPT_HEADER_OFFSET PLAT_PARTITION_BLOCK_SIZE -#define GPT_ENTRY_OFFSET (GPT_HEADER_OFFSET + \ - PLAT_PARTITION_BLOCK_SIZE) -#define GUID_LEN 16 - #define GPT_SIGNATURE "EFI PART" typedef struct gpt_entry { - unsigned char type_uuid[GUID_LEN]; - unsigned char unique_uuid[GUID_LEN]; + struct efi_guid type_uuid; + struct efi_guid unique_uuid; unsigned long long first_lba; unsigned long long last_lba; unsigned long long attr; @@ -36,7 +33,7 @@ typedef struct gpt_header { unsigned long long backup_lba; unsigned long long first_lba; unsigned long long last_lba; - unsigned char disk_uuid[16]; + struct efi_guid disk_uuid; /* starting LBA of array of partition entries */ unsigned long long part_lba; /* number of partition entries in array */ @@ -44,7 +41,7 @@ typedef struct gpt_header { /* size of a single partition entry (usually 128) */ unsigned int part_size; unsigned int part_crc; -} gpt_header_t; +} __packed gpt_header_t; int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry); diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h index 5f6483373f..9e22d34c4a 100644 --- a/include/drivers/partition/partition.h +++ b/include/drivers/partition/partition.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,8 @@ #include <stdint.h> #include <lib/cassert.h> +#include <drivers/partition/efi.h> +#include <tools_share/uuid.h> #if !PLAT_PARTITION_MAX_ENTRIES # define PLAT_PARTITION_MAX_ENTRIES 128 @@ -27,22 +29,29 @@ CASSERT((PLAT_PARTITION_BLOCK_SIZE == 512) || #define LEGACY_PARTITION_BLOCK_SIZE 512 -#define EFI_NAMELEN 36 +#define LBA(n) ((unsigned long long)(n) * PLAT_PARTITION_BLOCK_SIZE) typedef struct partition_entry { uint64_t start; uint64_t length; char name[EFI_NAMELEN]; + struct efi_guid part_guid; + struct efi_guid type_guid; } partition_entry_t; typedef struct partition_entry_list { partition_entry_t list[PLAT_PARTITION_MAX_ENTRIES]; - int entry_count; + unsigned int entry_count; } partition_entry_list_t; int load_partition_table(unsigned int image_id); const partition_entry_t *get_partition_entry(const char *name); +const partition_entry_t *get_partition_entry_by_type( + const struct efi_guid *type_guid); +const partition_entry_t *get_partition_entry_by_guid( + const struct efi_guid *part_guid); const partition_entry_list_t *get_partition_entry_list(void); void partition_init(unsigned int image_id); +int gpt_partition_init(void); #endif /* PARTITION_H */ diff --git a/include/drivers/rpi3/mailbox/rpi3_mbox.h b/include/drivers/rpi3/mailbox/rpi3_mbox.h index c1074402b0..33458e384d 100644 --- a/include/drivers/rpi3/mailbox/rpi3_mbox.h +++ b/include/drivers/rpi3/mailbox/rpi3_mbox.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,22 @@ typedef struct __packed __aligned(16) rpi3_mbox_request { uint32_t tags[0]; } rpi3_mbox_request_t; +/* VideoCore -> ARM */ +#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) +#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) +#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) +#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) +#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) +/* ARM -> VideoCore */ +#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) +#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) +#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) +#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) +#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) +/* Mailbox status constants */ +#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ +#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ + #define RPI3_MBOX_BUFFER_SIZE U(256) /* Constants to perform a request/check the status of a request. */ diff --git a/include/drivers/rpi3/sdhost/rpi3_sdhost.h b/include/drivers/rpi3/sdhost/rpi3_sdhost.h index 1653240c89..f4f6ec8b2c 100644 --- a/include/drivers/rpi3/sdhost/rpi3_sdhost.h +++ b/include/drivers/rpi3/sdhost/rpi3_sdhost.h @@ -15,6 +15,7 @@ struct rpi3_sdhost_params { uintptr_t reg_base; uint32_t clk_rate; + uint32_t clk_rate_initial; uint32_t bus_width; uint32_t flags; uint32_t current_cmd; @@ -57,6 +58,8 @@ void rpi3_sdhost_stop(void); #define HC_CMD_READ 0x0040 #define HC_CMD_COMMAND_MASK 0x003f +#define RPI3_SDHOST_MAX_CLOCK 250000000 // technically, we should obtain this number from the mailbox + #define HC_CLOCKDIVISOR_MAXVAL 0x07ff #define HC_CLOCKDIVISOR_PREFERVAL 0x027b #define HC_CLOCKDIVISOR_SLOWVAL 0x0148 diff --git a/include/drivers/scmi-msg.h b/include/drivers/scmi-msg.h index a9a99cf52c..c93c455004 100644 --- a/include/drivers/scmi-msg.h +++ b/include/drivers/scmi-msg.h @@ -22,7 +22,7 @@ struct scmi_msg_channel; * * @shm_addr: Address of the shared memory for the SCMI channel * @shm_size: Byte size of the shared memory for the SCMI channel - * @busy: True when channel is busy, flase when channel is free + * @busy: True when channel is busy, false when channel is free * @agent_name: Agent name, SCMI protocol exposes 16 bytes max, or NULL */ struct scmi_msg_channel { @@ -113,10 +113,12 @@ const char *plat_scmi_clock_get_name(unsigned int agent_id, * @scmi_id: SCMI clock ID * @rates: If NULL, function returns, else output rates array * @nb_elts: Array size of @rates. + * @start_idx: Start index of rates array * Return an SCMI compliant error code */ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, - unsigned long *rates, size_t *nb_elts); + unsigned long *rates, size_t *nb_elts, + uint32_t start_idx); /* * Get clock possible rate as range with regular steps in Hertz diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h index 40e2063751..869a0c689f 100644 --- a/include/drivers/spi_nand.h +++ b/include/drivers/spi_nand.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,9 +29,13 @@ #define SPI_NAND_STATUS_BUSY BIT(0) #define SPI_NAND_STATUS_ECC_UNCOR BIT(5) +/* Flags for specific configuration */ +#define SPI_NAND_HAS_QE_BIT BIT(0) + struct spinand_device { struct nand_device *nand_dev; struct spi_mem_op spi_read_cache_op; + uint32_t flags; uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ }; diff --git a/include/drivers/st/bsec.h b/include/drivers/st/bsec.h index d833e7ab27..4a1517af36 100644 --- a/include/drivers/st/bsec.h +++ b/include/drivers/st/bsec.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,20 +13,6 @@ #include <lib/utils_def.h> /* - * IP configuration - */ -#define BSEC_OTP_MASK GENMASK(4, 0) -#define BSEC_OTP_BANK_SHIFT 5 -#define BSEC_TIMEOUT_VALUE 0xFFFF - -#define ADDR_LOWER_OTP_PERLOCK_SHIFT 0x03 -#define DATA_LOWER_OTP_PERLOCK_BIT 0x03U /* 2 significants bits are used */ -#define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0) -#define ADDR_UPPER_OTP_PERLOCK_SHIFT 0x04 -#define DATA_UPPER_OTP_PERLOCK_BIT 0x01U /* 1 significants bits are used */ -#define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0) - -/* * Return status */ #define BSEC_OK 0U @@ -35,171 +21,53 @@ #define BSEC_INVALID_PARAM 0xFFFFFFFCU #define BSEC_PROG_FAIL 0xFFFFFFFBU #define BSEC_LOCK_FAIL 0xFFFFFFFAU -#define BSEC_WRITE_FAIL 0xFFFFFFF9U -#define BSEC_SHADOW_FAIL 0xFFFFFFF8U -#define BSEC_TIMEOUT 0xFFFFFFF7U - -/* - * BSEC REGISTER OFFSET (base relative) - */ -#define BSEC_OTP_CONF_OFF 0x000U -#define BSEC_OTP_CTRL_OFF 0x004U -#define BSEC_OTP_WRDATA_OFF 0x008U -#define BSEC_OTP_STATUS_OFF 0x00CU -#define BSEC_OTP_LOCK_OFF 0x010U -#define BSEC_DEN_OFF 0x014U -#define BSEC_DISTURBED_OFF 0x01CU -#define BSEC_DISTURBED1_OFF 0x020U -#define BSEC_DISTURBED2_OFF 0x024U -#define BSEC_ERROR_OFF 0x034U -#define BSEC_ERROR1_OFF 0x038U -#define BSEC_ERROR2_OFF 0x03CU -#define BSEC_WRLOCK_OFF 0x04CU /* Safmem permanent lock */ -#define BSEC_WRLOCK1_OFF 0x050U -#define BSEC_WRLOCK2_OFF 0x054U -#define BSEC_SPLOCK_OFF 0x064U /* Program safmem sticky lock */ -#define BSEC_SPLOCK1_OFF 0x068U -#define BSEC_SPLOCK2_OFF 0x06CU -#define BSEC_SWLOCK_OFF 0x07CU /* Write in OTP sticky lock */ -#define BSEC_SWLOCK1_OFF 0x080U -#define BSEC_SWLOCK2_OFF 0x084U -#define BSEC_SRLOCK_OFF 0x094U /* Shadowing sticky lock */ -#define BSEC_SRLOCK1_OFF 0x098U -#define BSEC_SRLOCK2_OFF 0x09CU -#define BSEC_JTAG_IN_OFF 0x0ACU -#define BSEC_JTAG_OUT_OFF 0x0B0U -#define BSEC_SCRATCH_OFF 0x0B4U -#define BSEC_OTP_DATA_OFF 0x200U -#define BSEC_IPHW_CFG_OFF 0xFF0U -#define BSEC_IPVR_OFF 0xFF4U -#define BSEC_IP_ID_OFF 0xFF8U -#define BSEC_IP_MAGIC_ID_OFF 0xFFCU - -/* - * BSEC_CONFIGURATION Register - */ -#define BSEC_CONF_POWER_UP_MASK BIT(0) -#define BSEC_CONF_POWER_UP_SHIFT 0 -#define BSEC_CONF_FRQ_MASK GENMASK(2, 1) -#define BSEC_CONF_FRQ_SHIFT 1 -#define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3) -#define BSEC_CONF_PRG_WIDTH_SHIFT 3 -#define BSEC_CONF_TREAD_MASK GENMASK(8, 7) -#define BSEC_CONF_TREAD_SHIFT 7 - -/* - * BSEC_CONTROL Register - */ -#define BSEC_READ 0x000U -#define BSEC_WRITE 0x100U -#define BSEC_LOCK 0x200U - -/* - * BSEC_OTP_LOCK register - */ -#define UPPER_OTP_LOCK_MASK BIT(0) -#define UPPER_OTP_LOCK_SHIFT 0 -#define DENREG_LOCK_MASK BIT(2) -#define DENREG_LOCK_SHIFT 2 -#define GPLOCK_LOCK_MASK BIT(4) -#define GPLOCK_LOCK_SHIFT 4 - -/* - * BSEC_OTP_STATUS Register - */ -#define BSEC_MODE_STATUS_MASK GENMASK(2, 0) -#define BSEC_MODE_BUSY_MASK BIT(3) -#define BSEC_MODE_PROGFAIL_MASK BIT(4) -#define BSEC_MODE_PWR_MASK BIT(5) -#define BSEC_MODE_BIST1_LOCK_MASK BIT(6) -#define BSEC_MODE_BIST2_LOCK_MASK BIT(7) - -/* OTP MODE*/ -#define BSEC_MODE_OPEN1 0x00 -#define BSEC_MODE_SECURED 0x01 -#define BSEC_MODE_OPEN2 0x02 -#define BSEC_MODE_INVALID 0x04 - -/* BSEC_DENABLE Register */ -#define BSEC_HDPEN BIT(4) -#define BSEC_SPIDEN BIT(5) -#define BSEC_SPINDEN BIT(6) -#define BSEC_DBGSWGEN BIT(10) -#define BSEC_DEN_ALL_MSK GENMASK(10, 0) - -/* BSEC_FENABLE Register */ -#define BSEC_FEN_ALL_MSK GENMASK(14, 0) +#define BSEC_TIMEOUT 0xFFFFFFF9U +#define BSEC_RETRY 0xFFFFFFF8U +#define BSEC_NOT_SUPPORTED 0xFFFFFFF7U +#define BSEC_WRITE_LOCKED 0xFFFFFFF6U /* - * OTP Lock services definition - * Value must corresponding to the bit number in the register + * get BSEC global state: result for bsec_get_secure_state() + * @state: global state + * [1:0] BSEC state + * 00b: Sec Open + * 01b: Sec Closed + * 11b: Invalid + * [8]: Hardware Key set = 1b */ -#define BSEC_LOCK_UPPER_OTP 0x00 -#define BSEC_LOCK_DEBUG 0x02 -#define BSEC_LOCK_PROGRAM 0x03 - -/* Values for struct bsec_config::freq */ -#define FREQ_10_20_MHZ 0x0 -#define FREQ_20_30_MHZ 0x1 -#define FREQ_30_45_MHZ 0x2 -#define FREQ_45_67_MHZ 0x3 - -/* - * Device info structure, providing device-specific functions and a means of - * adding driver-specific state - */ -struct bsec_config { - uint8_t tread; /* SAFMEM Reading current level default 0 */ - uint8_t pulse_width; /* SAFMEM Programming pulse width default 1 */ - uint8_t freq; /* SAFMEM CLOCK see freq value define - * default FREQ_45_67_MHZ - */ - uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */ - uint8_t prog_lock; /* Programming Sticky lock - * 1 programming is locked until next reset - */ - uint8_t den_lock; /* Debug enable sticky lock - * 1 debug enable is locked until next reset - */ - uint8_t upper_otp_lock; /* Shadowing of upper OTP sticky lock - * 1 shadowing of upper OTP is locked - * until next reset - */ -}; +#define BSEC_STATE_SEC_OPEN U(0x0) +#define BSEC_STATE_SEC_CLOSED U(0x1) +#define BSEC_STATE_INVALID U(0x3) +#define BSEC_STATE_MASK GENMASK_32(1, 0) uint32_t bsec_probe(void); -uint32_t bsec_get_base(void); - -uint32_t bsec_set_config(struct bsec_config *cfg); -uint32_t bsec_get_config(struct bsec_config *cfg); -uint32_t bsec_shadow_register(uint32_t otp); uint32_t bsec_read_otp(uint32_t *val, uint32_t otp); +uint32_t bsec_shadow_read_otp(uint32_t *val, uint32_t otp); uint32_t bsec_write_otp(uint32_t val, uint32_t otp); uint32_t bsec_program_otp(uint32_t val, uint32_t otp); -uint32_t bsec_permanent_lock_otp(uint32_t otp); -uint32_t bsec_write_debug_conf(uint32_t val); uint32_t bsec_read_debug_conf(void); -uint32_t bsec_write_feature_conf(uint32_t val); -uint32_t bsec_read_feature_conf(uint32_t *val); -uint32_t bsec_get_status(void); -uint32_t bsec_get_hw_conf(void); -uint32_t bsec_get_version(void); -uint32_t bsec_get_id(void); -uint32_t bsec_get_magic_id(void); +void bsec_write_scratch(uint32_t val); + +/* Sticky lock support */ +uint32_t bsec_set_sr_lock(uint32_t otp); +uint32_t bsec_read_sr_lock(uint32_t otp, bool *value); +uint32_t bsec_set_sw_lock(uint32_t otp); +uint32_t bsec_read_sw_lock(uint32_t otp, bool *value); +uint32_t bsec_set_sp_lock(uint32_t otp); +uint32_t bsec_read_sp_lock(uint32_t otp, bool *value); -bool bsec_write_sr_lock(uint32_t otp, uint32_t value); -bool bsec_read_sr_lock(uint32_t otp); -bool bsec_write_sw_lock(uint32_t otp, uint32_t value); -bool bsec_read_sw_lock(uint32_t otp); -bool bsec_write_sp_lock(uint32_t otp, uint32_t value); -bool bsec_read_sp_lock(uint32_t otp); -bool bsec_wr_lock(uint32_t otp); -uint32_t bsec_otp_lock(uint32_t service, uint32_t value); +uint32_t bsec_get_secure_state(void); +static inline bool bsec_mode_is_closed_device(void) +{ + return (bsec_get_secure_state() & BSEC_STATE_MASK) == BSEC_STATE_SEC_CLOSED; +} -uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word); +#if defined(IMAGE_BL32) +uint32_t bsec_permanent_lock_otp(uint32_t otp); uint32_t bsec_check_nsec_access_rights(uint32_t otp); +#endif #endif /* BSEC_H */ diff --git a/include/drivers/st/bsec2_reg.h b/include/drivers/st/bsec2_reg.h new file mode 100644 index 0000000000..fa44cf153e --- /dev/null +++ b/include/drivers/st/bsec2_reg.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2022-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BSEC2_REG_H +#define BSEC2_REG_H + +#include <lib/utils_def.h> + +/* IP configuration */ +#define ADDR_LOWER_OTP_PERLOCK_SHIFT 0x03 +#define DATA_LOWER_OTP_PERLOCK_BIT 0x03U /* 2 significants bits are used */ +#define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0) +#define ADDR_UPPER_OTP_PERLOCK_SHIFT 0x04 +#define DATA_UPPER_OTP_PERLOCK_BIT 0x01U /* 1 significants bits are used */ +#define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0) + +/* BSEC REGISTER OFFSET (base relative) */ +#define BSEC_OTP_CONF_OFF U(0x000) +#define BSEC_OTP_CTRL_OFF U(0x004) +#define BSEC_OTP_WRDATA_OFF U(0x008) +#define BSEC_OTP_STATUS_OFF U(0x00C) +#define BSEC_OTP_LOCK_OFF U(0x010) +#define BSEC_DEN_OFF U(0x014) +#define BSEC_DISTURBED_OFF U(0x01C) +#define BSEC_DISTURBED1_OFF U(0x020) +#define BSEC_DISTURBED2_OFF U(0x024) +#define BSEC_ERROR_OFF U(0x034) +#define BSEC_ERROR1_OFF U(0x038) +#define BSEC_ERROR2_OFF U(0x03C) +#define BSEC_WRLOCK_OFF U(0x04C) /* Safmem permanent lock */ +#define BSEC_WRLOCK1_OFF U(0x050) +#define BSEC_WRLOCK2_OFF U(0x054) +#define BSEC_SPLOCK_OFF U(0x064) /* Program safmem sticky lock */ +#define BSEC_SPLOCK1_OFF U(0x068) +#define BSEC_SPLOCK2_OFF U(0x06C) +#define BSEC_SWLOCK_OFF U(0x07C) /* Write in OTP sticky lock */ +#define BSEC_SWLOCK1_OFF U(0x080) +#define BSEC_SWLOCK2_OFF U(0x084) +#define BSEC_SRLOCK_OFF U(0x094) /* Shadowing sticky lock */ +#define BSEC_SRLOCK1_OFF U(0x098) +#define BSEC_SRLOCK2_OFF U(0x09C) +#define BSEC_JTAG_IN_OFF U(0x0AC) +#define BSEC_JTAG_OUT_OFF U(0x0B0) +#define BSEC_SCRATCH_OFF U(0x0B4) +#define BSEC_OTP_DATA_OFF U(0x200) +#define BSEC_IPHW_CFG_OFF U(0xFF0) +#define BSEC_IPVR_OFF U(0xFF4) +#define BSEC_IP_ID_OFF U(0xFF8) +#define BSEC_IP_MAGIC_ID_OFF U(0xFFC) + +#define BSEC_WRLOCK(n) (BSEC_WRLOCK_OFF + U(0x04) * (n)) +#define BSEC_SPLOCK(n) (BSEC_SPLOCK_OFF + U(0x04) * (n)) +#define BSEC_SWLOCK(n) (BSEC_SWLOCK_OFF + U(0x04) * (n)) +#define BSEC_SRLOCK(n) (BSEC_SRLOCK_OFF + U(0x04) * (n)) + +/* BSEC_CONFIGURATION Register */ +#define BSEC_CONF_POWER_UP_MASK BIT(0) +#define BSEC_CONF_POWER_UP_SHIFT 0 +#define BSEC_CONF_FRQ_MASK GENMASK(2, 1) +#define BSEC_CONF_FRQ_SHIFT 1 +#define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3) +#define BSEC_CONF_PRG_WIDTH_SHIFT 3 +#define BSEC_CONF_TREAD_MASK GENMASK(8, 7) +#define BSEC_CONF_TREAD_SHIFT 7 + +/* BSEC_CONTROL Register */ +#define BSEC_READ 0U +#define BSEC_WRITE BIT(8) +#define BSEC_LOCK BIT(9) + +/* BSEC_OTP_LOCK register */ +#define UPPER_OTP_LOCK_MASK BIT(0) +#define UPPER_OTP_LOCK_SHIFT 0 +#define DENREG_LOCK_MASK BIT(2) +#define DENREG_LOCK_SHIFT 2 +#define GPLOCK_LOCK_MASK BIT(4) +#define GPLOCK_LOCK_SHIFT 4 + +/* BSEC_OTP_STATUS Register */ +#define BSEC_OTP_STATUS_SECURE BIT(0) +#define BSEC_OTP_STATUS_INVALID BIT(2) +#define BSEC_OTP_STATUS_BUSY BIT(3) +#define BSEC_OTP_STATUS_PROGFAIL BIT(4) +#define BSEC_OTP_STATUS_PWRON BIT(5) + +/* BSEC_DENABLE Register */ +#define BSEC_HDPEN BIT(4) +#define BSEC_SPIDEN BIT(5) +#define BSEC_SPINDEN BIT(6) +#define BSEC_DBGSWGEN BIT(10) + +/* BSEC_FENABLE Register */ +#define BSEC_FEN_ALL_MSK GENMASK(14, 0) + +/* BSEC_IPVR Register */ +#define BSEC_IPVR_MSK GENMASK(7, 0) + +#endif /* BSEC2_REG_H */ diff --git a/include/drivers/st/bsec3_reg.h b/include/drivers/st/bsec3_reg.h new file mode 100644 index 0000000000..177e30ba51 --- /dev/null +++ b/include/drivers/st/bsec3_reg.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BSEC3_REG_H +#define BSEC3_REG_H + +#include <lib/utils_def.h> + +/* BSEC REGISTER OFFSET (base relative) */ +#define BSEC_FVR(x) (U(0x000) + 4U * (x)) +#define BSEC_SPLOCK(x) (U(0x800) + 4U * (x)) +#define BSEC_SWLOCK(x) (U(0x840) + 4U * (x)) +#define BSEC_SRLOCK(x) (U(0x880) + 4U * (x)) +#define BSEC_OTPVLDR(x) (U(0x8C0) + 4U * (x)) +#define BSEC_SFSR(x) (U(0x940) + 4U * (x)) +#define BSEC_OTPCR U(0xC04) +#define BSEC_WDR U(0xC08) +#define BSEC_SCRATCHR0 U(0xE00) +#define BSEC_SCRATCHR1 U(0xE04) +#define BSEC_SCRATCHR2 U(0xE08) +#define BSEC_SCRATCHR3 U(0xE0C) +#define BSEC_LOCKR U(0xE10) +#define BSEC_JTAGINR U(0xE14) +#define BSEC_JTAGOUTR U(0xE18) +#define BSEC_DENR U(0xE20) +#define BSEC_UNMAPR U(0xE24) +#define BSEC_SR U(0xE40) +#define BSEC_OTPSR U(0xE44) +#define BSEC_WRCR U(0xF00) +#define BSEC_HWCFGR U(0xFF0) +#define BSEC_VERR U(0xFF4) +#define BSEC_IPIDR U(0xFF8) +#define BSEC_SIDR U(0xFFC) + +/* BSEC_OTPCR register fields */ +#define BSEC_OTPCR_ADDR_MASK GENMASK_32(8, 0) +#define BSEC_OTPCR_ADDR_SHIFT U(0) +#define BSEC_OTPCR_PROG BIT_32(13) +#define BSEC_OTPCR_PPLOCK BIT_32(14) +#define BSEC_OTPCR_LASTCID_MASK GENMASK_32(21, 19) +#define BSEC_OTPCR_LASTCID_SHIFT U(19) + +/* BSEC_LOCKR register fields */ +#define BSEC_LOCKR_GWLOCK_MASK BIT_32(0) +#define BSEC_LOCKR_GWLOCK_SHIFT U(0) +#define BSEC_LOCKR_DENLOCK_MASK BIT_32(1) +#define BSEC_LOCKR_DENLOCK_SHIFT U(1) +#define BSEC_LOCKR_HKLOCK_MASK BIT_32(2) +#define BSEC_LOCKR_HKLOCK_SHIFT U(2) + +/* BSEC_DENR register fields */ +#define BSEC_DENR_LPDBGEN BIT_32(0) +#define BSEC_DENR_DBGENA BIT_32(1) +#define BSEC_DENR_NIDENA BIT_32(2) +#define BSEC_DENR_DEVICEEN BIT_32(3) +#define BSEC_DENR_HDPEN BIT_32(4) +#define BSEC_DENR_SPIDENA BIT_32(5) +#define BSEC_DENR_SPNIDENA BIT_32(6) +#define BSEC_DENR_DBGSWEN BIT_32(7) +#define BSEC_DENR_DBGENM BIT_32(8) +#define BSEC_DENR_NIDENM BIT_32(9) +#define BSEC_DENR_SPIDENM BIT_32(10) +#define BSEC_DENR_SPNIDENM BIT_32(11) +#define BSEC_DENR_CFGSDIS BIT_32(12) +#define BSEC_DENR_CP15SDIS_MASK GENMASK_32(14, 13) +#define BSEC_DENR_CP15SDIS_SHIFT U(13) +#define BSEC_DENR_LPDBGDIS BIT_32(15) +#define BSEC_DENR_ALL_MSK GENMASK_32(15, 0) + +/* BSEC_SR register fields */ +#define BSEC_SR_BUSY BIT_32(0) +#define BSEC_SR_HVALID BIT_32(1) +#define BSEC_SR_RNGERR BIT_32(2) +#define BSEC_SR_HKWW_MASK GENMASK_32(15, 8) +#define BSEC_SR_HKWW_SHIFT U(8) +#define BSEC_SR_NVSTATE_MASK GENMASK_32(31, 26) +#define BSEC_SR_NVSTATE_SHIFT U(26) +#define BSEC_SR_NVSTATE_OPEN U(0x16) +#define BSEC_SR_NVSTATE_CLOSED U(0x0D) +#define BSEC_SR_NVSTATE_OTP_LOCKED U(0x23) + +/* BSEC_OTPSR register fields */ +#define BSEC_OTPSR_BUSY BIT_32(0) +#define BSEC_OTPSR_FUSEOK BIT_32(1) +#define BSEC_OTPSR_HIDEUP BIT_32(2) +#define BSEC_OTPSR_OTPNVIR BIT_32(4) +#define BSEC_OTPSR_OTPERR BIT_32(5) +#define BSEC_OTPSR_OTPSEC BIT_32(6) +#define BSEC_OTPSR_PROGFAIL BIT_32(16) +#define BSEC_OTPSR_DISTURBF BIT_32(17) +#define BSEC_OTPSR_DEDF BIT_32(18) +#define BSEC_OTPSR_SECF BIT_32(19) +#define BSEC_OTPSR_PPLF BIT_32(20) +#define BSEC_OTPSR_PPLMF BIT_32(21) +#define BSEC_OTPSR_AMEF BIT_32(22) + +/* BSEC_VERR register fields */ +#define BSEC_VERR_MASK GENMASK_32(7, 0) + +#endif /* BSEC3_REG_H */ diff --git a/include/drivers/st/io_mmc.h b/include/drivers/st/io_mmc.h deleted file mode 100644 index 6179e89e2a..0000000000 --- a/include/drivers/st/io_mmc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef IO_MMC_H -#define IO_MMC_H - -#include <drivers/io/io_driver.h> - -struct io_mmc_dev_spec { - bool use_boot_part; -}; - -int register_io_dev_mmc(const io_dev_connector_t **dev_con); - -#endif /* IO_MMC_H */ diff --git a/include/drivers/st/io_stm32image.h b/include/drivers/st/io_stm32image.h deleted file mode 100644 index f9fa3630c6..0000000000 --- a/include/drivers/st/io_stm32image.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef IO_STM32IMAGE_H -#define IO_STM32IMAGE_H - -#include <drivers/io/io_driver.h> -#include <drivers/partition/partition.h> - -#define MAX_LBA_SIZE 512 -#define MAX_PART_NAME_SIZE (EFI_NAMELEN + 1) -#define STM32_PART_NUM (PLAT_PARTITION_MAX_ENTRIES - STM32_TF_A_COPIES) - -struct stm32image_part_info { - char name[MAX_PART_NAME_SIZE]; - uint32_t binary_type; - uintptr_t part_offset; - uint32_t bkp_offset; -}; - -struct stm32image_device_info { - struct stm32image_part_info part_info[STM32_PART_NUM]; - unsigned long long device_size; - uint32_t lba_size; -}; - -int register_io_dev_stm32image(const io_dev_connector_t **dev_con); - -#endif /* IO_STM32IMAGE_H */ diff --git a/include/drivers/st/regulator.h b/include/drivers/st/regulator.h new file mode 100644 index 0000000000..bf583e224b --- /dev/null +++ b/include/drivers/st/regulator.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef REGULATOR_H +#define REGULATOR_H + +#include <platform_def.h> + +#ifndef PLAT_NB_RDEVS +#error "Missing PLAT_NB_RDEVS" +#endif + +/* + * Consumer interface + */ + +/* regulator-always-on : regulator should never be disabled */ +#define REGUL_ALWAYS_ON BIT(0) +/* + * regulator-boot-on: + * It's expected that this regulator was left on by the bootloader. + * The core shouldn't prevent it from being turned off later. + * The regulator is needed to exit from suspend so it is turned on during suspend entry. + */ +#define REGUL_BOOT_ON BIT(1) +/* regulator-over-current-protection: Enable over current protection. */ +#define REGUL_OCP BIT(2) +/* regulator-active-discharge: enable active discharge. */ +#define REGUL_ACTIVE_DISCHARGE BIT(3) +/* regulator-pull-down: Enable pull down resistor when the regulator is disabled. */ +#define REGUL_PULL_DOWN BIT(4) +/* + * st,mask-reset: set mask reset for the regulator, meaning that the regulator + * setting is maintained during pmic reset. + */ +#define REGUL_MASK_RESET BIT(5) +/* st,regulator-sink-source: set the regulator in sink source mode */ +#define REGUL_SINK_SOURCE BIT(6) +/* st,regulator-bypass: set the regulator in bypass mode */ +#define REGUL_ENABLE_BYPASS BIT(7) + +struct rdev *regulator_get_by_name(const char *node_name); + +struct rdev *regulator_get_by_supply_name(const void *fdt, int node, const char *name); + +int regulator_enable(struct rdev *rdev); +int regulator_disable(struct rdev *rdev); +int regulator_is_enabled(const struct rdev *rdev); + +int regulator_set_voltage(struct rdev *rdev, uint16_t volt); +int regulator_set_min_voltage(struct rdev *rdev); +int regulator_get_voltage(const struct rdev *rdev); + +int regulator_list_voltages(const struct rdev *rdev, const uint16_t **levels, size_t *count); +void regulator_get_range(const struct rdev *rdev, uint16_t *min_mv, uint16_t *max_mv); +int regulator_set_flag(struct rdev *rdev, uint16_t flag); + +/* + * Driver Interface + */ + +/* set_state() arguments */ +#define STATE_DISABLE false +#define STATE_ENABLE true + +struct regul_description { + const char *node_name; + const struct regul_ops *ops; + const void *driver_data; + const char *supply_name; + const uint32_t enable_ramp_delay; +}; + +struct regul_ops { + int (*set_state)(const struct regul_description *desc, bool state); + int (*get_state)(const struct regul_description *desc); + int (*set_voltage)(const struct regul_description *desc, uint16_t mv); + int (*get_voltage)(const struct regul_description *desc); + int (*list_voltages)(const struct regul_description *desc, + const uint16_t **levels, size_t *count); + int (*set_flag)(const struct regul_description *desc, uint16_t flag); + void (*lock)(const struct regul_description *desc); + void (*unlock)(const struct regul_description *desc); +}; + +int regulator_register(const struct regul_description *desc, int node); + +/* + * Internal regulator structure + * The structure is internal to the core, and the content should not be used + * by a consumer nor a driver. + */ +struct rdev { + const struct regul_description *desc; + + int32_t phandle; + + uint16_t min_mv; + uint16_t max_mv; + + uint16_t flags; + + uint32_t enable_ramp_delay; +}; + +#endif /* REGULATOR_H */ diff --git a/include/drivers/st/regulator_fixed.h b/include/drivers/st/regulator_fixed.h new file mode 100644 index 0000000000..b981262e9a --- /dev/null +++ b/include/drivers/st/regulator_fixed.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef REGULATOR_FIXED_H +#define REGULATOR_FIXED_H + +int fixed_regulator_register(void); + +#endif /* REGULATOR_FIXED_H */ diff --git a/include/drivers/st/stm32_gpio.h b/include/drivers/st/stm32_gpio.h index e241f584f7..eeef9da5db 100644 --- a/include/drivers/st/stm32_gpio.h +++ b/include/drivers/st/stm32_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,7 @@ #define GPIO_TYPE_OFFSET U(0x04) #define GPIO_SPEED_OFFSET U(0x08) #define GPIO_PUPD_OFFSET U(0x0C) +#define GPIO_OD_OFFSET U(0x14) #define GPIO_BSRR_OFFSET U(0x18) #define GPIO_AFRL_OFFSET U(0x20) #define GPIO_AFRH_OFFSET U(0x24) @@ -26,32 +27,37 @@ #define GPIO_ALTERNATE_(_x) U(_x) #define GPIO_ALTERNATE_MASK U(0x0F) -#define GPIO_MODE_INPUT 0x00 -#define GPIO_MODE_OUTPUT 0x01 -#define GPIO_MODE_ALTERNATE 0x02 -#define GPIO_MODE_ANALOG 0x03 +#define GPIO_MODE_INPUT U(0x00) +#define GPIO_MODE_OUTPUT U(0x01) +#define GPIO_MODE_ALTERNATE U(0x02) +#define GPIO_MODE_ANALOG U(0x03) #define GPIO_MODE_MASK U(0x03) -#define GPIO_OPEN_DRAIN U(0x10) +#define GPIO_TYPE_PUSH_PULL U(0x00) +#define GPIO_TYPE_OPEN_DRAIN U(0x01) +#define GPIO_TYPE_MASK U(0x01) -#define GPIO_SPEED_LOW 0x00 -#define GPIO_SPEED_MEDIUM 0x01 -#define GPIO_SPEED_HIGH 0x02 -#define GPIO_SPEED_VERY_HIGH 0x03 +#define GPIO_SPEED_LOW U(0x00) +#define GPIO_SPEED_MEDIUM U(0x01) +#define GPIO_SPEED_HIGH U(0x02) +#define GPIO_SPEED_VERY_HIGH U(0x03) #define GPIO_SPEED_MASK U(0x03) -#define GPIO_NO_PULL 0x00 -#define GPIO_PULL_UP 0x01 -#define GPIO_PULL_DOWN 0x02 +#define GPIO_NO_PULL U(0x00) +#define GPIO_PULL_UP U(0x01) +#define GPIO_PULL_DOWN U(0x02) #define GPIO_PULL_MASK U(0x03) +#define GPIO_OD_OUTPUT_LOW U(0x00) +#define GPIO_OD_OUTPUT_HIGH U(0x01) +#define GPIO_OD_MASK U(0x01) + #ifndef __ASSEMBLER__ #include <stdint.h> int dt_set_pinctrl_config(int node); -void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, - uint32_t pull, uint32_t alternate, uint8_t status); void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure); +void set_gpio_reset_cfg(uint32_t bank, uint32_t pin); #endif /*__ASSEMBLER__*/ #endif /* STM32_GPIO_H */ diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h index df04730d6d..bebb4afdfd 100644 --- a/include/drivers/st/stm32_hash.h +++ b/include/drivers/st/stm32_hash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,19 @@ #ifndef STM32_HASH_H #define STM32_HASH_H +#include <stdint.h> + enum stm32_hash_algo_mode { +#if STM32_HASH_VER == 2 HASH_MD5SUM, +#endif HASH_SHA1, HASH_SHA224, - HASH_SHA256 + HASH_SHA256, +#if STM32_HASH_VER == 4 + HASH_SHA384, + HASH_SHA512, +#endif }; int stm32_hash_update(const uint8_t *buffer, size_t length); diff --git a/include/drivers/st/stm32_i2c.h b/include/drivers/st/stm32_i2c.h index 170d4cf815..ccb574b303 100644 --- a/include/drivers/st/stm32_i2c.h +++ b/include/drivers/st/stm32_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2016-2024, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -294,7 +294,6 @@ struct i2c_handle_s { /* STM32 specific defines */ #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ -#define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ #define STM32_I2C_DIGITAL_FILTER_MAX 16 diff --git a/include/drivers/st/stm32_pka.h b/include/drivers/st/stm32_pka.h new file mode 100644 index 0000000000..34b3f6b5fd --- /dev/null +++ b/include/drivers/st/stm32_pka.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_PKA_H +#define STM32_PKA_H + +#include <stdint.h> + +enum stm32_pka_ecdsa_curve_id { + PKA_NIST_P256, + PKA_BRAINPOOL_P256R1, + PKA_BRAINPOOL_P256T1, + PKA_NIST_P521, +}; + +struct stm32_pka_platdata { + uintptr_t base; + unsigned long clock_id; + unsigned int reset_id; +}; + +int stm32_pka_init(void); +int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size, + void *sig_r_ptr, unsigned int sig_r_size, + void *sig_s_ptr, unsigned int sig_s_size, + void *pk_x_ptr, unsigned int pk_x_size, + void *pk_y_ptr, unsigned int pk_y_size, + enum stm32_pka_ecdsa_curve_id cid); + +#endif /* STM32_PKA_H */ diff --git a/include/drivers/st/stm32_rng.h b/include/drivers/st/stm32_rng.h new file mode 100644 index 0000000000..6ac064d11e --- /dev/null +++ b/include/drivers/st/stm32_rng.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_RNG_H +#define STM32_RNG_H + +#include <stdint.h> + +int stm32_rng_read(uint8_t *out, uint32_t size); +int stm32_rng_init(void); + +#endif /* STM32_RNG_H */ diff --git a/include/drivers/st/stm32_saes.h b/include/drivers/st/stm32_saes.h new file mode 100644 index 0000000000..0a50438b93 --- /dev/null +++ b/include/drivers/st/stm32_saes.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_SAES_H +#define STM32_SAES_H + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#define DT_SAES_COMPAT "st,stm32-saes" + +struct stm32_saes_platdata { + uintptr_t base; + unsigned long clock_id; + unsigned int reset_id; +}; + +enum stm32_saes_chaining_mode { + STM32_SAES_MODE_ECB, + STM32_SAES_MODE_CBC, + STM32_SAES_MODE_CTR, + STM32_SAES_MODE_GCM, + STM32_SAES_MODE_CCM, /* Not use in TF-A */ +}; + +enum stm32_saes_key_selection { + STM32_SAES_KEY_SOFT, + STM32_SAES_KEY_DHU, /* Derived HW unique key */ + STM32_SAES_KEY_BH, /* Boot HW key */ + STM32_SAES_KEY_BHU_XOR_BH, /* XOR of DHUK and BHK */ + STM32_SAES_KEY_WRAPPED +}; + +struct stm32_saes_context { + uintptr_t base; + uint32_t cr; + uint32_t assoc_len; + uint32_t load_len; + uint32_t key[8]; /* In HW byte order */ + uint32_t iv[4]; /* In HW byte order */ +}; + +int stm32_saes_driver_init(void); + +int stm32_saes_init(struct stm32_saes_context *ctx, bool is_decrypt, + enum stm32_saes_chaining_mode ch_mode, enum stm32_saes_key_selection key_select, + const void *key, size_t key_len, const void *iv, size_t iv_len); +int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data_in, uint8_t *data_out, size_t data_len); +int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data, size_t data_len); +int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data_in, uint8_t *data_out, size_t data_len); +int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, size_t tag_len); +#endif diff --git a/include/drivers/st/stm32_sdmmc2.h b/include/drivers/st/stm32_sdmmc2.h index 4853208c2b..c83f62509a 100644 --- a/include/drivers/st/stm32_sdmmc2.h +++ b/include/drivers/st/stm32_sdmmc2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <stdbool.h> #include <drivers/mmc.h> +#include <drivers/st/regulator.h> struct stm32_sdmmc2_params { uintptr_t reg_base; @@ -24,6 +25,7 @@ struct stm32_sdmmc2_params { unsigned int reset_id; unsigned int max_freq; bool use_dma; + struct rdev *vmmc_regu; }; unsigned long long stm32_sdmmc2_mmc_get_device_size(void); diff --git a/include/drivers/st/stm32_uart.h b/include/drivers/st/stm32_uart.h new file mode 100644 index 0000000000..866e158907 --- /dev/null +++ b/include/drivers/st/stm32_uart.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_UART_H +#define STM32_UART_H + +/* UART word length */ +#define STM32_UART_WORDLENGTH_7B USART_CR1_M1 +#define STM32_UART_WORDLENGTH_8B 0x00000000U +#define STM32_UART_WORDLENGTH_9B USART_CR1_M0 + +/* UART number of stop bits */ +#define STM32_UART_STOPBITS_0_5 USART_CR2_STOP_0 +#define STM32_UART_STOPBITS_1 0x00000000U +#define STM32_UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) +#define STM32_UART_STOPBITS_2 USART_CR2_STOP_1 + +/* UART parity */ +#define STM32_UART_PARITY_NONE 0x00000000U +#define STM32_UART_PARITY_EVEN USART_CR1_PCE +#define STM32_UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) + +/* UART transfer mode */ +#define STM32_UART_MODE_RX USART_CR1_RE +#define STM32_UART_MODE_TX USART_CR1_TE +#define STM32_UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE) + +/* UART hardware flow control */ +#define STM32_UART_HWCONTROL_NONE 0x00000000U +#define STM32_UART_HWCONTROL_RTS USART_CR3_RTSE +#define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE +#define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) + +/* UART prescaler */ +#define STM32_UART_PRESCALER_DIV1 0x00000000U +#define STM32_UART_PRESCALER_DIV2 0x00000001U +#define STM32_UART_PRESCALER_DIV4 0x00000002U +#define STM32_UART_PRESCALER_DIV6 0x00000003U +#define STM32_UART_PRESCALER_DIV8 0x00000004U +#define STM32_UART_PRESCALER_DIV10 0x00000005U +#define STM32_UART_PRESCALER_DIV12 0x00000006U +#define STM32_UART_PRESCALER_DIV16 0x00000007U +#define STM32_UART_PRESCALER_DIV32 0x00000008U +#define STM32_UART_PRESCALER_DIV64 0x00000009U +#define STM32_UART_PRESCALER_DIV128 0x0000000AU +#define STM32_UART_PRESCALER_DIV256 0x0000000BU +#define STM32_UART_PRESCALER_NB 0x0000000CU + +/* UART fifo mode */ +#define STM32_UART_FIFOMODE_EN USART_CR1_FIFOEN +#define STM32_UART_FIFOMODE_DIS 0x00000000U + +/* UART TXFIFO threshold level */ +#define STM32_UART_TXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U +#define STM32_UART_TXFIFO_THRESHOLD_1QUARTERFUL USART_CR3_TXFTCFG_0 +#define STM32_UART_TXFIFO_THRESHOLD_HALFFULL USART_CR3_TXFTCFG_1 +#define STM32_UART_TXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_TXFTCFG_0 | USART_CR3_TXFTCFG_1) +#define STM32_UART_TXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_TXFTCFG_2 +#define STM32_UART_TXFIFO_THRESHOLD_EMPTY (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0) + +/* UART RXFIFO threshold level */ +#define STM32_UART_RXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U +#define STM32_UART_RXFIFO_THRESHOLD_1QUARTERFULL USART_CR3_RXFTCFG_0 +#define STM32_UART_RXFIFO_THRESHOLD_HALFFULL USART_CR3_RXFTCFG_1 +#define STM32_UART_RXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_RXFTCFG_0 | USART_CR3_RXFTCFG_1) +#define STM32_UART_RXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_RXFTCFG_2 +#define STM32_UART_RXFIFO_THRESHOLD_FULL (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0) + +struct stm32_uart_init_s { + uint32_t baud_rate; /* + * Configures the UART communication + * baud rate. + */ + + uint32_t word_length; /* + * Specifies the number of data bits + * transmitted or received in a frame. + * This parameter can be a value of + * @ref STM32_UART_WORDLENGTH_*. + */ + + uint32_t stop_bits; /* + * Specifies the number of stop bits + * transmitted. This parameter can be + * a value of @ref STM32_UART_STOPBITS_*. + */ + + uint32_t parity; /* + * Specifies the parity mode. + * This parameter can be a value of + * @ref STM32_UART_PARITY_*. + */ + + uint32_t mode; /* + * Specifies whether the receive or + * transmit mode is enabled or + * disabled. This parameter can be a + * value of @ref @ref STM32_UART_MODE_*. + */ + + uint32_t hw_flow_control; /* + * Specifies whether the hardware flow + * control mode is enabled or + * disabled. This parameter can be a + * value of @ref STM32_UARTHWCONTROL_*. + */ + + uint32_t one_bit_sampling; /* + * Specifies whether a single sample + * or three samples' majority vote is + * selected. This parameter can be 0 + * or USART_CR3_ONEBIT. + */ + + uint32_t prescaler; /* + * Specifies the prescaler value used + * to divide the UART clock source. + * This parameter can be a value of + * @ref STM32_UART_PRESCALER_*. + */ + + uint32_t fifo_mode; /* + * Specifies if the FIFO mode will be + * used. This parameter can be a value + * of @ref STM32_UART_FIFOMODE_*. + */ + + uint32_t tx_fifo_threshold; /* + * Specifies the TXFIFO threshold + * level. This parameter can be a + * value of @ref + * STM32_UART_TXFIFO_THRESHOLD_*. + */ + + uint32_t rx_fifo_threshold; /* + * Specifies the RXFIFO threshold + * level. This parameter can be a + * value of @ref + * STM32_UART_RXFIFO_THRESHOLD_*. + */ +}; + +struct stm32_uart_handle_s { + uint32_t base; + uint32_t rdr_mask; +}; + +int stm32_uart_init(struct stm32_uart_handle_s *huart, + uintptr_t base_addr, + const struct stm32_uart_init_s *init); +void stm32_uart_stop(uintptr_t base_addr); +int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c); +int stm32_uart_flush(struct stm32_uart_handle_s *huart); +int stm32_uart_getc(struct stm32_uart_handle_s *huart); + +#endif /* STM32_UART_H */ diff --git a/include/drivers/st/stm32mp13_rcc.h b/include/drivers/st/stm32mp13_rcc.h new file mode 100644 index 0000000000..1451c9a128 --- /dev/null +++ b/include/drivers/st/stm32mp13_rcc.h @@ -0,0 +1,1878 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP13_RCC_H +#define STM32MP13_RCC_H + +#include <lib/utils_def.h> + +#define RCC_SECCFGR U(0X0) +#define RCC_MP_SREQSETR U(0X100) +#define RCC_MP_SREQCLRR U(0X104) +#define RCC_MP_APRSTCR U(0X108) +#define RCC_MP_APRSTSR U(0X10C) +#define RCC_PWRLPDLYCR U(0X110) +#define RCC_MP_GRSTCSETR U(0X114) +#define RCC_BR_RSTSCLRR U(0X118) +#define RCC_MP_RSTSSETR U(0X11C) +#define RCC_MP_RSTSCLRR U(0X120) +#define RCC_MP_IWDGFZSETR U(0X124) +#define RCC_MP_IWDGFZCLRR U(0X128) +#define RCC_MP_CIER U(0X200) +#define RCC_MP_CIFR U(0X204) +#define RCC_BDCR U(0X400) +#define RCC_RDLSICR U(0X404) +#define RCC_OCENSETR U(0X420) +#define RCC_OCENCLRR U(0X424) +#define RCC_OCRDYR U(0X428) +#define RCC_HSICFGR U(0X440) +#define RCC_CSICFGR U(0X444) +#define RCC_MCO1CFGR U(0X460) +#define RCC_MCO2CFGR U(0X464) +#define RCC_DBGCFGR U(0X468) +#define RCC_RCK12SELR U(0X480) +#define RCC_RCK3SELR U(0X484) +#define RCC_RCK4SELR U(0X488) +#define RCC_PLL1CR U(0X4A0) +#define RCC_PLL1CFGR1 U(0X4A4) +#define RCC_PLL1CFGR2 U(0X4A8) +#define RCC_PLL1FRACR U(0X4AC) +#define RCC_PLL1CSGR U(0X4B0) +#define RCC_PLL2CR U(0X4D0) +#define RCC_PLL2CFGR1 U(0X4D4) +#define RCC_PLL2CFGR2 U(0X4D8) +#define RCC_PLL2FRACR U(0X4DC) +#define RCC_PLL2CSGR U(0X4E0) +#define RCC_PLL3CR U(0X500) +#define RCC_PLL3CFGR1 U(0X504) +#define RCC_PLL3CFGR2 U(0X508) +#define RCC_PLL3FRACR U(0X50C) +#define RCC_PLL3CSGR U(0X510) +#define RCC_PLL4CR U(0X520) +#define RCC_PLL4CFGR1 U(0X524) +#define RCC_PLL4CFGR2 U(0X528) +#define RCC_PLL4FRACR U(0X52C) +#define RCC_PLL4CSGR U(0X530) +#define RCC_MPCKSELR U(0X540) +#define RCC_ASSCKSELR U(0X544) +#define RCC_MSSCKSELR U(0X548) +#define RCC_CPERCKSELR U(0X54C) +#define RCC_RTCDIVR U(0X560) +#define RCC_MPCKDIVR U(0X564) +#define RCC_AXIDIVR U(0X568) +#define RCC_MLAHBDIVR U(0X56C) +#define RCC_APB1DIVR U(0X570) +#define RCC_APB2DIVR U(0X574) +#define RCC_APB3DIVR U(0X578) +#define RCC_APB4DIVR U(0X57C) +#define RCC_APB5DIVR U(0X580) +#define RCC_APB6DIVR U(0X584) +#define RCC_TIMG1PRER U(0X5A0) +#define RCC_TIMG2PRER U(0X5A4) +#define RCC_TIMG3PRER U(0X5A8) +#define RCC_DDRITFCR U(0X5C0) +#define RCC_I2C12CKSELR U(0X600) +#define RCC_I2C345CKSELR U(0X604) +#define RCC_SPI2S1CKSELR U(0X608) +#define RCC_SPI2S23CKSELR U(0X60C) +#define RCC_SPI45CKSELR U(0X610) +#define RCC_UART12CKSELR U(0X614) +#define RCC_UART35CKSELR U(0X618) +#define RCC_UART4CKSELR U(0X61C) +#define RCC_UART6CKSELR U(0X620) +#define RCC_UART78CKSELR U(0X624) +#define RCC_LPTIM1CKSELR U(0X628) +#define RCC_LPTIM23CKSELR U(0X62C) +#define RCC_LPTIM45CKSELR U(0X630) +#define RCC_SAI1CKSELR U(0X634) +#define RCC_SAI2CKSELR U(0X638) +#define RCC_FDCANCKSELR U(0X63C) +#define RCC_SPDIFCKSELR U(0X640) +#define RCC_ADC12CKSELR U(0X644) +#define RCC_SDMMC12CKSELR U(0X648) +#define RCC_ETH12CKSELR U(0X64C) +#define RCC_USBCKSELR U(0X650) +#define RCC_QSPICKSELR U(0X654) +#define RCC_FMCCKSELR U(0X658) +#define RCC_RNG1CKSELR U(0X65C) +#define RCC_STGENCKSELR U(0X660) +#define RCC_DCMIPPCKSELR U(0X664) +#define RCC_SAESCKSELR U(0X668) +#define RCC_APB1RSTSETR U(0X6A0) +#define RCC_APB1RSTCLRR U(0X6A4) +#define RCC_APB2RSTSETR U(0X6A8) +#define RCC_APB2RSTCLRR U(0X6AC) +#define RCC_APB3RSTSETR U(0X6B0) +#define RCC_APB3RSTCLRR U(0X6B4) +#define RCC_APB4RSTSETR U(0X6B8) +#define RCC_APB4RSTCLRR U(0X6BC) +#define RCC_APB5RSTSETR U(0X6C0) +#define RCC_APB5RSTCLRR U(0X6C4) +#define RCC_APB6RSTSETR U(0X6C8) +#define RCC_APB6RSTCLRR U(0X6CC) +#define RCC_AHB2RSTSETR U(0X6D0) +#define RCC_AHB2RSTCLRR U(0X6D4) +#define RCC_AHB4RSTSETR U(0X6E0) +#define RCC_AHB4RSTCLRR U(0X6E4) +#define RCC_AHB5RSTSETR U(0X6E8) +#define RCC_AHB5RSTCLRR U(0X6EC) +#define RCC_AHB6RSTSETR U(0X6F0) +#define RCC_AHB6RSTCLRR U(0X6F4) +#define RCC_MP_APB1ENSETR U(0X700) +#define RCC_MP_APB1ENCLRR U(0X704) +#define RCC_MP_APB2ENSETR U(0X708) +#define RCC_MP_APB2ENCLRR U(0X70C) +#define RCC_MP_APB3ENSETR U(0X710) +#define RCC_MP_APB3ENCLRR U(0X714) +#define RCC_MP_S_APB3ENSETR U(0X718) +#define RCC_MP_S_APB3ENCLRR U(0X71C) +#define RCC_MP_NS_APB3ENSETR U(0X720) +#define RCC_MP_NS_APB3ENCLRR U(0X724) +#define RCC_MP_APB4ENSETR U(0X728) +#define RCC_MP_APB4ENCLRR U(0X72C) +#define RCC_MP_S_APB4ENSETR U(0X730) +#define RCC_MP_S_APB4ENCLRR U(0X734) +#define RCC_MP_NS_APB4ENSETR U(0X738) +#define RCC_MP_NS_APB4ENCLRR U(0X73C) +#define RCC_MP_APB5ENSETR U(0X740) +#define RCC_MP_APB5ENCLRR U(0X744) +#define RCC_MP_APB6ENSETR U(0X748) +#define RCC_MP_APB6ENCLRR U(0X74C) +#define RCC_MP_AHB2ENSETR U(0X750) +#define RCC_MP_AHB2ENCLRR U(0X754) +#define RCC_MP_AHB4ENSETR U(0X760) +#define RCC_MP_AHB4ENCLRR U(0X764) +#define RCC_MP_S_AHB4ENSETR U(0X768) +#define RCC_MP_S_AHB4ENCLRR U(0X76C) +#define RCC_MP_NS_AHB4ENSETR U(0X770) +#define RCC_MP_NS_AHB4ENCLRR U(0X774) +#define RCC_MP_AHB5ENSETR U(0X778) +#define RCC_MP_AHB5ENCLRR U(0X77C) +#define RCC_MP_AHB6ENSETR U(0X780) +#define RCC_MP_AHB6ENCLRR U(0X784) +#define RCC_MP_S_AHB6ENSETR U(0X788) +#define RCC_MP_S_AHB6ENCLRR U(0X78C) +#define RCC_MP_NS_AHB6ENSETR U(0X790) +#define RCC_MP_NS_AHB6ENCLRR U(0X794) +#define RCC_MP_APB1LPENSETR U(0X800) +#define RCC_MP_APB1LPENCLRR U(0X804) +#define RCC_MP_APB2LPENSETR U(0X808) +#define RCC_MP_APB2LPENCLRR U(0X80C) +#define RCC_MP_APB3LPENSETR U(0X810) +#define RCC_MP_APB3LPENCLRR U(0X814) +#define RCC_MP_S_APB3LPENSETR U(0X818) +#define RCC_MP_S_APB3LPENCLRR U(0X81C) +#define RCC_MP_NS_APB3LPENSETR U(0X820) +#define RCC_MP_NS_APB3LPENCLRR U(0X824) +#define RCC_MP_APB4LPENSETR U(0X828) +#define RCC_MP_APB4LPENCLRR U(0X82C) +#define RCC_MP_S_APB4LPENSETR U(0X830) +#define RCC_MP_S_APB4LPENCLRR U(0X834) +#define RCC_MP_NS_APB4LPENSETR U(0X838) +#define RCC_MP_NS_APB4LPENCLRR U(0X83C) +#define RCC_MP_APB5LPENSETR U(0X840) +#define RCC_MP_APB5LPENCLRR U(0X844) +#define RCC_MP_APB6LPENSETR U(0X848) +#define RCC_MP_APB6LPENCLRR U(0X84C) +#define RCC_MP_AHB2LPENSETR U(0X850) +#define RCC_MP_AHB2LPENCLRR U(0X854) +#define RCC_MP_AHB4LPENSETR U(0X858) +#define RCC_MP_AHB4LPENCLRR U(0X85C) +#define RCC_MP_S_AHB4LPENSETR U(0X868) +#define RCC_MP_S_AHB4LPENCLRR U(0X86C) +#define RCC_MP_NS_AHB4LPENSETR U(0X870) +#define RCC_MP_NS_AHB4LPENCLRR U(0X874) +#define RCC_MP_AHB5LPENSETR U(0X878) +#define RCC_MP_AHB5LPENCLRR U(0X87C) +#define RCC_MP_AHB6LPENSETR U(0X880) +#define RCC_MP_AHB6LPENCLRR U(0X884) +#define RCC_MP_S_AHB6LPENSETR U(0X888) +#define RCC_MP_S_AHB6LPENCLRR U(0X88C) +#define RCC_MP_NS_AHB6LPENSETR U(0X890) +#define RCC_MP_NS_AHB6LPENCLRR U(0X894) +#define RCC_MP_S_AXIMLPENSETR U(0X898) +#define RCC_MP_S_AXIMLPENCLRR U(0X89C) +#define RCC_MP_NS_AXIMLPENSETR U(0X8A0) +#define RCC_MP_NS_AXIMLPENCLRR U(0X8A4) +#define RCC_MP_MLAHBLPENSETR U(0X8A8) +#define RCC_MP_MLAHBLPENCLRR U(0X8AC) +#define RCC_APB3SECSR U(0X8C0) +#define RCC_APB4SECSR U(0X8C4) +#define RCC_APB5SECSR U(0X8C8) +#define RCC_APB6SECSR U(0X8CC) +#define RCC_AHB2SECSR U(0X8D0) +#define RCC_AHB4SECSR U(0X8D4) +#define RCC_AHB5SECSR U(0X8D8) +#define RCC_AHB6SECSR U(0X8DC) +#define RCC_VERR U(0XFF4) +#define RCC_IDR U(0XFF8) +#define RCC_SIDR U(0XFFC) + +/* RCC_SECCFGR register fields */ +#define RCC_SECCFGR_HSISEC BIT(0) +#define RCC_SECCFGR_CSISEC BIT(1) +#define RCC_SECCFGR_HSESEC BIT(2) +#define RCC_SECCFGR_LSISEC BIT(3) +#define RCC_SECCFGR_LSESEC BIT(4) +#define RCC_SECCFGR_PLL12SEC BIT(8) +#define RCC_SECCFGR_PLL3SEC BIT(9) +#define RCC_SECCFGR_PLL4SEC BIT(10) +#define RCC_SECCFGR_MPUSEC BIT(11) +#define RCC_SECCFGR_AXISEC BIT(12) +#define RCC_SECCFGR_MLAHBSEC BIT(13) +#define RCC_SECCFGR_APB3DIVSEC BIT(16) +#define RCC_SECCFGR_APB4DIVSEC BIT(17) +#define RCC_SECCFGR_APB5DIVSEC BIT(18) +#define RCC_SECCFGR_APB6DIVSEC BIT(19) +#define RCC_SECCFGR_TIMG3SEC BIT(20) +#define RCC_SECCFGR_CPERSEC BIT(21) +#define RCC_SECCFGR_MCO1SEC BIT(22) +#define RCC_SECCFGR_MCO2SEC BIT(23) +#define RCC_SECCFGR_STPSEC BIT(24) +#define RCC_SECCFGR_RSTSEC BIT(25) +#define RCC_SECCFGR_PWRSEC BIT(31) + +/* RCC_MP_SREQSETR register fields */ +#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) + +/* RCC_MP_SREQCLRR register fields */ +#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) + +/* RCC_MP_APRSTCR register fields */ +#define RCC_MP_APRSTCR_RDCTLEN BIT(0) +#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) +#define RCC_MP_APRSTCR_RSTTO_SHIFT 8 + +/* RCC_MP_APRSTSR register fields */ +#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) +#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 + +/* RCC_MP_GRSTCSETR register fields */ +#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) + +/* RCC_BR_RSTSCLRR register fields */ +#define RCC_BR_RSTSCLRR_PORRSTF BIT(0) +#define RCC_BR_RSTSCLRR_BORRSTF BIT(1) +#define RCC_BR_RSTSCLRR_PADRSTF BIT(2) +#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_BR_RSTSCLRR_VCPURSTF BIT(5) +#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) + +/* RCC_MP_RSTSSETR register fields */ +#define RCC_MP_RSTSSETR_PORRSTF BIT(0) +#define RCC_MP_RSTSSETR_BORRSTF BIT(1) +#define RCC_MP_RSTSSETR_PADRSTF BIT(2) +#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSSETR_VCORERSTF BIT(4) +#define RCC_MP_RSTSSETR_VCPURSTF BIT(5) +#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSSETR_STP2RSTF BIT(10) +#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSSETR_SPARE BIT(15) + +/* RCC_MP_RSTSCLRR register fields */ +#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MP_RSTSCLRR_VCPURSTF BIT(5) +#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSCLRR_STP2RSTF BIT(10) +#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSCLRR_SPARE BIT(15) + +/* RCC_MP_IWDGFZSETR register fields */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) + +/* RCC_MP_IWDGFZCLRR register fields */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_MP_CIER register fields */ +#define RCC_MP_CIER_LSIRDYIE BIT(0) +#define RCC_MP_CIER_LSERDYIE BIT(1) +#define RCC_MP_CIER_HSIRDYIE BIT(2) +#define RCC_MP_CIER_HSERDYIE BIT(3) +#define RCC_MP_CIER_CSIRDYIE BIT(4) +#define RCC_MP_CIER_PLL1DYIE BIT(8) +#define RCC_MP_CIER_PLL2DYIE BIT(9) +#define RCC_MP_CIER_PLL3DYIE BIT(10) +#define RCC_MP_CIER_PLL4DYIE BIT(11) +#define RCC_MP_CIER_LSECSSIE BIT(16) +#define RCC_MP_CIER_WKUPIE BIT(20) + +/* RCC_MP_CIFR register fields */ +#define RCC_MP_CIFR_LSIRDYF BIT(0) +#define RCC_MP_CIFR_LSERDYF BIT(1) +#define RCC_MP_CIFR_HSIRDYF BIT(2) +#define RCC_MP_CIFR_HSERDYF BIT(3) +#define RCC_MP_CIFR_CSIRDYF BIT(4) +#define RCC_MP_CIFR_PLL1DYF BIT(8) +#define RCC_MP_CIFR_PLL2DYF BIT(9) +#define RCC_MP_CIFR_PLL3DYF BIT(10) +#define RCC_MP_CIFR_PLL4DYF BIT(11) +#define RCC_MP_CIFR_LSECSSF BIT(16) +#define RCC_MP_CIFR_WKUPF BIT(20) + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_DIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(8) +#define RCC_BDCR_LSECSSD BIT(9) +#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_VSWRST BIT(31) + +#define RCC_BDCR_LSEBYP_BIT 1 +#define RCC_BDCR_LSERDY_BIT 2 +#define RCC_BDCR_DIGBYP_BIT 3 +#define RCC_BDCR_LSECSSON_BIT 8 + +#define RCC_BDCR_LSEDRV_WIDTH 2 + +/* RCC_RDLSICR register fields */ +#define RCC_RDLSICR_LSION BIT(0) +#define RCC_RDLSICR_LSIRDY BIT(1) +#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) +#define RCC_RDLSICR_MRD_SHIFT 16 +#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) +#define RCC_RDLSICR_EADLY_SHIFT 24 +#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) +#define RCC_RDLSICR_SPARE_SHIFT 27 + +#define RCC_RDLSICR_LSIRDY_BIT 1 + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_CSION BIT(4) +#define RCC_OCENSETR_CSIKERON BIT(5) +#define RCC_OCENSETR_DIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +#define RCC_OCENR_DIGBYP_BIT 7 +#define RCC_OCENR_HSEBYP_BIT 10 +#define RCC_OCENR_HSECSSON_BIT 11 + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_CSION BIT(4) +#define RCC_OCENCLRR_CSIKERON BIT(5) +#define RCC_OCENCLRR_DIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSIDIVRDY BIT(2) +#define RCC_OCRDYR_CSIRDY BIT(4) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_MPUCKRDY BIT(23) +#define RCC_OCRDYR_AXICKRDY BIT(24) + +#define RCC_OCRDYR_HSIRDY_BIT 0 +#define RCC_OCRDYR_HSIDIVRDY_BIT 2 +#define RCC_OCRDYR_CSIRDY_BIT 4 +#define RCC_OCRDYR_HSERDY_BIT 8 + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) +#define RCC_HSICFGR_HSIDIV_SHIFT 0 +#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) +#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 +#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) +#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 +#define RCC_MCO1CFGR_MCO1ON BIT(12) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) +#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 +#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) +#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 +#define RCC_MCO2CFGR_MCO2ON BIT(12) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) +#define RCC_DBGCFGR_TRACEDIV_SHIFT 0 +#define RCC_DBGCFGR_DBGCKEN BIT(8) +#define RCC_DBGCFGR_TRACECKEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_RCK12SELR register fields */ +#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) +#define RCC_RCK12SELR_PLL12SRC_SHIFT 0 +#define RCC_RCK12SELR_PLL12SRCRDY BIT(31) + +/* RCC_RCK3SELR register fields */ +#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) +#define RCC_RCK3SELR_PLL3SRC_SHIFT 0 +#define RCC_RCK3SELR_PLL3SRCRDY BIT(31) + +/* RCC_RCK4SELR register fields */ +#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) +#define RCC_RCK4SELR_PLL4SRC_SHIFT 0 +#define RCC_RCK4SELR_PLL4SRCRDY BIT(31) + +/* RCC_PLL1CR register fields */ +#define RCC_PLL1CR_PLLON BIT(0) +#define RCC_PLL1CR_PLL1RDY BIT(1) +#define RCC_PLL1CR_SSCG_CTRL BIT(2) +#define RCC_PLL1CR_DIVPEN BIT(4) +#define RCC_PLL1CR_DIVQEN BIT(5) +#define RCC_PLL1CR_DIVREN BIT(6) + +/* RCC_PLL1CFGR1 register fields */ +#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL1CFGR1_DIVN_SHIFT 0 +#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) +#define RCC_PLL1CFGR1_DIVM1_SHIFT 16 + +/* RCC_PLL1CFGR2 register fields */ +#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL1CFGR2_DIVP_SHIFT 0 +#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL1CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL1CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL1FRACR register fields */ +#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL1FRACR_FRACV_SHIFT 3 +#define RCC_PLL1FRACR_FRACLE BIT(16) + +/* RCC_PLL1CSGR register fields */ +#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL1CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL1CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL1CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL1CSGR_SSCG_MODE BIT(15) +#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL1CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL2CR register fields */ +#define RCC_PLL2CR_PLLON BIT(0) +#define RCC_PLL2CR_PLL2RDY BIT(1) +#define RCC_PLL2CR_SSCG_CTRL BIT(2) +#define RCC_PLL2CR_DIVPEN BIT(4) +#define RCC_PLL2CR_DIVQEN BIT(5) +#define RCC_PLL2CR_DIVREN BIT(6) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL2CFGR1_DIVN_SHIFT 0 +#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) +#define RCC_PLL2CFGR1_DIVM2_SHIFT 16 + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL2CFGR2_DIVP_SHIFT 0 +#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL2CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL2CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL2FRACR register fields */ +#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL2FRACR_FRACV_SHIFT 3 +#define RCC_PLL2FRACR_FRACLE BIT(16) + +/* RCC_PLL2CSGR register fields */ +#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL2CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL2CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL2CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL2CSGR_SSCG_MODE BIT(15) +#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL2CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL3CR register fields */ +#define RCC_PLL3CR_PLLON BIT(0) +#define RCC_PLL3CR_PLL3RDY BIT(1) +#define RCC_PLL3CR_SSCG_CTRL BIT(2) +#define RCC_PLL3CR_DIVPEN BIT(4) +#define RCC_PLL3CR_DIVQEN BIT(5) +#define RCC_PLL3CR_DIVREN BIT(6) + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL3CFGR1_DIVN_SHIFT 0 +#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) +#define RCC_PLL3CFGR1_DIVM3_SHIFT 16 +#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL3CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL3CFGR2_DIVP_SHIFT 0 +#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL3CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL3CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL3FRACR register fields */ +#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL3FRACR_FRACV_SHIFT 3 +#define RCC_PLL3FRACR_FRACLE BIT(16) + +/* RCC_PLL3CSGR register fields */ +#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL3CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL3CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL3CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL3CSGR_SSCG_MODE BIT(15) +#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL3CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL4CR register fields */ +#define RCC_PLL4CR_PLLON BIT(0) +#define RCC_PLL4CR_PLL4RDY BIT(1) +#define RCC_PLL4CR_SSCG_CTRL BIT(2) +#define RCC_PLL4CR_DIVPEN BIT(4) +#define RCC_PLL4CR_DIVQEN BIT(5) +#define RCC_PLL4CR_DIVREN BIT(6) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL4CFGR1_DIVN_SHIFT 0 +#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) +#define RCC_PLL4CFGR1_DIVM4_SHIFT 16 +#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL4CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL4CFGR2_DIVP_SHIFT 0 +#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL4CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL4CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL4FRACR register fields */ +#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL4FRACR_FRACV_SHIFT 3 +#define RCC_PLL4FRACR_FRACLE BIT(16) + +/* RCC_PLL4CSGR register fields */ +#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL4CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL4CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL4CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL4CSGR_SSCG_MODE BIT(15) +#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL4CSGR_INC_STEP_SHIFT 16 + +/* RCC_MPCKSELR register fields */ +#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) +#define RCC_MPCKSELR_MPUSRC_SHIFT 0 +#define RCC_MPCKSELR_MPUSRCRDY BIT(31) + +/* RCC_ASSCKSELR register fields */ +#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) +#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 +#define RCC_ASSCKSELR_AXISSRCRDY BIT(31) + +/* RCC_MSSCKSELR register fields */ +#define RCC_MSSCKSELR_MLAHBSSRC_MASK GENMASK(1, 0) +#define RCC_MSSCKSELR_MLAHBSSRC_SHIFT 0 +#define RCC_MSSCKSELR_MLAHBSSRCRDY BIT(31) + +/* RCC_CPERCKSELR register fields */ +#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_MPCKDIVR register fields */ +#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(3, 0) +#define RCC_MPCKDIVR_MPUDIV_SHIFT 0 +#define RCC_MPCKDIVR_MPUDIVRDY BIT(31) + +/* RCC_AXIDIVR register fields */ +#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIVR_AXIDIV_SHIFT 0 +#define RCC_AXIDIVR_AXIDIVRDY BIT(31) + +/* RCC_MLAHBDIVR register fields */ +#define RCC_MLAHBDIVR_MLAHBDIV_MASK GENMASK(3, 0) +#define RCC_MLAHBDIVR_MLAHBDIV_SHIFT 0 +#define RCC_MLAHBDIVR_MLAHBDIVRDY BIT(31) + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APB5DIVR register fields */ +#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) +#define RCC_APB5DIVR_APB5DIV_SHIFT 0 +#define RCC_APB5DIVR_APB5DIVRDY BIT(31) + +/* RCC_APB6DIVR register fields */ +#define RCC_APB6DIVR_APB6DIV_MASK GENMASK(2, 0) +#define RCC_APB6DIVR_APB6DIV_SHIFT 0 +#define RCC_APB6DIVR_APB6DIVRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_TIMG3PRER register fields */ +#define RCC_TIMG3PRER_TIMG3PRE BIT(0) +#define RCC_TIMG3PRER_TIMG3PRERDY BIT(31) + +/* RCC_DDRITFCR register fields */ +#define RCC_DDRITFCR_DDRC1EN BIT(0) +#define RCC_DDRITFCR_DDRC1LPEN BIT(1) +#define RCC_DDRITFCR_DDRPHYCEN BIT(4) +#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) +#define RCC_DDRITFCR_DDRCAPBEN BIT(6) +#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) +#define RCC_DDRITFCR_AXIDCGEN BIT(8) +#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) +#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) +#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 +#define RCC_DDRITFCR_DDRCAPBRST BIT(14) +#define RCC_DDRITFCR_DDRCAXIRST BIT(15) +#define RCC_DDRITFCR_DDRCORERST BIT(16) +#define RCC_DDRITFCR_DPHYAPBRST BIT(17) +#define RCC_DDRITFCR_DPHYRST BIT(18) +#define RCC_DDRITFCR_DPHYCTLRST BIT(19) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 +#define RCC_DDRITFCR_GSKPMOD BIT(23) +#define RCC_DDRITFCR_GSKPCTRL BIT(24) +#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) +#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 +#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) +#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 + +/* RCC_I2C12CKSELR register fields */ +#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) +#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 + +/* RCC_I2C345CKSELR register fields */ +#define RCC_I2C345CKSELR_I2C3SRC_MASK GENMASK(2, 0) +#define RCC_I2C345CKSELR_I2C3SRC_SHIFT 0 +#define RCC_I2C345CKSELR_I2C4SRC_MASK GENMASK(5, 3) +#define RCC_I2C345CKSELR_I2C4SRC_SHIFT 3 +#define RCC_I2C345CKSELR_I2C5SRC_MASK GENMASK(8, 6) +#define RCC_I2C345CKSELR_I2C5SRC_SHIFT 6 + +/* RCC_SPI2S1CKSELR register fields */ +#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 + +/* RCC_SPI2S23CKSELR register fields */ +#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 + +/* RCC_SPI45CKSELR register fields */ +#define RCC_SPI45CKSELR_SPI4SRC_MASK GENMASK(2, 0) +#define RCC_SPI45CKSELR_SPI4SRC_SHIFT 0 +#define RCC_SPI45CKSELR_SPI5SRC_MASK GENMASK(5, 3) +#define RCC_SPI45CKSELR_SPI5SRC_SHIFT 3 + +/* RCC_UART12CKSELR register fields */ +#define RCC_UART12CKSELR_UART1SRC_MASK GENMASK(2, 0) +#define RCC_UART12CKSELR_UART1SRC_SHIFT 0 +#define RCC_UART12CKSELR_UART2SRC_MASK GENMASK(5, 3) +#define RCC_UART12CKSELR_UART2SRC_SHIFT 3 + +/* RCC_UART35CKSELR register fields */ +#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) +#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 + +/* RCC_UART4CKSELR register fields */ +#define RCC_UART4CKSELR_UART4SRC_MASK GENMASK(2, 0) +#define RCC_UART4CKSELR_UART4SRC_SHIFT 0 + +/* RCC_UART6CKSELR register fields */ +#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) +#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 + +/* RCC_UART78CKSELR register fields */ +#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) +#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 + +/* RCC_LPTIM1CKSELR register fields */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 + +/* RCC_LPTIM23CKSELR register fields */ +#define RCC_LPTIM23CKSELR_LPTIM2SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM23CKSELR_LPTIM2SRC_SHIFT 0 +#define RCC_LPTIM23CKSELR_LPTIM3SRC_MASK GENMASK(5, 3) +#define RCC_LPTIM23CKSELR_LPTIM3SRC_SHIFT 3 + +/* RCC_LPTIM45CKSELR register fields */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 + +/* RCC_SAI1CKSELR register fields */ +#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) +#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 + +/* RCC_SAI2CKSELR register fields */ +#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) +#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 + +/* RCC_FDCANCKSELR register fields */ +#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) +#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 + +/* RCC_SPDIFCKSELR register fields */ +#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) +#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 + +/* RCC_ADC12CKSELR register fields */ +#define RCC_ADC12CKSELR_ADC1SRC_MASK GENMASK(1, 0) +#define RCC_ADC12CKSELR_ADC1SRC_SHIFT 0 +#define RCC_ADC12CKSELR_ADC2SRC_MASK GENMASK(3, 2) +#define RCC_ADC12CKSELR_ADC2SRC_SHIFT 2 + +/* RCC_SDMMC12CKSELR register fields */ +#define RCC_SDMMC12CKSELR_SDMMC1SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC12CKSELR_SDMMC1SRC_SHIFT 0 +#define RCC_SDMMC12CKSELR_SDMMC2SRC_MASK GENMASK(5, 3) +#define RCC_SDMMC12CKSELR_SDMMC2SRC_SHIFT 3 + +/* RCC_ETH12CKSELR register fields */ +#define RCC_ETH12CKSELR_ETH1SRC_MASK GENMASK(1, 0) +#define RCC_ETH12CKSELR_ETH1SRC_SHIFT 0 +#define RCC_ETH12CKSELR_ETH1PTPDIV_MASK GENMASK(7, 4) +#define RCC_ETH12CKSELR_ETH1PTPDIV_SHIFT 4 +#define RCC_ETH12CKSELR_ETH2SRC_MASK GENMASK(9, 8) +#define RCC_ETH12CKSELR_ETH2SRC_SHIFT 8 +#define RCC_ETH12CKSELR_ETH2PTPDIV_MASK GENMASK(15, 12) +#define RCC_ETH12CKSELR_ETH2PTPDIV_SHIFT 12 + +/* RCC_USBCKSELR register fields */ +#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) +#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 +#define RCC_USBCKSELR_USBOSRC BIT(4) + +/* RCC_QSPICKSELR register fields */ +#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) +#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 + +/* RCC_FMCCKSELR register fields */ +#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) +#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 + +/* RCC_RNG1CKSELR register fields */ +#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) +#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 + +/* RCC_STGENCKSELR register fields */ +#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) +#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 + +/* RCC_DCMIPPCKSELR register fields */ +#define RCC_DCMIPPCKSELR_DCMIPPSRC_MASK GENMASK(1, 0) +#define RCC_DCMIPPCKSELR_DCMIPPSRC_SHIFT 0 + +/* RCC_SAESCKSELR register fields */ +#define RCC_SAESCKSELR_SAESSRC_MASK GENMASK(1, 0) +#define RCC_SAESCKSELR_SAESSRC_SHIFT 0 + +/* RCC_APB1RSTSETR register fields */ +#define RCC_APB1RSTSETR_TIM2RST BIT(0) +#define RCC_APB1RSTSETR_TIM3RST BIT(1) +#define RCC_APB1RSTSETR_TIM4RST BIT(2) +#define RCC_APB1RSTSETR_TIM5RST BIT(3) +#define RCC_APB1RSTSETR_TIM6RST BIT(4) +#define RCC_APB1RSTSETR_TIM7RST BIT(5) +#define RCC_APB1RSTSETR_LPTIM1RST BIT(9) +#define RCC_APB1RSTSETR_SPI2RST BIT(11) +#define RCC_APB1RSTSETR_SPI3RST BIT(12) +#define RCC_APB1RSTSETR_USART3RST BIT(15) +#define RCC_APB1RSTSETR_UART4RST BIT(16) +#define RCC_APB1RSTSETR_UART5RST BIT(17) +#define RCC_APB1RSTSETR_UART7RST BIT(18) +#define RCC_APB1RSTSETR_UART8RST BIT(19) +#define RCC_APB1RSTSETR_I2C1RST BIT(21) +#define RCC_APB1RSTSETR_I2C2RST BIT(22) +#define RCC_APB1RSTSETR_SPDIFRST BIT(26) + +/* RCC_APB1RSTCLRR register fields */ +#define RCC_APB1RSTCLRR_TIM2RST BIT(0) +#define RCC_APB1RSTCLRR_TIM3RST BIT(1) +#define RCC_APB1RSTCLRR_TIM4RST BIT(2) +#define RCC_APB1RSTCLRR_TIM5RST BIT(3) +#define RCC_APB1RSTCLRR_TIM6RST BIT(4) +#define RCC_APB1RSTCLRR_TIM7RST BIT(5) +#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) +#define RCC_APB1RSTCLRR_SPI2RST BIT(11) +#define RCC_APB1RSTCLRR_SPI3RST BIT(12) +#define RCC_APB1RSTCLRR_USART3RST BIT(15) +#define RCC_APB1RSTCLRR_UART4RST BIT(16) +#define RCC_APB1RSTCLRR_UART5RST BIT(17) +#define RCC_APB1RSTCLRR_UART7RST BIT(18) +#define RCC_APB1RSTCLRR_UART8RST BIT(19) +#define RCC_APB1RSTCLRR_I2C1RST BIT(21) +#define RCC_APB1RSTCLRR_I2C2RST BIT(22) +#define RCC_APB1RSTCLRR_SPDIFRST BIT(26) + +/* RCC_APB2RSTSETR register fields */ +#define RCC_APB2RSTSETR_TIM1RST BIT(0) +#define RCC_APB2RSTSETR_TIM8RST BIT(1) +#define RCC_APB2RSTSETR_SPI1RST BIT(8) +#define RCC_APB2RSTSETR_USART6RST BIT(13) +#define RCC_APB2RSTSETR_SAI1RST BIT(16) +#define RCC_APB2RSTSETR_SAI2RST BIT(17) +#define RCC_APB2RSTSETR_DFSDMRST BIT(20) +#define RCC_APB2RSTSETR_FDCANRST BIT(24) + +/* RCC_APB2RSTCLRR register fields */ +#define RCC_APB2RSTCLRR_TIM1RST BIT(0) +#define RCC_APB2RSTCLRR_TIM8RST BIT(1) +#define RCC_APB2RSTCLRR_SPI1RST BIT(8) +#define RCC_APB2RSTCLRR_USART6RST BIT(13) +#define RCC_APB2RSTCLRR_SAI1RST BIT(16) +#define RCC_APB2RSTCLRR_SAI2RST BIT(17) +#define RCC_APB2RSTCLRR_DFSDMRST BIT(20) +#define RCC_APB2RSTCLRR_FDCANRST BIT(24) + +/* RCC_APB3RSTSETR register fields */ +#define RCC_APB3RSTSETR_LPTIM2RST BIT(0) +#define RCC_APB3RSTSETR_LPTIM3RST BIT(1) +#define RCC_APB3RSTSETR_LPTIM4RST BIT(2) +#define RCC_APB3RSTSETR_LPTIM5RST BIT(3) +#define RCC_APB3RSTSETR_SYSCFGRST BIT(11) +#define RCC_APB3RSTSETR_VREFRST BIT(13) +#define RCC_APB3RSTSETR_DTSRST BIT(16) +#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) + +/* RCC_APB3RSTCLRR register fields */ +#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) +#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) +#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) +#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) +#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) +#define RCC_APB3RSTCLRR_VREFRST BIT(13) +#define RCC_APB3RSTCLRR_DTSRST BIT(16) +#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) + +/* RCC_APB4RSTSETR register fields */ +#define RCC_APB4RSTSETR_LTDCRST BIT(0) +#define RCC_APB4RSTSETR_DCMIPPRST BIT(1) +#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTSETR_USBPHYRST BIT(16) + +/* RCC_APB4RSTCLRR register fields */ +#define RCC_APB4RSTCLRR_LTDCRST BIT(0) +#define RCC_APB4RSTCLRR_DCMIPPRST BIT(1) +#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTCLRR_USBPHYRST BIT(16) + +/* RCC_APB5RSTSETR register fields */ +#define RCC_APB5RSTSETR_STGENRST BIT(20) + +/* RCC_APB5RSTCLRR register fields */ +#define RCC_APB5RSTCLRR_STGENRST BIT(20) + +/* RCC_APB6RSTSETR register fields */ +#define RCC_APB6RSTSETR_USART1RST BIT(0) +#define RCC_APB6RSTSETR_USART2RST BIT(1) +#define RCC_APB6RSTSETR_SPI4RST BIT(2) +#define RCC_APB6RSTSETR_SPI5RST BIT(3) +#define RCC_APB6RSTSETR_I2C3RST BIT(4) +#define RCC_APB6RSTSETR_I2C4RST BIT(5) +#define RCC_APB6RSTSETR_I2C5RST BIT(6) +#define RCC_APB6RSTSETR_TIM12RST BIT(7) +#define RCC_APB6RSTSETR_TIM13RST BIT(8) +#define RCC_APB6RSTSETR_TIM14RST BIT(9) +#define RCC_APB6RSTSETR_TIM15RST BIT(10) +#define RCC_APB6RSTSETR_TIM16RST BIT(11) +#define RCC_APB6RSTSETR_TIM17RST BIT(12) + +/* RCC_APB6RSTCLRR register fields */ +#define RCC_APB6RSTCLRR_USART1RST BIT(0) +#define RCC_APB6RSTCLRR_USART2RST BIT(1) +#define RCC_APB6RSTCLRR_SPI4RST BIT(2) +#define RCC_APB6RSTCLRR_SPI5RST BIT(3) +#define RCC_APB6RSTCLRR_I2C3RST BIT(4) +#define RCC_APB6RSTCLRR_I2C4RST BIT(5) +#define RCC_APB6RSTCLRR_I2C5RST BIT(6) +#define RCC_APB6RSTCLRR_TIM12RST BIT(7) +#define RCC_APB6RSTCLRR_TIM13RST BIT(8) +#define RCC_APB6RSTCLRR_TIM14RST BIT(9) +#define RCC_APB6RSTCLRR_TIM15RST BIT(10) +#define RCC_APB6RSTCLRR_TIM16RST BIT(11) +#define RCC_APB6RSTCLRR_TIM17RST BIT(12) + +/* RCC_AHB2RSTSETR register fields */ +#define RCC_AHB2RSTSETR_DMA1RST BIT(0) +#define RCC_AHB2RSTSETR_DMA2RST BIT(1) +#define RCC_AHB2RSTSETR_DMAMUX1RST BIT(2) +#define RCC_AHB2RSTSETR_DMA3RST BIT(3) +#define RCC_AHB2RSTSETR_DMAMUX2RST BIT(4) +#define RCC_AHB2RSTSETR_ADC1RST BIT(5) +#define RCC_AHB2RSTSETR_ADC2RST BIT(6) +#define RCC_AHB2RSTSETR_USBORST BIT(8) + +/* RCC_AHB2RSTCLRR register fields */ +#define RCC_AHB2RSTCLRR_DMA1RST BIT(0) +#define RCC_AHB2RSTCLRR_DMA2RST BIT(1) +#define RCC_AHB2RSTCLRR_DMAMUX1RST BIT(2) +#define RCC_AHB2RSTCLRR_DMA3RST BIT(3) +#define RCC_AHB2RSTCLRR_DMAMUX2RST BIT(4) +#define RCC_AHB2RSTCLRR_ADC1RST BIT(5) +#define RCC_AHB2RSTCLRR_ADC2RST BIT(6) +#define RCC_AHB2RSTCLRR_USBORST BIT(8) + +/* RCC_AHB4RSTSETR register fields */ +#define RCC_AHB4RSTSETR_GPIOARST BIT(0) +#define RCC_AHB4RSTSETR_GPIOBRST BIT(1) +#define RCC_AHB4RSTSETR_GPIOCRST BIT(2) +#define RCC_AHB4RSTSETR_GPIODRST BIT(3) +#define RCC_AHB4RSTSETR_GPIOERST BIT(4) +#define RCC_AHB4RSTSETR_GPIOFRST BIT(5) +#define RCC_AHB4RSTSETR_GPIOGRST BIT(6) +#define RCC_AHB4RSTSETR_GPIOHRST BIT(7) +#define RCC_AHB4RSTSETR_GPIOIRST BIT(8) +#define RCC_AHB4RSTSETR_TSCRST BIT(15) + +/* RCC_AHB4RSTCLRR register fields */ +#define RCC_AHB4RSTCLRR_GPIOARST BIT(0) +#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) +#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) +#define RCC_AHB4RSTCLRR_GPIODRST BIT(3) +#define RCC_AHB4RSTCLRR_GPIOERST BIT(4) +#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) +#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) +#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) +#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) +#define RCC_AHB4RSTCLRR_TSCRST BIT(15) + +/* RCC_AHB5RSTSETR register fields */ +#define RCC_AHB5RSTSETR_PKARST BIT(2) +#define RCC_AHB5RSTSETR_SAESRST BIT(3) +#define RCC_AHB5RSTSETR_CRYP1RST BIT(4) +#define RCC_AHB5RSTSETR_HASH1RST BIT(5) +#define RCC_AHB5RSTSETR_RNG1RST BIT(6) +#define RCC_AHB5RSTSETR_AXIMCRST BIT(16) + +/* RCC_AHB5RSTCLRR register fields */ +#define RCC_AHB5RSTCLRR_PKARST BIT(2) +#define RCC_AHB5RSTCLRR_SAESRST BIT(3) +#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) +#define RCC_AHB5RSTCLRR_HASH1RST BIT(5) +#define RCC_AHB5RSTCLRR_RNG1RST BIT(6) +#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) + +/* RCC_AHB6RSTSETR register fields */ +#define RCC_AHB6RSTSETR_MDMARST BIT(0) +#define RCC_AHB6RSTSETR_MCERST BIT(1) +#define RCC_AHB6RSTSETR_ETH1MACRST BIT(10) +#define RCC_AHB6RSTSETR_FMCRST BIT(12) +#define RCC_AHB6RSTSETR_QSPIRST BIT(14) +#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTSETR_CRC1RST BIT(20) +#define RCC_AHB6RSTSETR_USBHRST BIT(24) +#define RCC_AHB6RSTSETR_ETH2MACRST BIT(30) + +/* RCC_AHB6RSTCLRR register fields */ +#define RCC_AHB6RSTCLRR_MDMARST BIT(0) +#define RCC_AHB6RSTCLRR_MCERST BIT(1) +#define RCC_AHB6RSTCLRR_ETH1MACRST BIT(10) +#define RCC_AHB6RSTCLRR_FMCRST BIT(12) +#define RCC_AHB6RSTCLRR_QSPIRST BIT(14) +#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTCLRR_CRC1RST BIT(20) +#define RCC_AHB6RSTCLRR_USBHRST BIT(24) +#define RCC_AHB6RSTCLRR_ETH2MACRST BIT(30) + +/* RCC_MP_APB1ENSETR register fields */ +#define RCC_MP_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MP_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MP_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MP_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MP_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MP_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MP_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MP_APB1ENSETR_USART3EN BIT(15) +#define RCC_MP_APB1ENSETR_UART4EN BIT(16) +#define RCC_MP_APB1ENSETR_UART5EN BIT(17) +#define RCC_MP_APB1ENSETR_UART7EN BIT(18) +#define RCC_MP_APB1ENSETR_UART8EN BIT(19) +#define RCC_MP_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MP_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) + +/* RCC_MP_APB1ENCLRR register fields */ +#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MP_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MP_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MP_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MP_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MP_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) + +/* RCC_MP_APB2ENSETR register fields */ +#define RCC_MP_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MP_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MP_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MP_APB2ENSETR_USART6EN BIT(13) +#define RCC_MP_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MP_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MP_APB2ENCLRR register fields */ +#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MP_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MP_APB3ENSETR register fields */ +#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENSETR_VREFEN BIT(13) +#define RCC_MP_APB3ENSETR_DTSEN BIT(16) +#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MP_APB3ENCLRR register fields */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MP_APB3ENCLRR_DTSEN BIT(16) +#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MP_S_APB3ENSETR register fields */ +#define RCC_MP_S_APB3ENSETR_SYSCFGEN BIT(0) + +/* RCC_MP_S_APB3ENCLRR register fields */ +#define RCC_MP_S_APB3ENCLRR_SYSCFGEN BIT(0) + +/* RCC_MP_NS_APB3ENSETR register fields */ +#define RCC_MP_NS_APB3ENSETR_SYSCFGEN BIT(0) + +/* RCC_MP_NS_APB3ENCLRR register fields */ +#define RCC_MP_NS_APB3ENCLRR_SYSCFGEN BIT(0) + +/* RCC_MP_APB4ENSETR register fields */ +#define RCC_MP_APB4ENSETR_DCMIPPEN BIT(1) +#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MP_APB4ENCLRR register fields */ +#define RCC_MP_APB4ENCLRR_DCMIPPEN BIT(1) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MP_S_APB4ENSETR register fields */ +#define RCC_MP_S_APB4ENSETR_LTDCEN BIT(0) + +/* RCC_MP_S_APB4ENCLRR register fields */ +#define RCC_MP_S_APB4ENCLRR_LTDCEN BIT(0) + +/* RCC_MP_NS_APB4ENSETR register fields */ +#define RCC_MP_NS_APB4ENSETR_LTDCEN BIT(0) + +/* RCC_MP_NS_APB4ENCLRR register fields */ +#define RCC_MP_NS_APB4ENCLRR_LTDCEN BIT(0) + +/* RCC_MP_APB5ENSETR register fields */ +#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENSETR_TZCEN BIT(11) +#define RCC_MP_APB5ENSETR_ETZPCEN BIT(13) +#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENSETR_BSECEN BIT(16) +#define RCC_MP_APB5ENSETR_STGENCEN BIT(20) + +/* RCC_MP_APB5ENCLRR register fields */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENCLRR_TZCEN BIT(11) +#define RCC_MP_APB5ENCLRR_ETZPCEN BIT(13) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MP_APB5ENCLRR_STGENCEN BIT(20) + +/* RCC_MP_APB6ENSETR register fields */ +#define RCC_MP_APB6ENSETR_USART1EN BIT(0) +#define RCC_MP_APB6ENSETR_USART2EN BIT(1) +#define RCC_MP_APB6ENSETR_SPI4EN BIT(2) +#define RCC_MP_APB6ENSETR_SPI5EN BIT(3) +#define RCC_MP_APB6ENSETR_I2C3EN BIT(4) +#define RCC_MP_APB6ENSETR_I2C4EN BIT(5) +#define RCC_MP_APB6ENSETR_I2C5EN BIT(6) +#define RCC_MP_APB6ENSETR_TIM12EN BIT(7) +#define RCC_MP_APB6ENSETR_TIM13EN BIT(8) +#define RCC_MP_APB6ENSETR_TIM14EN BIT(9) +#define RCC_MP_APB6ENSETR_TIM15EN BIT(10) +#define RCC_MP_APB6ENSETR_TIM16EN BIT(11) +#define RCC_MP_APB6ENSETR_TIM17EN BIT(12) + +/* RCC_MP_APB6ENCLRR register fields */ +#define RCC_MP_APB6ENCLRR_USART1EN BIT(0) +#define RCC_MP_APB6ENCLRR_USART2EN BIT(1) +#define RCC_MP_APB6ENCLRR_SPI4EN BIT(2) +#define RCC_MP_APB6ENCLRR_SPI5EN BIT(3) +#define RCC_MP_APB6ENCLRR_I2C3EN BIT(4) +#define RCC_MP_APB6ENCLRR_I2C4EN BIT(5) +#define RCC_MP_APB6ENCLRR_I2C5EN BIT(6) +#define RCC_MP_APB6ENCLRR_TIM12EN BIT(7) +#define RCC_MP_APB6ENCLRR_TIM13EN BIT(8) +#define RCC_MP_APB6ENCLRR_TIM14EN BIT(9) +#define RCC_MP_APB6ENCLRR_TIM15EN BIT(10) +#define RCC_MP_APB6ENCLRR_TIM16EN BIT(11) +#define RCC_MP_APB6ENCLRR_TIM17EN BIT(12) + +/* RCC_MP_AHB2ENSETR register fields */ +#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENSETR_DMAMUX1EN BIT(2) +#define RCC_MP_AHB2ENSETR_DMA3EN BIT(3) +#define RCC_MP_AHB2ENSETR_DMAMUX2EN BIT(4) +#define RCC_MP_AHB2ENSETR_ADC1EN BIT(5) +#define RCC_MP_AHB2ENSETR_ADC2EN BIT(6) +#define RCC_MP_AHB2ENSETR_USBOEN BIT(8) + +/* RCC_MP_AHB2ENCLRR register fields */ +#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENCLRR_DMAMUX1EN BIT(2) +#define RCC_MP_AHB2ENCLRR_DMA3EN BIT(3) +#define RCC_MP_AHB2ENCLRR_DMAMUX2EN BIT(4) +#define RCC_MP_AHB2ENCLRR_ADC1EN BIT(5) +#define RCC_MP_AHB2ENCLRR_ADC2EN BIT(6) +#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) + +/* RCC_MP_AHB4ENSETR register fields */ +#define RCC_MP_AHB4ENSETR_TSCEN BIT(15) + +/* RCC_MP_AHB4ENCLRR register fields */ +#define RCC_MP_AHB4ENCLRR_TSCEN BIT(15) + +/* RCC_MP_S_AHB4ENSETR register fields */ +#define RCC_MP_S_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_S_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_S_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_S_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_S_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_S_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_S_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_S_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_S_AHB4ENSETR_GPIOIEN BIT(8) + +/* RCC_MP_S_AHB4ENCLRR register fields */ +#define RCC_MP_S_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_S_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_S_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_S_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_S_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_S_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_S_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_S_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_S_AHB4ENCLRR_GPIOIEN BIT(8) + +/* RCC_MP_NS_AHB4ENSETR register fields */ +#define RCC_MP_NS_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_NS_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_NS_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_NS_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_NS_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_NS_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_NS_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_NS_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_NS_AHB4ENSETR_GPIOIEN BIT(8) + +/* RCC_MP_NS_AHB4ENCLRR register fields */ +#define RCC_MP_NS_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_NS_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_NS_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_NS_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_NS_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_NS_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_NS_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_NS_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_NS_AHB4ENCLRR_GPIOIEN BIT(8) + +/* RCC_MP_AHB5ENSETR register fields */ +#define RCC_MP_AHB5ENSETR_PKAEN BIT(2) +#define RCC_MP_AHB5ENSETR_SAESEN BIT(3) +#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) + +/* RCC_MP_AHB5ENCLRR register fields */ +#define RCC_MP_AHB5ENCLRR_PKAEN BIT(2) +#define RCC_MP_AHB5ENCLRR_SAESEN BIT(3) +#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) + +/* RCC_MP_AHB6ENSETR register fields */ +#define RCC_MP_AHB6ENSETR_MCEEN BIT(1) +#define RCC_MP_AHB6ENSETR_ETH1CKEN BIT(7) +#define RCC_MP_AHB6ENSETR_ETH1TXEN BIT(8) +#define RCC_MP_AHB6ENSETR_ETH1RXEN BIT(9) +#define RCC_MP_AHB6ENSETR_ETH1MACEN BIT(10) +#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENSETR_USBHEN BIT(24) +#define RCC_MP_AHB6ENSETR_ETH2CKEN BIT(27) +#define RCC_MP_AHB6ENSETR_ETH2TXEN BIT(28) +#define RCC_MP_AHB6ENSETR_ETH2RXEN BIT(29) +#define RCC_MP_AHB6ENSETR_ETH2MACEN BIT(30) + +/* RCC_MP_AHB6ENCLRR register fields */ +#define RCC_MP_AHB6ENCLRR_MCEEN BIT(1) +#define RCC_MP_AHB6ENCLRR_ETH1CKEN BIT(7) +#define RCC_MP_AHB6ENCLRR_ETH1TXEN BIT(8) +#define RCC_MP_AHB6ENCLRR_ETH1RXEN BIT(9) +#define RCC_MP_AHB6ENCLRR_ETH1MACEN BIT(10) +#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) +#define RCC_MP_AHB6ENCLRR_ETH2CKEN BIT(27) +#define RCC_MP_AHB6ENCLRR_ETH2TXEN BIT(28) +#define RCC_MP_AHB6ENCLRR_ETH2RXEN BIT(29) +#define RCC_MP_AHB6ENCLRR_ETH2MACEN BIT(30) + +/* RCC_MP_S_AHB6ENSETR register fields */ +#define RCC_MP_S_AHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_S_AHB6ENCLRR register fields */ +#define RCC_MP_S_AHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MP_NS_AHB6ENSETR register fields */ +#define RCC_MP_NS_AHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_NS_AHB6ENCLRR register fields */ +#define RCC_MP_NS_AHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MP_APB1LPENSETR register fields */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) + +/* RCC_MP_APB1LPENCLRR register fields */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) + +/* RCC_MP_APB2LPENSETR register fields */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MP_APB2LPENCLRR register fields */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MP_APB3LPENSETR register fields */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENSETR_DTSLPEN BIT(16) +#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_APB3LPENCLRR register fields */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENCLRR_DTSLPEN BIT(16) +#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_S_APB3LPENSETR register fields */ +#define RCC_MP_S_APB3LPENSETR_SYSCFGLPEN BIT(0) + +/* RCC_MP_S_APB3LPENCLRR register fields */ +#define RCC_MP_S_APB3LPENCLRR_SYSCFGLPEN BIT(0) + +/* RCC_MP_NS_APB3LPENSETR register fields */ +#define RCC_MP_NS_APB3LPENSETR_SYSCFGLPEN BIT(0) + +/* RCC_MP_NS_APB3LPENCLRR register fields */ +#define RCC_MP_NS_APB3LPENCLRR_SYSCFGLPEN BIT(0) + +/* RCC_MP_APB4LPENSETR register fields */ +#define RCC_MP_APB4LPENSETR_DCMIPPLPEN BIT(1) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB4LPENCLRR register fields */ +#define RCC_MP_APB4LPENCLRR_DCMIPPLPEN BIT(1) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MP_S_APB4LPENSETR register fields */ +#define RCC_MP_S_APB4LPENSETR_LTDCLPEN BIT(0) + +/* RCC_MP_S_APB4LPENCLRR register fields */ +#define RCC_MP_S_APB4LPENCLRR_LTDCLPEN BIT(0) + +/* RCC_MP_NS_APB4LPENSETR register fields */ +#define RCC_MP_NS_APB4LPENSETR_LTDCLPEN BIT(0) + +/* RCC_MP_NS_APB4LPENCLRR register fields */ +#define RCC_MP_NS_APB4LPENCLRR_LTDCLPEN BIT(0) + +/* RCC_MP_APB5LPENSETR register fields */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENSETR_TZCLPEN BIT(11) +#define RCC_MP_APB5LPENSETR_ETZPCLPEN BIT(13) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENSETR_STGENCLPEN BIT(20) +#define RCC_MP_APB5LPENSETR_STGENCSTPEN BIT(21) + +/* RCC_MP_APB5LPENCLRR register fields */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENCLRR_TZCLPEN BIT(11) +#define RCC_MP_APB5LPENCLRR_ETZPCLPEN BIT(13) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENCLRR_STGENCLPEN BIT(20) +#define RCC_MP_APB5LPENCLRR_STGENCSTPEN BIT(21) + +/* RCC_MP_APB6LPENSETR register fields */ +#define RCC_MP_APB6LPENSETR_USART1LPEN BIT(0) +#define RCC_MP_APB6LPENSETR_USART2LPEN BIT(1) +#define RCC_MP_APB6LPENSETR_SPI4LPEN BIT(2) +#define RCC_MP_APB6LPENSETR_SPI5LPEN BIT(3) +#define RCC_MP_APB6LPENSETR_I2C3LPEN BIT(4) +#define RCC_MP_APB6LPENSETR_I2C4LPEN BIT(5) +#define RCC_MP_APB6LPENSETR_I2C5LPEN BIT(6) +#define RCC_MP_APB6LPENSETR_TIM12LPEN BIT(7) +#define RCC_MP_APB6LPENSETR_TIM13LPEN BIT(8) +#define RCC_MP_APB6LPENSETR_TIM14LPEN BIT(9) +#define RCC_MP_APB6LPENSETR_TIM15LPEN BIT(10) +#define RCC_MP_APB6LPENSETR_TIM16LPEN BIT(11) +#define RCC_MP_APB6LPENSETR_TIM17LPEN BIT(12) + +/* RCC_MP_APB6LPENCLRR register fields */ +#define RCC_MP_APB6LPENCLRR_USART1LPEN BIT(0) +#define RCC_MP_APB6LPENCLRR_USART2LPEN BIT(1) +#define RCC_MP_APB6LPENCLRR_SPI4LPEN BIT(2) +#define RCC_MP_APB6LPENCLRR_SPI5LPEN BIT(3) +#define RCC_MP_APB6LPENCLRR_I2C3LPEN BIT(4) +#define RCC_MP_APB6LPENCLRR_I2C4LPEN BIT(5) +#define RCC_MP_APB6LPENCLRR_I2C5LPEN BIT(6) +#define RCC_MP_APB6LPENCLRR_TIM12LPEN BIT(7) +#define RCC_MP_APB6LPENCLRR_TIM13LPEN BIT(8) +#define RCC_MP_APB6LPENCLRR_TIM14LPEN BIT(9) +#define RCC_MP_APB6LPENCLRR_TIM15LPEN BIT(10) +#define RCC_MP_APB6LPENCLRR_TIM16LPEN BIT(11) +#define RCC_MP_APB6LPENCLRR_TIM17LPEN BIT(12) + +/* RCC_MP_AHB2LPENSETR register fields */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENSETR_DMAMUX1LPEN BIT(2) +#define RCC_MP_AHB2LPENSETR_DMA3LPEN BIT(3) +#define RCC_MP_AHB2LPENSETR_DMAMUX2LPEN BIT(4) +#define RCC_MP_AHB2LPENSETR_ADC1LPEN BIT(5) +#define RCC_MP_AHB2LPENSETR_ADC2LPEN BIT(6) +#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) + +/* RCC_MP_AHB2LPENCLRR register fields */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENCLRR_DMAMUX1LPEN BIT(2) +#define RCC_MP_AHB2LPENCLRR_DMA3LPEN BIT(3) +#define RCC_MP_AHB2LPENCLRR_DMAMUX2LPEN BIT(4) +#define RCC_MP_AHB2LPENCLRR_ADC1LPEN BIT(5) +#define RCC_MP_AHB2LPENCLRR_ADC2LPEN BIT(6) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) + +/* RCC_MP_AHB4LPENSETR register fields */ +#define RCC_MP_AHB4LPENSETR_TSCLPEN BIT(15) + +/* RCC_MP_AHB4LPENCLRR register fields */ +#define RCC_MP_AHB4LPENCLRR_TSCLPEN BIT(15) + +/* RCC_MP_S_AHB4LPENSETR register fields */ +#define RCC_MP_S_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_S_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_S_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_S_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_S_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_S_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_S_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_S_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_S_AHB4LPENSETR_GPIOILPEN BIT(8) + +/* RCC_MP_S_AHB4LPENCLRR register fields */ +#define RCC_MP_S_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_S_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_S_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_S_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_S_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_S_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_S_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_S_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_S_AHB4LPENCLRR_GPIOILPEN BIT(8) + +/* RCC_MP_NS_AHB4LPENSETR register fields */ +#define RCC_MP_NS_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_NS_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_NS_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_NS_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_NS_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_NS_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_NS_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_NS_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_NS_AHB4LPENSETR_GPIOILPEN BIT(8) + +/* RCC_MP_NS_AHB4LPENCLRR register fields */ +#define RCC_MP_NS_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_NS_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOILPEN BIT(8) + +/* RCC_MP_AHB5LPENSETR register fields */ +#define RCC_MP_AHB5LPENSETR_PKALPEN BIT(2) +#define RCC_MP_AHB5LPENSETR_SAESLPEN BIT(3) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB5LPENCLRR register fields */ +#define RCC_MP_AHB5LPENCLRR_PKALPEN BIT(2) +#define RCC_MP_AHB5LPENCLRR_SAESLPEN BIT(3) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB6LPENSETR register fields */ +#define RCC_MP_AHB6LPENSETR_MCELPEN BIT(1) +#define RCC_MP_AHB6LPENSETR_ETH1CKLPEN BIT(7) +#define RCC_MP_AHB6LPENSETR_ETH1TXLPEN BIT(8) +#define RCC_MP_AHB6LPENSETR_ETH1RXLPEN BIT(9) +#define RCC_MP_AHB6LPENSETR_ETH1MACLPEN BIT(10) +#define RCC_MP_AHB6LPENSETR_ETH1STPEN BIT(11) +#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) +#define RCC_MP_AHB6LPENSETR_ETH2CKLPEN BIT(27) +#define RCC_MP_AHB6LPENSETR_ETH2TXLPEN BIT(28) +#define RCC_MP_AHB6LPENSETR_ETH2RXLPEN BIT(29) +#define RCC_MP_AHB6LPENSETR_ETH2MACLPEN BIT(30) +#define RCC_MP_AHB6LPENSETR_ETH2STPEN BIT(31) + +/* RCC_MP_AHB6LPENCLRR register fields */ +#define RCC_MP_AHB6LPENCLRR_MCELPEN BIT(1) +#define RCC_MP_AHB6LPENCLRR_ETH1CKLPEN BIT(7) +#define RCC_MP_AHB6LPENCLRR_ETH1TXLPEN BIT(8) +#define RCC_MP_AHB6LPENCLRR_ETH1RXLPEN BIT(9) +#define RCC_MP_AHB6LPENCLRR_ETH1MACLPEN BIT(10) +#define RCC_MP_AHB6LPENCLRR_ETH1STPEN BIT(11) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) +#define RCC_MP_AHB6LPENCLRR_ETH2CKLPEN BIT(27) +#define RCC_MP_AHB6LPENCLRR_ETH2TXLPEN BIT(28) +#define RCC_MP_AHB6LPENCLRR_ETH2RXLPEN BIT(29) +#define RCC_MP_AHB6LPENCLRR_ETH2MACLPEN BIT(30) +#define RCC_MP_AHB6LPENCLRR_ETH2STPEN BIT(31) + +/* RCC_MP_S_AHB6LPENSETR register fields */ +#define RCC_MP_S_AHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_S_AHB6LPENCLRR register fields */ +#define RCC_MP_S_AHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MP_NS_AHB6LPENSETR register fields */ +#define RCC_MP_NS_AHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_NS_AHB6LPENCLRR register fields */ +#define RCC_MP_NS_AHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MP_S_AXIMLPENSETR register fields */ +#define RCC_MP_S_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_S_AXIMLPENCLRR register fields */ +#define RCC_MP_S_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_NS_AXIMLPENSETR register fields */ +#define RCC_MP_NS_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_NS_AXIMLPENCLRR register fields */ +#define RCC_MP_NS_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_MLAHBLPENSETR register fields */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENSETR_SRAM3LPEN BIT(2) + +/* RCC_MP_MLAHBLPENCLRR register fields */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENCLRR_SRAM3LPEN BIT(2) + +/* RCC_APB3SECSR register fields */ +#define RCC_APB3SECSR_LPTIM2SECF BIT(0) +#define RCC_APB3SECSR_LPTIM3SECF BIT(1) +#define RCC_APB3SECSR_VREFSECF BIT(13) + +/* RCC_APB4SECSR register fields */ +#define RCC_APB4SECSR_DCMIPPSECF BIT(1) +#define RCC_APB4SECSR_USBPHYSECF BIT(16) + +/* RCC_APB5SECSR register fields */ +#define RCC_APB5SECSR_RTCSECF BIT(8) +#define RCC_APB5SECSR_TZCSECF BIT(11) +#define RCC_APB5SECSR_ETZPCSECF BIT(13) +#define RCC_APB5SECSR_IWDG1SECF BIT(15) +#define RCC_APB5SECSR_BSECSECF BIT(16) +#define RCC_APB5SECSR_STGENCSECF_MASK GENMASK(21, 20) +#define RCC_APB5SECSR_STGENCSECF_SHIFT 20 + +/* RCC_APB6SECSR register fields */ +#define RCC_APB6SECSR_USART1SECF BIT(0) +#define RCC_APB6SECSR_USART2SECF BIT(1) +#define RCC_APB6SECSR_SPI4SECF BIT(2) +#define RCC_APB6SECSR_SPI5SECF BIT(3) +#define RCC_APB6SECSR_I2C3SECF BIT(4) +#define RCC_APB6SECSR_I2C4SECF BIT(5) +#define RCC_APB6SECSR_I2C5SECF BIT(6) +#define RCC_APB6SECSR_TIM12SECF BIT(7) +#define RCC_APB6SECSR_TIM13SECF BIT(8) +#define RCC_APB6SECSR_TIM14SECF BIT(9) +#define RCC_APB6SECSR_TIM15SECF BIT(10) +#define RCC_APB6SECSR_TIM16SECF BIT(11) +#define RCC_APB6SECSR_TIM17SECF BIT(12) + +/* RCC_AHB2SECSR register fields */ +#define RCC_AHB2SECSR_DMA3SECF BIT(3) +#define RCC_AHB2SECSR_DMAMUX2SECF BIT(4) +#define RCC_AHB2SECSR_ADC1SECF BIT(5) +#define RCC_AHB2SECSR_ADC2SECF BIT(6) +#define RCC_AHB2SECSR_USBOSECF BIT(8) + +/* RCC_AHB4SECSR register fields */ +#define RCC_AHB4SECSR_TSCSECF BIT(15) + +/* RCC_AHB5SECSR register fields */ +#define RCC_AHB5SECSR_PKASECF BIT(2) +#define RCC_AHB5SECSR_SAESSECF BIT(3) +#define RCC_AHB5SECSR_CRYP1SECF BIT(4) +#define RCC_AHB5SECSR_HASH1SECF BIT(5) +#define RCC_AHB5SECSR_RNG1SECF BIT(6) +#define RCC_AHB5SECSR_BKPSRAMSECF BIT(8) + +/* RCC_AHB6SECSR register fields */ +#define RCC_AHB6SECSR_MCESECF BIT(1) +#define RCC_AHB6SECSR_ETH1SECF_MASK GENMASK(11, 7) +#define RCC_AHB6SECSR_ETH1SECF_SHIFT 7 +#define RCC_AHB6SECSR_FMCSECF BIT(12) +#define RCC_AHB6SECSR_QSPISECF BIT(14) +#define RCC_AHB6SECSR_SDMMC1SECF BIT(16) +#define RCC_AHB6SECSR_SDMMC2SECF BIT(17) +#define RCC_AHB6SECSR_ETH2SECF_MASK GENMASK(31, 27) +#define RCC_AHB6SECSR_ETH2SECF_SHIFT 27 + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +/* RCC_IDR register fields */ +#define RCC_IDR_ID_MASK GENMASK(31, 0) +#define RCC_IDR_ID_SHIFT 0 + +/* RCC_SIDR register fields */ +#define RCC_SIDR_SID_MASK GENMASK(31, 0) +#define RCC_SIDR_SID_SHIFT 0 + +/* Used for all RCC_PLL<n>CR registers */ +#define RCC_PLLNCR_PLLON BIT(0) +#define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) +#define RCC_PLLNCR_DIVPEN BIT(4) +#define RCC_PLLNCR_DIVQEN BIT(5) +#define RCC_PLLNCR_DIVREN BIT(6) +#define RCC_PLLNCR_DIVEN_SHIFT 4 + +/* Used for all RCC_PLL<n>CFGR1 registers */ +#define RCC_PLLNCFGR1_DIVM_SHIFT 16 +#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) +#define RCC_PLLNCFGR1_DIVN_SHIFT 0 +#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) + +/* Only for PLL3 and PLL4 */ +#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 +#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) + +/* Used for all RCC_PLL<n>CFGR2 registers */ +#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_SHIFT 0 +#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 +#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLLNCFGR2_DIVR_SHIFT 16 +#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) + +/* Used for all RCC_PLL<n>FRACR registers */ +#define RCC_PLLNFRACR_FRACV_SHIFT 3 +#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLLNFRACR_FRACLE BIT(16) + +/* Used for all RCC_PLL<n>CSGR registers */ +#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 +#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 +#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 +#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) + +/* Used for most of RCC_<x>SELR registers */ +#define RCC_SELR_SRC_MASK GENMASK(2, 0) +#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) +#define RCC_SELR_SRCRDY BIT(31) + +/* Values of RCC_MPCKSELR register */ +#define RCC_MPCKSELR_HSI 0x00000000 +#define RCC_MPCKSELR_HSE 0x00000001 +#define RCC_MPCKSELR_PLL 0x00000002 +#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 + +/* Values of RCC_ASSCKSELR register */ +#define RCC_ASSCKSELR_HSI 0x00000000 +#define RCC_ASSCKSELR_HSE 0x00000001 +#define RCC_ASSCKSELR_PLL 0x00000002 + +/* Values of RCC_MSSCKSELR register */ +#define RCC_MSSCKSELR_HSI 0x00000000 +#define RCC_MSSCKSELR_HSE 0x00000001 +#define RCC_MSSCKSELR_CSI 0x00000002 +#define RCC_MSSCKSELR_PLL 0x00000003 + +/* Values of RCC_CPERCKSELR register */ +#define RCC_CPERCKSELR_HSI 0x00000000 +#define RCC_CPERCKSELR_CSI 0x00000001 +#define RCC_CPERCKSELR_HSE 0x00000002 + +/* Used for most of DIVR register: max div for RTC */ +#define RCC_DIVR_DIV_MASK GENMASK(5, 0) +#define RCC_DIVR_DIVRDY BIT(31) + +/* Masks for specific DIVR registers */ +#define RCC_APBXDIV_MASK GENMASK(2, 0) +#define RCC_MPUDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MLAHBDIV_MASK GENMASK(3, 0) + +/* Used for TIMER Prescaler */ +#define RCC_TIMGXPRER_TIMGXPRE BIT(0) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ +#define RCC_RSTCLRR_OFFSET U(4) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENR_HSION BIT(0) +#define RCC_OCENR_HSIKERON BIT(1) +#define RCC_OCENR_CSION BIT(4) +#define RCC_OCENR_CSIKERON BIT(5) +#define RCC_OCENR_DIGBYP BIT(7) +#define RCC_OCENR_HSEON BIT(8) +#define RCC_OCENR_HSEKERON BIT(9) +#define RCC_OCENR_HSEBYP BIT(10) +#define RCC_OCENR_HSECSSON BIT(11) + +#define RCC_OCENR_DIGBYP_BIT 7 +#define RCC_OCENR_HSEBYP_BIT 10 +#define RCC_OCENR_HSECSSON_BIT 11 + +/* Used for RCC_MCO related operations */ +#define RCC_MCOCFG_MCOON BIT(12) +#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) +#define RCC_MCOCFG_MCODIV_SHIFT 4 +#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) + +#define RCC_UART4CKSELR_HSI 0x00000002 + +#define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_PERSRC_SHIFT 0 + +#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) +#define RCC_USBCKSELR_USBOSRC_SHIFT 4 + +#define RCC_DDRITFCR_DDRCKMOD_SSR 0 +#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) +#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) + +#define RCC_DDRITFCR_DDRC2EN BIT(0) +#define RCC_DDRITFCR_DDRC2LPEN BIT(1) + +#define RCC_MP_CIFR_MASK U(0x110F1F) +#define RCC_OFFSET_MASK GENMASK(11, 0) + +#endif /* STM32MP1_RCC_H */ diff --git a/include/drivers/st/stm32mp15_rcc.h b/include/drivers/st/stm32mp15_rcc.h new file mode 100644 index 0000000000..ddc0397d79 --- /dev/null +++ b/include/drivers/st/stm32mp15_rcc.h @@ -0,0 +1,2328 @@ +/* + * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_RCC_H +#define STM32MP1_RCC_H + +#include <lib/utils_def.h> + +#define RCC_TZCR U(0x00) +#define RCC_OCENSETR U(0x0C) +#define RCC_OCENCLRR U(0x10) +#define RCC_HSICFGR U(0x18) +#define RCC_CSICFGR U(0x1C) +#define RCC_MPCKSELR U(0x20) +#define RCC_ASSCKSELR U(0x24) +#define RCC_RCK12SELR U(0x28) +#define RCC_MPCKDIVR U(0x2C) +#define RCC_AXIDIVR U(0x30) +#define RCC_APB4DIVR U(0x3C) +#define RCC_APB5DIVR U(0x40) +#define RCC_RTCDIVR U(0x44) +#define RCC_MSSCKSELR U(0x48) +#define RCC_PLL1CR U(0x80) +#define RCC_PLL1CFGR1 U(0x84) +#define RCC_PLL1CFGR2 U(0x88) +#define RCC_PLL1FRACR U(0x8C) +#define RCC_PLL1CSGR U(0x90) +#define RCC_PLL2CR U(0x94) +#define RCC_PLL2CFGR1 U(0x98) +#define RCC_PLL2CFGR2 U(0x9C) +#define RCC_PLL2FRACR U(0xA0) +#define RCC_PLL2CSGR U(0xA4) +#define RCC_I2C46CKSELR U(0xC0) +#define RCC_SPI6CKSELR U(0xC4) +#define RCC_UART1CKSELR U(0xC8) +#define RCC_RNG1CKSELR U(0xCC) +#define RCC_CPERCKSELR U(0xD0) +#define RCC_STGENCKSELR U(0xD4) +#define RCC_DDRITFCR U(0xD8) +#define RCC_MP_BOOTCR U(0x100) +#define RCC_MP_SREQSETR U(0x104) +#define RCC_MP_SREQCLRR U(0x108) +#define RCC_MP_GCR U(0x10C) +#define RCC_MP_APRSTCR U(0x110) +#define RCC_MP_APRSTSR U(0x114) +#define RCC_BDCR U(0x140) +#define RCC_RDLSICR U(0x144) +#define RCC_APB4RSTSETR U(0x180) +#define RCC_APB4RSTCLRR U(0x184) +#define RCC_APB5RSTSETR U(0x188) +#define RCC_APB5RSTCLRR U(0x18C) +#define RCC_AHB5RSTSETR U(0x190) +#define RCC_AHB5RSTCLRR U(0x194) +#define RCC_AHB6RSTSETR U(0x198) +#define RCC_AHB6RSTCLRR U(0x19C) +#define RCC_TZAHB6RSTSETR U(0x1A0) +#define RCC_TZAHB6RSTCLRR U(0x1A4) +#define RCC_MP_APB4ENSETR U(0x200) +#define RCC_MP_APB4ENCLRR U(0x204) +#define RCC_MP_APB5ENSETR U(0x208) +#define RCC_MP_APB5ENCLRR U(0x20C) +#define RCC_MP_AHB5ENSETR U(0x210) +#define RCC_MP_AHB5ENCLRR U(0x214) +#define RCC_MP_AHB6ENSETR U(0x218) +#define RCC_MP_AHB6ENCLRR U(0x21C) +#define RCC_MP_TZAHB6ENSETR U(0x220) +#define RCC_MP_TZAHB6ENCLRR U(0x224) +#define RCC_MC_APB4ENSETR U(0x280) +#define RCC_MC_APB4ENCLRR U(0x284) +#define RCC_MC_APB5ENSETR U(0x288) +#define RCC_MC_APB5ENCLRR U(0x28C) +#define RCC_MC_AHB5ENSETR U(0x290) +#define RCC_MC_AHB5ENCLRR U(0x294) +#define RCC_MC_AHB6ENSETR U(0x298) +#define RCC_MC_AHB6ENCLRR U(0x29C) +#define RCC_MP_APB4LPENSETR U(0x300) +#define RCC_MP_APB4LPENCLRR U(0x304) +#define RCC_MP_APB5LPENSETR U(0x308) +#define RCC_MP_APB5LPENCLRR U(0x30C) +#define RCC_MP_AHB5LPENSETR U(0x310) +#define RCC_MP_AHB5LPENCLRR U(0x314) +#define RCC_MP_AHB6LPENSETR U(0x318) +#define RCC_MP_AHB6LPENCLRR U(0x31C) +#define RCC_MP_TZAHB6LPENSETR U(0x320) +#define RCC_MP_TZAHB6LPENCLRR U(0x324) +#define RCC_MC_APB4LPENSETR U(0x380) +#define RCC_MC_APB4LPENCLRR U(0x384) +#define RCC_MC_APB5LPENSETR U(0x388) +#define RCC_MC_APB5LPENCLRR U(0x38C) +#define RCC_MC_AHB5LPENSETR U(0x390) +#define RCC_MC_AHB5LPENCLRR U(0x394) +#define RCC_MC_AHB6LPENSETR U(0x398) +#define RCC_MC_AHB6LPENCLRR U(0x39C) +#define RCC_BR_RSTSCLRR U(0x400) +#define RCC_MP_GRSTCSETR U(0x404) +#define RCC_MP_RSTSCLRR U(0x408) +#define RCC_MP_IWDGFZSETR U(0x40C) +#define RCC_MP_IWDGFZCLRR U(0x410) +#define RCC_MP_CIER U(0x414) +#define RCC_MP_CIFR U(0x418) +#define RCC_PWRLPDLYCR U(0x41C) +#define RCC_MP_RSTSSETR U(0x420) +#define RCC_MCO1CFGR U(0x800) +#define RCC_MCO2CFGR U(0x804) +#define RCC_OCRDYR U(0x808) +#define RCC_DBGCFGR U(0x80C) +#define RCC_RCK3SELR U(0x820) +#define RCC_RCK4SELR U(0x824) +#define RCC_TIMG1PRER U(0x828) +#define RCC_TIMG2PRER U(0x82C) +#define RCC_MCUDIVR U(0x830) +#define RCC_APB1DIVR U(0x834) +#define RCC_APB2DIVR U(0x838) +#define RCC_APB3DIVR U(0x83C) +#define RCC_PLL3CR U(0x880) +#define RCC_PLL3CFGR1 U(0x884) +#define RCC_PLL3CFGR2 U(0x888) +#define RCC_PLL3FRACR U(0x88C) +#define RCC_PLL3CSGR U(0x890) +#define RCC_PLL4CR U(0x894) +#define RCC_PLL4CFGR1 U(0x898) +#define RCC_PLL4CFGR2 U(0x89C) +#define RCC_PLL4FRACR U(0x8A0) +#define RCC_PLL4CSGR U(0x8A4) +#define RCC_I2C12CKSELR U(0x8C0) +#define RCC_I2C35CKSELR U(0x8C4) +#define RCC_SAI1CKSELR U(0x8C8) +#define RCC_SAI2CKSELR U(0x8CC) +#define RCC_SAI3CKSELR U(0x8D0) +#define RCC_SAI4CKSELR U(0x8D4) +#define RCC_SPI2S1CKSELR U(0x8D8) +#define RCC_SPI2S23CKSELR U(0x8DC) +#define RCC_SPI45CKSELR U(0x8E0) +#define RCC_UART6CKSELR U(0x8E4) +#define RCC_UART24CKSELR U(0x8E8) +#define RCC_UART35CKSELR U(0x8EC) +#define RCC_UART78CKSELR U(0x8F0) +#define RCC_SDMMC12CKSELR U(0x8F4) +#define RCC_SDMMC3CKSELR U(0x8F8) +#define RCC_ETHCKSELR U(0x8FC) +#define RCC_QSPICKSELR U(0x900) +#define RCC_FMCCKSELR U(0x904) +#define RCC_FDCANCKSELR U(0x90C) +#define RCC_SPDIFCKSELR U(0x914) +#define RCC_CECCKSELR U(0x918) +#define RCC_USBCKSELR U(0x91C) +#define RCC_RNG2CKSELR U(0x920) +#define RCC_DSICKSELR U(0x924) +#define RCC_ADCCKSELR U(0x928) +#define RCC_LPTIM45CKSELR U(0x92C) +#define RCC_LPTIM23CKSELR U(0x930) +#define RCC_LPTIM1CKSELR U(0x934) +#define RCC_APB1RSTSETR U(0x980) +#define RCC_APB1RSTCLRR U(0x984) +#define RCC_APB2RSTSETR U(0x988) +#define RCC_APB2RSTCLRR U(0x98C) +#define RCC_APB3RSTSETR U(0x990) +#define RCC_APB3RSTCLRR U(0x994) +#define RCC_AHB2RSTSETR U(0x998) +#define RCC_AHB2RSTCLRR U(0x99C) +#define RCC_AHB3RSTSETR U(0x9A0) +#define RCC_AHB3RSTCLRR U(0x9A4) +#define RCC_AHB4RSTSETR U(0x9A8) +#define RCC_AHB4RSTCLRR U(0x9AC) +#define RCC_MP_APB1ENSETR U(0xA00) +#define RCC_MP_APB1ENCLRR U(0xA04) +#define RCC_MP_APB2ENSETR U(0xA08) +#define RCC_MP_APB2ENCLRR U(0xA0C) +#define RCC_MP_APB3ENSETR U(0xA10) +#define RCC_MP_APB3ENCLRR U(0xA14) +#define RCC_MP_AHB2ENSETR U(0xA18) +#define RCC_MP_AHB2ENCLRR U(0xA1C) +#define RCC_MP_AHB3ENSETR U(0xA20) +#define RCC_MP_AHB3ENCLRR U(0xA24) +#define RCC_MP_AHB4ENSETR U(0xA28) +#define RCC_MP_AHB4ENCLRR U(0xA2C) +#define RCC_MP_MLAHBENSETR U(0xA38) +#define RCC_MP_MLAHBENCLRR U(0xA3C) +#define RCC_MC_APB1ENSETR U(0xA80) +#define RCC_MC_APB1ENCLRR U(0xA84) +#define RCC_MC_APB2ENSETR U(0xA88) +#define RCC_MC_APB2ENCLRR U(0xA8C) +#define RCC_MC_APB3ENSETR U(0xA90) +#define RCC_MC_APB3ENCLRR U(0xA94) +#define RCC_MC_AHB2ENSETR U(0xA98) +#define RCC_MC_AHB2ENCLRR U(0xA9C) +#define RCC_MC_AHB3ENSETR U(0xAA0) +#define RCC_MC_AHB3ENCLRR U(0xAA4) +#define RCC_MC_AHB4ENSETR U(0xAA8) +#define RCC_MC_AHB4ENCLRR U(0xAAC) +#define RCC_MC_AXIMENSETR U(0xAB0) +#define RCC_MC_AXIMENCLRR U(0xAB4) +#define RCC_MC_MLAHBENSETR U(0xAB8) +#define RCC_MC_MLAHBENCLRR U(0xABC) +#define RCC_MP_APB1LPENSETR U(0xB00) +#define RCC_MP_APB1LPENCLRR U(0xB04) +#define RCC_MP_APB2LPENSETR U(0xB08) +#define RCC_MP_APB2LPENCLRR U(0xB0C) +#define RCC_MP_APB3LPENSETR U(0xB10) +#define RCC_MP_APB3LPENCLRR U(0xB14) +#define RCC_MP_AHB2LPENSETR U(0xB18) +#define RCC_MP_AHB2LPENCLRR U(0xB1C) +#define RCC_MP_AHB3LPENSETR U(0xB20) +#define RCC_MP_AHB3LPENCLRR U(0xB24) +#define RCC_MP_AHB4LPENSETR U(0xB28) +#define RCC_MP_AHB4LPENCLRR U(0xB2C) +#define RCC_MP_AXIMLPENSETR U(0xB30) +#define RCC_MP_AXIMLPENCLRR U(0xB34) +#define RCC_MP_MLAHBLPENSETR U(0xB38) +#define RCC_MP_MLAHBLPENCLRR U(0xB3C) +#define RCC_MC_APB1LPENSETR U(0xB80) +#define RCC_MC_APB1LPENCLRR U(0xB84) +#define RCC_MC_APB2LPENSETR U(0xB88) +#define RCC_MC_APB2LPENCLRR U(0xB8C) +#define RCC_MC_APB3LPENSETR U(0xB90) +#define RCC_MC_APB3LPENCLRR U(0xB94) +#define RCC_MC_AHB2LPENSETR U(0xB98) +#define RCC_MC_AHB2LPENCLRR U(0xB9C) +#define RCC_MC_AHB3LPENSETR U(0xBA0) +#define RCC_MC_AHB3LPENCLRR U(0xBA4) +#define RCC_MC_AHB4LPENSETR U(0xBA8) +#define RCC_MC_AHB4LPENCLRR U(0xBAC) +#define RCC_MC_AXIMLPENSETR U(0xBB0) +#define RCC_MC_AXIMLPENCLRR U(0xBB4) +#define RCC_MC_MLAHBLPENSETR U(0xBB8) +#define RCC_MC_MLAHBLPENCLRR U(0xBBC) +#define RCC_MC_RSTSCLRR U(0xC00) +#define RCC_MC_CIER U(0xC14) +#define RCC_MC_CIFR U(0xC18) +#define RCC_VERR U(0xFF4) +#define RCC_IDR U(0xFF8) +#define RCC_SIDR U(0xFFC) + +/* RCC_TZCR register fields */ +#define RCC_TZCR_TZEN BIT(0) +#define RCC_TZCR_MCKPROT BIT(1) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_CSION BIT(4) +#define RCC_OCENSETR_CSIKERON BIT(5) +#define RCC_OCENSETR_DIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_CSION BIT(4) +#define RCC_OCENCLRR_CSIKERON BIT(5) +#define RCC_OCENCLRR_DIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) +#define RCC_HSICFGR_HSIDIV_SHIFT 0 +#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK(24, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 +#define RCC_HSICFGR_HSICAL_TEMP_MASK GENMASK(27, 25) + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_MPCKSELR register fields */ +#define RCC_MPCKSELR_HSI 0x00000000 +#define RCC_MPCKSELR_HSE 0x00000001 +#define RCC_MPCKSELR_PLL 0x00000002 +#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 +#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) +#define RCC_MPCKSELR_MPUSRC_SHIFT 0 +#define RCC_MPCKSELR_MPUSRCRDY BIT(31) + +/* RCC_ASSCKSELR register fields */ +#define RCC_ASSCKSELR_HSI 0x00000000 +#define RCC_ASSCKSELR_HSE 0x00000001 +#define RCC_ASSCKSELR_PLL 0x00000002 +#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) +#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 +#define RCC_ASSCKSELR_AXISSRCRDY BIT(31) + +/* RCC_RCK12SELR register fields */ +#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) +#define RCC_RCK12SELR_PLL12SRC_SHIFT 0 +#define RCC_RCK12SELR_PLL12SRCRDY BIT(31) + +/* RCC_MPCKDIVR register fields */ +#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(2, 0) +#define RCC_MPCKDIVR_MPUDIV_SHIFT 0 +#define RCC_MPCKDIVR_MPUDIVRDY BIT(31) + +/* RCC_AXIDIVR register fields */ +#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIVR_AXIDIV_SHIFT 0 +#define RCC_AXIDIVR_AXIDIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APB5DIVR register fields */ +#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) +#define RCC_APB5DIVR_APB5DIV_SHIFT 0 +#define RCC_APB5DIVR_APB5DIVRDY BIT(31) + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_MSSCKSELR register fields */ +#define RCC_MSSCKSELR_HSI 0x00000000 +#define RCC_MSSCKSELR_HSE 0x00000001 +#define RCC_MSSCKSELR_CSI 0x00000002 +#define RCC_MSSCKSELR_PLL 0x00000003 +#define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0) +#define RCC_MSSCKSELR_MCUSSRC_SHIFT 0 +#define RCC_MSSCKSELR_MCUSSRCRDY BIT(31) + +/* RCC_PLL1CR register fields */ +#define RCC_PLL1CR_PLLON BIT(0) +#define RCC_PLL1CR_PLL1RDY BIT(1) +#define RCC_PLL1CR_SSCG_CTRL BIT(2) +#define RCC_PLL1CR_DIVPEN BIT(4) +#define RCC_PLL1CR_DIVQEN BIT(5) +#define RCC_PLL1CR_DIVREN BIT(6) + +/* RCC_PLL1CFGR1 register fields */ +#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL1CFGR1_DIVN_SHIFT 0 +#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) +#define RCC_PLL1CFGR1_DIVM1_SHIFT 16 + +/* RCC_PLL1CFGR2 register fields */ +#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL1CFGR2_DIVP_SHIFT 0 +#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL1CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL1CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL1FRACR register fields */ +#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL1FRACR_FRACV_SHIFT 3 +#define RCC_PLL1FRACR_FRACLE BIT(16) + +/* RCC_PLL1CSGR register fields */ +#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL1CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL1CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL1CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL1CSGR_SSCG_MODE BIT(15) +#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL1CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL2CR register fields */ +#define RCC_PLL2CR_PLLON BIT(0) +#define RCC_PLL2CR_PLL2RDY BIT(1) +#define RCC_PLL2CR_SSCG_CTRL BIT(2) +#define RCC_PLL2CR_DIVPEN BIT(4) +#define RCC_PLL2CR_DIVQEN BIT(5) +#define RCC_PLL2CR_DIVREN BIT(6) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL2CFGR1_DIVN_SHIFT 0 +#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) +#define RCC_PLL2CFGR1_DIVM2_SHIFT 16 + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL2CFGR2_DIVP_SHIFT 0 +#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL2CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL2CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL2FRACR register fields */ +#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL2FRACR_FRACV_SHIFT 3 +#define RCC_PLL2FRACR_FRACLE BIT(16) + +/* RCC_PLL2CSGR register fields */ +#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL2CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL2CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL2CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL2CSGR_SSCG_MODE BIT(15) +#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL2CSGR_INC_STEP_SHIFT 16 + +/* RCC_I2C46CKSELR register fields */ +#define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0) +#define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0 + +/* RCC_SPI6CKSELR register fields */ +#define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0) +#define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0 + +/* RCC_UART1CKSELR register fields */ +#define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0) +#define RCC_UART1CKSELR_UART1SRC_SHIFT 0 + +/* RCC_RNG1CKSELR register fields */ +#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) +#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 + +/* RCC_CPERCKSELR register fields */ +#define RCC_CPERCKSELR_HSI 0x00000000 +#define RCC_CPERCKSELR_CSI 0x00000001 +#define RCC_CPERCKSELR_HSE 0x00000002 +#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 + +/* RCC_STGENCKSELR register fields */ +#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) +#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 + +/* RCC_DDRITFCR register fields */ +#define RCC_DDRITFCR_DDRC1EN BIT(0) +#define RCC_DDRITFCR_DDRC1LPEN BIT(1) +#define RCC_DDRITFCR_DDRC2EN BIT(2) +#define RCC_DDRITFCR_DDRC2LPEN BIT(3) +#define RCC_DDRITFCR_DDRPHYCEN BIT(4) +#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) +#define RCC_DDRITFCR_DDRCAPBEN BIT(6) +#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) +#define RCC_DDRITFCR_AXIDCGEN BIT(8) +#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) +#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) +#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 +#define RCC_DDRITFCR_DDRCAPBRST BIT(14) +#define RCC_DDRITFCR_DDRCAXIRST BIT(15) +#define RCC_DDRITFCR_DDRCORERST BIT(16) +#define RCC_DDRITFCR_DPHYAPBRST BIT(17) +#define RCC_DDRITFCR_DPHYRST BIT(18) +#define RCC_DDRITFCR_DPHYCTLRST BIT(19) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 +#define RCC_DDRITFCR_DDRCKMOD_SSR 0 +#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) +#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) +#define RCC_DDRITFCR_GSKPMOD BIT(23) +#define RCC_DDRITFCR_GSKPCTRL BIT(24) +#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) +#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 +#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) +#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 + +/* RCC_MP_BOOTCR register fields */ +#define RCC_MP_BOOTCR_MCU_BEN BIT(0) +#define RCC_MP_BOOTCR_MPU_BEN BIT(1) + +/* RCC_MP_SREQSETR register fields */ +#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) +#define RCC_MP_SREQSETR_STPREQ_P1 BIT(1) + +/* RCC_MP_SREQCLRR register fields */ +#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) +#define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1) + +/* RCC_MP_GCR register fields */ +#define RCC_MP_GCR_BOOT_MCU BIT(0) + +/* RCC_MP_APRSTCR register fields */ +#define RCC_MP_APRSTCR_RDCTLEN BIT(0) +#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) +#define RCC_MP_APRSTCR_RSTTO_SHIFT 8 + +/* RCC_MP_APRSTSR register fields */ +#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) +#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_DIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(8) +#define RCC_BDCR_LSECSSD BIT(9) +#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_VSWRST BIT(31) + +/* RCC_RDLSICR register fields */ +#define RCC_RDLSICR_LSION BIT(0) +#define RCC_RDLSICR_LSIRDY BIT(1) +#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) +#define RCC_RDLSICR_MRD_SHIFT 16 +#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) +#define RCC_RDLSICR_EADLY_SHIFT 24 +#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) +#define RCC_RDLSICR_SPARE_SHIFT 27 + +/* RCC_APB4RSTSETR register fields */ +#define RCC_APB4RSTSETR_LTDCRST BIT(0) +#define RCC_APB4RSTSETR_DSIRST BIT(4) +#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTSETR_USBPHYRST BIT(16) + +/* RCC_APB4RSTCLRR register fields */ +#define RCC_APB4RSTCLRR_LTDCRST BIT(0) +#define RCC_APB4RSTCLRR_DSIRST BIT(4) +#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTCLRR_USBPHYRST BIT(16) + +/* RCC_APB5RSTSETR register fields */ +#define RCC_APB5RSTSETR_SPI6RST BIT(0) +#define RCC_APB5RSTSETR_I2C4RST BIT(2) +#define RCC_APB5RSTSETR_I2C6RST BIT(3) +#define RCC_APB5RSTSETR_USART1RST BIT(4) +#define RCC_APB5RSTSETR_STGENRST BIT(20) + +/* RCC_APB5RSTCLRR register fields */ +#define RCC_APB5RSTCLRR_SPI6RST BIT(0) +#define RCC_APB5RSTCLRR_I2C4RST BIT(2) +#define RCC_APB5RSTCLRR_I2C6RST BIT(3) +#define RCC_APB5RSTCLRR_USART1RST BIT(4) +#define RCC_APB5RSTCLRR_STGENRST BIT(20) + +/* RCC_AHB5RSTSETR register fields */ +#define RCC_AHB5RSTSETR_GPIOZRST BIT(0) +#define RCC_AHB5RSTSETR_CRYP1RST BIT(4) +#define RCC_AHB5RSTSETR_HASH1RST BIT(5) +#define RCC_AHB5RSTSETR_RNG1RST BIT(6) +#define RCC_AHB5RSTSETR_AXIMCRST BIT(16) + +/* RCC_AHB5RSTCLRR register fields */ +#define RCC_AHB5RSTCLRR_GPIOZRST BIT(0) +#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) +#define RCC_AHB5RSTCLRR_HASH1RST BIT(5) +#define RCC_AHB5RSTCLRR_RNG1RST BIT(6) +#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) + +/* RCC_AHB6RSTSETR register fields */ +#define RCC_AHB6RSTSETR_GPURST BIT(5) +#define RCC_AHB6RSTSETR_ETHMACRST BIT(10) +#define RCC_AHB6RSTSETR_FMCRST BIT(12) +#define RCC_AHB6RSTSETR_QSPIRST BIT(14) +#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTSETR_CRC1RST BIT(20) +#define RCC_AHB6RSTSETR_USBHRST BIT(24) + +/* RCC_AHB6RSTCLRR register fields */ +#define RCC_AHB6RSTCLRR_ETHMACRST BIT(10) +#define RCC_AHB6RSTCLRR_FMCRST BIT(12) +#define RCC_AHB6RSTCLRR_QSPIRST BIT(14) +#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTCLRR_CRC1RST BIT(20) +#define RCC_AHB6RSTCLRR_USBHRST BIT(24) + +/* RCC_TZAHB6RSTSETR register fields */ +#define RCC_TZAHB6RSTSETR_MDMARST BIT(0) + +/* RCC_TZAHB6RSTCLRR register fields */ +#define RCC_TZAHB6RSTCLRR_MDMARST BIT(0) + +/* RCC_MP_APB4ENSETR register fields */ +#define RCC_MP_APB4ENSETR_LTDCEN BIT(0) +#define RCC_MP_APB4ENSETR_DSIEN BIT(4) +#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MP_APB4ENCLRR register fields */ +#define RCC_MP_APB4ENCLRR_LTDCEN BIT(0) +#define RCC_MP_APB4ENCLRR_DSIEN BIT(4) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MP_APB5ENSETR register fields */ +#define RCC_MP_APB5ENSETR_SPI6EN BIT(0) +#define RCC_MP_APB5ENSETR_I2C4EN BIT(2) +#define RCC_MP_APB5ENSETR_I2C6EN BIT(3) +#define RCC_MP_APB5ENSETR_USART1EN BIT(4) +#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENSETR_TZC1EN BIT(11) +#define RCC_MP_APB5ENSETR_TZC2EN BIT(12) +#define RCC_MP_APB5ENSETR_TZPCEN BIT(13) +#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENSETR_BSECEN BIT(16) +#define RCC_MP_APB5ENSETR_STGENEN BIT(20) + +/* RCC_MP_APB5ENCLRR register fields */ +#define RCC_MP_APB5ENCLRR_SPI6EN BIT(0) +#define RCC_MP_APB5ENCLRR_I2C4EN BIT(2) +#define RCC_MP_APB5ENCLRR_I2C6EN BIT(3) +#define RCC_MP_APB5ENCLRR_USART1EN BIT(4) +#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENCLRR_TZC1EN BIT(11) +#define RCC_MP_APB5ENCLRR_TZC2EN BIT(12) +#define RCC_MP_APB5ENCLRR_TZPCEN BIT(13) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MP_APB5ENCLRR_STGENEN BIT(20) + +/* RCC_MP_AHB5ENSETR register fields */ +#define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0) +#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) + +/* RCC_MP_AHB5ENCLRR register fields */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN BIT(0) +#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) + +/* RCC_MP_AHB6ENSETR register fields */ +#define RCC_MP_AHB6ENSETR_MDMAEN BIT(0) +#define RCC_MP_AHB6ENSETR_GPUEN BIT(5) +#define RCC_MP_AHB6ENSETR_ETHCKEN BIT(7) +#define RCC_MP_AHB6ENSETR_ETHTXEN BIT(8) +#define RCC_MP_AHB6ENSETR_ETHRXEN BIT(9) +#define RCC_MP_AHB6ENSETR_ETHMACEN BIT(10) +#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENSETR_USBHEN BIT(24) + +/* RCC_MP_AHB6ENCLRR register fields */ +#define RCC_MP_AHB6ENCLRR_MDMAEN BIT(0) +#define RCC_MP_AHB6ENCLRR_GPUEN BIT(5) +#define RCC_MP_AHB6ENCLRR_ETHCKEN BIT(7) +#define RCC_MP_AHB6ENCLRR_ETHTXEN BIT(8) +#define RCC_MP_AHB6ENCLRR_ETHRXEN BIT(9) +#define RCC_MP_AHB6ENCLRR_ETHMACEN BIT(10) +#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) + +/* RCC_MP_TZAHB6ENSETR register fields */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_TZAHB6ENCLRR register fields */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MC_APB4ENSETR register fields */ +#define RCC_MC_APB4ENSETR_LTDCEN BIT(0) +#define RCC_MC_APB4ENSETR_DSIEN BIT(4) +#define RCC_MC_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MC_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MC_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MC_APB4ENCLRR register fields */ +#define RCC_MC_APB4ENCLRR_LTDCEN BIT(0) +#define RCC_MC_APB4ENCLRR_DSIEN BIT(4) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MC_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MC_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MC_APB5ENSETR register fields */ +#define RCC_MC_APB5ENSETR_SPI6EN BIT(0) +#define RCC_MC_APB5ENSETR_I2C4EN BIT(2) +#define RCC_MC_APB5ENSETR_I2C6EN BIT(3) +#define RCC_MC_APB5ENSETR_USART1EN BIT(4) +#define RCC_MC_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MC_APB5ENSETR_TZC1EN BIT(11) +#define RCC_MC_APB5ENSETR_TZC2EN BIT(12) +#define RCC_MC_APB5ENSETR_TZPCEN BIT(13) +#define RCC_MC_APB5ENSETR_BSECEN BIT(16) +#define RCC_MC_APB5ENSETR_STGENEN BIT(20) + +/* RCC_MC_APB5ENCLRR register fields */ +#define RCC_MC_APB5ENCLRR_SPI6EN BIT(0) +#define RCC_MC_APB5ENCLRR_I2C4EN BIT(2) +#define RCC_MC_APB5ENCLRR_I2C6EN BIT(3) +#define RCC_MC_APB5ENCLRR_USART1EN BIT(4) +#define RCC_MC_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MC_APB5ENCLRR_TZC1EN BIT(11) +#define RCC_MC_APB5ENCLRR_TZC2EN BIT(12) +#define RCC_MC_APB5ENCLRR_TZPCEN BIT(13) +#define RCC_MC_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MC_APB5ENCLRR_STGENEN BIT(20) + +/* RCC_MC_AHB5ENSETR register fields */ +#define RCC_MC_AHB5ENSETR_GPIOZEN BIT(0) +#define RCC_MC_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MC_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MC_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN BIT(8) + +/* RCC_MC_AHB5ENCLRR register fields */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN BIT(0) +#define RCC_MC_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MC_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MC_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN BIT(8) + +/* RCC_MC_AHB6ENSETR register fields */ +#define RCC_MC_AHB6ENSETR_MDMAEN BIT(0) +#define RCC_MC_AHB6ENSETR_GPUEN BIT(5) +#define RCC_MC_AHB6ENSETR_ETHCKEN BIT(7) +#define RCC_MC_AHB6ENSETR_ETHTXEN BIT(8) +#define RCC_MC_AHB6ENSETR_ETHRXEN BIT(9) +#define RCC_MC_AHB6ENSETR_ETHMACEN BIT(10) +#define RCC_MC_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MC_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MC_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MC_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MC_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MC_AHB6ENSETR_USBHEN BIT(24) + +/* RCC_MC_AHB6ENCLRR register fields */ +#define RCC_MC_AHB6ENCLRR_MDMAEN BIT(0) +#define RCC_MC_AHB6ENCLRR_GPUEN BIT(5) +#define RCC_MC_AHB6ENCLRR_ETHCKEN BIT(7) +#define RCC_MC_AHB6ENCLRR_ETHTXEN BIT(8) +#define RCC_MC_AHB6ENCLRR_ETHRXEN BIT(9) +#define RCC_MC_AHB6ENCLRR_ETHMACEN BIT(10) +#define RCC_MC_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MC_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MC_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MC_AHB6ENCLRR_USBHEN BIT(24) + +/* RCC_MP_APB4LPENSETR register fields */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN BIT(0) +#define RCC_MP_APB4LPENSETR_DSILPEN BIT(4) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB4LPENCLRR register fields */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN BIT(0) +#define RCC_MP_APB4LPENCLRR_DSILPEN BIT(4) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB5LPENSETR register fields */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN BIT(0) +#define RCC_MP_APB5LPENSETR_I2C4LPEN BIT(2) +#define RCC_MP_APB5LPENSETR_I2C6LPEN BIT(3) +#define RCC_MP_APB5LPENSETR_USART1LPEN BIT(4) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENSETR_TZC1LPEN BIT(11) +#define RCC_MP_APB5LPENSETR_TZC2LPEN BIT(12) +#define RCC_MP_APB5LPENSETR_TZPCLPEN BIT(13) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENSETR_STGENLPEN BIT(20) +#define RCC_MP_APB5LPENSETR_STGENSTPEN BIT(21) + +/* RCC_MP_APB5LPENCLRR register fields */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN BIT(0) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN BIT(2) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN BIT(3) +#define RCC_MP_APB5LPENCLRR_USART1LPEN BIT(4) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN BIT(11) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN BIT(12) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN BIT(13) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENCLRR_STGENLPEN BIT(20) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN BIT(21) + +/* RCC_MP_AHB5LPENSETR register fields */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN BIT(0) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB5LPENCLRR register fields */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN BIT(0) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB6LPENSETR register fields */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN BIT(0) +#define RCC_MP_AHB6LPENSETR_GPULPEN BIT(5) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN BIT(7) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN BIT(8) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN BIT(9) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN BIT(10) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN BIT(11) +#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) + +/* RCC_MP_AHB6LPENCLRR register fields */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN BIT(0) +#define RCC_MP_AHB6LPENCLRR_GPULPEN BIT(5) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN BIT(7) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN BIT(8) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN BIT(9) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN BIT(10) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN BIT(11) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) + +/* RCC_MP_TZAHB6LPENSETR register fields */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_TZAHB6LPENCLRR register fields */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MC_APB4LPENSETR register fields */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN BIT(0) +#define RCC_MC_APB4LPENSETR_DSILPEN BIT(4) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MC_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MC_APB4LPENCLRR register fields */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN BIT(0) +#define RCC_MC_APB4LPENCLRR_DSILPEN BIT(4) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MC_APB5LPENSETR register fields */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN BIT(0) +#define RCC_MC_APB5LPENSETR_I2C4LPEN BIT(2) +#define RCC_MC_APB5LPENSETR_I2C6LPEN BIT(3) +#define RCC_MC_APB5LPENSETR_USART1LPEN BIT(4) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MC_APB5LPENSETR_TZC1LPEN BIT(11) +#define RCC_MC_APB5LPENSETR_TZC2LPEN BIT(12) +#define RCC_MC_APB5LPENSETR_TZPCLPEN BIT(13) +#define RCC_MC_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MC_APB5LPENSETR_STGENLPEN BIT(20) +#define RCC_MC_APB5LPENSETR_STGENSTPEN BIT(21) + +/* RCC_MC_APB5LPENCLRR register fields */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN BIT(0) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN BIT(2) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN BIT(3) +#define RCC_MC_APB5LPENCLRR_USART1LPEN BIT(4) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN BIT(11) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN BIT(12) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN BIT(13) +#define RCC_MC_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MC_APB5LPENCLRR_STGENLPEN BIT(20) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN BIT(21) + +/* RCC_MC_AHB5LPENSETR register fields */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN BIT(0) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MC_AHB5LPENCLRR register fields */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN BIT(0) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MC_AHB6LPENSETR register fields */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN BIT(0) +#define RCC_MC_AHB6LPENSETR_GPULPEN BIT(5) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN BIT(7) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN BIT(8) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN BIT(9) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN BIT(10) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN BIT(11) +#define RCC_MC_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MC_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MC_AHB6LPENSETR_USBHLPEN BIT(24) + +/* RCC_MC_AHB6LPENCLRR register fields */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN BIT(0) +#define RCC_MC_AHB6LPENCLRR_GPULPEN BIT(5) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN BIT(7) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN BIT(8) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN BIT(9) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN BIT(10) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN BIT(11) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN BIT(24) + +/* RCC_BR_RSTSCLRR register fields */ +#define RCC_BR_RSTSCLRR_PORRSTF BIT(0) +#define RCC_BR_RSTSCLRR_BORRSTF BIT(1) +#define RCC_BR_RSTSCLRR_PADRSTF BIT(2) +#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_BR_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_BR_RSTSCLRR_MPUP1RSTF BIT(14) + +/* RCC_MP_GRSTCSETR register fields */ +#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MCURST BIT(1) +#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) +#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) + +/* RCC_MP_RSTSCLRR register fields */ +#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14) +#define RCC_MP_RSTSCLRR_SPARE BIT(15) + +/* RCC_MP_IWDGFZSETR register fields */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) + +/* RCC_MP_IWDGFZCLRR register fields */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_MP_CIER register fields */ +#define RCC_MP_CIER_LSIRDYIE BIT(0) +#define RCC_MP_CIER_LSERDYIE BIT(1) +#define RCC_MP_CIER_HSIRDYIE BIT(2) +#define RCC_MP_CIER_HSERDYIE BIT(3) +#define RCC_MP_CIER_CSIRDYIE BIT(4) +#define RCC_MP_CIER_PLL1DYIE BIT(8) +#define RCC_MP_CIER_PLL2DYIE BIT(9) +#define RCC_MP_CIER_PLL3DYIE BIT(10) +#define RCC_MP_CIER_PLL4DYIE BIT(11) +#define RCC_MP_CIER_LSECSSIE BIT(16) +#define RCC_MP_CIER_WKUPIE BIT(20) + +/* RCC_MP_CIFR register fields */ +#define RCC_MP_CIFR_MASK U(0x110F1F) +#define RCC_MP_CIFR_LSIRDYF BIT(0) +#define RCC_MP_CIFR_LSERDYF BIT(1) +#define RCC_MP_CIFR_HSIRDYF BIT(2) +#define RCC_MP_CIFR_HSERDYF BIT(3) +#define RCC_MP_CIFR_CSIRDYF BIT(4) +#define RCC_MP_CIFR_PLL1DYF BIT(8) +#define RCC_MP_CIFR_PLL2DYF BIT(9) +#define RCC_MP_CIFR_PLL3DYF BIT(10) +#define RCC_MP_CIFR_PLL4DYF BIT(11) +#define RCC_MP_CIFR_LSECSSF BIT(16) +#define RCC_MP_CIFR_WKUPF BIT(20) + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 +#define RCC_PWRLPDLYCR_MCTMPSKP BIT(24) + +/* RCC_MP_RSTSSETR register fields */ +#define RCC_MP_RSTSSETR_PORRSTF BIT(0) +#define RCC_MP_RSTSSETR_BORRSTF BIT(1) +#define RCC_MP_RSTSSETR_PADRSTF BIT(2) +#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSSETR_VCORERSTF BIT(4) +#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSSETR_MCSYSRSTF BIT(7) +#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSSETR_MPUP1RSTF BIT(14) +#define RCC_MP_RSTSSETR_SPARE BIT(15) + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) +#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 +#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) +#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 +#define RCC_MCO1CFGR_MCO1ON BIT(12) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) +#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 +#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) +#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 +#define RCC_MCO2CFGR_MCO2ON BIT(12) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSIDIVRDY BIT(2) +#define RCC_OCRDYR_CSIRDY BIT(4) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_MPUCKRDY BIT(23) +#define RCC_OCRDYR_AXICKRDY BIT(24) +#define RCC_OCRDYR_CKREST BIT(25) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) +#define RCC_DBGCFGR_TRACEDIV_SHIFT 0 +#define RCC_DBGCFGR_DBGCKEN BIT(8) +#define RCC_DBGCFGR_TRACECKEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_RCK3SELR register fields */ +#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) +#define RCC_RCK3SELR_PLL3SRC_SHIFT 0 +#define RCC_RCK3SELR_PLL3SRCRDY BIT(31) + +/* RCC_RCK4SELR register fields */ +#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) +#define RCC_RCK4SELR_PLL4SRC_SHIFT 0 +#define RCC_RCK4SELR_PLL4SRCRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_MCUDIVR register fields */ +#define RCC_MCUDIVR_MCUDIV_MASK GENMASK(3, 0) +#define RCC_MCUDIVR_MCUDIV_SHIFT 0 +#define RCC_MCUDIVR_MCUDIVRDY BIT(31) + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_PLL3CR register fields */ +#define RCC_PLL3CR_PLLON BIT(0) +#define RCC_PLL3CR_PLL3RDY BIT(1) +#define RCC_PLL3CR_SSCG_CTRL BIT(2) +#define RCC_PLL3CR_DIVPEN BIT(4) +#define RCC_PLL3CR_DIVQEN BIT(5) +#define RCC_PLL3CR_DIVREN BIT(6) + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL3CFGR1_DIVN_SHIFT 0 +#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) +#define RCC_PLL3CFGR1_DIVM3_SHIFT 16 +#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL3CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL3CFGR2_DIVP_SHIFT 0 +#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL3CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL3CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL3FRACR register fields */ +#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL3FRACR_FRACV_SHIFT 3 +#define RCC_PLL3FRACR_FRACLE BIT(16) + +/* RCC_PLL3CSGR register fields */ +#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL3CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL3CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL3CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL3CSGR_SSCG_MODE BIT(15) +#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL3CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL4CR register fields */ +#define RCC_PLL4CR_PLLON BIT(0) +#define RCC_PLL4CR_PLL4RDY BIT(1) +#define RCC_PLL4CR_SSCG_CTRL BIT(2) +#define RCC_PLL4CR_DIVPEN BIT(4) +#define RCC_PLL4CR_DIVQEN BIT(5) +#define RCC_PLL4CR_DIVREN BIT(6) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL4CFGR1_DIVN_SHIFT 0 +#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) +#define RCC_PLL4CFGR1_DIVM4_SHIFT 16 +#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL4CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL4CFGR2_DIVP_SHIFT 0 +#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL4CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL4CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL4FRACR register fields */ +#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL4FRACR_FRACV_SHIFT 3 +#define RCC_PLL4FRACR_FRACLE BIT(16) + +/* RCC_PLL4CSGR register fields */ +#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL4CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL4CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL4CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL4CSGR_SSCG_MODE BIT(15) +#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL4CSGR_INC_STEP_SHIFT 16 + +/* RCC_I2C12CKSELR register fields */ +#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) +#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 + +/* RCC_I2C35CKSELR register fields */ +#define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0) +#define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0 + +/* RCC_SAI1CKSELR register fields */ +#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) +#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 + +/* RCC_SAI2CKSELR register fields */ +#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) +#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 + +/* RCC_SAI3CKSELR register fields */ +#define RCC_SAI3CKSELR_SAI3SRC_MASK GENMASK(2, 0) +#define RCC_SAI3CKSELR_SAI3SRC_SHIFT 0 + +/* RCC_SAI4CKSELR register fields */ +#define RCC_SAI4CKSELR_SAI4SRC_MASK GENMASK(2, 0) +#define RCC_SAI4CKSELR_SAI4SRC_SHIFT 0 + +/* RCC_SPI2S1CKSELR register fields */ +#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 + +/* RCC_SPI2S23CKSELR register fields */ +#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 + +/* RCC_SPI45CKSELR register fields */ +#define RCC_SPI45CKSELR_SPI45SRC_MASK GENMASK(2, 0) +#define RCC_SPI45CKSELR_SPI45SRC_SHIFT 0 + +/* RCC_UART6CKSELR register fields */ +#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) +#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 + +/* RCC_UART24CKSELR register fields */ +#define RCC_UART24CKSELR_HSI 0x00000002 +#define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0) +#define RCC_UART24CKSELR_UART24SRC_SHIFT 0 + +/* RCC_UART35CKSELR register fields */ +#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) +#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 + +/* RCC_UART78CKSELR register fields */ +#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) +#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 + +/* RCC_SDMMC12CKSELR register fields */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0 + +/* RCC_SDMMC3CKSELR register fields */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0 + +/* RCC_ETHCKSELR register fields */ +#define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0) +#define RCC_ETHCKSELR_ETHSRC_SHIFT 0 +#define RCC_ETHCKSELR_ETHPTPDIV_MASK GENMASK(7, 4) +#define RCC_ETHCKSELR_ETHPTPDIV_SHIFT 4 + +/* RCC_QSPICKSELR register fields */ +#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) +#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 + +/* RCC_FMCCKSELR register fields */ +#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) +#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 + +/* RCC_FDCANCKSELR register fields */ +#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) +#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 + +/* RCC_SPDIFCKSELR register fields */ +#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) +#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 + +/* RCC_CECCKSELR register fields */ +#define RCC_CECCKSELR_CECSRC_MASK GENMASK(1, 0) +#define RCC_CECCKSELR_CECSRC_SHIFT 0 + +/* RCC_USBCKSELR register fields */ +#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) +#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 +#define RCC_USBCKSELR_USBOSRC BIT(4) +#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) +#define RCC_USBCKSELR_USBOSRC_SHIFT 4 + +/* RCC_RNG2CKSELR register fields */ +#define RCC_RNG2CKSELR_RNG2SRC_MASK GENMASK(1, 0) +#define RCC_RNG2CKSELR_RNG2SRC_SHIFT 0 + +/* RCC_DSICKSELR register fields */ +#define RCC_DSICKSELR_DSISRC BIT(0) + +/* RCC_ADCCKSELR register fields */ +#define RCC_ADCCKSELR_ADCSRC_MASK GENMASK(1, 0) +#define RCC_ADCCKSELR_ADCSRC_SHIFT 0 + +/* RCC_LPTIM45CKSELR register fields */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 + +/* RCC_LPTIM23CKSELR register fields */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_SHIFT 0 + +/* RCC_LPTIM1CKSELR register fields */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 + +/* RCC_APB1RSTSETR register fields */ +#define RCC_APB1RSTSETR_TIM2RST BIT(0) +#define RCC_APB1RSTSETR_TIM3RST BIT(1) +#define RCC_APB1RSTSETR_TIM4RST BIT(2) +#define RCC_APB1RSTSETR_TIM5RST BIT(3) +#define RCC_APB1RSTSETR_TIM6RST BIT(4) +#define RCC_APB1RSTSETR_TIM7RST BIT(5) +#define RCC_APB1RSTSETR_TIM12RST BIT(6) +#define RCC_APB1RSTSETR_TIM13RST BIT(7) +#define RCC_APB1RSTSETR_TIM14RST BIT(8) +#define RCC_APB1RSTSETR_LPTIM1RST BIT(9) +#define RCC_APB1RSTSETR_SPI2RST BIT(11) +#define RCC_APB1RSTSETR_SPI3RST BIT(12) +#define RCC_APB1RSTSETR_USART2RST BIT(14) +#define RCC_APB1RSTSETR_USART3RST BIT(15) +#define RCC_APB1RSTSETR_UART4RST BIT(16) +#define RCC_APB1RSTSETR_UART5RST BIT(17) +#define RCC_APB1RSTSETR_UART7RST BIT(18) +#define RCC_APB1RSTSETR_UART8RST BIT(19) +#define RCC_APB1RSTSETR_I2C1RST BIT(21) +#define RCC_APB1RSTSETR_I2C2RST BIT(22) +#define RCC_APB1RSTSETR_I2C3RST BIT(23) +#define RCC_APB1RSTSETR_I2C5RST BIT(24) +#define RCC_APB1RSTSETR_SPDIFRST BIT(26) +#define RCC_APB1RSTSETR_CECRST BIT(27) +#define RCC_APB1RSTSETR_DAC12RST BIT(29) +#define RCC_APB1RSTSETR_MDIOSRST BIT(31) + +/* RCC_APB1RSTCLRR register fields */ +#define RCC_APB1RSTCLRR_TIM2RST BIT(0) +#define RCC_APB1RSTCLRR_TIM3RST BIT(1) +#define RCC_APB1RSTCLRR_TIM4RST BIT(2) +#define RCC_APB1RSTCLRR_TIM5RST BIT(3) +#define RCC_APB1RSTCLRR_TIM6RST BIT(4) +#define RCC_APB1RSTCLRR_TIM7RST BIT(5) +#define RCC_APB1RSTCLRR_TIM12RST BIT(6) +#define RCC_APB1RSTCLRR_TIM13RST BIT(7) +#define RCC_APB1RSTCLRR_TIM14RST BIT(8) +#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) +#define RCC_APB1RSTCLRR_SPI2RST BIT(11) +#define RCC_APB1RSTCLRR_SPI3RST BIT(12) +#define RCC_APB1RSTCLRR_USART2RST BIT(14) +#define RCC_APB1RSTCLRR_USART3RST BIT(15) +#define RCC_APB1RSTCLRR_UART4RST BIT(16) +#define RCC_APB1RSTCLRR_UART5RST BIT(17) +#define RCC_APB1RSTCLRR_UART7RST BIT(18) +#define RCC_APB1RSTCLRR_UART8RST BIT(19) +#define RCC_APB1RSTCLRR_I2C1RST BIT(21) +#define RCC_APB1RSTCLRR_I2C2RST BIT(22) +#define RCC_APB1RSTCLRR_I2C3RST BIT(23) +#define RCC_APB1RSTCLRR_I2C5RST BIT(24) +#define RCC_APB1RSTCLRR_SPDIFRST BIT(26) +#define RCC_APB1RSTCLRR_CECRST BIT(27) +#define RCC_APB1RSTCLRR_DAC12RST BIT(29) +#define RCC_APB1RSTCLRR_MDIOSRST BIT(31) + +/* RCC_APB2RSTSETR register fields */ +#define RCC_APB2RSTSETR_TIM1RST BIT(0) +#define RCC_APB2RSTSETR_TIM8RST BIT(1) +#define RCC_APB2RSTSETR_TIM15RST BIT(2) +#define RCC_APB2RSTSETR_TIM16RST BIT(3) +#define RCC_APB2RSTSETR_TIM17RST BIT(4) +#define RCC_APB2RSTSETR_SPI1RST BIT(8) +#define RCC_APB2RSTSETR_SPI4RST BIT(9) +#define RCC_APB2RSTSETR_SPI5RST BIT(10) +#define RCC_APB2RSTSETR_USART6RST BIT(13) +#define RCC_APB2RSTSETR_SAI1RST BIT(16) +#define RCC_APB2RSTSETR_SAI2RST BIT(17) +#define RCC_APB2RSTSETR_SAI3RST BIT(18) +#define RCC_APB2RSTSETR_DFSDMRST BIT(20) +#define RCC_APB2RSTSETR_FDCANRST BIT(24) + +/* RCC_APB2RSTCLRR register fields */ +#define RCC_APB2RSTCLRR_TIM1RST BIT(0) +#define RCC_APB2RSTCLRR_TIM8RST BIT(1) +#define RCC_APB2RSTCLRR_TIM15RST BIT(2) +#define RCC_APB2RSTCLRR_TIM16RST BIT(3) +#define RCC_APB2RSTCLRR_TIM17RST BIT(4) +#define RCC_APB2RSTCLRR_SPI1RST BIT(8) +#define RCC_APB2RSTCLRR_SPI4RST BIT(9) +#define RCC_APB2RSTCLRR_SPI5RST BIT(10) +#define RCC_APB2RSTCLRR_USART6RST BIT(13) +#define RCC_APB2RSTCLRR_SAI1RST BIT(16) +#define RCC_APB2RSTCLRR_SAI2RST BIT(17) +#define RCC_APB2RSTCLRR_SAI3RST BIT(18) +#define RCC_APB2RSTCLRR_DFSDMRST BIT(20) +#define RCC_APB2RSTCLRR_FDCANRST BIT(24) + +/* RCC_APB3RSTSETR register fields */ +#define RCC_APB3RSTSETR_LPTIM2RST BIT(0) +#define RCC_APB3RSTSETR_LPTIM3RST BIT(1) +#define RCC_APB3RSTSETR_LPTIM4RST BIT(2) +#define RCC_APB3RSTSETR_LPTIM5RST BIT(3) +#define RCC_APB3RSTSETR_SAI4RST BIT(8) +#define RCC_APB3RSTSETR_SYSCFGRST BIT(11) +#define RCC_APB3RSTSETR_VREFRST BIT(13) +#define RCC_APB3RSTSETR_TMPSENSRST BIT(16) +#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) + +/* RCC_APB3RSTCLRR register fields */ +#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) +#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) +#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) +#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) +#define RCC_APB3RSTCLRR_SAI4RST BIT(8) +#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) +#define RCC_APB3RSTCLRR_VREFRST BIT(13) +#define RCC_APB3RSTCLRR_TMPSENSRST BIT(16) +#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) + +/* RCC_AHB2RSTSETR register fields */ +#define RCC_AHB2RSTSETR_DMA1RST BIT(0) +#define RCC_AHB2RSTSETR_DMA2RST BIT(1) +#define RCC_AHB2RSTSETR_DMAMUXRST BIT(2) +#define RCC_AHB2RSTSETR_ADC12RST BIT(5) +#define RCC_AHB2RSTSETR_USBORST BIT(8) +#define RCC_AHB2RSTSETR_SDMMC3RST BIT(16) + +/* RCC_AHB2RSTCLRR register fields */ +#define RCC_AHB2RSTCLRR_DMA1RST BIT(0) +#define RCC_AHB2RSTCLRR_DMA2RST BIT(1) +#define RCC_AHB2RSTCLRR_DMAMUXRST BIT(2) +#define RCC_AHB2RSTCLRR_ADC12RST BIT(5) +#define RCC_AHB2RSTCLRR_USBORST BIT(8) +#define RCC_AHB2RSTCLRR_SDMMC3RST BIT(16) + +/* RCC_AHB3RSTSETR register fields */ +#define RCC_AHB3RSTSETR_DCMIRST BIT(0) +#define RCC_AHB3RSTSETR_CRYP2RST BIT(4) +#define RCC_AHB3RSTSETR_HASH2RST BIT(5) +#define RCC_AHB3RSTSETR_RNG2RST BIT(6) +#define RCC_AHB3RSTSETR_CRC2RST BIT(7) +#define RCC_AHB3RSTSETR_HSEMRST BIT(11) +#define RCC_AHB3RSTSETR_IPCCRST BIT(12) + +/* RCC_AHB3RSTCLRR register fields */ +#define RCC_AHB3RSTCLRR_DCMIRST BIT(0) +#define RCC_AHB3RSTCLRR_CRYP2RST BIT(4) +#define RCC_AHB3RSTCLRR_HASH2RST BIT(5) +#define RCC_AHB3RSTCLRR_RNG2RST BIT(6) +#define RCC_AHB3RSTCLRR_CRC2RST BIT(7) +#define RCC_AHB3RSTCLRR_HSEMRST BIT(11) +#define RCC_AHB3RSTCLRR_IPCCRST BIT(12) + +/* RCC_AHB4RSTSETR register fields */ +#define RCC_AHB4RSTSETR_GPIOARST BIT(0) +#define RCC_AHB4RSTSETR_GPIOBRST BIT(1) +#define RCC_AHB4RSTSETR_GPIOCRST BIT(2) +#define RCC_AHB4RSTSETR_GPIODRST BIT(3) +#define RCC_AHB4RSTSETR_GPIOERST BIT(4) +#define RCC_AHB4RSTSETR_GPIOFRST BIT(5) +#define RCC_AHB4RSTSETR_GPIOGRST BIT(6) +#define RCC_AHB4RSTSETR_GPIOHRST BIT(7) +#define RCC_AHB4RSTSETR_GPIOIRST BIT(8) +#define RCC_AHB4RSTSETR_GPIOJRST BIT(9) +#define RCC_AHB4RSTSETR_GPIOKRST BIT(10) + +/* RCC_AHB4RSTCLRR register fields */ +#define RCC_AHB4RSTCLRR_GPIOARST BIT(0) +#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) +#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) +#define RCC_AHB4RSTCLRR_GPIODRST BIT(3) +#define RCC_AHB4RSTCLRR_GPIOERST BIT(4) +#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) +#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) +#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) +#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) +#define RCC_AHB4RSTCLRR_GPIOJRST BIT(9) +#define RCC_AHB4RSTCLRR_GPIOKRST BIT(10) + +/* RCC_MP_APB1ENSETR register fields */ +#define RCC_MP_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MP_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MP_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MP_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MP_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MP_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MP_APB1ENSETR_TIM12EN BIT(6) +#define RCC_MP_APB1ENSETR_TIM13EN BIT(7) +#define RCC_MP_APB1ENSETR_TIM14EN BIT(8) +#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MP_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MP_APB1ENSETR_USART2EN BIT(14) +#define RCC_MP_APB1ENSETR_USART3EN BIT(15) +#define RCC_MP_APB1ENSETR_UART4EN BIT(16) +#define RCC_MP_APB1ENSETR_UART5EN BIT(17) +#define RCC_MP_APB1ENSETR_UART7EN BIT(18) +#define RCC_MP_APB1ENSETR_UART8EN BIT(19) +#define RCC_MP_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MP_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MP_APB1ENSETR_I2C3EN BIT(23) +#define RCC_MP_APB1ENSETR_I2C5EN BIT(24) +#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) +#define RCC_MP_APB1ENSETR_CECEN BIT(27) +#define RCC_MP_APB1ENSETR_DAC12EN BIT(29) +#define RCC_MP_APB1ENSETR_MDIOSEN BIT(31) + +/* RCC_MP_APB1ENCLRR register fields */ +#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MP_APB1ENCLRR_TIM12EN BIT(6) +#define RCC_MP_APB1ENCLRR_TIM13EN BIT(7) +#define RCC_MP_APB1ENCLRR_TIM14EN BIT(8) +#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MP_APB1ENCLRR_USART2EN BIT(14) +#define RCC_MP_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MP_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MP_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MP_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MP_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MP_APB1ENCLRR_I2C3EN BIT(23) +#define RCC_MP_APB1ENCLRR_I2C5EN BIT(24) +#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) +#define RCC_MP_APB1ENCLRR_CECEN BIT(27) +#define RCC_MP_APB1ENCLRR_DAC12EN BIT(29) +#define RCC_MP_APB1ENCLRR_MDIOSEN BIT(31) + +/* RCC_MP_APB2ENSETR register fields */ +#define RCC_MP_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MP_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MP_APB2ENSETR_TIM15EN BIT(2) +#define RCC_MP_APB2ENSETR_TIM16EN BIT(3) +#define RCC_MP_APB2ENSETR_TIM17EN BIT(4) +#define RCC_MP_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MP_APB2ENSETR_SPI4EN BIT(9) +#define RCC_MP_APB2ENSETR_SPI5EN BIT(10) +#define RCC_MP_APB2ENSETR_USART6EN BIT(13) +#define RCC_MP_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MP_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MP_APB2ENSETR_SAI3EN BIT(18) +#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MP_APB2ENCLRR register fields */ +#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MP_APB2ENCLRR_TIM15EN BIT(2) +#define RCC_MP_APB2ENCLRR_TIM16EN BIT(3) +#define RCC_MP_APB2ENCLRR_TIM17EN BIT(4) +#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MP_APB2ENCLRR_SPI4EN BIT(9) +#define RCC_MP_APB2ENCLRR_SPI5EN BIT(10) +#define RCC_MP_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MP_APB2ENCLRR_SAI3EN BIT(18) +#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MP_APB3ENSETR register fields */ +#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENSETR_SAI4EN BIT(8) +#define RCC_MP_APB3ENSETR_SYSCFGEN BIT(11) +#define RCC_MP_APB3ENSETR_VREFEN BIT(13) +#define RCC_MP_APB3ENSETR_TMPSENSEN BIT(16) +#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MP_APB3ENCLRR register fields */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENCLRR_SAI4EN BIT(8) +#define RCC_MP_APB3ENCLRR_SYSCFGEN BIT(11) +#define RCC_MP_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MP_APB3ENCLRR_TMPSENSEN BIT(16) +#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MP_AHB2ENSETR register fields */ +#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENSETR_DMAMUXEN BIT(2) +#define RCC_MP_AHB2ENSETR_ADC12EN BIT(5) +#define RCC_MP_AHB2ENSETR_USBOEN BIT(8) +#define RCC_MP_AHB2ENSETR_SDMMC3EN BIT(16) + +/* RCC_MP_AHB2ENCLRR register fields */ +#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN BIT(2) +#define RCC_MP_AHB2ENCLRR_ADC12EN BIT(5) +#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN BIT(16) + +/* RCC_MP_AHB3ENSETR register fields */ +#define RCC_MP_AHB3ENSETR_DCMIEN BIT(0) +#define RCC_MP_AHB3ENSETR_CRYP2EN BIT(4) +#define RCC_MP_AHB3ENSETR_HASH2EN BIT(5) +#define RCC_MP_AHB3ENSETR_RNG2EN BIT(6) +#define RCC_MP_AHB3ENSETR_CRC2EN BIT(7) +#define RCC_MP_AHB3ENSETR_HSEMEN BIT(11) +#define RCC_MP_AHB3ENSETR_IPCCEN BIT(12) + +/* RCC_MP_AHB3ENCLRR register fields */ +#define RCC_MP_AHB3ENCLRR_DCMIEN BIT(0) +#define RCC_MP_AHB3ENCLRR_CRYP2EN BIT(4) +#define RCC_MP_AHB3ENCLRR_HASH2EN BIT(5) +#define RCC_MP_AHB3ENCLRR_RNG2EN BIT(6) +#define RCC_MP_AHB3ENCLRR_CRC2EN BIT(7) +#define RCC_MP_AHB3ENCLRR_HSEMEN BIT(11) +#define RCC_MP_AHB3ENCLRR_IPCCEN BIT(12) + +/* RCC_MP_AHB4ENSETR register fields */ +#define RCC_MP_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_AHB4ENSETR_GPIOIEN BIT(8) +#define RCC_MP_AHB4ENSETR_GPIOJEN BIT(9) +#define RCC_MP_AHB4ENSETR_GPIOKEN BIT(10) + +/* RCC_MP_AHB4ENCLRR register fields */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_AHB4ENCLRR_GPIOIEN BIT(8) +#define RCC_MP_AHB4ENCLRR_GPIOJEN BIT(9) +#define RCC_MP_AHB4ENCLRR_GPIOKEN BIT(10) + +/* RCC_MP_MLAHBENSETR register fields */ +#define RCC_MP_MLAHBENSETR_RETRAMEN BIT(4) + +/* RCC_MP_MLAHBENCLRR register fields */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN BIT(4) + +/* RCC_MC_APB1ENSETR register fields */ +#define RCC_MC_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MC_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MC_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MC_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MC_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MC_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MC_APB1ENSETR_TIM12EN BIT(6) +#define RCC_MC_APB1ENSETR_TIM13EN BIT(7) +#define RCC_MC_APB1ENSETR_TIM14EN BIT(8) +#define RCC_MC_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MC_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MC_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MC_APB1ENSETR_USART2EN BIT(14) +#define RCC_MC_APB1ENSETR_USART3EN BIT(15) +#define RCC_MC_APB1ENSETR_UART4EN BIT(16) +#define RCC_MC_APB1ENSETR_UART5EN BIT(17) +#define RCC_MC_APB1ENSETR_UART7EN BIT(18) +#define RCC_MC_APB1ENSETR_UART8EN BIT(19) +#define RCC_MC_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MC_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MC_APB1ENSETR_I2C3EN BIT(23) +#define RCC_MC_APB1ENSETR_I2C5EN BIT(24) +#define RCC_MC_APB1ENSETR_SPDIFEN BIT(26) +#define RCC_MC_APB1ENSETR_CECEN BIT(27) +#define RCC_MC_APB1ENSETR_WWDG1EN BIT(28) +#define RCC_MC_APB1ENSETR_DAC12EN BIT(29) +#define RCC_MC_APB1ENSETR_MDIOSEN BIT(31) + +/* RCC_MC_APB1ENCLRR register fields */ +#define RCC_MC_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MC_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MC_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MC_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MC_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MC_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MC_APB1ENCLRR_TIM12EN BIT(6) +#define RCC_MC_APB1ENCLRR_TIM13EN BIT(7) +#define RCC_MC_APB1ENCLRR_TIM14EN BIT(8) +#define RCC_MC_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MC_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MC_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MC_APB1ENCLRR_USART2EN BIT(14) +#define RCC_MC_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MC_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MC_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MC_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MC_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MC_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MC_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MC_APB1ENCLRR_I2C3EN BIT(23) +#define RCC_MC_APB1ENCLRR_I2C5EN BIT(24) +#define RCC_MC_APB1ENCLRR_SPDIFEN BIT(26) +#define RCC_MC_APB1ENCLRR_CECEN BIT(27) +#define RCC_MC_APB1ENCLRR_DAC12EN BIT(29) +#define RCC_MC_APB1ENCLRR_MDIOSEN BIT(31) + +/* RCC_MC_APB2ENSETR register fields */ +#define RCC_MC_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MC_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MC_APB2ENSETR_TIM15EN BIT(2) +#define RCC_MC_APB2ENSETR_TIM16EN BIT(3) +#define RCC_MC_APB2ENSETR_TIM17EN BIT(4) +#define RCC_MC_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MC_APB2ENSETR_SPI4EN BIT(9) +#define RCC_MC_APB2ENSETR_SPI5EN BIT(10) +#define RCC_MC_APB2ENSETR_USART6EN BIT(13) +#define RCC_MC_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MC_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MC_APB2ENSETR_SAI3EN BIT(18) +#define RCC_MC_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MC_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MC_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MC_APB2ENCLRR register fields */ +#define RCC_MC_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MC_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MC_APB2ENCLRR_TIM15EN BIT(2) +#define RCC_MC_APB2ENCLRR_TIM16EN BIT(3) +#define RCC_MC_APB2ENCLRR_TIM17EN BIT(4) +#define RCC_MC_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MC_APB2ENCLRR_SPI4EN BIT(9) +#define RCC_MC_APB2ENCLRR_SPI5EN BIT(10) +#define RCC_MC_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MC_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MC_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MC_APB2ENCLRR_SAI3EN BIT(18) +#define RCC_MC_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MC_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MC_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MC_APB3ENSETR register fields */ +#define RCC_MC_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MC_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MC_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MC_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MC_APB3ENSETR_SAI4EN BIT(8) +#define RCC_MC_APB3ENSETR_SYSCFGEN BIT(11) +#define RCC_MC_APB3ENSETR_VREFEN BIT(13) +#define RCC_MC_APB3ENSETR_TMPSENSEN BIT(16) +#define RCC_MC_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MC_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MC_APB3ENCLRR register fields */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MC_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MC_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MC_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MC_APB3ENCLRR_SAI4EN BIT(8) +#define RCC_MC_APB3ENCLRR_SYSCFGEN BIT(11) +#define RCC_MC_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MC_APB3ENCLRR_TMPSENSEN BIT(16) +#define RCC_MC_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MC_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MC_AHB2ENSETR register fields */ +#define RCC_MC_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MC_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MC_AHB2ENSETR_DMAMUXEN BIT(2) +#define RCC_MC_AHB2ENSETR_ADC12EN BIT(5) +#define RCC_MC_AHB2ENSETR_USBOEN BIT(8) +#define RCC_MC_AHB2ENSETR_SDMMC3EN BIT(16) + +/* RCC_MC_AHB2ENCLRR register fields */ +#define RCC_MC_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MC_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN BIT(2) +#define RCC_MC_AHB2ENCLRR_ADC12EN BIT(5) +#define RCC_MC_AHB2ENCLRR_USBOEN BIT(8) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN BIT(16) + +/* RCC_MC_AHB3ENSETR register fields */ +#define RCC_MC_AHB3ENSETR_DCMIEN BIT(0) +#define RCC_MC_AHB3ENSETR_CRYP2EN BIT(4) +#define RCC_MC_AHB3ENSETR_HASH2EN BIT(5) +#define RCC_MC_AHB3ENSETR_RNG2EN BIT(6) +#define RCC_MC_AHB3ENSETR_CRC2EN BIT(7) +#define RCC_MC_AHB3ENSETR_HSEMEN BIT(11) +#define RCC_MC_AHB3ENSETR_IPCCEN BIT(12) + +/* RCC_MC_AHB3ENCLRR register fields */ +#define RCC_MC_AHB3ENCLRR_DCMIEN BIT(0) +#define RCC_MC_AHB3ENCLRR_CRYP2EN BIT(4) +#define RCC_MC_AHB3ENCLRR_HASH2EN BIT(5) +#define RCC_MC_AHB3ENCLRR_RNG2EN BIT(6) +#define RCC_MC_AHB3ENCLRR_CRC2EN BIT(7) +#define RCC_MC_AHB3ENCLRR_HSEMEN BIT(11) +#define RCC_MC_AHB3ENCLRR_IPCCEN BIT(12) + +/* RCC_MC_AHB4ENSETR register fields */ +#define RCC_MC_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MC_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MC_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MC_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MC_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MC_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MC_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MC_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MC_AHB4ENSETR_GPIOIEN BIT(8) +#define RCC_MC_AHB4ENSETR_GPIOJEN BIT(9) +#define RCC_MC_AHB4ENSETR_GPIOKEN BIT(10) + +/* RCC_MC_AHB4ENCLRR register fields */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MC_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MC_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MC_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MC_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MC_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MC_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MC_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MC_AHB4ENCLRR_GPIOIEN BIT(8) +#define RCC_MC_AHB4ENCLRR_GPIOJEN BIT(9) +#define RCC_MC_AHB4ENCLRR_GPIOKEN BIT(10) + +/* RCC_MC_AXIMENSETR register fields */ +#define RCC_MC_AXIMENSETR_SYSRAMEN BIT(0) + +/* RCC_MC_AXIMENCLRR register fields */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN BIT(0) + +/* RCC_MC_MLAHBENSETR register fields */ +#define RCC_MC_MLAHBENSETR_RETRAMEN BIT(4) + +/* RCC_MC_MLAHBENCLRR register fields */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN BIT(4) + +/* RCC_MP_APB1LPENSETR register fields */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENSETR_TIM12LPEN BIT(6) +#define RCC_MP_APB1LPENSETR_TIM13LPEN BIT(7) +#define RCC_MP_APB1LPENSETR_TIM14LPEN BIT(8) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENSETR_USART2LPEN BIT(14) +#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENSETR_I2C3LPEN BIT(23) +#define RCC_MP_APB1LPENSETR_I2C5LPEN BIT(24) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) +#define RCC_MP_APB1LPENSETR_CECLPEN BIT(27) +#define RCC_MP_APB1LPENSETR_DAC12LPEN BIT(29) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN BIT(31) + +/* RCC_MP_APB1LPENCLRR register fields */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN BIT(6) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN BIT(7) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN BIT(8) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENCLRR_USART2LPEN BIT(14) +#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN BIT(23) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN BIT(24) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) +#define RCC_MP_APB1LPENCLRR_CECLPEN BIT(27) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN BIT(29) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN BIT(31) + +/* RCC_MP_APB2LPENSETR register fields */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENSETR_TIM15LPEN BIT(2) +#define RCC_MP_APB2LPENSETR_TIM16LPEN BIT(3) +#define RCC_MP_APB2LPENSETR_TIM17LPEN BIT(4) +#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENSETR_SPI4LPEN BIT(9) +#define RCC_MP_APB2LPENSETR_SPI5LPEN BIT(10) +#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENSETR_SAI3LPEN BIT(18) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MP_APB2LPENCLRR register fields */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN BIT(2) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN BIT(3) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN BIT(4) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN BIT(9) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN BIT(10) +#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN BIT(18) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MP_APB3LPENSETR register fields */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENSETR_SAI4LPEN BIT(8) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN BIT(11) +#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENSETR_TMPSENSLPEN BIT(16) +#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_APB3LPENCLRR register fields */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN BIT(8) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN BIT(11) +#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENCLRR_TMPSENSLPEN BIT(16) +#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_AHB2LPENSETR register fields */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN BIT(2) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN BIT(5) +#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN BIT(16) + +/* RCC_MP_AHB2LPENCLRR register fields */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN BIT(2) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN BIT(5) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN BIT(16) + +/* RCC_MP_AHB3LPENSETR register fields */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN BIT(0) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN BIT(4) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN BIT(5) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN BIT(6) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN BIT(7) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN BIT(11) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN BIT(12) + +/* RCC_MP_AHB3LPENCLRR register fields */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN BIT(0) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN BIT(4) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN BIT(5) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN BIT(6) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN BIT(7) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN BIT(11) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN BIT(12) + +/* RCC_MP_AHB4LPENSETR register fields */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN BIT(8) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN BIT(9) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN BIT(10) + +/* RCC_MP_AHB4LPENCLRR register fields */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN BIT(8) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN BIT(9) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN BIT(10) + +/* RCC_MP_AXIMLPENSETR register fields */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_AXIMLPENCLRR register fields */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_MLAHBLPENSETR register fields */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN BIT(2) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN BIT(4) + +/* RCC_MP_MLAHBLPENCLRR register fields */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN BIT(2) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN BIT(4) + +/* RCC_MC_APB1LPENSETR register fields */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MC_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MC_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MC_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MC_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MC_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MC_APB1LPENSETR_TIM12LPEN BIT(6) +#define RCC_MC_APB1LPENSETR_TIM13LPEN BIT(7) +#define RCC_MC_APB1LPENSETR_TIM14LPEN BIT(8) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MC_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MC_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MC_APB1LPENSETR_USART2LPEN BIT(14) +#define RCC_MC_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MC_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MC_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MC_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MC_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MC_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MC_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MC_APB1LPENSETR_I2C3LPEN BIT(23) +#define RCC_MC_APB1LPENSETR_I2C5LPEN BIT(24) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN BIT(26) +#define RCC_MC_APB1LPENSETR_CECLPEN BIT(27) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN BIT(28) +#define RCC_MC_APB1LPENSETR_DAC12LPEN BIT(29) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN BIT(31) + +/* RCC_MC_APB1LPENCLRR register fields */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN BIT(6) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN BIT(7) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN BIT(8) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MC_APB1LPENCLRR_USART2LPEN BIT(14) +#define RCC_MC_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MC_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MC_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MC_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MC_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN BIT(23) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN BIT(24) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN BIT(26) +#define RCC_MC_APB1LPENCLRR_CECLPEN BIT(27) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN BIT(28) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN BIT(29) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN BIT(31) + +/* RCC_MC_APB2LPENSETR register fields */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MC_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MC_APB2LPENSETR_TIM15LPEN BIT(2) +#define RCC_MC_APB2LPENSETR_TIM16LPEN BIT(3) +#define RCC_MC_APB2LPENSETR_TIM17LPEN BIT(4) +#define RCC_MC_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MC_APB2LPENSETR_SPI4LPEN BIT(9) +#define RCC_MC_APB2LPENSETR_SPI5LPEN BIT(10) +#define RCC_MC_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MC_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MC_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MC_APB2LPENSETR_SAI3LPEN BIT(18) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MC_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MC_APB2LPENCLRR register fields */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN BIT(2) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN BIT(3) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN BIT(4) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN BIT(9) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN BIT(10) +#define RCC_MC_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN BIT(18) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MC_APB3LPENSETR register fields */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MC_APB3LPENSETR_SAI4LPEN BIT(8) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN BIT(11) +#define RCC_MC_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MC_APB3LPENSETR_TMPSENSLPEN BIT(16) +#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MC_APB3LPENCLRR register fields */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN BIT(8) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN BIT(11) +#define RCC_MC_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MC_APB3LPENCLRR_TMPSENSLPEN BIT(16) +#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MC_AHB2LPENSETR register fields */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN BIT(2) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN BIT(5) +#define RCC_MC_AHB2LPENSETR_USBOLPEN BIT(8) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN BIT(16) + +/* RCC_MC_AHB2LPENCLRR register fields */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN BIT(2) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN BIT(5) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN BIT(8) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN BIT(16) + +/* RCC_MC_AHB3LPENSETR register fields */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN BIT(0) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN BIT(4) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN BIT(5) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN BIT(6) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN BIT(7) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN BIT(11) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN BIT(12) + +/* RCC_MC_AHB3LPENCLRR register fields */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN BIT(0) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN BIT(4) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN BIT(5) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN BIT(6) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN BIT(7) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN BIT(11) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN BIT(12) + +/* RCC_MC_AHB4LPENSETR register fields */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN BIT(8) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN BIT(9) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN BIT(10) + +/* RCC_MC_AHB4LPENCLRR register fields */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN BIT(8) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN BIT(9) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN BIT(10) + +/* RCC_MC_AXIMLPENSETR register fields */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MC_AXIMLPENCLRR register fields */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MC_MLAHBLPENSETR register fields */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN BIT(2) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN BIT(4) + +/* RCC_MC_MLAHBLPENCLRR register fields */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN BIT(2) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN BIT(4) + +/* RCC_MC_RSTSCLRR register fields */ +#define RCC_MC_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MC_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MC_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MC_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MC_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MC_RSTSCLRR_MCURSTF BIT(5) +#define RCC_MC_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MC_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_MC_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MC_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MC_RSTSCLRR_WWDG1RSTF BIT(10) + +/* RCC_MC_CIER register fields */ +#define RCC_MC_CIER_LSIRDYIE BIT(0) +#define RCC_MC_CIER_LSERDYIE BIT(1) +#define RCC_MC_CIER_HSIRDYIE BIT(2) +#define RCC_MC_CIER_HSERDYIE BIT(3) +#define RCC_MC_CIER_CSIRDYIE BIT(4) +#define RCC_MC_CIER_PLL1DYIE BIT(8) +#define RCC_MC_CIER_PLL2DYIE BIT(9) +#define RCC_MC_CIER_PLL3DYIE BIT(10) +#define RCC_MC_CIER_PLL4DYIE BIT(11) +#define RCC_MC_CIER_LSECSSIE BIT(16) +#define RCC_MC_CIER_WKUPIE BIT(20) + +/* RCC_MC_CIFR register fields */ +#define RCC_MC_CIFR_LSIRDYF BIT(0) +#define RCC_MC_CIFR_LSERDYF BIT(1) +#define RCC_MC_CIFR_HSIRDYF BIT(2) +#define RCC_MC_CIFR_HSERDYF BIT(3) +#define RCC_MC_CIFR_CSIRDYF BIT(4) +#define RCC_MC_CIFR_PLL1DYF BIT(8) +#define RCC_MC_CIFR_PLL2DYF BIT(9) +#define RCC_MC_CIFR_PLL3DYF BIT(10) +#define RCC_MC_CIFR_PLL4DYF BIT(11) +#define RCC_MC_CIFR_LSECSSF BIT(16) +#define RCC_MC_CIFR_WKUPF BIT(20) + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */ +#define RCC_OCENR_HSION BIT(0) +#define RCC_OCENR_HSIKERON BIT(1) +#define RCC_OCENR_CSION BIT(4) +#define RCC_OCENR_CSIKERON BIT(5) +#define RCC_OCENR_DIGBYP BIT(7) +#define RCC_OCENR_HSEON BIT(8) +#define RCC_OCENR_HSEKERON BIT(9) +#define RCC_OCENR_HSEBYP BIT(10) +#define RCC_OCENR_HSECSSON BIT(11) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ +#define RCC_RSTCLRR_OFFSET U(4) + +/* Used for most of DIVR register: max div for RTC */ +#define RCC_DIVR_DIV_MASK GENMASK(5, 0) +#define RCC_DIVR_DIVRDY BIT(31) + +/* Masks for specific DIVR registers */ +#define RCC_APBXDIV_MASK GENMASK(2, 0) +#define RCC_MPUDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MCUDIV_MASK GENMASK(3, 0) + +/* Used for most of RCC_<x>SELR registers */ +#define RCC_SELR_SRC_MASK GENMASK(2, 0) +#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) +#define RCC_SELR_SRCRDY BIT(31) + +/* Used for all RCC_PLL<n>CR registers */ +#define RCC_PLLNCR_PLLON BIT(0) +#define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) +#define RCC_PLLNCR_DIVPEN BIT(4) +#define RCC_PLLNCR_DIVQEN BIT(5) +#define RCC_PLLNCR_DIVREN BIT(6) +#define RCC_PLLNCR_DIVEN_SHIFT 4 + +/* Used for all RCC_PLL<n>CFGR1 registers */ +#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) +#define RCC_PLLNCFGR1_DIVM_SHIFT 16 +#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLLNCFGR1_DIVN_SHIFT 0 + +/* Only for PLL3 and PLL4 */ +#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 + +/* Used for all RCC_PLL<n>CFGR2 registers */ +#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_SHIFT 0 +#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 +#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLLNCFGR2_DIVR_SHIFT 16 + +/* Used for all RCC_PLL<n>FRACR registers */ +#define RCC_PLLNFRACR_FRACV_SHIFT 3 +#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLLNFRACR_FRACLE BIT(16) + +/* Used for all RCC_PLL<n>CSGR registers */ +#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 +#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 +#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 +#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) + +/* Used for TIMER Prescaler */ +#define RCC_TIMGXPRER_TIMGXPRE BIT(0) + +/* Used for RCC_MCO related operations */ +#define RCC_MCOCFG_MCOON BIT(12) +#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) +#define RCC_MCOCFG_MCODIV_SHIFT 4 +#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) + +#endif /* STM32MP1_RCC_H */ diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h index c46892b78e..93ec1c59f5 100644 --- a/include/drivers/st/stm32mp1_clk.h +++ b/include/drivers/st/stm32mp1_clk.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,36 +28,11 @@ int stm32mp1_clk_init(void); bool stm32mp1_rcc_is_secure(void); bool stm32mp1_rcc_is_mckprot(void); -void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure); -void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure); - -static inline void stm32mp1_clk_enable_non_secure(unsigned long id) -{ - __stm32mp1_clk_enable(id, false); -} - -static inline void stm32mp1_clk_enable_secure(unsigned long id) -{ - __stm32mp1_clk_enable(id, true); -} - -static inline void stm32mp1_clk_disable_non_secure(unsigned long id) -{ - __stm32mp1_clk_disable(id, false); -} - -static inline void stm32mp1_clk_disable_secure(unsigned long id) -{ - __stm32mp1_clk_disable(id, true); -} - -unsigned int stm32mp1_clk_get_refcount(unsigned long id); - /* SMP protection on RCC registers access */ void stm32mp1_clk_rcc_regs_lock(void); void stm32mp1_clk_rcc_regs_unlock(void); -void stm32mp1_stgen_increment(unsigned long long offset_in_ms); +void stm32mp1_clk_mcuss_protect(bool enable); #ifdef STM32MP_SHARED_RESOURCES void stm32mp1_register_clock_parents_secure(unsigned long id); diff --git a/include/drivers/st/stm32mp1_ddr.h b/include/drivers/st/stm32mp1_ddr.h index 4ab37d6b44..df71f35b1f 100644 --- a/include/drivers/st/stm32mp1_ddr.h +++ b/include/drivers/st/stm32mp1_ddr.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -10,29 +10,7 @@ #include <stdbool.h> #include <stdint.h> -#define DT_DDR_COMPAT "st,stm32mp1-ddr" - -struct stm32mp1_ddr_size { - uint64_t base; - uint64_t size; -}; - -/** - * struct ddr_info - * - * @dev: pointer for the device - * @info: UCLASS RAM information - * @ctl: DDR controleur base address - * @phy: DDR PHY base address - * @syscfg: syscfg base address - */ -struct ddr_info { - struct stm32mp1_ddr_size info; - struct stm32mp1_ddrctl *ctl; - struct stm32mp1_ddrphy *phy; - uintptr_t pwr; - uintptr_t rcc; -}; +#include <drivers/st/stm32mp_ddr.h> struct stm32mp1_ddrctrl_reg { uint32_t mstr; @@ -101,12 +79,14 @@ struct stm32mp1_ddrctrl_perf { uint32_t pcfgqos1_0; uint32_t pcfgwqos0_0; uint32_t pcfgwqos1_0; +#if STM32MP_DDR_DUAL_AXI_PORT uint32_t pcfgr_1; uint32_t pcfgw_1; uint32_t pcfgqos0_1; uint32_t pcfgqos1_1; uint32_t pcfgwqos0_1; uint32_t pcfgwqos1_1; +#endif }; struct stm32mp1_ddrphy_reg { @@ -119,8 +99,10 @@ struct stm32mp1_ddrphy_reg { uint32_t zq0cr1; uint32_t dx0gcr; uint32_t dx1gcr; +#if STM32MP_DDR_32BIT_INTERFACE uint32_t dx2gcr; uint32_t dx3gcr; +#endif }; struct stm32mp1_ddrphy_timing { @@ -136,39 +118,17 @@ struct stm32mp1_ddrphy_timing { uint32_t mr3; }; -struct stm32mp1_ddrphy_cal { - uint32_t dx0dllcr; - uint32_t dx0dqtr; - uint32_t dx0dqstr; - uint32_t dx1dllcr; - uint32_t dx1dqtr; - uint32_t dx1dqstr; - uint32_t dx2dllcr; - uint32_t dx2dqtr; - uint32_t dx2dqstr; - uint32_t dx3dllcr; - uint32_t dx3dqtr; - uint32_t dx3dqstr; -}; - -struct stm32mp1_ddr_info { - const char *name; - uint32_t speed; /* in kHZ */ - uint32_t size; /* Memory size in byte = col * row * width */ -}; - -struct stm32mp1_ddr_config { - struct stm32mp1_ddr_info info; +struct stm32mp_ddr_config { + struct stm32mp_ddr_info info; struct stm32mp1_ddrctrl_reg c_reg; struct stm32mp1_ddrctrl_timing c_timing; struct stm32mp1_ddrctrl_map c_map; struct stm32mp1_ddrctrl_perf c_perf; struct stm32mp1_ddrphy_reg p_reg; struct stm32mp1_ddrphy_timing p_timing; - struct stm32mp1_ddrphy_cal p_cal; }; -int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed); -void stm32mp1_ddr_init(struct ddr_info *priv, - struct stm32mp1_ddr_config *config); +int stm32mp1_ddr_clk_enable(struct stm32mp_ddr_priv *priv, uint32_t mem_speed); +void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config); + #endif /* STM32MP1_DDR_H */ diff --git a/include/drivers/st/stm32mp1_ddr_regs.h b/include/drivers/st/stm32mp1_ddr_regs.h index 01d6638348..2fbe1c8a58 100644 --- a/include/drivers/st/stm32mp1_ddr_regs.h +++ b/include/drivers/st/stm32mp1_ddr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -7,140 +7,11 @@ #ifndef STM32MP1_DDR_REGS_H #define STM32MP1_DDR_REGS_H +#include <drivers/st/stm32mp_ddrctrl_regs.h> #include <lib/utils_def.h> -/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */ -struct stm32mp1_ddrctl { - uint32_t mstr ; /* 0x0 Master */ - uint32_t stat; /* 0x4 Operating Mode Status */ - uint8_t reserved008[0x10 - 0x8]; - uint32_t mrctrl0; /* 0x10 Control 0 */ - uint32_t mrctrl1; /* 0x14 Control 1 */ - uint32_t mrstat; /* 0x18 Status */ - uint32_t reserved01c; /* 0x1c */ - uint32_t derateen; /* 0x20 Temperature Derate Enable */ - uint32_t derateint; /* 0x24 Temperature Derate Interval */ - uint8_t reserved028[0x30 - 0x28]; - uint32_t pwrctl; /* 0x30 Low Power Control */ - uint32_t pwrtmg; /* 0x34 Low Power Timing */ - uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */ - uint8_t reserved03c[0x50 - 0x3C]; - uint32_t rfshctl0; /* 0x50 Refresh Control 0 */ - uint32_t reserved054; /* 0x54 Refresh Control 1 */ - uint32_t reserved058; /* 0x58 Refresh Control 2 */ - uint32_t reserved05C; - uint32_t rfshctl3; /* 0x60 Refresh Control 0 */ - uint32_t rfshtmg; /* 0x64 Refresh Timing */ - uint8_t reserved068[0xc0 - 0x68]; - uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */ - uint32_t reserved0c4; /* 0xc4 CRC Parity Control1 */ - uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */ - uint32_t crcparstat; /* 0xcc CRC Parity Status */ - uint32_t init0; /* 0xd0 SDRAM Initialization 0 */ - uint32_t init1; /* 0xd4 SDRAM Initialization 1 */ - uint32_t init2; /* 0xd8 SDRAM Initialization 2 */ - uint32_t init3; /* 0xdc SDRAM Initialization 3 */ - uint32_t init4; /* 0xe0 SDRAM Initialization 4 */ - uint32_t init5; /* 0xe4 SDRAM Initialization 5 */ - uint32_t reserved0e8; - uint32_t reserved0ec; - uint32_t dimmctl; /* 0xf0 DIMM Control */ - uint8_t reserved0f4[0x100 - 0xf4]; - uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */ - uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */ - uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */ - uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */ - uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */ - uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */ - uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */ - uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */ - uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */ - uint8_t reserved124[0x138 - 0x124]; - uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */ - uint32_t dramtmg15; /* 0x13C SDRAM Timing 15 */ - uint8_t reserved140[0x180 - 0x140]; - uint32_t zqctl0; /* 0x180 ZQ Control 0 */ - uint32_t zqctl1; /* 0x184 ZQ Control 1 */ - uint32_t zqctl2; /* 0x188 ZQ Control 2 */ - uint32_t zqstat; /* 0x18c ZQ Status */ - uint32_t dfitmg0; /* 0x190 DFI Timing 0 */ - uint32_t dfitmg1; /* 0x194 DFI Timing 1 */ - uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */ - uint32_t reserved19c; - uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */ - uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */ - uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */ - uint32_t reserved1ac; - uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */ - uint8_t reserved1b4[0x1bc - 0x1b4]; - uint32_t dfistat; /* 0x1bc DFI Miscellaneous Control */ - uint8_t reserved1c0[0x1c4 - 0x1c0]; - uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */ - uint8_t reserved1c8[0x204 - 0x1c8]; - uint32_t addrmap1; /* 0x204 Address Map 1 */ - uint32_t addrmap2; /* 0x208 Address Map 2 */ - uint32_t addrmap3; /* 0x20c Address Map 3 */ - uint32_t addrmap4; /* 0x210 Address Map 4 */ - uint32_t addrmap5; /* 0x214 Address Map 5 */ - uint32_t addrmap6; /* 0x218 Address Map 6 */ - uint8_t reserved21c[0x224 - 0x21c]; - uint32_t addrmap9; /* 0x224 Address Map 9 */ - uint32_t addrmap10; /* 0x228 Address Map 10 */ - uint32_t addrmap11; /* 0x22C Address Map 11 */ - uint8_t reserved230[0x240 - 0x230]; - uint32_t odtcfg; /* 0x240 ODT Configuration */ - uint32_t odtmap; /* 0x244 ODT/Rank Map */ - uint8_t reserved248[0x250 - 0x248]; - uint32_t sched; /* 0x250 Scheduler Control */ - uint32_t sched1; /* 0x254 Scheduler Control 1 */ - uint32_t reserved258; - uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */ - uint32_t reserved260; - uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */ - uint32_t reserved268; - uint32_t perfwr1; /* 0x26c Write CAM 1 */ - uint8_t reserved27c[0x300 - 0x270]; - uint32_t dbg0; /* 0x300 Debug 0 */ - uint32_t dbg1; /* 0x304 Debug 1 */ - uint32_t dbgcam; /* 0x308 CAM Debug */ - uint32_t dbgcmd; /* 0x30c Command Debug */ - uint32_t dbgstat; /* 0x310 Status Debug */ - uint8_t reserved314[0x320 - 0x314]; - uint32_t swctl; /* 0x320 Software Programming Control Enable */ - uint32_t swstat; /* 0x324 Software Programming Control Status */ - uint8_t reserved328[0x36c - 0x328]; - uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */ - uint32_t poisonstat; /* 0x370 AXI Poison Status Register */ - uint8_t reserved374[0x3fc - 0x374]; - - /* Multi Port registers */ - uint32_t pstat; /* 0x3fc Port Status */ - uint32_t pccfg; /* 0x400 Port Common Configuration */ - - /* PORT 0 */ - uint32_t pcfgr_0; /* 0x404 Configuration Read */ - uint32_t pcfgw_0; /* 0x408 Configuration Write */ - uint8_t reserved40c[0x490 - 0x40c]; - uint32_t pctrl_0; /* 0x490 Port Control Register */ - uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */ - uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */ - uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */ - uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */ - uint8_t reserved4a4[0x4b4 - 0x4a4]; - - /* PORT 1 */ - uint32_t pcfgr_1; /* 0x4b4 Configuration Read */ - uint32_t pcfgw_1; /* 0x4b8 Configuration Write */ - uint8_t reserved4bc[0x540 - 0x4bc]; - uint32_t pctrl_1; /* 0x540 Port 2 Control Register */ - uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */ - uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */ - uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */ - uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */ -} __packed; - /* DDR Physical Interface Control (DDRPHYC) registers*/ -struct stm32mp1_ddrphy { +struct stm32mp_ddrphy { uint32_t ridr; /* 0x00 R Revision Identification */ uint32_t pir; /* 0x04 R/W PHY Initialization */ uint32_t pgcr; /* 0x08 R/W PHY General Configuration */ @@ -214,6 +85,7 @@ struct stm32mp1_ddrphy { uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */ uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */ uint8_t res6[0x240 - 0x218]; /* 0x218 */ +#if STM32MP_DDR_32BIT_INTERFACE uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */ uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */ uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */ @@ -227,103 +99,9 @@ struct stm32mp1_ddrphy { uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */ uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */ uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */ +#endif } __packed; -/* DDR Controller registers offsets */ -#define DDRCTRL_MSTR 0x000 -#define DDRCTRL_STAT 0x004 -#define DDRCTRL_MRCTRL0 0x010 -#define DDRCTRL_MRSTAT 0x018 -#define DDRCTRL_PWRCTL 0x030 -#define DDRCTRL_PWRTMG 0x034 -#define DDRCTRL_HWLPCTL 0x038 -#define DDRCTRL_RFSHCTL3 0x060 -#define DDRCTRL_RFSHTMG 0x064 -#define DDRCTRL_INIT0 0x0D0 -#define DDRCTRL_DFIMISC 0x1B0 -#define DDRCTRL_DBG1 0x304 -#define DDRCTRL_DBGCAM 0x308 -#define DDRCTRL_DBGCMD 0x30C -#define DDRCTRL_DBGSTAT 0x310 -#define DDRCTRL_SWCTL 0x320 -#define DDRCTRL_SWSTAT 0x324 -#define DDRCTRL_PSTAT 0x3FC -#define DDRCTRL_PCTRL_0 0x490 -#define DDRCTRL_PCTRL_1 0x540 - -/* DDR Controller Register fields */ -#define DDRCTRL_MSTR_DDR3 BIT(0) -#define DDRCTRL_MSTR_LPDDR2 BIT(2) -#define DDRCTRL_MSTR_LPDDR3 BIT(3) -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL 0 -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12) -#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER BIT(13) -#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15) - -#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) -#define DDRCTRL_STAT_OPERATING_MODE_NORMAL BIT(0) -#define DDRCTRL_STAT_OPERATING_MODE_SR (BIT(0) | BIT(1)) -#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) -#define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5)) -#define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5) - -#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0) -/* Only one rank supported */ -#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4 -#define DDRCTRL_MRCTRL0_MR_RANK_ALL \ - BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT) -#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12 -#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12) -#define DDRCTRL_MRCTRL0_MR_WR BIT(31) - -#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) - -#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) -#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) -#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) -#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) - -#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) -#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) - -#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) - -#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) - -#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) -#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16 - -#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30) -#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30) - -#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) - -#define DDRCTRL_DBG1_DIS_HIF BIT(1) - -#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) -#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28) -#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26) -#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8) -#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0) -#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \ - (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \ - DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY) -#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \ - (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \ - DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \ - DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH) - -#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0) - -#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0) - -#define DDRCTRL_SWCTL_SW_DONE BIT(0) - -#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) - -#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) - /* DDR PHY registers offsets */ #define DDRPHYC_PIR 0x004 #define DDRPHYC_PGCR 0x008 @@ -339,10 +117,12 @@ struct stm32mp1_ddrphy { #define DDRPHYC_DX0DLLCR 0x1CC #define DDRPHYC_DX1GCR 0x200 #define DDRPHYC_DX1DLLCR 0x20C +#if STM32MP_DDR_32BIT_INTERFACE #define DDRPHYC_DX2GCR 0x240 #define DDRPHYC_DX2DLLCR 0x24C #define DDRPHYC_DX3GCR 0x280 #define DDRPHYC_DX3DLLCR 0x28C +#endif /* DDR PHY Register fields */ #define DDRPHYC_PIR_INIT BIT(0) @@ -353,6 +133,7 @@ struct stm32mp1_ddrphy { #define DDRPHYC_PIR_DRAMRST BIT(5) #define DDRPHYC_PIR_DRAMINIT BIT(6) #define DDRPHYC_PIR_QSTRN BIT(7) +#define DDRPHYC_PIR_RVTRN BIT(8) #define DDRPHYC_PIR_ICPC BIT(16) #define DDRPHYC_PIR_ZCALBYP BIT(30) #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index 2ffc3b2bc2..d79422508e 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -1,565 +1,12 @@ /* - * Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef STM32MP1_RCC_H -#define STM32MP1_RCC_H - -#include <lib/utils_def.h> - -#define RCC_TZCR U(0x00) -#define RCC_OCENSETR U(0x0C) -#define RCC_OCENCLRR U(0x10) -#define RCC_HSICFGR U(0x18) -#define RCC_CSICFGR U(0x1C) -#define RCC_MPCKSELR U(0x20) -#define RCC_ASSCKSELR U(0x24) -#define RCC_RCK12SELR U(0x28) -#define RCC_MPCKDIVR U(0x2C) -#define RCC_AXIDIVR U(0x30) -#define RCC_APB4DIVR U(0x3C) -#define RCC_APB5DIVR U(0x40) -#define RCC_RTCDIVR U(0x44) -#define RCC_MSSCKSELR U(0x48) -#define RCC_PLL1CR U(0x80) -#define RCC_PLL1CFGR1 U(0x84) -#define RCC_PLL1CFGR2 U(0x88) -#define RCC_PLL1FRACR U(0x8C) -#define RCC_PLL1CSGR U(0x90) -#define RCC_PLL2CR U(0x94) -#define RCC_PLL2CFGR1 U(0x98) -#define RCC_PLL2CFGR2 U(0x9C) -#define RCC_PLL2FRACR U(0xA0) -#define RCC_PLL2CSGR U(0xA4) -#define RCC_I2C46CKSELR U(0xC0) -#define RCC_SPI6CKSELR U(0xC4) -#define RCC_UART1CKSELR U(0xC8) -#define RCC_RNG1CKSELR U(0xCC) -#define RCC_CPERCKSELR U(0xD0) -#define RCC_STGENCKSELR U(0xD4) -#define RCC_DDRITFCR U(0xD8) -#define RCC_MP_BOOTCR U(0x100) -#define RCC_MP_SREQSETR U(0x104) -#define RCC_MP_SREQCLRR U(0x108) -#define RCC_MP_GCR U(0x10C) -#define RCC_MP_APRSTCR U(0x110) -#define RCC_MP_APRSTSR U(0x114) -#define RCC_BDCR U(0x140) -#define RCC_RDLSICR U(0x144) -#define RCC_APB4RSTSETR U(0x180) -#define RCC_APB4RSTCLRR U(0x184) -#define RCC_APB5RSTSETR U(0x188) -#define RCC_APB5RSTCLRR U(0x18C) -#define RCC_AHB5RSTSETR U(0x190) -#define RCC_AHB5RSTCLRR U(0x194) -#define RCC_AHB6RSTSETR U(0x198) -#define RCC_AHB6RSTCLRR U(0x19C) -#define RCC_TZAHB6RSTSETR U(0x1A0) -#define RCC_TZAHB6RSTCLRR U(0x1A4) -#define RCC_MP_APB4ENSETR U(0x200) -#define RCC_MP_APB4ENCLRR U(0x204) -#define RCC_MP_APB5ENSETR U(0x208) -#define RCC_MP_APB5ENCLRR U(0x20C) -#define RCC_MP_AHB5ENSETR U(0x210) -#define RCC_MP_AHB5ENCLRR U(0x214) -#define RCC_MP_AHB6ENSETR U(0x218) -#define RCC_MP_AHB6ENCLRR U(0x21C) -#define RCC_MP_TZAHB6ENSETR U(0x220) -#define RCC_MP_TZAHB6ENCLRR U(0x224) -#define RCC_MC_APB4ENSETR U(0x280) -#define RCC_MC_APB4ENCLRR U(0x284) -#define RCC_MC_APB5ENSETR U(0x288) -#define RCC_MC_APB5ENCLRR U(0x28C) -#define RCC_MC_AHB5ENSETR U(0x290) -#define RCC_MC_AHB5ENCLRR U(0x294) -#define RCC_MC_AHB6ENSETR U(0x298) -#define RCC_MC_AHB6ENCLRR U(0x29C) -#define RCC_MP_APB4LPENSETR U(0x300) -#define RCC_MP_APB4LPENCLRR U(0x304) -#define RCC_MP_APB5LPENSETR U(0x308) -#define RCC_MP_APB5LPENCLRR U(0x30C) -#define RCC_MP_AHB5LPENSETR U(0x310) -#define RCC_MP_AHB5LPENCLRR U(0x314) -#define RCC_MP_AHB6LPENSETR U(0x318) -#define RCC_MP_AHB6LPENCLRR U(0x31C) -#define RCC_MP_TZAHB6LPENSETR U(0x320) -#define RCC_MP_TZAHB6LPENCLRR U(0x324) -#define RCC_MC_APB4LPENSETR U(0x380) -#define RCC_MC_APB4LPENCLRR U(0x384) -#define RCC_MC_APB5LPENSETR U(0x388) -#define RCC_MC_APB5LPENCLRR U(0x38C) -#define RCC_MC_AHB5LPENSETR U(0x390) -#define RCC_MC_AHB5LPENCLRR U(0x394) -#define RCC_MC_AHB6LPENSETR U(0x398) -#define RCC_MC_AHB6LPENCLRR U(0x39C) -#define RCC_BR_RSTSCLRR U(0x400) -#define RCC_MP_GRSTCSETR U(0x404) -#define RCC_MP_RSTSCLRR U(0x408) -#define RCC_MP_IWDGFZSETR U(0x40C) -#define RCC_MP_IWDGFZCLRR U(0x410) -#define RCC_MP_CIER U(0x414) -#define RCC_MP_CIFR U(0x418) -#define RCC_PWRLPDLYCR U(0x41C) -#define RCC_MP_RSTSSETR U(0x420) -#define RCC_MCO1CFGR U(0x800) -#define RCC_MCO2CFGR U(0x804) -#define RCC_OCRDYR U(0x808) -#define RCC_DBGCFGR U(0x80C) -#define RCC_RCK3SELR U(0x820) -#define RCC_RCK4SELR U(0x824) -#define RCC_TIMG1PRER U(0x828) -#define RCC_TIMG2PRER U(0x82C) -#define RCC_MCUDIVR U(0x830) -#define RCC_APB1DIVR U(0x834) -#define RCC_APB2DIVR U(0x838) -#define RCC_APB3DIVR U(0x83C) -#define RCC_PLL3CR U(0x880) -#define RCC_PLL3CFGR1 U(0x884) -#define RCC_PLL3CFGR2 U(0x888) -#define RCC_PLL3FRACR U(0x88C) -#define RCC_PLL3CSGR U(0x890) -#define RCC_PLL4CR U(0x894) -#define RCC_PLL4CFGR1 U(0x898) -#define RCC_PLL4CFGR2 U(0x89C) -#define RCC_PLL4FRACR U(0x8A0) -#define RCC_PLL4CSGR U(0x8A4) -#define RCC_I2C12CKSELR U(0x8C0) -#define RCC_I2C35CKSELR U(0x8C4) -#define RCC_SAI1CKSELR U(0x8C8) -#define RCC_SAI2CKSELR U(0x8CC) -#define RCC_SAI3CKSELR U(0x8D0) -#define RCC_SAI4CKSELR U(0x8D4) -#define RCC_SPI2S1CKSELR U(0x8D8) -#define RCC_SPI2S23CKSELR U(0x8DC) -#define RCC_SPI45CKSELR U(0x8E0) -#define RCC_UART6CKSELR U(0x8E4) -#define RCC_UART24CKSELR U(0x8E8) -#define RCC_UART35CKSELR U(0x8EC) -#define RCC_UART78CKSELR U(0x8F0) -#define RCC_SDMMC12CKSELR U(0x8F4) -#define RCC_SDMMC3CKSELR U(0x8F8) -#define RCC_ETHCKSELR U(0x8FC) -#define RCC_QSPICKSELR U(0x900) -#define RCC_FMCCKSELR U(0x904) -#define RCC_FDCANCKSELR U(0x90C) -#define RCC_SPDIFCKSELR U(0x914) -#define RCC_CECCKSELR U(0x918) -#define RCC_USBCKSELR U(0x91C) -#define RCC_RNG2CKSELR U(0x920) -#define RCC_DSICKSELR U(0x924) -#define RCC_ADCCKSELR U(0x928) -#define RCC_LPTIM45CKSELR U(0x92C) -#define RCC_LPTIM23CKSELR U(0x930) -#define RCC_LPTIM1CKSELR U(0x934) -#define RCC_APB1RSTSETR U(0x980) -#define RCC_APB1RSTCLRR U(0x984) -#define RCC_APB2RSTSETR U(0x988) -#define RCC_APB2RSTCLRR U(0x98C) -#define RCC_APB3RSTSETR U(0x990) -#define RCC_APB3RSTCLRR U(0x994) -#define RCC_AHB2RSTSETR U(0x998) -#define RCC_AHB2RSTCLRR U(0x99C) -#define RCC_AHB3RSTSETR U(0x9A0) -#define RCC_AHB3RSTCLRR U(0x9A4) -#define RCC_AHB4RSTSETR U(0x9A8) -#define RCC_AHB4RSTCLRR U(0x9AC) -#define RCC_MP_APB1ENSETR U(0xA00) -#define RCC_MP_APB1ENCLRR U(0xA04) -#define RCC_MP_APB2ENSETR U(0xA08) -#define RCC_MP_APB2ENCLRR U(0xA0C) -#define RCC_MP_APB3ENSETR U(0xA10) -#define RCC_MP_APB3ENCLRR U(0xA14) -#define RCC_MP_AHB2ENSETR U(0xA18) -#define RCC_MP_AHB2ENCLRR U(0xA1C) -#define RCC_MP_AHB3ENSETR U(0xA20) -#define RCC_MP_AHB3ENCLRR U(0xA24) -#define RCC_MP_AHB4ENSETR U(0xA28) -#define RCC_MP_AHB4ENCLRR U(0xA2C) -#define RCC_MP_MLAHBENSETR U(0xA38) -#define RCC_MP_MLAHBENCLRR U(0xA3C) -#define RCC_MC_APB1ENSETR U(0xA80) -#define RCC_MC_APB1ENCLRR U(0xA84) -#define RCC_MC_APB2ENSETR U(0xA88) -#define RCC_MC_APB2ENCLRR U(0xA8C) -#define RCC_MC_APB3ENSETR U(0xA90) -#define RCC_MC_APB3ENCLRR U(0xA94) -#define RCC_MC_AHB2ENSETR U(0xA98) -#define RCC_MC_AHB2ENCLRR U(0xA9C) -#define RCC_MC_AHB3ENSETR U(0xAA0) -#define RCC_MC_AHB3ENCLRR U(0xAA4) -#define RCC_MC_AHB4ENSETR U(0xAA8) -#define RCC_MC_AHB4ENCLRR U(0xAAC) -#define RCC_MC_AXIMENSETR U(0xAB0) -#define RCC_MC_AXIMENCLRR U(0xAB4) -#define RCC_MC_MLAHBENSETR U(0xAB8) -#define RCC_MC_MLAHBENCLRR U(0xABC) -#define RCC_MP_APB1LPENSETR U(0xB00) -#define RCC_MP_APB1LPENCLRR U(0xB04) -#define RCC_MP_APB2LPENSETR U(0xB08) -#define RCC_MP_APB2LPENCLRR U(0xB0C) -#define RCC_MP_APB3LPENSETR U(0xB10) -#define RCC_MP_APB3LPENCLRR U(0xB14) -#define RCC_MP_AHB2LPENSETR U(0xB18) -#define RCC_MP_AHB2LPENCLRR U(0xB1C) -#define RCC_MP_AHB3LPENSETR U(0xB20) -#define RCC_MP_AHB3LPENCLRR U(0xB24) -#define RCC_MP_AHB4LPENSETR U(0xB28) -#define RCC_MP_AHB4LPENCLRR U(0xB2C) -#define RCC_MP_AXIMLPENSETR U(0xB30) -#define RCC_MP_AXIMLPENCLRR U(0xB34) -#define RCC_MP_MLAHBLPENSETR U(0xB38) -#define RCC_MP_MLAHBLPENCLRR U(0xB3C) -#define RCC_MC_APB1LPENSETR U(0xB80) -#define RCC_MC_APB1LPENCLRR U(0xB84) -#define RCC_MC_APB2LPENSETR U(0xB88) -#define RCC_MC_APB2LPENCLRR U(0xB8C) -#define RCC_MC_APB3LPENSETR U(0xB90) -#define RCC_MC_APB3LPENCLRR U(0xB94) -#define RCC_MC_AHB2LPENSETR U(0xB98) -#define RCC_MC_AHB2LPENCLRR U(0xB9C) -#define RCC_MC_AHB3LPENSETR U(0xBA0) -#define RCC_MC_AHB3LPENCLRR U(0xBA4) -#define RCC_MC_AHB4LPENSETR U(0xBA8) -#define RCC_MC_AHB4LPENCLRR U(0xBAC) -#define RCC_MC_AXIMLPENSETR U(0xBB0) -#define RCC_MC_AXIMLPENCLRR U(0xBB4) -#define RCC_MC_MLAHBLPENSETR U(0xBB8) -#define RCC_MC_MLAHBLPENCLRR U(0xBBC) -#define RCC_MC_RSTSCLRR U(0xC00) -#define RCC_MC_CIER U(0xC14) -#define RCC_MC_CIFR U(0xC18) -#define RCC_VERR U(0xFF4) -#define RCC_IDR U(0xFF8) -#define RCC_SIDR U(0xFFC) - -#define RCC_OFFSET_MASK GENMASK(11, 0) - -/* Values for RCC_TZCR register */ -#define RCC_TZCR_TZEN BIT(0) -#define RCC_TZCR_MCKPROT BIT(1) - -/* Used for most of RCC_<x>SELR registers */ -#define RCC_SELR_SRC_MASK GENMASK(2, 0) -#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) -#define RCC_SELR_SRCRDY BIT(31) - -/* Values of RCC_MPCKSELR register */ -#define RCC_MPCKSELR_HSI 0x00000000 -#define RCC_MPCKSELR_HSE 0x00000001 -#define RCC_MPCKSELR_PLL 0x00000002 -#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 -#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) -#define RCC_MPCKSELR_MPUSRC_SHIFT 0 - -/* Values of RCC_ASSCKSELR register */ -#define RCC_ASSCKSELR_HSI 0x00000000 -#define RCC_ASSCKSELR_HSE 0x00000001 -#define RCC_ASSCKSELR_PLL 0x00000002 - -/* Values of RCC_MSSCKSELR register */ -#define RCC_MSSCKSELR_HSI 0x00000000 -#define RCC_MSSCKSELR_HSE 0x00000001 -#define RCC_MSSCKSELR_CSI 0x00000002 -#define RCC_MSSCKSELR_PLL 0x00000003 - -/* Values of RCC_CPERCKSELR register */ -#define RCC_CPERCKSELR_HSI 0x00000000 -#define RCC_CPERCKSELR_CSI 0x00000001 -#define RCC_CPERCKSELR_HSE 0x00000002 -#define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0) -#define RCC_CPERCKSELR_PERSRC_SHIFT 0 - -/* Used for most of DIVR register: max div for RTC */ -#define RCC_DIVR_DIV_MASK GENMASK(5, 0) -#define RCC_DIVR_DIVRDY BIT(31) - -/* Masks for specific DIVR registers */ -#define RCC_APBXDIV_MASK GENMASK(2, 0) -#define RCC_MPUDIV_MASK GENMASK(2, 0) -#define RCC_AXIDIV_MASK GENMASK(2, 0) -#define RCC_MCUDIV_MASK GENMASK(3, 0) - -/* Used for TIMER Prescaler */ -#define RCC_TIMGXPRER_TIMGXPRE BIT(0) - -/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ -#define RCC_MP_ENCLRR_OFFSET U(4) - -/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ -#define RCC_RSTCLRR_OFFSET U(4) - -/* Fields of RCC_BDCR register */ -#define RCC_BDCR_LSEON BIT(0) -#define RCC_BDCR_LSEBYP BIT(1) -#define RCC_BDCR_LSERDY BIT(2) -#define RCC_BDCR_DIGBYP BIT(3) -#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) -#define RCC_BDCR_LSEDRV_SHIFT 4 -#define RCC_BDCR_LSECSSON BIT(8) -#define RCC_BDCR_RTCCKEN BIT(20) -#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) -#define RCC_BDCR_RTCSRC_SHIFT 16 -#define RCC_BDCR_VSWRST BIT(31) - -/* Fields of RCC_RDLSICR register */ -#define RCC_RDLSICR_LSION BIT(0) -#define RCC_RDLSICR_LSIRDY BIT(1) - -/* Used for all RCC_PLL<n>CR registers */ -#define RCC_PLLNCR_PLLON BIT(0) -#define RCC_PLLNCR_PLLRDY BIT(1) -#define RCC_PLLNCR_SSCG_CTRL BIT(2) -#define RCC_PLLNCR_DIVPEN BIT(4) -#define RCC_PLLNCR_DIVQEN BIT(5) -#define RCC_PLLNCR_DIVREN BIT(6) -#define RCC_PLLNCR_DIVEN_SHIFT 4 - -/* Used for all RCC_PLL<n>CFGR1 registers */ -#define RCC_PLLNCFGR1_DIVM_SHIFT 16 -#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) -#define RCC_PLLNCFGR1_DIVN_SHIFT 0 -#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) -/* Only for PLL3 and PLL4 */ -#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 -#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) - -/* Used for all RCC_PLL<n>CFGR2 registers */ -#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) -#define RCC_PLLNCFGR2_DIVP_SHIFT 0 -#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) -#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 -#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) -#define RCC_PLLNCFGR2_DIVR_SHIFT 16 -#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) - -/* Used for all RCC_PLL<n>FRACR registers */ -#define RCC_PLLNFRACR_FRACV_SHIFT 3 -#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) -#define RCC_PLLNFRACR_FRACLE BIT(16) - -/* Used for all RCC_PLL<n>CSGR registers */ -#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 -#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) -#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 -#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) -#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 -#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) - -/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */ -#define RCC_OCENR_HSION BIT(0) -#define RCC_OCENR_HSIKERON BIT(1) -#define RCC_OCENR_CSION BIT(4) -#define RCC_OCENR_CSIKERON BIT(5) -#define RCC_OCENR_DIGBYP BIT(7) -#define RCC_OCENR_HSEON BIT(8) -#define RCC_OCENR_HSEKERON BIT(9) -#define RCC_OCENR_HSEBYP BIT(10) -#define RCC_OCENR_HSECSSON BIT(11) - -/* Fields of RCC_OCRDYR register */ -#define RCC_OCRDYR_HSIRDY BIT(0) -#define RCC_OCRDYR_HSIDIVRDY BIT(2) -#define RCC_OCRDYR_CSIRDY BIT(4) -#define RCC_OCRDYR_HSERDY BIT(8) - -/* Fields of RCC_DDRITFCR register */ -#define RCC_DDRITFCR_DDRC1EN BIT(0) -#define RCC_DDRITFCR_DDRC1LPEN BIT(1) -#define RCC_DDRITFCR_DDRC2EN BIT(2) -#define RCC_DDRITFCR_DDRC2LPEN BIT(3) -#define RCC_DDRITFCR_DDRPHYCEN BIT(4) -#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) -#define RCC_DDRITFCR_DDRCAPBEN BIT(6) -#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) -#define RCC_DDRITFCR_AXIDCGEN BIT(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) -#define RCC_DDRITFCR_DDRCAPBRST BIT(14) -#define RCC_DDRITFCR_DDRCAXIRST BIT(15) -#define RCC_DDRITFCR_DDRCORERST BIT(16) -#define RCC_DDRITFCR_DPHYAPBRST BIT(17) -#define RCC_DDRITFCR_DPHYRST BIT(18) -#define RCC_DDRITFCR_DPHYCTLRST BIT(19) -#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) -#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 -#define RCC_DDRITFCR_DDRCKMOD_SSR 0 -#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) -#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) -#define RCC_DDRITFCR_GSKPCTRL BIT(24) - -/* Fields of RCC_HSICFGR register */ -#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) -#define RCC_HSICFGR_HSITRIM_SHIFT 8 -#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) -#define RCC_HSICFGR_HSICAL_SHIFT 16 -#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16) - -/* Fields of RCC_CSICFGR register */ -#define RCC_CSICFGR_CSITRIM_SHIFT 8 -#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) -#define RCC_CSICFGR_CSICAL_SHIFT 16 -#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) - -/* Used for RCC_MCO related operations */ -#define RCC_MCOCFG_MCOON BIT(12) -#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) -#define RCC_MCOCFG_MCODIV_SHIFT 4 -#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) - -/* Fields of RCC_DBGCFGR register */ -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -/* RCC register fields for reset reasons */ -#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) -#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) -#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) -#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) -#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) -#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) -#define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7) -#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) -#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) -#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) -#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) -#define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14) - -/* Global Reset Register */ -#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) -#define RCC_MP_GRSTCSETR_MCURST BIT(1) -#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) -#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) - -/* Clock Source Interrupt Flag Register */ -#define RCC_MP_CIFR_MASK U(0x110F1F) -#define RCC_MP_CIFR_LSIRDYF BIT(0) -#define RCC_MP_CIFR_LSERDYF BIT(1) -#define RCC_MP_CIFR_HSIRDYF BIT(2) -#define RCC_MP_CIFR_HSERDYF BIT(3) -#define RCC_MP_CIFR_CSIRDYF BIT(4) -#define RCC_MP_CIFR_PLL1DYF BIT(8) -#define RCC_MP_CIFR_PLL2DYF BIT(9) -#define RCC_MP_CIFR_PLL3DYF BIT(10) -#define RCC_MP_CIFR_PLL4DYF BIT(11) -#define RCC_MP_CIFR_WKUPF BIT(20) - -/* Stop Request Set Register */ -#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) -#define RCC_MP_SREQSETR_STPREQ_P1 BIT(1) - -/* Stop Request Clear Register */ -#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) -#define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1) - -/* Values of RCC_UART24CKSELR register */ -#define RCC_UART24CKSELR_HSI 0x00000002 - -/* Values of RCC_MP_APB1ENSETR register */ -#define RCC_MP_APB1ENSETR_UART4EN BIT(16) - -/* Values of RCC_MP_APB5ENSETR register */ -#define RCC_MP_APB5ENSETR_SPI6EN BIT(0) -#define RCC_MP_APB5ENSETR_I2C4EN BIT(2) -#define RCC_MP_APB5ENSETR_I2C6EN BIT(3) -#define RCC_MP_APB5ENSETR_USART1EN BIT(4) -#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) -#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) - -/* Values of RCC_MP_AHB4ENSETR register */ -#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6) -#define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7) - -/* Values of RCC_MP_AHB5ENSETR register */ -#define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0) -#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) -#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) -#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) - -/* Values of RCC_MP_IWDGFZSETR register */ -#define RCC_MP_IWDGFZSETR_IWDG1 BIT(0) -#define RCC_MP_IWDGFZSETR_IWDG2 BIT(1) - -/* Values of RCC_PWRLPDLYCR register */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) - -/* RCC_ASSCKSELR register fields */ -#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) -#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 - -/* RCC_MSSCKSELR register fields */ -#define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0) -#define RCC_MSSCKSELR_MCUSSRC_SHIFT 0 - -/* RCC_I2C46CKSELR register fields */ -#define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0) -#define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0 - -/* RCC_SPI6CKSELR register fields */ -#define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0) -#define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0 - -/* RCC_UART1CKSELR register fields */ -#define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0) -#define RCC_UART1CKSELR_UART1SRC_SHIFT 0 - -/* RCC_RNG1CKSELR register fields */ -#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) -#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 - -/* RCC_STGENCKSELR register fields */ -#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) -#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 - -/* RCC_I2C12CKSELR register fields */ -#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) -#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 - -/* RCC_I2C35CKSELR register fields */ -#define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0) -#define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0 - -/* RCC_UART6CKSELR register fields */ -#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) -#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 - -/* RCC_UART24CKSELR register fields */ -#define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0) -#define RCC_UART24CKSELR_UART24SRC_SHIFT 0 - -/* RCC_UART35CKSELR register fields */ -#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) -#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 - -/* RCC_UART78CKSELR register fields */ -#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) -#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 - -/* RCC_SDMMC12CKSELR register fields */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0 - -/* RCC_SDMMC3CKSELR register fields */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0 - -/* RCC_ETHCKSELR register fields */ -#define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0) -#define RCC_ETHCKSELR_ETHSRC_SHIFT 0 - -/* RCC_QSPICKSELR register fields */ -#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) -#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 - -/* RCC_FMCCKSELR register fields */ -#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) -#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 - -/* RCC_USBCKSELR register fields */ -#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) -#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 -#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) -#define RCC_USBCKSELR_USBOSRC_SHIFT 4 - -#endif /* STM32MP1_RCC_H */ +#if STM32MP13 +#include "stm32mp13_rcc.h" +#endif +#if STM32MP15 +#include "stm32mp15_rcc.h" +#endif diff --git a/include/drivers/st/stm32mp1_usb.h b/include/drivers/st/stm32mp1_usb.h new file mode 100644 index 0000000000..06a34cb27b --- /dev/null +++ b/include/drivers/st/stm32mp1_usb.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_USB_H +#define STM32MP1_USB_H + +#include <drivers/usb_device.h> + +void stm32mp1_usb_init_driver(struct usb_handle *usb_core_handle, + struct pcd_handle *pcd_handle, + void *base_register); + +#endif /* STM32MP1_USB_H */ diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h new file mode 100644 index 0000000000..9dd25f3cd1 --- /dev/null +++ b/include/drivers/st/stm32mp25_rcc.h @@ -0,0 +1,4986 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP2_RCC_H +#define STM32MP2_RCC_H + +#include <lib/utils_def.h> + +#define RCC_SECCFGR0 U(0x0) +#define RCC_SECCFGR1 U(0x4) +#define RCC_SECCFGR2 U(0x8) +#define RCC_SECCFGR3 U(0xC) +#define RCC_PRIVCFGR0 U(0x10) +#define RCC_PRIVCFGR1 U(0x14) +#define RCC_PRIVCFGR2 U(0x18) +#define RCC_PRIVCFGR3 U(0x1C) +#define RCC_RCFGLOCKR0 U(0x20) +#define RCC_RCFGLOCKR1 U(0x24) +#define RCC_RCFGLOCKR2 U(0x28) +#define RCC_RCFGLOCKR3 U(0x2C) +#define RCC_R0CIDCFGR U(0x30) +#define RCC_R0SEMCR U(0x34) +#define RCC_R1CIDCFGR U(0x38) +#define RCC_R1SEMCR U(0x3C) +#define RCC_R2CIDCFGR U(0x40) +#define RCC_R2SEMCR U(0x44) +#define RCC_R3CIDCFGR U(0x48) +#define RCC_R3SEMCR U(0x4C) +#define RCC_R4CIDCFGR U(0x50) +#define RCC_R4SEMCR U(0x54) +#define RCC_R5CIDCFGR U(0x58) +#define RCC_R5SEMCR U(0x5C) +#define RCC_R6CIDCFGR U(0x60) +#define RCC_R6SEMCR U(0x64) +#define RCC_R7CIDCFGR U(0x68) +#define RCC_R7SEMCR U(0x6C) +#define RCC_R8CIDCFGR U(0x70) +#define RCC_R8SEMCR U(0x74) +#define RCC_R9CIDCFGR U(0x78) +#define RCC_R9SEMCR U(0x7C) +#define RCC_R10CIDCFGR U(0x80) +#define RCC_R10SEMCR U(0x84) +#define RCC_R11CIDCFGR U(0x88) +#define RCC_R11SEMCR U(0x8C) +#define RCC_R12CIDCFGR U(0x90) +#define RCC_R12SEMCR U(0x94) +#define RCC_R13CIDCFGR U(0x98) +#define RCC_R13SEMCR U(0x9C) +#define RCC_R14CIDCFGR U(0xA0) +#define RCC_R14SEMCR U(0xA4) +#define RCC_R15CIDCFGR U(0xA8) +#define RCC_R15SEMCR U(0xAC) +#define RCC_R16CIDCFGR U(0xB0) +#define RCC_R16SEMCR U(0xB4) +#define RCC_R17CIDCFGR U(0xB8) +#define RCC_R17SEMCR U(0xBC) +#define RCC_R18CIDCFGR U(0xC0) +#define RCC_R18SEMCR U(0xC4) +#define RCC_R19CIDCFGR U(0xC8) +#define RCC_R19SEMCR U(0xCC) +#define RCC_R20CIDCFGR U(0xD0) +#define RCC_R20SEMCR U(0xD4) +#define RCC_R21CIDCFGR U(0xD8) +#define RCC_R21SEMCR U(0xDC) +#define RCC_R22CIDCFGR U(0xE0) +#define RCC_R22SEMCR U(0xE4) +#define RCC_R23CIDCFGR U(0xE8) +#define RCC_R23SEMCR U(0xEC) +#define RCC_R24CIDCFGR U(0xF0) +#define RCC_R24SEMCR U(0xF4) +#define RCC_R25CIDCFGR U(0xF8) +#define RCC_R25SEMCR U(0xFC) +#define RCC_R26CIDCFGR U(0x100) +#define RCC_R26SEMCR U(0x104) +#define RCC_R27CIDCFGR U(0x108) +#define RCC_R27SEMCR U(0x10C) +#define RCC_R28CIDCFGR U(0x110) +#define RCC_R28SEMCR U(0x114) +#define RCC_R29CIDCFGR U(0x118) +#define RCC_R29SEMCR U(0x11C) +#define RCC_R30CIDCFGR U(0x120) +#define RCC_R30SEMCR U(0x124) +#define RCC_R31CIDCFGR U(0x128) +#define RCC_R31SEMCR U(0x12C) +#define RCC_R32CIDCFGR U(0x130) +#define RCC_R32SEMCR U(0x134) +#define RCC_R33CIDCFGR U(0x138) +#define RCC_R33SEMCR U(0x13C) +#define RCC_R34CIDCFGR U(0x140) +#define RCC_R34SEMCR U(0x144) +#define RCC_R35CIDCFGR U(0x148) +#define RCC_R35SEMCR U(0x14C) +#define RCC_R36CIDCFGR U(0x150) +#define RCC_R36SEMCR U(0x154) +#define RCC_R37CIDCFGR U(0x158) +#define RCC_R37SEMCR U(0x15C) +#define RCC_R38CIDCFGR U(0x160) +#define RCC_R38SEMCR U(0x164) +#define RCC_R39CIDCFGR U(0x168) +#define RCC_R39SEMCR U(0x16C) +#define RCC_R40CIDCFGR U(0x170) +#define RCC_R40SEMCR U(0x174) +#define RCC_R41CIDCFGR U(0x178) +#define RCC_R41SEMCR U(0x17C) +#define RCC_R42CIDCFGR U(0x180) +#define RCC_R42SEMCR U(0x184) +#define RCC_R43CIDCFGR U(0x188) +#define RCC_R43SEMCR U(0x18C) +#define RCC_R44CIDCFGR U(0x190) +#define RCC_R44SEMCR U(0x194) +#define RCC_R45CIDCFGR U(0x198) +#define RCC_R45SEMCR U(0x19C) +#define RCC_R46CIDCFGR U(0x1A0) +#define RCC_R46SEMCR U(0x1A4) +#define RCC_R47CIDCFGR U(0x1A8) +#define RCC_R47SEMCR U(0x1AC) +#define RCC_R48CIDCFGR U(0x1B0) +#define RCC_R48SEMCR U(0x1B4) +#define RCC_R49CIDCFGR U(0x1B8) +#define RCC_R49SEMCR U(0x1BC) +#define RCC_R50CIDCFGR U(0x1C0) +#define RCC_R50SEMCR U(0x1C4) +#define RCC_R51CIDCFGR U(0x1C8) +#define RCC_R51SEMCR U(0x1CC) +#define RCC_R52CIDCFGR U(0x1D0) +#define RCC_R52SEMCR U(0x1D4) +#define RCC_R53CIDCFGR U(0x1D8) +#define RCC_R53SEMCR U(0x1DC) +#define RCC_R54CIDCFGR U(0x1E0) +#define RCC_R54SEMCR U(0x1E4) +#define RCC_R55CIDCFGR U(0x1E8) +#define RCC_R55SEMCR U(0x1EC) +#define RCC_R56CIDCFGR U(0x1F0) +#define RCC_R56SEMCR U(0x1F4) +#define RCC_R57CIDCFGR U(0x1F8) +#define RCC_R57SEMCR U(0x1FC) +#define RCC_R58CIDCFGR U(0x200) +#define RCC_R58SEMCR U(0x204) +#define RCC_R59CIDCFGR U(0x208) +#define RCC_R59SEMCR U(0x20C) +#define RCC_R60CIDCFGR U(0x210) +#define RCC_R60SEMCR U(0x214) +#define RCC_R61CIDCFGR U(0x218) +#define RCC_R61SEMCR U(0x21C) +#define RCC_R62CIDCFGR U(0x220) +#define RCC_R62SEMCR U(0x224) +#define RCC_R63CIDCFGR U(0x228) +#define RCC_R63SEMCR U(0x22C) +#define RCC_R64CIDCFGR U(0x230) +#define RCC_R64SEMCR U(0x234) +#define RCC_R65CIDCFGR U(0x238) +#define RCC_R65SEMCR U(0x23C) +#define RCC_R66CIDCFGR U(0x240) +#define RCC_R66SEMCR U(0x244) +#define RCC_R67CIDCFGR U(0x248) +#define RCC_R67SEMCR U(0x24C) +#define RCC_R68CIDCFGR U(0x250) +#define RCC_R68SEMCR U(0x254) +#define RCC_R69CIDCFGR U(0x258) +#define RCC_R69SEMCR U(0x25C) +#define RCC_R70CIDCFGR U(0x260) +#define RCC_R70SEMCR U(0x264) +#define RCC_R71CIDCFGR U(0x268) +#define RCC_R71SEMCR U(0x26C) +#define RCC_R72CIDCFGR U(0x270) +#define RCC_R72SEMCR U(0x274) +#define RCC_R73CIDCFGR U(0x278) +#define RCC_R73SEMCR U(0x27C) +#define RCC_R74CIDCFGR U(0x280) +#define RCC_R74SEMCR U(0x284) +#define RCC_R75CIDCFGR U(0x288) +#define RCC_R75SEMCR U(0x28C) +#define RCC_R76CIDCFGR U(0x290) +#define RCC_R76SEMCR U(0x294) +#define RCC_R77CIDCFGR U(0x298) +#define RCC_R77SEMCR U(0x29C) +#define RCC_R78CIDCFGR U(0x2A0) +#define RCC_R78SEMCR U(0x2A4) +#define RCC_R79CIDCFGR U(0x2A8) +#define RCC_R79SEMCR U(0x2AC) +#define RCC_R80CIDCFGR U(0x2B0) +#define RCC_R80SEMCR U(0x2B4) +#define RCC_R81CIDCFGR U(0x2B8) +#define RCC_R81SEMCR U(0x2BC) +#define RCC_R82CIDCFGR U(0x2C0) +#define RCC_R82SEMCR U(0x2C4) +#define RCC_R83CIDCFGR U(0x2C8) +#define RCC_R83SEMCR U(0x2CC) +#define RCC_R84CIDCFGR U(0x2D0) +#define RCC_R84SEMCR U(0x2D4) +#define RCC_R85CIDCFGR U(0x2D8) +#define RCC_R85SEMCR U(0x2DC) +#define RCC_R86CIDCFGR U(0x2E0) +#define RCC_R86SEMCR U(0x2E4) +#define RCC_R87CIDCFGR U(0x2E8) +#define RCC_R87SEMCR U(0x2EC) +#define RCC_R88CIDCFGR U(0x2F0) +#define RCC_R88SEMCR U(0x2F4) +#define RCC_R89CIDCFGR U(0x2F8) +#define RCC_R89SEMCR U(0x2FC) +#define RCC_R90CIDCFGR U(0x300) +#define RCC_R90SEMCR U(0x304) +#define RCC_R91CIDCFGR U(0x308) +#define RCC_R91SEMCR U(0x30C) +#define RCC_R92CIDCFGR U(0x310) +#define RCC_R92SEMCR U(0x314) +#define RCC_R93CIDCFGR U(0x318) +#define RCC_R93SEMCR U(0x31C) +#define RCC_R94CIDCFGR U(0x320) +#define RCC_R94SEMCR U(0x324) +#define RCC_R95CIDCFGR U(0x328) +#define RCC_R95SEMCR U(0x32C) +#define RCC_R96CIDCFGR U(0x330) +#define RCC_R96SEMCR U(0x334) +#define RCC_R97CIDCFGR U(0x338) +#define RCC_R97SEMCR U(0x33C) +#define RCC_R98CIDCFGR U(0x340) +#define RCC_R98SEMCR U(0x344) +#define RCC_R99CIDCFGR U(0x348) +#define RCC_R99SEMCR U(0x34C) +#define RCC_R100CIDCFGR U(0x350) +#define RCC_R100SEMCR U(0x354) +#define RCC_R101CIDCFGR U(0x358) +#define RCC_R101SEMCR U(0x35C) +#define RCC_R102CIDCFGR U(0x360) +#define RCC_R102SEMCR U(0x364) +#define RCC_R103CIDCFGR U(0x368) +#define RCC_R103SEMCR U(0x36C) +#define RCC_R104CIDCFGR U(0x370) +#define RCC_R104SEMCR U(0x374) +#define RCC_R105CIDCFGR U(0x378) +#define RCC_R105SEMCR U(0x37C) +#define RCC_R106CIDCFGR U(0x380) +#define RCC_R106SEMCR U(0x384) +#define RCC_R107CIDCFGR U(0x388) +#define RCC_R107SEMCR U(0x38C) +#define RCC_R108CIDCFGR U(0x390) +#define RCC_R108SEMCR U(0x394) +#define RCC_R109CIDCFGR U(0x398) +#define RCC_R109SEMCR U(0x39C) +#define RCC_R110CIDCFGR U(0x3A0) +#define RCC_R110SEMCR U(0x3A4) +#define RCC_R111CIDCFGR U(0x3A8) +#define RCC_R111SEMCR U(0x3AC) +#define RCC_R112CIDCFGR U(0x3B0) +#define RCC_R112SEMCR U(0x3B4) +#define RCC_R113CIDCFGR U(0x3B8) +#define RCC_R113SEMCR U(0x3BC) +#define RCC_GRSTCSETR U(0x400) +#define RCC_C1RSTCSETR U(0x404) +#define RCC_C1P1RSTCSETR U(0x408) +#define RCC_C2RSTCSETR U(0x40C) +#define RCC_HWRSTSCLRR U(0x410) +#define RCC_C1HWRSTSCLRR U(0x414) +#define RCC_C2HWRSTSCLRR U(0x418) +#define RCC_C1BOOTRSTSSETR U(0x41C) +#define RCC_C1BOOTRSTSCLRR U(0x420) +#define RCC_C2BOOTRSTSSETR U(0x424) +#define RCC_C2BOOTRSTSCLRR U(0x428) +#define RCC_C1SREQSETR U(0x42C) +#define RCC_C1SREQCLRR U(0x430) +#define RCC_CPUBOOTCR U(0x434) +#define RCC_STBYBOOTCR U(0x438) +#define RCC_LEGBOOTCR U(0x43C) +#define RCC_BDCR U(0x440) +#define RCC_D3DCR U(0x444) +#define RCC_D3DSR U(0x448) +#define RCC_RDCR U(0x44C) +#define RCC_C1MSRDCR U(0x450) +#define RCC_PWRLPDLYCR U(0x454) +#define RCC_C1CIESETR U(0x458) +#define RCC_C1CIFCLRR U(0x45C) +#define RCC_C2CIESETR U(0x460) +#define RCC_C2CIFCLRR U(0x464) +#define RCC_IWDGC1FZSETR U(0x468) +#define RCC_IWDGC1FZCLRR U(0x46C) +#define RCC_IWDGC1CFGSETR U(0x470) +#define RCC_IWDGC1CFGCLRR U(0x474) +#define RCC_IWDGC2FZSETR U(0x478) +#define RCC_IWDGC2FZCLRR U(0x47C) +#define RCC_IWDGC2CFGSETR U(0x480) +#define RCC_IWDGC2CFGCLRR U(0x484) +#define RCC_IWDGC3CFGSETR U(0x488) +#define RCC_IWDGC3CFGCLRR U(0x48C) +#define RCC_C3CFGR U(0x490) +#define RCC_MCO1CFGR U(0x494) +#define RCC_MCO2CFGR U(0x498) +#define RCC_OCENSETR U(0x49C) +#define RCC_OCENCLRR U(0x4A0) +#define RCC_OCRDYR U(0x4A4) +#define RCC_HSICFGR U(0x4A8) +#define RCC_CSICFGR U(0x4AC) +#define RCC_RTCDIVR U(0x4B0) +#define RCC_APB1DIVR U(0x4B4) +#define RCC_APB2DIVR U(0x4B8) +#define RCC_APB3DIVR U(0x4BC) +#define RCC_APB4DIVR U(0x4C0) +#define RCC_APBDBGDIVR U(0x4C4) +#define RCC_TIMG1PRER U(0x4C8) +#define RCC_TIMG2PRER U(0x4CC) +#define RCC_LSMCUDIVR U(0x4D0) +#define RCC_DDRCPCFGR U(0x4D4) +#define RCC_DDRCAPBCFGR U(0x4D8) +#define RCC_DDRPHYCAPBCFGR U(0x4DC) +#define RCC_DDRPHYCCFGR U(0x4E0) +#define RCC_DDRCFGR U(0x4E4) +#define RCC_DDRITFCFGR U(0x4E8) +#define RCC_SYSRAMCFGR U(0x4F0) +#define RCC_VDERAMCFGR U(0x4F4) +#define RCC_SRAM1CFGR U(0x4F8) +#define RCC_SRAM2CFGR U(0x4FC) +#define RCC_RETRAMCFGR U(0x500) +#define RCC_BKPSRAMCFGR U(0x504) +#define RCC_LPSRAM1CFGR U(0x508) +#define RCC_LPSRAM2CFGR U(0x50C) +#define RCC_LPSRAM3CFGR U(0x510) +#define RCC_OSPI1CFGR U(0x514) +#define RCC_OSPI2CFGR U(0x518) +#define RCC_FMCCFGR U(0x51C) +#define RCC_DBGCFGR U(0x520) +#define RCC_STM500CFGR U(0x524) +#define RCC_ETRCFGR U(0x528) +#define RCC_GPIOACFGR U(0x52C) +#define RCC_GPIOBCFGR U(0x530) +#define RCC_GPIOCCFGR U(0x534) +#define RCC_GPIODCFGR U(0x538) +#define RCC_GPIOECFGR U(0x53C) +#define RCC_GPIOFCFGR U(0x540) +#define RCC_GPIOGCFGR U(0x544) +#define RCC_GPIOHCFGR U(0x548) +#define RCC_GPIOICFGR U(0x54C) +#define RCC_GPIOJCFGR U(0x550) +#define RCC_GPIOKCFGR U(0x554) +#define RCC_GPIOZCFGR U(0x558) +#define RCC_HPDMA1CFGR U(0x55C) +#define RCC_HPDMA2CFGR U(0x560) +#define RCC_HPDMA3CFGR U(0x564) +#define RCC_LPDMACFGR U(0x568) +#define RCC_HSEMCFGR U(0x56C) +#define RCC_IPCC1CFGR U(0x570) +#define RCC_IPCC2CFGR U(0x574) +#define RCC_RTCCFGR U(0x578) +#define RCC_SYSCPU1CFGR U(0x580) +#define RCC_BSECCFGR U(0x584) +#define RCC_IS2MCFGR U(0x58C) +#define RCC_PLL2CFGR1 U(0x590) +#define RCC_PLL2CFGR2 U(0x594) +#define RCC_PLL2CFGR3 U(0x598) +#define RCC_PLL2CFGR4 U(0x59C) +#define RCC_PLL2CFGR5 U(0x5A0) +#define RCC_PLL2CFGR6 U(0x5A8) +#define RCC_PLL2CFGR7 U(0x5AC) +#define RCC_PLL3CFGR1 U(0x5B8) +#define RCC_PLL3CFGR2 U(0x5BC) +#define RCC_PLL3CFGR3 U(0x5C0) +#define RCC_PLL3CFGR4 U(0x5C4) +#define RCC_PLL3CFGR5 U(0x5C8) +#define RCC_PLL3CFGR6 U(0x5D0) +#define RCC_PLL3CFGR7 U(0x5D4) +#define RCC_HSIFMONCR U(0x5E0) +#define RCC_HSIFVALR U(0x5E4) +#define RCC_TIM1CFGR U(0x700) +#define RCC_TIM2CFGR U(0x704) +#define RCC_TIM3CFGR U(0x708) +#define RCC_TIM4CFGR U(0x70C) +#define RCC_TIM5CFGR U(0x710) +#define RCC_TIM6CFGR U(0x714) +#define RCC_TIM7CFGR U(0x718) +#define RCC_TIM8CFGR U(0x71C) +#define RCC_TIM10CFGR U(0x720) +#define RCC_TIM11CFGR U(0x724) +#define RCC_TIM12CFGR U(0x728) +#define RCC_TIM13CFGR U(0x72C) +#define RCC_TIM14CFGR U(0x730) +#define RCC_TIM15CFGR U(0x734) +#define RCC_TIM16CFGR U(0x738) +#define RCC_TIM17CFGR U(0x73C) +#define RCC_TIM20CFGR U(0x740) +#define RCC_LPTIM1CFGR U(0x744) +#define RCC_LPTIM2CFGR U(0x748) +#define RCC_LPTIM3CFGR U(0x74C) +#define RCC_LPTIM4CFGR U(0x750) +#define RCC_LPTIM5CFGR U(0x754) +#define RCC_SPI1CFGR U(0x758) +#define RCC_SPI2CFGR U(0x75C) +#define RCC_SPI3CFGR U(0x760) +#define RCC_SPI4CFGR U(0x764) +#define RCC_SPI5CFGR U(0x768) +#define RCC_SPI6CFGR U(0x76C) +#define RCC_SPI7CFGR U(0x770) +#define RCC_SPI8CFGR U(0x774) +#define RCC_SPDIFRXCFGR U(0x778) +#define RCC_USART1CFGR U(0x77C) +#define RCC_USART2CFGR U(0x780) +#define RCC_USART3CFGR U(0x784) +#define RCC_UART4CFGR U(0x788) +#define RCC_UART5CFGR U(0x78C) +#define RCC_USART6CFGR U(0x790) +#define RCC_UART7CFGR U(0x794) +#define RCC_UART8CFGR U(0x798) +#define RCC_UART9CFGR U(0x79C) +#define RCC_LPUART1CFGR U(0x7A0) +#define RCC_I2C1CFGR U(0x7A4) +#define RCC_I2C2CFGR U(0x7A8) +#define RCC_I2C3CFGR U(0x7AC) +#define RCC_I2C4CFGR U(0x7B0) +#define RCC_I2C5CFGR U(0x7B4) +#define RCC_I2C6CFGR U(0x7B8) +#define RCC_I2C7CFGR U(0x7BC) +#define RCC_I2C8CFGR U(0x7C0) +#define RCC_SAI1CFGR U(0x7C4) +#define RCC_SAI2CFGR U(0x7C8) +#define RCC_SAI3CFGR U(0x7CC) +#define RCC_SAI4CFGR U(0x7D0) +#define RCC_MDF1CFGR U(0x7D8) +#define RCC_ADF1CFGR U(0x7DC) +#define RCC_FDCANCFGR U(0x7E0) +#define RCC_HDPCFGR U(0x7E4) +#define RCC_ADC12CFGR U(0x7E8) +#define RCC_ADC3CFGR U(0x7EC) +#define RCC_ETH1CFGR U(0x7F0) +#define RCC_ETH2CFGR U(0x7F4) +#define RCC_USB2CFGR U(0x7FC) +#define RCC_USB2PHY1CFGR U(0x800) +#define RCC_USB2PHY2CFGR U(0x804) +#define RCC_USB3DRDCFGR U(0x808) +#define RCC_USB3PCIEPHYCFGR U(0x80C) +#define RCC_PCIECFGR U(0x810) +#define RCC_USBTCCFGR U(0x814) +#define RCC_ETHSWCFGR U(0x818) +#define RCC_ETHSWACMCFGR U(0x81C) +#define RCC_ETHSWACMMSGCFGR U(0x820) +#define RCC_STGENCFGR U(0x824) +#define RCC_SDMMC1CFGR U(0x830) +#define RCC_SDMMC2CFGR U(0x834) +#define RCC_SDMMC3CFGR U(0x838) +#define RCC_GPUCFGR U(0x83C) +#define RCC_LTDCCFGR U(0x840) +#define RCC_DSICFGR U(0x844) +#define RCC_LVDSCFGR U(0x850) +#define RCC_CSI2CFGR U(0x858) +#define RCC_DCMIPPCFGR U(0x85C) +#define RCC_CCICFGR U(0x860) +#define RCC_VDECCFGR U(0x864) +#define RCC_VENCCFGR U(0x868) +#define RCC_RNGCFGR U(0x870) +#define RCC_PKACFGR U(0x874) +#define RCC_SAESCFGR U(0x878) +#define RCC_HASHCFGR U(0x87C) +#define RCC_CRYP1CFGR U(0x880) +#define RCC_CRYP2CFGR U(0x884) +#define RCC_IWDG1CFGR U(0x888) +#define RCC_IWDG2CFGR U(0x88C) +#define RCC_IWDG3CFGR U(0x890) +#define RCC_IWDG4CFGR U(0x894) +#define RCC_IWDG5CFGR U(0x898) +#define RCC_WWDG1CFGR U(0x89C) +#define RCC_WWDG2CFGR U(0x8A0) +#define RCC_BUSPERFMCFGR U(0x8A4) +#define RCC_VREFCFGR U(0x8A8) +#define RCC_TMPSENSCFGR U(0x8AC) +#define RCC_CRCCFGR U(0x8B4) +#define RCC_SERCCFGR U(0x8B8) +#define RCC_OSPIIOMCFGR U(0x8BC) +#define RCC_GICV2MCFGR U(0x8C0) +#define RCC_I3C1CFGR U(0x8C8) +#define RCC_I3C2CFGR U(0x8CC) +#define RCC_I3C3CFGR U(0x8D0) +#define RCC_I3C4CFGR U(0x8D4) +#define RCC_MUXSELCFGR U(0x1000) +#define RCC_XBAR0CFGR U(0x1018) +#define RCC_XBAR1CFGR U(0x101C) +#define RCC_XBAR2CFGR U(0x1020) +#define RCC_XBAR3CFGR U(0x1024) +#define RCC_XBAR4CFGR U(0x1028) +#define RCC_XBAR5CFGR U(0x102C) +#define RCC_XBAR6CFGR U(0x1030) +#define RCC_XBAR7CFGR U(0x1034) +#define RCC_XBAR8CFGR U(0x1038) +#define RCC_XBAR9CFGR U(0x103C) +#define RCC_XBAR10CFGR U(0x1040) +#define RCC_XBAR11CFGR U(0x1044) +#define RCC_XBAR12CFGR U(0x1048) +#define RCC_XBAR13CFGR U(0x104C) +#define RCC_XBAR14CFGR U(0x1050) +#define RCC_XBAR15CFGR U(0x1054) +#define RCC_XBAR16CFGR U(0x1058) +#define RCC_XBAR17CFGR U(0x105C) +#define RCC_XBAR18CFGR U(0x1060) +#define RCC_XBAR19CFGR U(0x1064) +#define RCC_XBAR20CFGR U(0x1068) +#define RCC_XBAR21CFGR U(0x106C) +#define RCC_XBAR22CFGR U(0x1070) +#define RCC_XBAR23CFGR U(0x1074) +#define RCC_XBAR24CFGR U(0x1078) +#define RCC_XBAR25CFGR U(0x107C) +#define RCC_XBAR26CFGR U(0x1080) +#define RCC_XBAR27CFGR U(0x1084) +#define RCC_XBAR28CFGR U(0x1088) +#define RCC_XBAR29CFGR U(0x108C) +#define RCC_XBAR30CFGR U(0x1090) +#define RCC_XBAR31CFGR U(0x1094) +#define RCC_XBAR32CFGR U(0x1098) +#define RCC_XBAR33CFGR U(0x109C) +#define RCC_XBAR34CFGR U(0x10A0) +#define RCC_XBAR35CFGR U(0x10A4) +#define RCC_XBAR36CFGR U(0x10A8) +#define RCC_XBAR37CFGR U(0x10AC) +#define RCC_XBAR38CFGR U(0x10B0) +#define RCC_XBAR39CFGR U(0x10B4) +#define RCC_XBAR40CFGR U(0x10B8) +#define RCC_XBAR41CFGR U(0x10BC) +#define RCC_XBAR42CFGR U(0x10C0) +#define RCC_XBAR43CFGR U(0x10C4) +#define RCC_XBAR44CFGR U(0x10C8) +#define RCC_XBAR45CFGR U(0x10CC) +#define RCC_XBAR46CFGR U(0x10D0) +#define RCC_XBAR47CFGR U(0x10D4) +#define RCC_XBAR48CFGR U(0x10D8) +#define RCC_XBAR49CFGR U(0x10DC) +#define RCC_XBAR50CFGR U(0x10E0) +#define RCC_XBAR51CFGR U(0x10E4) +#define RCC_XBAR52CFGR U(0x10E8) +#define RCC_XBAR53CFGR U(0x10EC) +#define RCC_XBAR54CFGR U(0x10F0) +#define RCC_XBAR55CFGR U(0x10F4) +#define RCC_XBAR56CFGR U(0x10F8) +#define RCC_XBAR57CFGR U(0x10FC) +#define RCC_XBAR58CFGR U(0x1100) +#define RCC_XBAR59CFGR U(0x1104) +#define RCC_XBAR60CFGR U(0x1108) +#define RCC_XBAR61CFGR U(0x110C) +#define RCC_XBAR62CFGR U(0x1110) +#define RCC_XBAR63CFGR U(0x1114) +#define RCC_PREDIV0CFGR U(0x1118) +#define RCC_PREDIV1CFGR U(0x111C) +#define RCC_PREDIV2CFGR U(0x1120) +#define RCC_PREDIV3CFGR U(0x1124) +#define RCC_PREDIV4CFGR U(0x1128) +#define RCC_PREDIV5CFGR U(0x112C) +#define RCC_PREDIV6CFGR U(0x1130) +#define RCC_PREDIV7CFGR U(0x1134) +#define RCC_PREDIV8CFGR U(0x1138) +#define RCC_PREDIV9CFGR U(0x113C) +#define RCC_PREDIV10CFGR U(0x1140) +#define RCC_PREDIV11CFGR U(0x1144) +#define RCC_PREDIV12CFGR U(0x1148) +#define RCC_PREDIV13CFGR U(0x114C) +#define RCC_PREDIV14CFGR U(0x1150) +#define RCC_PREDIV15CFGR U(0x1154) +#define RCC_PREDIV16CFGR U(0x1158) +#define RCC_PREDIV17CFGR U(0x115C) +#define RCC_PREDIV18CFGR U(0x1160) +#define RCC_PREDIV19CFGR U(0x1164) +#define RCC_PREDIV20CFGR U(0x1168) +#define RCC_PREDIV21CFGR U(0x116C) +#define RCC_PREDIV22CFGR U(0x1170) +#define RCC_PREDIV23CFGR U(0x1174) +#define RCC_PREDIV24CFGR U(0x1178) +#define RCC_PREDIV25CFGR U(0x117C) +#define RCC_PREDIV26CFGR U(0x1180) +#define RCC_PREDIV27CFGR U(0x1184) +#define RCC_PREDIV28CFGR U(0x1188) +#define RCC_PREDIV29CFGR U(0x118C) +#define RCC_PREDIV30CFGR U(0x1190) +#define RCC_PREDIV31CFGR U(0x1194) +#define RCC_PREDIV32CFGR U(0x1198) +#define RCC_PREDIV33CFGR U(0x119C) +#define RCC_PREDIV34CFGR U(0x11A0) +#define RCC_PREDIV35CFGR U(0x11A4) +#define RCC_PREDIV36CFGR U(0x11A8) +#define RCC_PREDIV37CFGR U(0x11AC) +#define RCC_PREDIV38CFGR U(0x11B0) +#define RCC_PREDIV39CFGR U(0x11B4) +#define RCC_PREDIV40CFGR U(0x11B8) +#define RCC_PREDIV41CFGR U(0x11BC) +#define RCC_PREDIV42CFGR U(0x11C0) +#define RCC_PREDIV43CFGR U(0x11C4) +#define RCC_PREDIV44CFGR U(0x11C8) +#define RCC_PREDIV45CFGR U(0x11CC) +#define RCC_PREDIV46CFGR U(0x11D0) +#define RCC_PREDIV47CFGR U(0x11D4) +#define RCC_PREDIV48CFGR U(0x11D8) +#define RCC_PREDIV49CFGR U(0x11DC) +#define RCC_PREDIV50CFGR U(0x11E0) +#define RCC_PREDIV51CFGR U(0x11E4) +#define RCC_PREDIV52CFGR U(0x11E8) +#define RCC_PREDIV53CFGR U(0x11EC) +#define RCC_PREDIV54CFGR U(0x11F0) +#define RCC_PREDIV55CFGR U(0x11F4) +#define RCC_PREDIV56CFGR U(0x11F8) +#define RCC_PREDIV57CFGR U(0x11FC) +#define RCC_PREDIV58CFGR U(0x1200) +#define RCC_PREDIV59CFGR U(0x1204) +#define RCC_PREDIV60CFGR U(0x1208) +#define RCC_PREDIV61CFGR U(0x120C) +#define RCC_PREDIV62CFGR U(0x1210) +#define RCC_PREDIV63CFGR U(0x1214) +#define RCC_PREDIVSR1 U(0x1218) +#define RCC_PREDIVSR2 U(0x121C) +#define RCC_FINDIV0CFGR U(0x1224) +#define RCC_FINDIV1CFGR U(0x1228) +#define RCC_FINDIV2CFGR U(0x122C) +#define RCC_FINDIV3CFGR U(0x1230) +#define RCC_FINDIV4CFGR U(0x1234) +#define RCC_FINDIV5CFGR U(0x1238) +#define RCC_FINDIV6CFGR U(0x123C) +#define RCC_FINDIV7CFGR U(0x1240) +#define RCC_FINDIV8CFGR U(0x1244) +#define RCC_FINDIV9CFGR U(0x1248) +#define RCC_FINDIV10CFGR U(0x124C) +#define RCC_FINDIV11CFGR U(0x1250) +#define RCC_FINDIV12CFGR U(0x1254) +#define RCC_FINDIV13CFGR U(0x1258) +#define RCC_FINDIV14CFGR U(0x125C) +#define RCC_FINDIV15CFGR U(0x1260) +#define RCC_FINDIV16CFGR U(0x1264) +#define RCC_FINDIV17CFGR U(0x1268) +#define RCC_FINDIV18CFGR U(0x126C) +#define RCC_FINDIV19CFGR U(0x1270) +#define RCC_FINDIV20CFGR U(0x1274) +#define RCC_FINDIV21CFGR U(0x1278) +#define RCC_FINDIV22CFGR U(0x127C) +#define RCC_FINDIV23CFGR U(0x1280) +#define RCC_FINDIV24CFGR U(0x1284) +#define RCC_FINDIV25CFGR U(0x1288) +#define RCC_FINDIV26CFGR U(0x128C) +#define RCC_FINDIV27CFGR U(0x1290) +#define RCC_FINDIV28CFGR U(0x1294) +#define RCC_FINDIV29CFGR U(0x1298) +#define RCC_FINDIV30CFGR U(0x129C) +#define RCC_FINDIV31CFGR U(0x12A0) +#define RCC_FINDIV32CFGR U(0x12A4) +#define RCC_FINDIV33CFGR U(0x12A8) +#define RCC_FINDIV34CFGR U(0x12AC) +#define RCC_FINDIV35CFGR U(0x12B0) +#define RCC_FINDIV36CFGR U(0x12B4) +#define RCC_FINDIV37CFGR U(0x12B8) +#define RCC_FINDIV38CFGR U(0x12BC) +#define RCC_FINDIV39CFGR U(0x12C0) +#define RCC_FINDIV40CFGR U(0x12C4) +#define RCC_FINDIV41CFGR U(0x12C8) +#define RCC_FINDIV42CFGR U(0x12CC) +#define RCC_FINDIV43CFGR U(0x12D0) +#define RCC_FINDIV44CFGR U(0x12D4) +#define RCC_FINDIV45CFGR U(0x12D8) +#define RCC_FINDIV46CFGR U(0x12DC) +#define RCC_FINDIV47CFGR U(0x12E0) +#define RCC_FINDIV48CFGR U(0x12E4) +#define RCC_FINDIV49CFGR U(0x12E8) +#define RCC_FINDIV50CFGR U(0x12EC) +#define RCC_FINDIV51CFGR U(0x12F0) +#define RCC_FINDIV52CFGR U(0x12F4) +#define RCC_FINDIV53CFGR U(0x12F8) +#define RCC_FINDIV54CFGR U(0x12FC) +#define RCC_FINDIV55CFGR U(0x1300) +#define RCC_FINDIV56CFGR U(0x1304) +#define RCC_FINDIV57CFGR U(0x1308) +#define RCC_FINDIV58CFGR U(0x130C) +#define RCC_FINDIV59CFGR U(0x1310) +#define RCC_FINDIV60CFGR U(0x1314) +#define RCC_FINDIV61CFGR U(0x1318) +#define RCC_FINDIV62CFGR U(0x131C) +#define RCC_FINDIV63CFGR U(0x1320) +#define RCC_FINDIVSR1 U(0x1324) +#define RCC_FINDIVSR2 U(0x1328) +#define RCC_FCALCOBS0CFGR U(0x1340) +#define RCC_FCALCOBS1CFGR U(0x1344) +#define RCC_FCALCREFCFGR U(0x1348) +#define RCC_FCALCCR1 U(0x134C) +#define RCC_FCALCCR2 U(0x1354) +#define RCC_FCALCSR U(0x1358) +#define RCC_PLL4CFGR1 U(0x1360) +#define RCC_PLL4CFGR2 U(0x1364) +#define RCC_PLL4CFGR3 U(0x1368) +#define RCC_PLL4CFGR4 U(0x136C) +#define RCC_PLL4CFGR5 U(0x1370) +#define RCC_PLL4CFGR6 U(0x1378) +#define RCC_PLL4CFGR7 U(0x137C) +#define RCC_PLL5CFGR1 U(0x1388) +#define RCC_PLL5CFGR2 U(0x138C) +#define RCC_PLL5CFGR3 U(0x1390) +#define RCC_PLL5CFGR4 U(0x1394) +#define RCC_PLL5CFGR5 U(0x1398) +#define RCC_PLL5CFGR6 U(0x13A0) +#define RCC_PLL5CFGR7 U(0x13A4) +#define RCC_PLL6CFGR1 U(0x13B0) +#define RCC_PLL6CFGR2 U(0x13B4) +#define RCC_PLL6CFGR3 U(0x13B8) +#define RCC_PLL6CFGR4 U(0x13BC) +#define RCC_PLL6CFGR5 U(0x13C0) +#define RCC_PLL6CFGR6 U(0x13C8) +#define RCC_PLL6CFGR7 U(0x13CC) +#define RCC_PLL7CFGR1 U(0x13D8) +#define RCC_PLL7CFGR2 U(0x13DC) +#define RCC_PLL7CFGR3 U(0x13E0) +#define RCC_PLL7CFGR4 U(0x13E4) +#define RCC_PLL7CFGR5 U(0x13E8) +#define RCC_PLL7CFGR6 U(0x13F0) +#define RCC_PLL7CFGR7 U(0x13F4) +#define RCC_PLL8CFGR1 U(0x1400) +#define RCC_PLL8CFGR2 U(0x1404) +#define RCC_PLL8CFGR3 U(0x1408) +#define RCC_PLL8CFGR4 U(0x140C) +#define RCC_PLL8CFGR5 U(0x1410) +#define RCC_PLL8CFGR6 U(0x1418) +#define RCC_PLL8CFGR7 U(0x141C) +#define RCC_VERR U(0xFFF4) +#define RCC_IDR U(0xFFF8) +#define RCC_SIDR U(0xFFFC) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* RCC_SECCFGR3 register fields */ +#define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0) +#define RCC_SECCFGR3_SEC_SHIFT 0 + +/* RCC_PRIVCFGR3 register fields */ +#define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0) +#define RCC_PRIVCFGR3_PRIV_SHIFT 0 + +/* RCC_RCFGLOCKR3 register fields */ +#define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0) +#define RCC_RCFGLOCKR3_RLOCK_SHIFT 0 + +/* RCC_R0CIDCFGR register fields */ +#define RCC_R0CIDCFGR_CFEN BIT(0) +#define RCC_R0CIDCFGR_SEM_EN BIT(1) +#define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R0CIDCFGR_SCID_SHIFT 4 +#define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R0CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R0SEMCR register fields */ +#define RCC_R0SEMCR_SEM_MUTEX BIT(0) +#define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R0SEMCR_SEMCID_SHIFT 4 + +/* RCC_R1CIDCFGR register fields */ +#define RCC_R1CIDCFGR_CFEN BIT(0) +#define RCC_R1CIDCFGR_SEM_EN BIT(1) +#define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R1CIDCFGR_SCID_SHIFT 4 +#define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R1CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R1SEMCR register fields */ +#define RCC_R1SEMCR_SEM_MUTEX BIT(0) +#define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R1SEMCR_SEMCID_SHIFT 4 + +/* RCC_R2CIDCFGR register fields */ +#define RCC_R2CIDCFGR_CFEN BIT(0) +#define RCC_R2CIDCFGR_SEM_EN BIT(1) +#define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R2CIDCFGR_SCID_SHIFT 4 +#define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R2CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R2SEMCR register fields */ +#define RCC_R2SEMCR_SEM_MUTEX BIT(0) +#define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R2SEMCR_SEMCID_SHIFT 4 + +/* RCC_R3CIDCFGR register fields */ +#define RCC_R3CIDCFGR_CFEN BIT(0) +#define RCC_R3CIDCFGR_SEM_EN BIT(1) +#define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R3CIDCFGR_SCID_SHIFT 4 +#define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R3CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R3SEMCR register fields */ +#define RCC_R3SEMCR_SEM_MUTEX BIT(0) +#define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R3SEMCR_SEMCID_SHIFT 4 + +/* RCC_R4CIDCFGR register fields */ +#define RCC_R4CIDCFGR_CFEN BIT(0) +#define RCC_R4CIDCFGR_SEM_EN BIT(1) +#define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R4CIDCFGR_SCID_SHIFT 4 +#define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R4CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R4SEMCR register fields */ +#define RCC_R4SEMCR_SEM_MUTEX BIT(0) +#define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R4SEMCR_SEMCID_SHIFT 4 + +/* RCC_R5CIDCFGR register fields */ +#define RCC_R5CIDCFGR_CFEN BIT(0) +#define RCC_R5CIDCFGR_SEM_EN BIT(1) +#define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R5CIDCFGR_SCID_SHIFT 4 +#define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R5CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R5SEMCR register fields */ +#define RCC_R5SEMCR_SEM_MUTEX BIT(0) +#define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R5SEMCR_SEMCID_SHIFT 4 + +/* RCC_R6CIDCFGR register fields */ +#define RCC_R6CIDCFGR_CFEN BIT(0) +#define RCC_R6CIDCFGR_SEM_EN BIT(1) +#define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R6CIDCFGR_SCID_SHIFT 4 +#define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R6CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R6SEMCR register fields */ +#define RCC_R6SEMCR_SEM_MUTEX BIT(0) +#define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R6SEMCR_SEMCID_SHIFT 4 + +/* RCC_R7CIDCFGR register fields */ +#define RCC_R7CIDCFGR_CFEN BIT(0) +#define RCC_R7CIDCFGR_SEM_EN BIT(1) +#define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R7CIDCFGR_SCID_SHIFT 4 +#define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R7CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R7SEMCR register fields */ +#define RCC_R7SEMCR_SEM_MUTEX BIT(0) +#define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R7SEMCR_SEMCID_SHIFT 4 + +/* RCC_R8CIDCFGR register fields */ +#define RCC_R8CIDCFGR_CFEN BIT(0) +#define RCC_R8CIDCFGR_SEM_EN BIT(1) +#define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R8CIDCFGR_SCID_SHIFT 4 +#define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R8CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R8SEMCR register fields */ +#define RCC_R8SEMCR_SEM_MUTEX BIT(0) +#define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R8SEMCR_SEMCID_SHIFT 4 + +/* RCC_R9CIDCFGR register fields */ +#define RCC_R9CIDCFGR_CFEN BIT(0) +#define RCC_R9CIDCFGR_SEM_EN BIT(1) +#define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R9CIDCFGR_SCID_SHIFT 4 +#define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R9CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R9SEMCR register fields */ +#define RCC_R9SEMCR_SEM_MUTEX BIT(0) +#define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R9SEMCR_SEMCID_SHIFT 4 + +/* RCC_R10CIDCFGR register fields */ +#define RCC_R10CIDCFGR_CFEN BIT(0) +#define RCC_R10CIDCFGR_SEM_EN BIT(1) +#define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R10CIDCFGR_SCID_SHIFT 4 +#define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R10CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R10SEMCR register fields */ +#define RCC_R10SEMCR_SEM_MUTEX BIT(0) +#define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R10SEMCR_SEMCID_SHIFT 4 + +/* RCC_R11CIDCFGR register fields */ +#define RCC_R11CIDCFGR_CFEN BIT(0) +#define RCC_R11CIDCFGR_SEM_EN BIT(1) +#define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R11CIDCFGR_SCID_SHIFT 4 +#define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R11CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R11SEMCR register fields */ +#define RCC_R11SEMCR_SEM_MUTEX BIT(0) +#define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R11SEMCR_SEMCID_SHIFT 4 + +/* RCC_R12CIDCFGR register fields */ +#define RCC_R12CIDCFGR_CFEN BIT(0) +#define RCC_R12CIDCFGR_SEM_EN BIT(1) +#define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R12CIDCFGR_SCID_SHIFT 4 +#define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R12CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R12SEMCR register fields */ +#define RCC_R12SEMCR_SEM_MUTEX BIT(0) +#define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R12SEMCR_SEMCID_SHIFT 4 + +/* RCC_R13CIDCFGR register fields */ +#define RCC_R13CIDCFGR_CFEN BIT(0) +#define RCC_R13CIDCFGR_SEM_EN BIT(1) +#define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R13CIDCFGR_SCID_SHIFT 4 +#define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R13CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R13SEMCR register fields */ +#define RCC_R13SEMCR_SEM_MUTEX BIT(0) +#define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R13SEMCR_SEMCID_SHIFT 4 + +/* RCC_R14CIDCFGR register fields */ +#define RCC_R14CIDCFGR_CFEN BIT(0) +#define RCC_R14CIDCFGR_SEM_EN BIT(1) +#define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R14CIDCFGR_SCID_SHIFT 4 +#define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R14CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R14SEMCR register fields */ +#define RCC_R14SEMCR_SEM_MUTEX BIT(0) +#define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R14SEMCR_SEMCID_SHIFT 4 + +/* RCC_R15CIDCFGR register fields */ +#define RCC_R15CIDCFGR_CFEN BIT(0) +#define RCC_R15CIDCFGR_SEM_EN BIT(1) +#define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R15CIDCFGR_SCID_SHIFT 4 +#define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R15CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R15SEMCR register fields */ +#define RCC_R15SEMCR_SEM_MUTEX BIT(0) +#define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R15SEMCR_SEMCID_SHIFT 4 + +/* RCC_R16CIDCFGR register fields */ +#define RCC_R16CIDCFGR_CFEN BIT(0) +#define RCC_R16CIDCFGR_SEM_EN BIT(1) +#define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R16CIDCFGR_SCID_SHIFT 4 +#define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R16CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R16SEMCR register fields */ +#define RCC_R16SEMCR_SEM_MUTEX BIT(0) +#define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R16SEMCR_SEMCID_SHIFT 4 + +/* RCC_R17CIDCFGR register fields */ +#define RCC_R17CIDCFGR_CFEN BIT(0) +#define RCC_R17CIDCFGR_SEM_EN BIT(1) +#define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R17CIDCFGR_SCID_SHIFT 4 +#define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R17CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R17SEMCR register fields */ +#define RCC_R17SEMCR_SEM_MUTEX BIT(0) +#define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R17SEMCR_SEMCID_SHIFT 4 + +/* RCC_R18CIDCFGR register fields */ +#define RCC_R18CIDCFGR_CFEN BIT(0) +#define RCC_R18CIDCFGR_SEM_EN BIT(1) +#define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R18CIDCFGR_SCID_SHIFT 4 +#define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R18CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R18SEMCR register fields */ +#define RCC_R18SEMCR_SEM_MUTEX BIT(0) +#define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R18SEMCR_SEMCID_SHIFT 4 + +/* RCC_R19CIDCFGR register fields */ +#define RCC_R19CIDCFGR_CFEN BIT(0) +#define RCC_R19CIDCFGR_SEM_EN BIT(1) +#define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R19CIDCFGR_SCID_SHIFT 4 +#define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R19CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R19SEMCR register fields */ +#define RCC_R19SEMCR_SEM_MUTEX BIT(0) +#define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R19SEMCR_SEMCID_SHIFT 4 + +/* RCC_R20CIDCFGR register fields */ +#define RCC_R20CIDCFGR_CFEN BIT(0) +#define RCC_R20CIDCFGR_SEM_EN BIT(1) +#define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R20CIDCFGR_SCID_SHIFT 4 +#define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R20CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R20SEMCR register fields */ +#define RCC_R20SEMCR_SEM_MUTEX BIT(0) +#define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R20SEMCR_SEMCID_SHIFT 4 + +/* RCC_R21CIDCFGR register fields */ +#define RCC_R21CIDCFGR_CFEN BIT(0) +#define RCC_R21CIDCFGR_SEM_EN BIT(1) +#define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R21CIDCFGR_SCID_SHIFT 4 +#define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R21CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R21SEMCR register fields */ +#define RCC_R21SEMCR_SEM_MUTEX BIT(0) +#define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R21SEMCR_SEMCID_SHIFT 4 + +/* RCC_R22CIDCFGR register fields */ +#define RCC_R22CIDCFGR_CFEN BIT(0) +#define RCC_R22CIDCFGR_SEM_EN BIT(1) +#define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R22CIDCFGR_SCID_SHIFT 4 +#define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R22CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R22SEMCR register fields */ +#define RCC_R22SEMCR_SEM_MUTEX BIT(0) +#define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R22SEMCR_SEMCID_SHIFT 4 + +/* RCC_R23CIDCFGR register fields */ +#define RCC_R23CIDCFGR_CFEN BIT(0) +#define RCC_R23CIDCFGR_SEM_EN BIT(1) +#define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R23CIDCFGR_SCID_SHIFT 4 +#define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R23CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R23SEMCR register fields */ +#define RCC_R23SEMCR_SEM_MUTEX BIT(0) +#define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R23SEMCR_SEMCID_SHIFT 4 + +/* RCC_R24CIDCFGR register fields */ +#define RCC_R24CIDCFGR_CFEN BIT(0) +#define RCC_R24CIDCFGR_SEM_EN BIT(1) +#define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R24CIDCFGR_SCID_SHIFT 4 +#define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R24CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R24SEMCR register fields */ +#define RCC_R24SEMCR_SEM_MUTEX BIT(0) +#define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R24SEMCR_SEMCID_SHIFT 4 + +/* RCC_R25CIDCFGR register fields */ +#define RCC_R25CIDCFGR_CFEN BIT(0) +#define RCC_R25CIDCFGR_SEM_EN BIT(1) +#define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R25CIDCFGR_SCID_SHIFT 4 +#define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R25CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R25SEMCR register fields */ +#define RCC_R25SEMCR_SEM_MUTEX BIT(0) +#define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R25SEMCR_SEMCID_SHIFT 4 + +/* RCC_R26CIDCFGR register fields */ +#define RCC_R26CIDCFGR_CFEN BIT(0) +#define RCC_R26CIDCFGR_SEM_EN BIT(1) +#define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R26CIDCFGR_SCID_SHIFT 4 +#define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R26CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R26SEMCR register fields */ +#define RCC_R26SEMCR_SEM_MUTEX BIT(0) +#define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R26SEMCR_SEMCID_SHIFT 4 + +/* RCC_R27CIDCFGR register fields */ +#define RCC_R27CIDCFGR_CFEN BIT(0) +#define RCC_R27CIDCFGR_SEM_EN BIT(1) +#define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R27CIDCFGR_SCID_SHIFT 4 +#define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R27CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R27SEMCR register fields */ +#define RCC_R27SEMCR_SEM_MUTEX BIT(0) +#define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R27SEMCR_SEMCID_SHIFT 4 + +/* RCC_R28CIDCFGR register fields */ +#define RCC_R28CIDCFGR_CFEN BIT(0) +#define RCC_R28CIDCFGR_SEM_EN BIT(1) +#define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R28CIDCFGR_SCID_SHIFT 4 +#define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R28CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R28SEMCR register fields */ +#define RCC_R28SEMCR_SEM_MUTEX BIT(0) +#define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R28SEMCR_SEMCID_SHIFT 4 + +/* RCC_R29CIDCFGR register fields */ +#define RCC_R29CIDCFGR_CFEN BIT(0) +#define RCC_R29CIDCFGR_SEM_EN BIT(1) +#define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R29CIDCFGR_SCID_SHIFT 4 +#define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R29CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R29SEMCR register fields */ +#define RCC_R29SEMCR_SEM_MUTEX BIT(0) +#define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R29SEMCR_SEMCID_SHIFT 4 + +/* RCC_R30CIDCFGR register fields */ +#define RCC_R30CIDCFGR_CFEN BIT(0) +#define RCC_R30CIDCFGR_SEM_EN BIT(1) +#define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R30CIDCFGR_SCID_SHIFT 4 +#define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R30CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R30SEMCR register fields */ +#define RCC_R30SEMCR_SEM_MUTEX BIT(0) +#define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R30SEMCR_SEMCID_SHIFT 4 + +/* RCC_R31CIDCFGR register fields */ +#define RCC_R31CIDCFGR_CFEN BIT(0) +#define RCC_R31CIDCFGR_SEM_EN BIT(1) +#define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R31CIDCFGR_SCID_SHIFT 4 +#define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R31CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R31SEMCR register fields */ +#define RCC_R31SEMCR_SEM_MUTEX BIT(0) +#define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R31SEMCR_SEMCID_SHIFT 4 + +/* RCC_R32CIDCFGR register fields */ +#define RCC_R32CIDCFGR_CFEN BIT(0) +#define RCC_R32CIDCFGR_SEM_EN BIT(1) +#define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R32CIDCFGR_SCID_SHIFT 4 +#define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R32CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R32SEMCR register fields */ +#define RCC_R32SEMCR_SEM_MUTEX BIT(0) +#define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R32SEMCR_SEMCID_SHIFT 4 + +/* RCC_R33CIDCFGR register fields */ +#define RCC_R33CIDCFGR_CFEN BIT(0) +#define RCC_R33CIDCFGR_SEM_EN BIT(1) +#define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R33CIDCFGR_SCID_SHIFT 4 +#define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R33CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R33SEMCR register fields */ +#define RCC_R33SEMCR_SEM_MUTEX BIT(0) +#define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R33SEMCR_SEMCID_SHIFT 4 + +/* RCC_R34CIDCFGR register fields */ +#define RCC_R34CIDCFGR_CFEN BIT(0) +#define RCC_R34CIDCFGR_SEM_EN BIT(1) +#define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R34CIDCFGR_SCID_SHIFT 4 +#define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R34CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R34SEMCR register fields */ +#define RCC_R34SEMCR_SEM_MUTEX BIT(0) +#define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R34SEMCR_SEMCID_SHIFT 4 + +/* RCC_R35CIDCFGR register fields */ +#define RCC_R35CIDCFGR_CFEN BIT(0) +#define RCC_R35CIDCFGR_SEM_EN BIT(1) +#define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R35CIDCFGR_SCID_SHIFT 4 +#define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R35CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R35SEMCR register fields */ +#define RCC_R35SEMCR_SEM_MUTEX BIT(0) +#define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R35SEMCR_SEMCID_SHIFT 4 + +/* RCC_R36CIDCFGR register fields */ +#define RCC_R36CIDCFGR_CFEN BIT(0) +#define RCC_R36CIDCFGR_SEM_EN BIT(1) +#define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R36CIDCFGR_SCID_SHIFT 4 +#define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R36CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R36SEMCR register fields */ +#define RCC_R36SEMCR_SEM_MUTEX BIT(0) +#define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R36SEMCR_SEMCID_SHIFT 4 + +/* RCC_R37CIDCFGR register fields */ +#define RCC_R37CIDCFGR_CFEN BIT(0) +#define RCC_R37CIDCFGR_SEM_EN BIT(1) +#define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R37CIDCFGR_SCID_SHIFT 4 +#define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R37CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R37SEMCR register fields */ +#define RCC_R37SEMCR_SEM_MUTEX BIT(0) +#define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R37SEMCR_SEMCID_SHIFT 4 + +/* RCC_R38CIDCFGR register fields */ +#define RCC_R38CIDCFGR_CFEN BIT(0) +#define RCC_R38CIDCFGR_SEM_EN BIT(1) +#define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R38CIDCFGR_SCID_SHIFT 4 +#define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R38CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R38SEMCR register fields */ +#define RCC_R38SEMCR_SEM_MUTEX BIT(0) +#define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R38SEMCR_SEMCID_SHIFT 4 + +/* RCC_R39CIDCFGR register fields */ +#define RCC_R39CIDCFGR_CFEN BIT(0) +#define RCC_R39CIDCFGR_SEM_EN BIT(1) +#define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R39CIDCFGR_SCID_SHIFT 4 +#define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R39CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R39SEMCR register fields */ +#define RCC_R39SEMCR_SEM_MUTEX BIT(0) +#define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R39SEMCR_SEMCID_SHIFT 4 + +/* RCC_R40CIDCFGR register fields */ +#define RCC_R40CIDCFGR_CFEN BIT(0) +#define RCC_R40CIDCFGR_SEM_EN BIT(1) +#define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R40CIDCFGR_SCID_SHIFT 4 +#define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R40CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R40SEMCR register fields */ +#define RCC_R40SEMCR_SEM_MUTEX BIT(0) +#define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R40SEMCR_SEMCID_SHIFT 4 + +/* RCC_R41CIDCFGR register fields */ +#define RCC_R41CIDCFGR_CFEN BIT(0) +#define RCC_R41CIDCFGR_SEM_EN BIT(1) +#define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R41CIDCFGR_SCID_SHIFT 4 +#define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R41CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R41SEMCR register fields */ +#define RCC_R41SEMCR_SEM_MUTEX BIT(0) +#define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R41SEMCR_SEMCID_SHIFT 4 + +/* RCC_R42CIDCFGR register fields */ +#define RCC_R42CIDCFGR_CFEN BIT(0) +#define RCC_R42CIDCFGR_SEM_EN BIT(1) +#define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R42CIDCFGR_SCID_SHIFT 4 +#define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R42CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R42SEMCR register fields */ +#define RCC_R42SEMCR_SEM_MUTEX BIT(0) +#define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R42SEMCR_SEMCID_SHIFT 4 + +/* RCC_R43CIDCFGR register fields */ +#define RCC_R43CIDCFGR_CFEN BIT(0) +#define RCC_R43CIDCFGR_SEM_EN BIT(1) +#define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R43CIDCFGR_SCID_SHIFT 4 +#define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R43CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R43SEMCR register fields */ +#define RCC_R43SEMCR_SEM_MUTEX BIT(0) +#define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R43SEMCR_SEMCID_SHIFT 4 + +/* RCC_R44CIDCFGR register fields */ +#define RCC_R44CIDCFGR_CFEN BIT(0) +#define RCC_R44CIDCFGR_SEM_EN BIT(1) +#define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R44CIDCFGR_SCID_SHIFT 4 +#define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R44CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R44SEMCR register fields */ +#define RCC_R44SEMCR_SEM_MUTEX BIT(0) +#define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R44SEMCR_SEMCID_SHIFT 4 + +/* RCC_R45CIDCFGR register fields */ +#define RCC_R45CIDCFGR_CFEN BIT(0) +#define RCC_R45CIDCFGR_SEM_EN BIT(1) +#define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R45CIDCFGR_SCID_SHIFT 4 +#define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R45CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R45SEMCR register fields */ +#define RCC_R45SEMCR_SEM_MUTEX BIT(0) +#define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R45SEMCR_SEMCID_SHIFT 4 + +/* RCC_R46CIDCFGR register fields */ +#define RCC_R46CIDCFGR_CFEN BIT(0) +#define RCC_R46CIDCFGR_SEM_EN BIT(1) +#define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R46CIDCFGR_SCID_SHIFT 4 +#define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R46CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R46SEMCR register fields */ +#define RCC_R46SEMCR_SEM_MUTEX BIT(0) +#define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R46SEMCR_SEMCID_SHIFT 4 + +/* RCC_R47CIDCFGR register fields */ +#define RCC_R47CIDCFGR_CFEN BIT(0) +#define RCC_R47CIDCFGR_SEM_EN BIT(1) +#define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R47CIDCFGR_SCID_SHIFT 4 +#define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R47CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R47SEMCR register fields */ +#define RCC_R47SEMCR_SEM_MUTEX BIT(0) +#define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R47SEMCR_SEMCID_SHIFT 4 + +/* RCC_R48CIDCFGR register fields */ +#define RCC_R48CIDCFGR_CFEN BIT(0) +#define RCC_R48CIDCFGR_SEM_EN BIT(1) +#define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R48CIDCFGR_SCID_SHIFT 4 +#define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R48CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R48SEMCR register fields */ +#define RCC_R48SEMCR_SEM_MUTEX BIT(0) +#define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R48SEMCR_SEMCID_SHIFT 4 + +/* RCC_R49CIDCFGR register fields */ +#define RCC_R49CIDCFGR_CFEN BIT(0) +#define RCC_R49CIDCFGR_SEM_EN BIT(1) +#define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R49CIDCFGR_SCID_SHIFT 4 +#define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R49CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R49SEMCR register fields */ +#define RCC_R49SEMCR_SEM_MUTEX BIT(0) +#define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R49SEMCR_SEMCID_SHIFT 4 + +/* RCC_R50CIDCFGR register fields */ +#define RCC_R50CIDCFGR_CFEN BIT(0) +#define RCC_R50CIDCFGR_SEM_EN BIT(1) +#define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R50CIDCFGR_SCID_SHIFT 4 +#define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R50CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R50SEMCR register fields */ +#define RCC_R50SEMCR_SEM_MUTEX BIT(0) +#define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R50SEMCR_SEMCID_SHIFT 4 + +/* RCC_R51CIDCFGR register fields */ +#define RCC_R51CIDCFGR_CFEN BIT(0) +#define RCC_R51CIDCFGR_SEM_EN BIT(1) +#define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R51CIDCFGR_SCID_SHIFT 4 +#define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R51CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R51SEMCR register fields */ +#define RCC_R51SEMCR_SEM_MUTEX BIT(0) +#define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R51SEMCR_SEMCID_SHIFT 4 + +/* RCC_R52CIDCFGR register fields */ +#define RCC_R52CIDCFGR_CFEN BIT(0) +#define RCC_R52CIDCFGR_SEM_EN BIT(1) +#define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R52CIDCFGR_SCID_SHIFT 4 +#define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R52CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R52SEMCR register fields */ +#define RCC_R52SEMCR_SEM_MUTEX BIT(0) +#define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R52SEMCR_SEMCID_SHIFT 4 + +/* RCC_R53CIDCFGR register fields */ +#define RCC_R53CIDCFGR_CFEN BIT(0) +#define RCC_R53CIDCFGR_SEM_EN BIT(1) +#define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R53CIDCFGR_SCID_SHIFT 4 +#define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R53CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R53SEMCR register fields */ +#define RCC_R53SEMCR_SEM_MUTEX BIT(0) +#define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R53SEMCR_SEMCID_SHIFT 4 + +/* RCC_R54CIDCFGR register fields */ +#define RCC_R54CIDCFGR_CFEN BIT(0) +#define RCC_R54CIDCFGR_SEM_EN BIT(1) +#define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R54CIDCFGR_SCID_SHIFT 4 +#define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R54CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R54SEMCR register fields */ +#define RCC_R54SEMCR_SEM_MUTEX BIT(0) +#define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R54SEMCR_SEMCID_SHIFT 4 + +/* RCC_R55CIDCFGR register fields */ +#define RCC_R55CIDCFGR_CFEN BIT(0) +#define RCC_R55CIDCFGR_SEM_EN BIT(1) +#define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R55CIDCFGR_SCID_SHIFT 4 +#define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R55CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R55SEMCR register fields */ +#define RCC_R55SEMCR_SEM_MUTEX BIT(0) +#define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R55SEMCR_SEMCID_SHIFT 4 + +/* RCC_R56CIDCFGR register fields */ +#define RCC_R56CIDCFGR_CFEN BIT(0) +#define RCC_R56CIDCFGR_SEM_EN BIT(1) +#define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R56CIDCFGR_SCID_SHIFT 4 +#define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R56CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R56SEMCR register fields */ +#define RCC_R56SEMCR_SEM_MUTEX BIT(0) +#define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R56SEMCR_SEMCID_SHIFT 4 + +/* RCC_R57CIDCFGR register fields */ +#define RCC_R57CIDCFGR_CFEN BIT(0) +#define RCC_R57CIDCFGR_SEM_EN BIT(1) +#define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R57CIDCFGR_SCID_SHIFT 4 +#define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R57CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R57SEMCR register fields */ +#define RCC_R57SEMCR_SEM_MUTEX BIT(0) +#define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R57SEMCR_SEMCID_SHIFT 4 + +/* RCC_R58CIDCFGR register fields */ +#define RCC_R58CIDCFGR_CFEN BIT(0) +#define RCC_R58CIDCFGR_SEM_EN BIT(1) +#define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R58CIDCFGR_SCID_SHIFT 4 +#define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R58CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R58SEMCR register fields */ +#define RCC_R58SEMCR_SEM_MUTEX BIT(0) +#define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R58SEMCR_SEMCID_SHIFT 4 + +/* RCC_R59CIDCFGR register fields */ +#define RCC_R59CIDCFGR_CFEN BIT(0) +#define RCC_R59CIDCFGR_SEM_EN BIT(1) +#define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R59CIDCFGR_SCID_SHIFT 4 +#define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R59CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R59SEMCR register fields */ +#define RCC_R59SEMCR_SEM_MUTEX BIT(0) +#define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R59SEMCR_SEMCID_SHIFT 4 + +/* RCC_R60CIDCFGR register fields */ +#define RCC_R60CIDCFGR_CFEN BIT(0) +#define RCC_R60CIDCFGR_SEM_EN BIT(1) +#define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R60CIDCFGR_SCID_SHIFT 4 +#define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R60CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R60SEMCR register fields */ +#define RCC_R60SEMCR_SEM_MUTEX BIT(0) +#define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R60SEMCR_SEMCID_SHIFT 4 + +/* RCC_R61CIDCFGR register fields */ +#define RCC_R61CIDCFGR_CFEN BIT(0) +#define RCC_R61CIDCFGR_SEM_EN BIT(1) +#define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R61CIDCFGR_SCID_SHIFT 4 +#define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R61CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R61SEMCR register fields */ +#define RCC_R61SEMCR_SEM_MUTEX BIT(0) +#define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R61SEMCR_SEMCID_SHIFT 4 + +/* RCC_R62CIDCFGR register fields */ +#define RCC_R62CIDCFGR_CFEN BIT(0) +#define RCC_R62CIDCFGR_SEM_EN BIT(1) +#define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R62CIDCFGR_SCID_SHIFT 4 +#define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R62CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R62SEMCR register fields */ +#define RCC_R62SEMCR_SEM_MUTEX BIT(0) +#define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R62SEMCR_SEMCID_SHIFT 4 + +/* RCC_R63CIDCFGR register fields */ +#define RCC_R63CIDCFGR_CFEN BIT(0) +#define RCC_R63CIDCFGR_SEM_EN BIT(1) +#define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R63CIDCFGR_SCID_SHIFT 4 +#define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R63CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R63SEMCR register fields */ +#define RCC_R63SEMCR_SEM_MUTEX BIT(0) +#define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R63SEMCR_SEMCID_SHIFT 4 + +/* RCC_R64CIDCFGR register fields */ +#define RCC_R64CIDCFGR_CFEN BIT(0) +#define RCC_R64CIDCFGR_SEM_EN BIT(1) +#define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R64CIDCFGR_SCID_SHIFT 4 +#define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R64CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R64SEMCR register fields */ +#define RCC_R64SEMCR_SEM_MUTEX BIT(0) +#define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R64SEMCR_SEMCID_SHIFT 4 + +/* RCC_R65CIDCFGR register fields */ +#define RCC_R65CIDCFGR_CFEN BIT(0) +#define RCC_R65CIDCFGR_SEM_EN BIT(1) +#define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R65CIDCFGR_SCID_SHIFT 4 +#define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R65CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R65SEMCR register fields */ +#define RCC_R65SEMCR_SEM_MUTEX BIT(0) +#define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R65SEMCR_SEMCID_SHIFT 4 + +/* RCC_R66CIDCFGR register fields */ +#define RCC_R66CIDCFGR_CFEN BIT(0) +#define RCC_R66CIDCFGR_SEM_EN BIT(1) +#define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R66CIDCFGR_SCID_SHIFT 4 +#define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R66CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R66SEMCR register fields */ +#define RCC_R66SEMCR_SEM_MUTEX BIT(0) +#define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R66SEMCR_SEMCID_SHIFT 4 + +/* RCC_R67CIDCFGR register fields */ +#define RCC_R67CIDCFGR_CFEN BIT(0) +#define RCC_R67CIDCFGR_SEM_EN BIT(1) +#define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R67CIDCFGR_SCID_SHIFT 4 +#define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R67CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R67SEMCR register fields */ +#define RCC_R67SEMCR_SEM_MUTEX BIT(0) +#define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R67SEMCR_SEMCID_SHIFT 4 + +/* RCC_R68CIDCFGR register fields */ +#define RCC_R68CIDCFGR_CFEN BIT(0) +#define RCC_R68CIDCFGR_SEM_EN BIT(1) +#define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R68CIDCFGR_SCID_SHIFT 4 +#define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R68CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R68SEMCR register fields */ +#define RCC_R68SEMCR_SEM_MUTEX BIT(0) +#define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R68SEMCR_SEMCID_SHIFT 4 + +/* RCC_R69CIDCFGR register fields */ +#define RCC_R69CIDCFGR_CFEN BIT(0) +#define RCC_R69CIDCFGR_SEM_EN BIT(1) +#define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R69CIDCFGR_SCID_SHIFT 4 +#define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R69CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R69SEMCR register fields */ +#define RCC_R69SEMCR_SEM_MUTEX BIT(0) +#define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R69SEMCR_SEMCID_SHIFT 4 + +/* RCC_R70CIDCFGR register fields */ +#define RCC_R70CIDCFGR_CFEN BIT(0) +#define RCC_R70CIDCFGR_SEM_EN BIT(1) +#define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R70CIDCFGR_SCID_SHIFT 4 +#define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R70CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R70SEMCR register fields */ +#define RCC_R70SEMCR_SEM_MUTEX BIT(0) +#define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R70SEMCR_SEMCID_SHIFT 4 + +/* RCC_R71CIDCFGR register fields */ +#define RCC_R71CIDCFGR_CFEN BIT(0) +#define RCC_R71CIDCFGR_SEM_EN BIT(1) +#define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R71CIDCFGR_SCID_SHIFT 4 +#define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R71CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R71SEMCR register fields */ +#define RCC_R71SEMCR_SEM_MUTEX BIT(0) +#define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R71SEMCR_SEMCID_SHIFT 4 + +/* RCC_R72CIDCFGR register fields */ +#define RCC_R72CIDCFGR_CFEN BIT(0) +#define RCC_R72CIDCFGR_SEM_EN BIT(1) +#define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R72CIDCFGR_SCID_SHIFT 4 +#define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R72CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R72SEMCR register fields */ +#define RCC_R72SEMCR_SEM_MUTEX BIT(0) +#define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R72SEMCR_SEMCID_SHIFT 4 + +/* RCC_R73CIDCFGR register fields */ +#define RCC_R73CIDCFGR_CFEN BIT(0) +#define RCC_R73CIDCFGR_SEM_EN BIT(1) +#define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R73CIDCFGR_SCID_SHIFT 4 +#define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R73CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R73SEMCR register fields */ +#define RCC_R73SEMCR_SEM_MUTEX BIT(0) +#define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R73SEMCR_SEMCID_SHIFT 4 + +/* RCC_R74CIDCFGR register fields */ +#define RCC_R74CIDCFGR_CFEN BIT(0) +#define RCC_R74CIDCFGR_SEM_EN BIT(1) +#define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R74CIDCFGR_SCID_SHIFT 4 +#define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R74CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R74SEMCR register fields */ +#define RCC_R74SEMCR_SEM_MUTEX BIT(0) +#define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R74SEMCR_SEMCID_SHIFT 4 + +/* RCC_R75CIDCFGR register fields */ +#define RCC_R75CIDCFGR_CFEN BIT(0) +#define RCC_R75CIDCFGR_SEM_EN BIT(1) +#define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R75CIDCFGR_SCID_SHIFT 4 +#define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R75CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R75SEMCR register fields */ +#define RCC_R75SEMCR_SEM_MUTEX BIT(0) +#define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R75SEMCR_SEMCID_SHIFT 4 + +/* RCC_R76CIDCFGR register fields */ +#define RCC_R76CIDCFGR_CFEN BIT(0) +#define RCC_R76CIDCFGR_SEM_EN BIT(1) +#define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R76CIDCFGR_SCID_SHIFT 4 +#define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R76CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R76SEMCR register fields */ +#define RCC_R76SEMCR_SEM_MUTEX BIT(0) +#define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R76SEMCR_SEMCID_SHIFT 4 + +/* RCC_R77CIDCFGR register fields */ +#define RCC_R77CIDCFGR_CFEN BIT(0) +#define RCC_R77CIDCFGR_SEM_EN BIT(1) +#define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R77CIDCFGR_SCID_SHIFT 4 +#define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R77CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R77SEMCR register fields */ +#define RCC_R77SEMCR_SEM_MUTEX BIT(0) +#define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R77SEMCR_SEMCID_SHIFT 4 + +/* RCC_R78CIDCFGR register fields */ +#define RCC_R78CIDCFGR_CFEN BIT(0) +#define RCC_R78CIDCFGR_SEM_EN BIT(1) +#define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R78CIDCFGR_SCID_SHIFT 4 +#define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R78CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R78SEMCR register fields */ +#define RCC_R78SEMCR_SEM_MUTEX BIT(0) +#define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R78SEMCR_SEMCID_SHIFT 4 + +/* RCC_R79CIDCFGR register fields */ +#define RCC_R79CIDCFGR_CFEN BIT(0) +#define RCC_R79CIDCFGR_SEM_EN BIT(1) +#define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R79CIDCFGR_SCID_SHIFT 4 +#define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R79CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R79SEMCR register fields */ +#define RCC_R79SEMCR_SEM_MUTEX BIT(0) +#define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R79SEMCR_SEMCID_SHIFT 4 + +/* RCC_R80CIDCFGR register fields */ +#define RCC_R80CIDCFGR_CFEN BIT(0) +#define RCC_R80CIDCFGR_SEM_EN BIT(1) +#define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R80CIDCFGR_SCID_SHIFT 4 +#define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R80CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R80SEMCR register fields */ +#define RCC_R80SEMCR_SEM_MUTEX BIT(0) +#define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R80SEMCR_SEMCID_SHIFT 4 + +/* RCC_R81CIDCFGR register fields */ +#define RCC_R81CIDCFGR_CFEN BIT(0) +#define RCC_R81CIDCFGR_SEM_EN BIT(1) +#define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R81CIDCFGR_SCID_SHIFT 4 +#define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R81CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R81SEMCR register fields */ +#define RCC_R81SEMCR_SEM_MUTEX BIT(0) +#define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R81SEMCR_SEMCID_SHIFT 4 + +/* RCC_R82CIDCFGR register fields */ +#define RCC_R82CIDCFGR_CFEN BIT(0) +#define RCC_R82CIDCFGR_SEM_EN BIT(1) +#define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R82CIDCFGR_SCID_SHIFT 4 +#define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R82CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R82SEMCR register fields */ +#define RCC_R82SEMCR_SEM_MUTEX BIT(0) +#define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R82SEMCR_SEMCID_SHIFT 4 + +/* RCC_R83CIDCFGR register fields */ +#define RCC_R83CIDCFGR_CFEN BIT(0) +#define RCC_R83CIDCFGR_SEM_EN BIT(1) +#define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R83CIDCFGR_SCID_SHIFT 4 +#define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R83CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R83SEMCR register fields */ +#define RCC_R83SEMCR_SEM_MUTEX BIT(0) +#define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R83SEMCR_SEMCID_SHIFT 4 + +/* RCC_R84CIDCFGR register fields */ +#define RCC_R84CIDCFGR_CFEN BIT(0) +#define RCC_R84CIDCFGR_SEM_EN BIT(1) +#define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R84CIDCFGR_SCID_SHIFT 4 +#define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R84CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R84SEMCR register fields */ +#define RCC_R84SEMCR_SEM_MUTEX BIT(0) +#define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R84SEMCR_SEMCID_SHIFT 4 + +/* RCC_R85CIDCFGR register fields */ +#define RCC_R85CIDCFGR_CFEN BIT(0) +#define RCC_R85CIDCFGR_SEM_EN BIT(1) +#define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R85CIDCFGR_SCID_SHIFT 4 +#define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R85CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R85SEMCR register fields */ +#define RCC_R85SEMCR_SEM_MUTEX BIT(0) +#define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R85SEMCR_SEMCID_SHIFT 4 + +/* RCC_R86CIDCFGR register fields */ +#define RCC_R86CIDCFGR_CFEN BIT(0) +#define RCC_R86CIDCFGR_SEM_EN BIT(1) +#define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R86CIDCFGR_SCID_SHIFT 4 +#define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R86CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R86SEMCR register fields */ +#define RCC_R86SEMCR_SEM_MUTEX BIT(0) +#define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R86SEMCR_SEMCID_SHIFT 4 + +/* RCC_R87CIDCFGR register fields */ +#define RCC_R87CIDCFGR_CFEN BIT(0) +#define RCC_R87CIDCFGR_SEM_EN BIT(1) +#define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R87CIDCFGR_SCID_SHIFT 4 +#define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R87CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R87SEMCR register fields */ +#define RCC_R87SEMCR_SEM_MUTEX BIT(0) +#define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R87SEMCR_SEMCID_SHIFT 4 + +/* RCC_R88CIDCFGR register fields */ +#define RCC_R88CIDCFGR_CFEN BIT(0) +#define RCC_R88CIDCFGR_SEM_EN BIT(1) +#define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R88CIDCFGR_SCID_SHIFT 4 +#define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R88CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R88SEMCR register fields */ +#define RCC_R88SEMCR_SEM_MUTEX BIT(0) +#define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R88SEMCR_SEMCID_SHIFT 4 + +/* RCC_R89CIDCFGR register fields */ +#define RCC_R89CIDCFGR_CFEN BIT(0) +#define RCC_R89CIDCFGR_SEM_EN BIT(1) +#define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R89CIDCFGR_SCID_SHIFT 4 +#define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R89CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R89SEMCR register fields */ +#define RCC_R89SEMCR_SEM_MUTEX BIT(0) +#define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R89SEMCR_SEMCID_SHIFT 4 + +/* RCC_R90CIDCFGR register fields */ +#define RCC_R90CIDCFGR_CFEN BIT(0) +#define RCC_R90CIDCFGR_SEM_EN BIT(1) +#define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R90CIDCFGR_SCID_SHIFT 4 +#define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R90CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R90SEMCR register fields */ +#define RCC_R90SEMCR_SEM_MUTEX BIT(0) +#define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R90SEMCR_SEMCID_SHIFT 4 + +/* RCC_R91CIDCFGR register fields */ +#define RCC_R91CIDCFGR_CFEN BIT(0) +#define RCC_R91CIDCFGR_SEM_EN BIT(1) +#define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R91CIDCFGR_SCID_SHIFT 4 +#define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R91CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R91SEMCR register fields */ +#define RCC_R91SEMCR_SEM_MUTEX BIT(0) +#define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R91SEMCR_SEMCID_SHIFT 4 + +/* RCC_R92CIDCFGR register fields */ +#define RCC_R92CIDCFGR_CFEN BIT(0) +#define RCC_R92CIDCFGR_SEM_EN BIT(1) +#define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R92CIDCFGR_SCID_SHIFT 4 +#define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R92CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R92SEMCR register fields */ +#define RCC_R92SEMCR_SEM_MUTEX BIT(0) +#define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R92SEMCR_SEMCID_SHIFT 4 + +/* RCC_R93CIDCFGR register fields */ +#define RCC_R93CIDCFGR_CFEN BIT(0) +#define RCC_R93CIDCFGR_SEM_EN BIT(1) +#define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R93CIDCFGR_SCID_SHIFT 4 +#define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R93CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R93SEMCR register fields */ +#define RCC_R93SEMCR_SEM_MUTEX BIT(0) +#define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R93SEMCR_SEMCID_SHIFT 4 + +/* RCC_R94CIDCFGR register fields */ +#define RCC_R94CIDCFGR_CFEN BIT(0) +#define RCC_R94CIDCFGR_SEM_EN BIT(1) +#define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R94CIDCFGR_SCID_SHIFT 4 +#define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R94CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R94SEMCR register fields */ +#define RCC_R94SEMCR_SEM_MUTEX BIT(0) +#define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R94SEMCR_SEMCID_SHIFT 4 + +/* RCC_R95CIDCFGR register fields */ +#define RCC_R95CIDCFGR_CFEN BIT(0) +#define RCC_R95CIDCFGR_SEM_EN BIT(1) +#define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R95CIDCFGR_SCID_SHIFT 4 +#define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R95CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R95SEMCR register fields */ +#define RCC_R95SEMCR_SEM_MUTEX BIT(0) +#define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R95SEMCR_SEMCID_SHIFT 4 + +/* RCC_R96CIDCFGR register fields */ +#define RCC_R96CIDCFGR_CFEN BIT(0) +#define RCC_R96CIDCFGR_SEM_EN BIT(1) +#define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R96CIDCFGR_SCID_SHIFT 4 +#define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R96CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R96SEMCR register fields */ +#define RCC_R96SEMCR_SEM_MUTEX BIT(0) +#define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R96SEMCR_SEMCID_SHIFT 4 + +/* RCC_R97CIDCFGR register fields */ +#define RCC_R97CIDCFGR_CFEN BIT(0) +#define RCC_R97CIDCFGR_SEM_EN BIT(1) +#define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R97CIDCFGR_SCID_SHIFT 4 +#define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R97CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R97SEMCR register fields */ +#define RCC_R97SEMCR_SEM_MUTEX BIT(0) +#define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R97SEMCR_SEMCID_SHIFT 4 + +/* RCC_R98CIDCFGR register fields */ +#define RCC_R98CIDCFGR_CFEN BIT(0) +#define RCC_R98CIDCFGR_SEM_EN BIT(1) +#define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R98CIDCFGR_SCID_SHIFT 4 +#define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R98CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R98SEMCR register fields */ +#define RCC_R98SEMCR_SEM_MUTEX BIT(0) +#define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R98SEMCR_SEMCID_SHIFT 4 + +/* RCC_R99CIDCFGR register fields */ +#define RCC_R99CIDCFGR_CFEN BIT(0) +#define RCC_R99CIDCFGR_SEM_EN BIT(1) +#define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R99CIDCFGR_SCID_SHIFT 4 +#define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R99CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R99SEMCR register fields */ +#define RCC_R99SEMCR_SEM_MUTEX BIT(0) +#define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R99SEMCR_SEMCID_SHIFT 4 + +/* RCC_R100CIDCFGR register fields */ +#define RCC_R100CIDCFGR_CFEN BIT(0) +#define RCC_R100CIDCFGR_SEM_EN BIT(1) +#define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R100CIDCFGR_SCID_SHIFT 4 +#define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R100CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R100SEMCR register fields */ +#define RCC_R100SEMCR_SEM_MUTEX BIT(0) +#define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R100SEMCR_SEMCID_SHIFT 4 + +/* RCC_R101CIDCFGR register fields */ +#define RCC_R101CIDCFGR_CFEN BIT(0) +#define RCC_R101CIDCFGR_SEM_EN BIT(1) +#define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R101CIDCFGR_SCID_SHIFT 4 +#define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R101CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R101SEMCR register fields */ +#define RCC_R101SEMCR_SEM_MUTEX BIT(0) +#define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R101SEMCR_SEMCID_SHIFT 4 + +/* RCC_R102CIDCFGR register fields */ +#define RCC_R102CIDCFGR_CFEN BIT(0) +#define RCC_R102CIDCFGR_SEM_EN BIT(1) +#define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R102CIDCFGR_SCID_SHIFT 4 +#define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R102CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R102SEMCR register fields */ +#define RCC_R102SEMCR_SEM_MUTEX BIT(0) +#define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R102SEMCR_SEMCID_SHIFT 4 + +/* RCC_R103CIDCFGR register fields */ +#define RCC_R103CIDCFGR_CFEN BIT(0) +#define RCC_R103CIDCFGR_SEM_EN BIT(1) +#define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R103CIDCFGR_SCID_SHIFT 4 +#define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R103CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R103SEMCR register fields */ +#define RCC_R103SEMCR_SEM_MUTEX BIT(0) +#define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R103SEMCR_SEMCID_SHIFT 4 + +/* RCC_R104CIDCFGR register fields */ +#define RCC_R104CIDCFGR_CFEN BIT(0) +#define RCC_R104CIDCFGR_SEM_EN BIT(1) +#define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R104CIDCFGR_SCID_SHIFT 4 +#define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R104CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R104SEMCR register fields */ +#define RCC_R104SEMCR_SEM_MUTEX BIT(0) +#define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R104SEMCR_SEMCID_SHIFT 4 + +/* RCC_R105CIDCFGR register fields */ +#define RCC_R105CIDCFGR_CFEN BIT(0) +#define RCC_R105CIDCFGR_SEM_EN BIT(1) +#define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R105CIDCFGR_SCID_SHIFT 4 +#define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R105CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R105SEMCR register fields */ +#define RCC_R105SEMCR_SEM_MUTEX BIT(0) +#define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R105SEMCR_SEMCID_SHIFT 4 + +/* RCC_R106CIDCFGR register fields */ +#define RCC_R106CIDCFGR_CFEN BIT(0) +#define RCC_R106CIDCFGR_SEM_EN BIT(1) +#define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R106CIDCFGR_SCID_SHIFT 4 +#define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R106CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R106SEMCR register fields */ +#define RCC_R106SEMCR_SEM_MUTEX BIT(0) +#define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R106SEMCR_SEMCID_SHIFT 4 + +/* RCC_R107CIDCFGR register fields */ +#define RCC_R107CIDCFGR_CFEN BIT(0) +#define RCC_R107CIDCFGR_SEM_EN BIT(1) +#define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R107CIDCFGR_SCID_SHIFT 4 +#define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R107CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R107SEMCR register fields */ +#define RCC_R107SEMCR_SEM_MUTEX BIT(0) +#define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R107SEMCR_SEMCID_SHIFT 4 + +/* RCC_R108CIDCFGR register fields */ +#define RCC_R108CIDCFGR_CFEN BIT(0) +#define RCC_R108CIDCFGR_SEM_EN BIT(1) +#define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R108CIDCFGR_SCID_SHIFT 4 +#define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R108CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R108SEMCR register fields */ +#define RCC_R108SEMCR_SEM_MUTEX BIT(0) +#define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R108SEMCR_SEMCID_SHIFT 4 + +/* RCC_R109CIDCFGR register fields */ +#define RCC_R109CIDCFGR_CFEN BIT(0) +#define RCC_R109CIDCFGR_SEM_EN BIT(1) +#define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R109CIDCFGR_SCID_SHIFT 4 +#define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R109CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R109SEMCR register fields */ +#define RCC_R109SEMCR_SEM_MUTEX BIT(0) +#define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R109SEMCR_SEMCID_SHIFT 4 + +/* RCC_R110CIDCFGR register fields */ +#define RCC_R110CIDCFGR_CFEN BIT(0) +#define RCC_R110CIDCFGR_SEM_EN BIT(1) +#define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R110CIDCFGR_SCID_SHIFT 4 +#define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R110CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R110SEMCR register fields */ +#define RCC_R110SEMCR_SEM_MUTEX BIT(0) +#define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R110SEMCR_SEMCID_SHIFT 4 + +/* RCC_R111CIDCFGR register fields */ +#define RCC_R111CIDCFGR_CFEN BIT(0) +#define RCC_R111CIDCFGR_SEM_EN BIT(1) +#define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R111CIDCFGR_SCID_SHIFT 4 +#define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R111CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R111SEMCR register fields */ +#define RCC_R111SEMCR_SEM_MUTEX BIT(0) +#define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R111SEMCR_SEMCID_SHIFT 4 + +/* RCC_R112CIDCFGR register fields */ +#define RCC_R112CIDCFGR_CFEN BIT(0) +#define RCC_R112CIDCFGR_SEM_EN BIT(1) +#define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R112CIDCFGR_SCID_SHIFT 4 +#define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R112CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R112SEMCR register fields */ +#define RCC_R112SEMCR_SEM_MUTEX BIT(0) +#define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R112SEMCR_SEMCID_SHIFT 4 + +/* RCC_R113CIDCFGR register fields */ +#define RCC_R113CIDCFGR_CFEN BIT(0) +#define RCC_R113CIDCFGR_SEM_EN BIT(1) +#define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R113CIDCFGR_SCID_SHIFT 4 +#define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R113CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R113SEMCR register fields */ +#define RCC_R113SEMCR_SEM_MUTEX BIT(0) +#define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R113SEMCR_SEMCID_SHIFT 4 + +/* RCC_RxCIDCFGR register fields */ +#define RCC_RxCIDCFGR_CFEN BIT(0) +#define RCC_RxCIDCFGR_SEM_EN BIT(1) +#define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_RxCIDCFGR_SCID_SHIFT 4 +#define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_RxCIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_RxSEMCR register fields */ +#define RCC_RxSEMCR_SEM_MUTEX BIT(0) +#define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_RxSEMCR_SEMCID_SHIFT 4 + +/* RCC_GRSTCSETR register fields */ +#define RCC_GRSTCSETR_SYSRST BIT(0) + +/* RCC_C1RSTCSETR register fields */ +#define RCC_C1RSTCSETR_C1RST BIT(0) + +/* RCC_C1P1RSTCSETR register fields */ +#define RCC_C1P1RSTCSETR_C1P1PORRST BIT(0) +#define RCC_C1P1RSTCSETR_C1P1RST BIT(1) + +/* RCC_C2RSTCSETR register fields */ +#define RCC_C2RSTCSETR_C2RST BIT(0) + +/* RCC_CxRSTCSETR register fields */ +#define RCC_CxRSTCSETR_CxRST BIT(0) + +/* RCC_HWRSTSCLRR register fields */ +#define RCC_HWRSTSCLRR_PORRSTF BIT(0) +#define RCC_HWRSTSCLRR_BORRSTF BIT(1) +#define RCC_HWRSTSCLRR_PADRSTF BIT(2) +#define RCC_HWRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_HWRSTSCLRR_VCORERSTF BIT(4) +#define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5) +#define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6) +#define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7) +#define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8) +#define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9) +#define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10) +#define RCC_HWRSTSCLRR_IWDG5SYSRSTF BIT(11) +#define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12) +#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13) +#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14) + +/* RCC_C1HWRSTSCLRR register fields */ +#define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0) +#define RCC_C1HWRSTSCLRR_C1RSTF BIT(1) +#define RCC_C1HWRSTSCLRR_C1P1RSTF BIT(2) + +/* RCC_C2HWRSTSCLRR register fields */ +#define RCC_C2HWRSTSCLRR_C2RSTF BIT(0) + +/* RCC_C1BOOTRSTSSETR register fields */ +#define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0) +#define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1) +#define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2) +#define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3) +#define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4) +#define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5) +#define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6) +#define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7) +#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) +#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) +#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) +#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) +#define RCC_C1BOOTRSTSSETR_IWDG5SYSRSTF BIT(12) +#define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13) +#define RCC_C1BOOTRSTSSETR_C1P1RSTF BIT(16) +#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17) +#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20) +#define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22) +#define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23) + +/* RCC_C1BOOTRSTSCLRR register fields */ +#define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0) +#define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1) +#define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2) +#define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4) +#define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5) +#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6) +#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7) +#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) +#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) +#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) +#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) +#define RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12) +#define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13) +#define RCC_C1BOOTRSTSCLRR_C1P1RSTF BIT(16) +#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) +#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20) +#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22) +#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23) + +/* RCC_C2BOOTRSTSSETR register fields */ +#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0) +#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1) +#define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2) +#define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3) +#define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4) +#define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6) +#define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7) +#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) +#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) +#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) +#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) +#define RCC_C2BOOTRSTSSETR_IWDG5SYSRSTF BIT(12) +#define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14) +#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17) +#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21) +#define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23) + +/* RCC_C2BOOTRSTSCLRR register fields */ +#define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0) +#define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1) +#define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2) +#define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4) +#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6) +#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7) +#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) +#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) +#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) +#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) +#define RCC_C2BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12) +#define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14) +#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) +#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21) +#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23) + +/* RCC_C1SREQSETR register fields */ +#define RCC_C1SREQSETR_STPREQ_P0 BIT(0) +#define RCC_C1SREQSETR_STPREQ_P1 BIT(1) +#define RCC_C1SREQSETR_ESLPREQ BIT(16) + +/* RCC_C1SREQCLRR register fields */ +#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0) +#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1) +#define RCC_C1SREQCLRR_ESLPREQ BIT(16) + +/* RCC_CPUBOOTCR register fields */ +#define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0) +#define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1) + +/* RCC_STBYBOOTCR register fields */ +#define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1) +#define RCC_STBYBOOTCR_COLD_CPU2 BIT(2) +#define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4) +#define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5) +#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8) + +/* RCC_LEGBOOTCR register fields */ +#define RCC_LEGBOOTCR_LEGACY_BEN BIT(0) + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_LSEDIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(6) +#define RCC_BDCR_LSEGFON BIT(7) +#define RCC_BDCR_LSECSSD BIT(8) +#define RCC_BDCR_LSION BIT(9) +#define RCC_BDCR_LSIRDY BIT(10) +#define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_MSIFREQSEL BIT(24) +#define RCC_BDCR_C3SYSTICKSEL BIT(25) +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_LSEBYP_BIT 1 +#define RCC_BDCR_LSEDIGBYP_BIT 3 +#define RCC_BDCR_LSECSSON_BIT 6 +#define RCC_BDCR_LSERDY_BIT 2 +#define RCC_BDCR_LSIRDY_BIT 10 + +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSEDRV_WIDTH 2 + +/* RCC_D3DCR register fields */ +#define RCC_D3DCR_CSION BIT(0) +#define RCC_D3DCR_CSIKERON BIT(1) +#define RCC_D3DCR_CSIRDY BIT(2) +#define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16) +#define RCC_D3DCR_D3PERCKSEL_SHIFT 16 +#define RCC_D3DCR_CSIRDY_BIT 2 + +/* RCC_D3DSR register fields */ +#define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0) +#define RCC_D3DSR_D3STATE_SHIFT 0 + +/* RCC_RDCR register fields */ +#define RCC_RDCR_MRD_MASK GENMASK_32(20, 16) +#define RCC_RDCR_MRD_SHIFT 16 +#define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24) +#define RCC_RDCR_EADLY_SHIFT 24 + +/* RCC_C1MSRDCR register fields */ +#define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0) +#define RCC_C1MSRDCR_C1MSRD_SHIFT 0 +#define RCC_C1MSRDCR_C1MSRST BIT(8) + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 +#define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24) + +/* RCC_C1CIESETR register fields */ +#define RCC_C1CIESETR_LSIRDYIE BIT(0) +#define RCC_C1CIESETR_LSERDYIE BIT(1) +#define RCC_C1CIESETR_HSIRDYIE BIT(2) +#define RCC_C1CIESETR_HSERDYIE BIT(3) +#define RCC_C1CIESETR_CSIRDYIE BIT(4) +#define RCC_C1CIESETR_PLL1RDYIE BIT(5) +#define RCC_C1CIESETR_PLL2RDYIE BIT(6) +#define RCC_C1CIESETR_PLL3RDYIE BIT(7) +#define RCC_C1CIESETR_PLL4RDYIE BIT(8) +#define RCC_C1CIESETR_PLL5RDYIE BIT(9) +#define RCC_C1CIESETR_PLL6RDYIE BIT(10) +#define RCC_C1CIESETR_PLL7RDYIE BIT(11) +#define RCC_C1CIESETR_PLL8RDYIE BIT(12) +#define RCC_C1CIESETR_LSECSSIE BIT(16) +#define RCC_C1CIESETR_WKUPIE BIT(20) + +/* RCC_C1CIFCLRR register fields */ +#define RCC_C1CIFCLRR_LSIRDYF BIT(0) +#define RCC_C1CIFCLRR_LSERDYF BIT(1) +#define RCC_C1CIFCLRR_HSIRDYF BIT(2) +#define RCC_C1CIFCLRR_HSERDYF BIT(3) +#define RCC_C1CIFCLRR_CSIRDYF BIT(4) +#define RCC_C1CIFCLRR_PLL1RDYF BIT(5) +#define RCC_C1CIFCLRR_PLL2RDYF BIT(6) +#define RCC_C1CIFCLRR_PLL3RDYF BIT(7) +#define RCC_C1CIFCLRR_PLL4RDYF BIT(8) +#define RCC_C1CIFCLRR_PLL5RDYF BIT(9) +#define RCC_C1CIFCLRR_PLL6RDYF BIT(10) +#define RCC_C1CIFCLRR_PLL7RDYF BIT(11) +#define RCC_C1CIFCLRR_PLL8RDYF BIT(12) +#define RCC_C1CIFCLRR_LSECSSF BIT(16) +#define RCC_C1CIFCLRR_WKUPF BIT(20) + +/* RCC_C2CIESETR register fields */ +#define RCC_C2CIESETR_LSIRDYIE BIT(0) +#define RCC_C2CIESETR_LSERDYIE BIT(1) +#define RCC_C2CIESETR_HSIRDYIE BIT(2) +#define RCC_C2CIESETR_HSERDYIE BIT(3) +#define RCC_C2CIESETR_CSIRDYIE BIT(4) +#define RCC_C2CIESETR_PLL1RDYIE BIT(5) +#define RCC_C2CIESETR_PLL2RDYIE BIT(6) +#define RCC_C2CIESETR_PLL3RDYIE BIT(7) +#define RCC_C2CIESETR_PLL4RDYIE BIT(8) +#define RCC_C2CIESETR_PLL5RDYIE BIT(9) +#define RCC_C2CIESETR_PLL6RDYIE BIT(10) +#define RCC_C2CIESETR_PLL7RDYIE BIT(11) +#define RCC_C2CIESETR_PLL8RDYIE BIT(12) +#define RCC_C2CIESETR_LSECSSIE BIT(16) +#define RCC_C2CIESETR_WKUPIE BIT(20) + +/* RCC_C2CIFCLRR register fields */ +#define RCC_C2CIFCLRR_LSIRDYF BIT(0) +#define RCC_C2CIFCLRR_LSERDYF BIT(1) +#define RCC_C2CIFCLRR_HSIRDYF BIT(2) +#define RCC_C2CIFCLRR_HSERDYF BIT(3) +#define RCC_C2CIFCLRR_CSIRDYF BIT(4) +#define RCC_C2CIFCLRR_PLL1RDYF BIT(5) +#define RCC_C2CIFCLRR_PLL2RDYF BIT(6) +#define RCC_C2CIFCLRR_PLL3RDYF BIT(7) +#define RCC_C2CIFCLRR_PLL4RDYF BIT(8) +#define RCC_C2CIFCLRR_PLL5RDYF BIT(9) +#define RCC_C2CIFCLRR_PLL6RDYF BIT(10) +#define RCC_C2CIFCLRR_PLL7RDYF BIT(11) +#define RCC_C2CIFCLRR_PLL8RDYF BIT(12) +#define RCC_C2CIFCLRR_LSECSSF BIT(16) +#define RCC_C2CIFCLRR_WKUPF BIT(20) + +/* RCC_CxCIESETR register fields */ +#define RCC_CxCIESETR_LSIRDYIE BIT(0) +#define RCC_CxCIESETR_LSERDYIE BIT(1) +#define RCC_CxCIESETR_HSIRDYIE BIT(2) +#define RCC_CxCIESETR_HSERDYIE BIT(3) +#define RCC_CxCIESETR_CSIRDYIE BIT(4) +#define RCC_CxCIESETR_SHSIRDYIE BIT(5) +#define RCC_CxCIESETR_PLL1RDYIE BIT(6) +#define RCC_CxCIESETR_PLL2RDYIE BIT(7) +#define RCC_CxCIESETR_PLL3RDYIE BIT(8) +#define RCC_CxCIESETR_PLL4RDYIE BIT(9) +#define RCC_CxCIESETR_PLL5RDYIE BIT(10) +#define RCC_CxCIESETR_PLL6RDYIE BIT(11) +#define RCC_CxCIESETR_PLL7RDYIE BIT(12) +#define RCC_CxCIESETR_PLL8RDYIE BIT(13) +#define RCC_CxCIESETR_LSECSSIE BIT(16) +#define RCC_CxCIESETR_WKUPIE BIT(20) + +/* RCC_CxCIFCLRR register fields */ +#define RCC_CxCIFCLRR_LSIRDYF BIT(0) +#define RCC_CxCIFCLRR_LSERDYF BIT(1) +#define RCC_CxCIFCLRR_HSIRDYF BIT(2) +#define RCC_CxCIFCLRR_HSERDYF BIT(3) +#define RCC_CxCIFCLRR_CSIRDYF BIT(4) +#define RCC_CxCIFCLRR_SHSIRDYF BIT(5) +#define RCC_CxCIFCLRR_PLL1RDYF BIT(6) +#define RCC_CxCIFCLRR_PLL2RDYF BIT(7) +#define RCC_CxCIFCLRR_PLL3RDYF BIT(8) +#define RCC_CxCIFCLRR_PLL4RDYF BIT(9) +#define RCC_CxCIFCLRR_PLL5RDYF BIT(10) +#define RCC_CxCIFCLRR_PLL6RDYF BIT(11) +#define RCC_CxCIFCLRR_PLL7RDYF BIT(12) +#define RCC_CxCIFCLRR_PLL8RDYF BIT(13) +#define RCC_CxCIFCLRR_LSECSSF BIT(16) +#define RCC_CxCIFCLRR_WKUPF BIT(20) + +/* RCC_IWDGC1FZSETR register fields */ +#define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0) +#define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1) + +/* RCC_IWDGC1FZCLRR register fields */ +#define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0) +#define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_IWDGC1CFGSETR register fields */ +#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0) +#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2) +#define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18) + +/* RCC_IWDGC1CFGCLRR register fields */ +#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0) +#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2) +#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18) + +/* RCC_IWDGC2FZSETR register fields */ +#define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0) +#define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1) + +/* RCC_IWDGC2FZCLRR register fields */ +#define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0) +#define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1) + +/* RCC_IWDGC2CFGSETR register fields */ +#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0) +#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2) +#define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18) + +/* RCC_IWDGC2CFGCLRR register fields */ +#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0) +#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2) +#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18) + +/* RCC_IWDGC3CFGSETR register fields */ +#define RCC_IWDGC3CFGSETR_IWDG5_SYSRSTEN BIT(0) + +/* RCC_IWDGC3CFGCLRR register fields */ +#define RCC_IWDGC3CFGCLRR_IWDG5_SYSRSTEN BIT(0) + +/* RCC_C3CFGR register fields */ +#define RCC_C3CFGR_C3RST BIT(0) +#define RCC_C3CFGR_C3EN BIT(1) +#define RCC_C3CFGR_C3LPEN BIT(2) +#define RCC_C3CFGR_C3AMEN BIT(3) +#define RCC_C3CFGR_LPTIM3C3EN BIT(16) +#define RCC_C3CFGR_LPTIM4C3EN BIT(17) +#define RCC_C3CFGR_LPTIM5C3EN BIT(18) +#define RCC_C3CFGR_SPI8C3EN BIT(19) +#define RCC_C3CFGR_LPUART1C3EN BIT(20) +#define RCC_C3CFGR_I2C8C3EN BIT(21) +#define RCC_C3CFGR_ADF1C3EN BIT(23) +#define RCC_C3CFGR_GPIOZC3EN BIT(24) +#define RCC_C3CFGR_LPDMAC3EN BIT(25) +#define RCC_C3CFGR_RTCC3EN BIT(26) +#define RCC_C3CFGR_I3C4C3EN BIT(27) + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL BIT(0) +#define RCC_MCO1CFGR_MCO1ON BIT(8) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL BIT(0) +#define RCC_MCO2CFGR_MCO2ON BIT(8) + +/* RCC_MCOxCFGR register fields */ +#define RCC_MCOxCFGR_MCOxSEL BIT(0) +#define RCC_MCOxCFGR_MCOxON BIT(8) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_HSEDIV2ON BIT(5) +#define RCC_OCENSETR_HSEDIV2BYP BIT(6) +#define RCC_OCENSETR_HSEDIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_HSEDIV2ON BIT(5) +#define RCC_OCENCLRR_HSEDIV2BYP BIT(6) +#define RCC_OCENCLRR_HSEDIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_CKREST BIT(25) + +#define RCC_OCRDYR_HSIRDY_BIT 0 +#define RCC_OCRDYR_HSERDY_BIT 8 + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK_32(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK_32(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APBDBGDIVR register fields */ +#define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0) +#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0 +#define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31) + +/* RCC_APBxDIVR register fields */ +#define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0) +#define RCC_APBxDIVR_APBxDIV_SHIFT 0 +#define RCC_APBxDIVR_APBxDIVRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_TIMGxPRER register fields */ +#define RCC_TIMGxPRER_TIMGxPRE BIT(0) +#define RCC_TIMGxPRER_TIMGxPRERDY BIT(31) + +/* RCC_LSMCUDIVR register fields */ +#define RCC_LSMCUDIVR_LSMCUDIV BIT(0) +#define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31) + +/* RCC_DDRCPCFGR register fields */ +#define RCC_DDRCPCFGR_DDRCPRST BIT(0) +#define RCC_DDRCPCFGR_DDRCPEN BIT(1) +#define RCC_DDRCPCFGR_DDRCPLPEN BIT(2) + +/* RCC_DDRCAPBCFGR register fields */ +#define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0) +#define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1) +#define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2) + +/* RCC_DDRPHYCAPBCFGR register fields */ +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0) +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1) +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2) + +/* RCC_DDRPHYCCFGR register fields */ +#define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1) + +/* RCC_DDRCFGR register fields */ +#define RCC_DDRCFGR_DDRCFGRST BIT(0) +#define RCC_DDRCFGR_DDRCFGEN BIT(1) +#define RCC_DDRCFGR_DDRCFGLPEN BIT(2) + +/* RCC_DDRITFCFGR register fields */ +#define RCC_DDRITFCFGR_DDRRST BIT(0) +#define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4) +#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4 +#define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5) +#define RCC_DDRITFCFGR_DDRSHR BIT(8) +#define RCC_DDRITFCFGR_DDRPHYDLP BIT(16) + +/* RCC_SYSRAMCFGR register fields */ +#define RCC_SYSRAMCFGR_SYSRAMEN BIT(1) +#define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2) + +/* RCC_VDERAMCFGR register fields */ +#define RCC_VDERAMCFGR_VDERAMEN BIT(1) +#define RCC_VDERAMCFGR_VDERAMLPEN BIT(2) + +/* RCC_SRAM1CFGR register fields */ +#define RCC_SRAM1CFGR_SRAM1EN BIT(1) +#define RCC_SRAM1CFGR_SRAM1LPEN BIT(2) + +/* RCC_SRAM2CFGR register fields */ +#define RCC_SRAM2CFGR_SRAM2EN BIT(1) +#define RCC_SRAM2CFGR_SRAM2LPEN BIT(2) + +/* RCC_RETRAMCFGR register fields */ +#define RCC_RETRAMCFGR_RETRAMEN BIT(1) +#define RCC_RETRAMCFGR_RETRAMLPEN BIT(2) + +/* RCC_BKPSRAMCFGR register fields */ +#define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1) +#define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2) + +/* RCC_LPSRAM1CFGR register fields */ +#define RCC_LPSRAM1CFGR_LPSRAM1EN BIT(1) +#define RCC_LPSRAM1CFGR_LPSRAM1LPEN BIT(2) +#define RCC_LPSRAM1CFGR_LPSRAM1AMEN BIT(3) + +/* RCC_LPSRAM2CFGR register fields */ +#define RCC_LPSRAM2CFGR_LPSRAM2EN BIT(1) +#define RCC_LPSRAM2CFGR_LPSRAM2LPEN BIT(2) +#define RCC_LPSRAM2CFGR_LPSRAM2AMEN BIT(3) + +/* RCC_LPSRAM3CFGR register fields */ +#define RCC_LPSRAM3CFGR_LPSRAM3EN BIT(1) +#define RCC_LPSRAM3CFGR_LPSRAM3LPEN BIT(2) +#define RCC_LPSRAM3CFGR_LPSRAM3AMEN BIT(3) + +/* RCC_OSPI1CFGR register fields */ +#define RCC_OSPI1CFGR_OSPI1RST BIT(0) +#define RCC_OSPI1CFGR_OSPI1EN BIT(1) +#define RCC_OSPI1CFGR_OSPI1LPEN BIT(2) +#define RCC_OSPI1CFGR_OTFDEC1RST BIT(8) +#define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16) + +/* RCC_OSPI2CFGR register fields */ +#define RCC_OSPI2CFGR_OSPI2RST BIT(0) +#define RCC_OSPI2CFGR_OSPI2EN BIT(1) +#define RCC_OSPI2CFGR_OSPI2LPEN BIT(2) +#define RCC_OSPI2CFGR_OTFDEC2RST BIT(8) +#define RCC_OSPI2CFGR_OSPI2DLLRST BIT(16) + +/* RCC_OSPIxCFGR register fields */ +#define RCC_OSPIxCFGR_OSPIxRST BIT(0) +#define RCC_OSPIxCFGR_OSPIxEN BIT(1) +#define RCC_OSPIxCFGR_OSPIxLPEN BIT(2) +#define RCC_OSPIxCFGR_OTFDECxRST BIT(8) +#define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16) + +/* RCC_FMCCFGR register fields */ +#define RCC_FMCCFGR_FMCRST BIT(0) +#define RCC_FMCCFGR_FMCEN BIT(1) +#define RCC_FMCCFGR_FMCLPEN BIT(2) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_DBGEN BIT(8) +#define RCC_DBGCFGR_TRACEEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_STM500CFGR register fields */ +#define RCC_STM500CFGR_STM500EN BIT(1) +#define RCC_STM500CFGR_STM500LPEN BIT(2) + +/* RCC_ETRCFGR register fields */ +#define RCC_ETRCFGR_ETREN BIT(1) +#define RCC_ETRCFGR_ETRLPEN BIT(2) + +/* RCC_GPIOACFGR register fields */ +#define RCC_GPIOACFGR_GPIOARST BIT(0) +#define RCC_GPIOACFGR_GPIOAEN BIT(1) +#define RCC_GPIOACFGR_GPIOALPEN BIT(2) + +/* RCC_GPIOBCFGR register fields */ +#define RCC_GPIOBCFGR_GPIOBRST BIT(0) +#define RCC_GPIOBCFGR_GPIOBEN BIT(1) +#define RCC_GPIOBCFGR_GPIOBLPEN BIT(2) + +/* RCC_GPIOCCFGR register fields */ +#define RCC_GPIOCCFGR_GPIOCRST BIT(0) +#define RCC_GPIOCCFGR_GPIOCEN BIT(1) +#define RCC_GPIOCCFGR_GPIOCLPEN BIT(2) + +/* RCC_GPIODCFGR register fields */ +#define RCC_GPIODCFGR_GPIODRST BIT(0) +#define RCC_GPIODCFGR_GPIODEN BIT(1) +#define RCC_GPIODCFGR_GPIODLPEN BIT(2) + +/* RCC_GPIOECFGR register fields */ +#define RCC_GPIOECFGR_GPIOERST BIT(0) +#define RCC_GPIOECFGR_GPIOEEN BIT(1) +#define RCC_GPIOECFGR_GPIOELPEN BIT(2) + +/* RCC_GPIOFCFGR register fields */ +#define RCC_GPIOFCFGR_GPIOFRST BIT(0) +#define RCC_GPIOFCFGR_GPIOFEN BIT(1) +#define RCC_GPIOFCFGR_GPIOFLPEN BIT(2) + +/* RCC_GPIOGCFGR register fields */ +#define RCC_GPIOGCFGR_GPIOGRST BIT(0) +#define RCC_GPIOGCFGR_GPIOGEN BIT(1) +#define RCC_GPIOGCFGR_GPIOGLPEN BIT(2) + +/* RCC_GPIOHCFGR register fields */ +#define RCC_GPIOHCFGR_GPIOHRST BIT(0) +#define RCC_GPIOHCFGR_GPIOHEN BIT(1) +#define RCC_GPIOHCFGR_GPIOHLPEN BIT(2) + +/* RCC_GPIOICFGR register fields */ +#define RCC_GPIOICFGR_GPIOIRST BIT(0) +#define RCC_GPIOICFGR_GPIOIEN BIT(1) +#define RCC_GPIOICFGR_GPIOILPEN BIT(2) + +/* RCC_GPIOJCFGR register fields */ +#define RCC_GPIOJCFGR_GPIOJRST BIT(0) +#define RCC_GPIOJCFGR_GPIOJEN BIT(1) +#define RCC_GPIOJCFGR_GPIOJLPEN BIT(2) + +/* RCC_GPIOKCFGR register fields */ +#define RCC_GPIOKCFGR_GPIOKRST BIT(0) +#define RCC_GPIOKCFGR_GPIOKEN BIT(1) +#define RCC_GPIOKCFGR_GPIOKLPEN BIT(2) + +/* RCC_GPIOZCFGR register fields */ +#define RCC_GPIOZCFGR_GPIOZRST BIT(0) +#define RCC_GPIOZCFGR_GPIOZEN BIT(1) +#define RCC_GPIOZCFGR_GPIOZLPEN BIT(2) +#define RCC_GPIOZCFGR_GPIOZAMEN BIT(3) + +/* RCC_GPIOxCFGR register fields */ +#define RCC_GPIOxCFGR_GPIOxRST BIT(0) +#define RCC_GPIOxCFGR_GPIOxEN BIT(1) +#define RCC_GPIOxCFGR_GPIOxLPEN BIT(2) +#define RCC_GPIOxCFGR_GPIOxAMEN BIT(3) + +/* RCC_HPDMA1CFGR register fields */ +#define RCC_HPDMA1CFGR_HPDMA1RST BIT(0) +#define RCC_HPDMA1CFGR_HPDMA1EN BIT(1) +#define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2) + +/* RCC_HPDMA2CFGR register fields */ +#define RCC_HPDMA2CFGR_HPDMA2RST BIT(0) +#define RCC_HPDMA2CFGR_HPDMA2EN BIT(1) +#define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2) + +/* RCC_HPDMA3CFGR register fields */ +#define RCC_HPDMA3CFGR_HPDMA3RST BIT(0) +#define RCC_HPDMA3CFGR_HPDMA3EN BIT(1) +#define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2) + +/* RCC_HPDMAxCFGR register fields */ +#define RCC_HPDMAxCFGR_HPDMAxRST BIT(0) +#define RCC_HPDMAxCFGR_HPDMAxEN BIT(1) +#define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2) + +/* RCC_LPDMACFGR register fields */ +#define RCC_LPDMACFGR_LPDMARST BIT(0) +#define RCC_LPDMACFGR_LPDMAEN BIT(1) +#define RCC_LPDMACFGR_LPDMALPEN BIT(2) +#define RCC_LPDMACFGR_LPDMAAMEN BIT(3) + +/* RCC_HSEMCFGR register fields */ +#define RCC_HSEMCFGR_HSEMRST BIT(0) +#define RCC_HSEMCFGR_HSEMEN BIT(1) +#define RCC_HSEMCFGR_HSEMLPEN BIT(2) +#define RCC_HSEMCFGR_HSEMAMEN BIT(3) + +/* RCC_IPCC1CFGR register fields */ +#define RCC_IPCC1CFGR_IPCC1RST BIT(0) +#define RCC_IPCC1CFGR_IPCC1EN BIT(1) +#define RCC_IPCC1CFGR_IPCC1LPEN BIT(2) + +/* RCC_IPCC2CFGR register fields */ +#define RCC_IPCC2CFGR_IPCC2RST BIT(0) +#define RCC_IPCC2CFGR_IPCC2EN BIT(1) +#define RCC_IPCC2CFGR_IPCC2LPEN BIT(2) +#define RCC_IPCC2CFGR_IPCC2AMEN BIT(3) + +/* RCC_RTCCFGR register fields */ +#define RCC_RTCCFGR_RTCEN BIT(1) +#define RCC_RTCCFGR_RTCLPEN BIT(2) +#define RCC_RTCCFGR_RTCAMEN BIT(3) + +/* RCC_SYSCPU1CFGR register fields */ +#define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1) +#define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2) + +/* RCC_BSECCFGR register fields */ +#define RCC_BSECCFGR_BSECEN BIT(1) +#define RCC_BSECCFGR_BSECLPEN BIT(2) + +/* RCC_IS2MCFGR register fields */ +#define RCC_IS2MCFGR_IS2MRST BIT(0) +#define RCC_IS2MCFGR_IS2MEN BIT(1) +#define RCC_IS2MCFGR_IS2MLPEN BIT(2) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_SSMODRST BIT(0) +#define RCC_PLL2CFGR1_PLLEN BIT(8) +#define RCC_PLL2CFGR1_PLLRDY BIT(24) +#define RCC_PLL2CFGR1_CKREFST BIT(28) + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL2CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL2CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL2CFGR3 register fields */ +#define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL2CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL2CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL2CFGR3_DACEN BIT(25) +#define RCC_PLL2CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL2CFGR4 register fields */ +#define RCC_PLL2CFGR4_DSMEN BIT(8) +#define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL2CFGR4_BYPASS BIT(10) + +/* RCC_PLL2CFGR5 register fields */ +#define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL2CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL2CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL2CFGR6 register fields */ +#define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL2CFGR7 register fields */ +#define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_SSMODRST BIT(0) +#define RCC_PLL3CFGR1_PLLEN BIT(8) +#define RCC_PLL3CFGR1_PLLRDY BIT(24) +#define RCC_PLL3CFGR1_CKREFST BIT(28) + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL3CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL3CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL3CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL3CFGR3 register fields */ +#define RCC_PLL3CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL3CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL3CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL3CFGR3_DACEN BIT(25) +#define RCC_PLL3CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL3CFGR4 register fields */ +#define RCC_PLL3CFGR4_DSMEN BIT(8) +#define RCC_PLL3CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL3CFGR4_BYPASS BIT(10) + +/* RCC_PLL3CFGR5 register fields */ +#define RCC_PLL3CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL3CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL3CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL3CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL3CFGR6 register fields */ +#define RCC_PLL3CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL3CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL3CFGR7 register fields */ +#define RCC_PLL3CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL3CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLLxCFGR1 register fields */ +#define RCC_PLLxCFGR1_SSMODRST BIT(0) +#define RCC_PLLxCFGR1_PLLEN BIT(8) +#define RCC_PLLxCFGR1_PLLRDY BIT(24) +#define RCC_PLLxCFGR1_CKREFST BIT(28) + +/* RCC_PLLxCFGR2 register fields */ +#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 +#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLLxCFGR2_FBDIV_SHIFT 16 + +/* RCC_PLLxCFGR3 register fields */ +#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLLxCFGR3_FRACIN_SHIFT 0 +#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) +#define RCC_PLLxCFGR3_DACEN BIT(25) +#define RCC_PLLxCFGR3_SSCGDIS BIT(26) + +/* RCC_PLLxCFGR4 register fields */ +#define RCC_PLLxCFGR4_DSMEN BIT(8) +#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLLxCFGR4_BYPASS BIT(10) + +/* RCC_PLLxCFGR5 register fields */ +#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 +#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLLxCFGR5_SPREAD_SHIFT 16 + +/* RCC_PLLxCFGR6 register fields */ +#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLLxCFGR7 register fields */ +#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 + +/* RCC_HSIFMONCR register fields */ +#define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0) +#define RCC_HSIFMONCR_HSIREF_SHIFT 0 +#define RCC_HSIFMONCR_HSIMONEN BIT(15) +#define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16) +#define RCC_HSIFMONCR_HSIDEV_SHIFT 16 +#define RCC_HSIFMONCR_HSIMONIE BIT(30) +#define RCC_HSIFMONCR_HSIMONF BIT(31) + +/* RCC_HSIFVALR register fields */ +#define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0) +#define RCC_HSIFVALR_HSIVAL_SHIFT 0 + +/* RCC_TIM1CFGR register fields */ +#define RCC_TIM1CFGR_TIM1RST BIT(0) +#define RCC_TIM1CFGR_TIM1EN BIT(1) +#define RCC_TIM1CFGR_TIM1LPEN BIT(2) + +/* RCC_TIM2CFGR register fields */ +#define RCC_TIM2CFGR_TIM2RST BIT(0) +#define RCC_TIM2CFGR_TIM2EN BIT(1) +#define RCC_TIM2CFGR_TIM2LPEN BIT(2) + +/* RCC_TIM3CFGR register fields */ +#define RCC_TIM3CFGR_TIM3RST BIT(0) +#define RCC_TIM3CFGR_TIM3EN BIT(1) +#define RCC_TIM3CFGR_TIM3LPEN BIT(2) + +/* RCC_TIM4CFGR register fields */ +#define RCC_TIM4CFGR_TIM4RST BIT(0) +#define RCC_TIM4CFGR_TIM4EN BIT(1) +#define RCC_TIM4CFGR_TIM4LPEN BIT(2) + +/* RCC_TIM5CFGR register fields */ +#define RCC_TIM5CFGR_TIM5RST BIT(0) +#define RCC_TIM5CFGR_TIM5EN BIT(1) +#define RCC_TIM5CFGR_TIM5LPEN BIT(2) + +/* RCC_TIM6CFGR register fields */ +#define RCC_TIM6CFGR_TIM6RST BIT(0) +#define RCC_TIM6CFGR_TIM6EN BIT(1) +#define RCC_TIM6CFGR_TIM6LPEN BIT(2) + +/* RCC_TIM7CFGR register fields */ +#define RCC_TIM7CFGR_TIM7RST BIT(0) +#define RCC_TIM7CFGR_TIM7EN BIT(1) +#define RCC_TIM7CFGR_TIM7LPEN BIT(2) + +/* RCC_TIM8CFGR register fields */ +#define RCC_TIM8CFGR_TIM8RST BIT(0) +#define RCC_TIM8CFGR_TIM8EN BIT(1) +#define RCC_TIM8CFGR_TIM8LPEN BIT(2) + +/* RCC_TIM10CFGR register fields */ +#define RCC_TIM10CFGR_TIM10RST BIT(0) +#define RCC_TIM10CFGR_TIM10EN BIT(1) +#define RCC_TIM10CFGR_TIM10LPEN BIT(2) + +/* RCC_TIM11CFGR register fields */ +#define RCC_TIM11CFGR_TIM11RST BIT(0) +#define RCC_TIM11CFGR_TIM11EN BIT(1) +#define RCC_TIM11CFGR_TIM11LPEN BIT(2) + +/* RCC_TIM12CFGR register fields */ +#define RCC_TIM12CFGR_TIM12RST BIT(0) +#define RCC_TIM12CFGR_TIM12EN BIT(1) +#define RCC_TIM12CFGR_TIM12LPEN BIT(2) + +/* RCC_TIM13CFGR register fields */ +#define RCC_TIM13CFGR_TIM13RST BIT(0) +#define RCC_TIM13CFGR_TIM13EN BIT(1) +#define RCC_TIM13CFGR_TIM13LPEN BIT(2) + +/* RCC_TIM14CFGR register fields */ +#define RCC_TIM14CFGR_TIM14RST BIT(0) +#define RCC_TIM14CFGR_TIM14EN BIT(1) +#define RCC_TIM14CFGR_TIM14LPEN BIT(2) + +/* RCC_TIM15CFGR register fields */ +#define RCC_TIM15CFGR_TIM15RST BIT(0) +#define RCC_TIM15CFGR_TIM15EN BIT(1) +#define RCC_TIM15CFGR_TIM15LPEN BIT(2) + +/* RCC_TIM16CFGR register fields */ +#define RCC_TIM16CFGR_TIM16RST BIT(0) +#define RCC_TIM16CFGR_TIM16EN BIT(1) +#define RCC_TIM16CFGR_TIM16LPEN BIT(2) + +/* RCC_TIM17CFGR register fields */ +#define RCC_TIM17CFGR_TIM17RST BIT(0) +#define RCC_TIM17CFGR_TIM17EN BIT(1) +#define RCC_TIM17CFGR_TIM17LPEN BIT(2) + +/* RCC_TIM20CFGR register fields */ +#define RCC_TIM20CFGR_TIM20RST BIT(0) +#define RCC_TIM20CFGR_TIM20EN BIT(1) +#define RCC_TIM20CFGR_TIM20LPEN BIT(2) + +/* RCC_LPTIM1CFGR register fields */ +#define RCC_LPTIM1CFGR_LPTIM1RST BIT(0) +#define RCC_LPTIM1CFGR_LPTIM1EN BIT(1) +#define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2) + +/* RCC_LPTIM2CFGR register fields */ +#define RCC_LPTIM2CFGR_LPTIM2RST BIT(0) +#define RCC_LPTIM2CFGR_LPTIM2EN BIT(1) +#define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2) + +/* RCC_LPTIM3CFGR register fields */ +#define RCC_LPTIM3CFGR_LPTIM3RST BIT(0) +#define RCC_LPTIM3CFGR_LPTIM3EN BIT(1) +#define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2) +#define RCC_LPTIM3CFGR_LPTIM3AMEN BIT(3) + +/* RCC_LPTIM4CFGR register fields */ +#define RCC_LPTIM4CFGR_LPTIM4RST BIT(0) +#define RCC_LPTIM4CFGR_LPTIM4EN BIT(1) +#define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2) +#define RCC_LPTIM4CFGR_LPTIM4AMEN BIT(3) + +/* RCC_LPTIM5CFGR register fields */ +#define RCC_LPTIM5CFGR_LPTIM5RST BIT(0) +#define RCC_LPTIM5CFGR_LPTIM5EN BIT(1) +#define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2) +#define RCC_LPTIM5CFGR_LPTIM5AMEN BIT(3) + +/* RCC_LPTIMxCFGR register fields */ +#define RCC_LPTIMxCFGR_LPTIMxRST BIT(0) +#define RCC_LPTIMxCFGR_LPTIMxEN BIT(1) +#define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2) +#define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3) + +/* RCC_SPI1CFGR register fields */ +#define RCC_SPI1CFGR_SPI1RST BIT(0) +#define RCC_SPI1CFGR_SPI1EN BIT(1) +#define RCC_SPI1CFGR_SPI1LPEN BIT(2) + +/* RCC_SPI2CFGR register fields */ +#define RCC_SPI2CFGR_SPI2RST BIT(0) +#define RCC_SPI2CFGR_SPI2EN BIT(1) +#define RCC_SPI2CFGR_SPI2LPEN BIT(2) + +/* RCC_SPI3CFGR register fields */ +#define RCC_SPI3CFGR_SPI3RST BIT(0) +#define RCC_SPI3CFGR_SPI3EN BIT(1) +#define RCC_SPI3CFGR_SPI3LPEN BIT(2) + +/* RCC_SPI4CFGR register fields */ +#define RCC_SPI4CFGR_SPI4RST BIT(0) +#define RCC_SPI4CFGR_SPI4EN BIT(1) +#define RCC_SPI4CFGR_SPI4LPEN BIT(2) + +/* RCC_SPI5CFGR register fields */ +#define RCC_SPI5CFGR_SPI5RST BIT(0) +#define RCC_SPI5CFGR_SPI5EN BIT(1) +#define RCC_SPI5CFGR_SPI5LPEN BIT(2) + +/* RCC_SPI6CFGR register fields */ +#define RCC_SPI6CFGR_SPI6RST BIT(0) +#define RCC_SPI6CFGR_SPI6EN BIT(1) +#define RCC_SPI6CFGR_SPI6LPEN BIT(2) + +/* RCC_SPI7CFGR register fields */ +#define RCC_SPI7CFGR_SPI7RST BIT(0) +#define RCC_SPI7CFGR_SPI7EN BIT(1) +#define RCC_SPI7CFGR_SPI7LPEN BIT(2) + +/* RCC_SPI8CFGR register fields */ +#define RCC_SPI8CFGR_SPI8RST BIT(0) +#define RCC_SPI8CFGR_SPI8EN BIT(1) +#define RCC_SPI8CFGR_SPI8LPEN BIT(2) +#define RCC_SPI8CFGR_SPI8AMEN BIT(3) + +/* RCC_SPIxCFGR register fields */ +#define RCC_SPIxCFGR_SPIxRST BIT(0) +#define RCC_SPIxCFGR_SPIxEN BIT(1) +#define RCC_SPIxCFGR_SPIxLPEN BIT(2) +#define RCC_SPIxCFGR_SPIxAMEN BIT(3) + +/* RCC_SPDIFRXCFGR register fields */ +#define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0) +#define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1) +#define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2) + +/* RCC_USART1CFGR register fields */ +#define RCC_USART1CFGR_USART1RST BIT(0) +#define RCC_USART1CFGR_USART1EN BIT(1) +#define RCC_USART1CFGR_USART1LPEN BIT(2) + +/* RCC_USART2CFGR register fields */ +#define RCC_USART2CFGR_USART2RST BIT(0) +#define RCC_USART2CFGR_USART2EN BIT(1) +#define RCC_USART2CFGR_USART2LPEN BIT(2) + +/* RCC_USART3CFGR register fields */ +#define RCC_USART3CFGR_USART3RST BIT(0) +#define RCC_USART3CFGR_USART3EN BIT(1) +#define RCC_USART3CFGR_USART3LPEN BIT(2) + +/* RCC_UART4CFGR register fields */ +#define RCC_UART4CFGR_UART4RST BIT(0) +#define RCC_UART4CFGR_UART4EN BIT(1) +#define RCC_UART4CFGR_UART4LPEN BIT(2) + +/* RCC_UART5CFGR register fields */ +#define RCC_UART5CFGR_UART5RST BIT(0) +#define RCC_UART5CFGR_UART5EN BIT(1) +#define RCC_UART5CFGR_UART5LPEN BIT(2) + +/* RCC_USART6CFGR register fields */ +#define RCC_USART6CFGR_USART6RST BIT(0) +#define RCC_USART6CFGR_USART6EN BIT(1) +#define RCC_USART6CFGR_USART6LPEN BIT(2) + +/* RCC_UART7CFGR register fields */ +#define RCC_UART7CFGR_UART7RST BIT(0) +#define RCC_UART7CFGR_UART7EN BIT(1) +#define RCC_UART7CFGR_UART7LPEN BIT(2) + +/* RCC_UART8CFGR register fields */ +#define RCC_UART8CFGR_UART8RST BIT(0) +#define RCC_UART8CFGR_UART8EN BIT(1) +#define RCC_UART8CFGR_UART8LPEN BIT(2) + +/* RCC_UART9CFGR register fields */ +#define RCC_UART9CFGR_UART9RST BIT(0) +#define RCC_UART9CFGR_UART9EN BIT(1) +#define RCC_UART9CFGR_UART9LPEN BIT(2) + +/* RCC_USARTxCFGR register fields */ +#define RCC_USARTxCFGR_USARTxRST BIT(0) +#define RCC_USARTxCFGR_USARTxEN BIT(1) +#define RCC_USARTxCFGR_USARTxLPEN BIT(2) + +/* RCC_UARTxCFGR register fields */ +#define RCC_UARTxCFGR_UARTxRST BIT(0) +#define RCC_UARTxCFGR_UARTxEN BIT(1) +#define RCC_UARTxCFGR_UARTxLPEN BIT(2) + +/* RCC_LPUART1CFGR register fields */ +#define RCC_LPUART1CFGR_LPUART1RST BIT(0) +#define RCC_LPUART1CFGR_LPUART1EN BIT(1) +#define RCC_LPUART1CFGR_LPUART1LPEN BIT(2) +#define RCC_LPUART1CFGR_LPUART1AMEN BIT(3) + +/* RCC_I2C1CFGR register fields */ +#define RCC_I2C1CFGR_I2C1RST BIT(0) +#define RCC_I2C1CFGR_I2C1EN BIT(1) +#define RCC_I2C1CFGR_I2C1LPEN BIT(2) + +/* RCC_I2C2CFGR register fields */ +#define RCC_I2C2CFGR_I2C2RST BIT(0) +#define RCC_I2C2CFGR_I2C2EN BIT(1) +#define RCC_I2C2CFGR_I2C2LPEN BIT(2) + +/* RCC_I2C3CFGR register fields */ +#define RCC_I2C3CFGR_I2C3RST BIT(0) +#define RCC_I2C3CFGR_I2C3EN BIT(1) +#define RCC_I2C3CFGR_I2C3LPEN BIT(2) + +/* RCC_I2C4CFGR register fields */ +#define RCC_I2C4CFGR_I2C4RST BIT(0) +#define RCC_I2C4CFGR_I2C4EN BIT(1) +#define RCC_I2C4CFGR_I2C4LPEN BIT(2) + +/* RCC_I2C5CFGR register fields */ +#define RCC_I2C5CFGR_I2C5RST BIT(0) +#define RCC_I2C5CFGR_I2C5EN BIT(1) +#define RCC_I2C5CFGR_I2C5LPEN BIT(2) + +/* RCC_I2C6CFGR register fields */ +#define RCC_I2C6CFGR_I2C6RST BIT(0) +#define RCC_I2C6CFGR_I2C6EN BIT(1) +#define RCC_I2C6CFGR_I2C6LPEN BIT(2) + +/* RCC_I2C7CFGR register fields */ +#define RCC_I2C7CFGR_I2C7RST BIT(0) +#define RCC_I2C7CFGR_I2C7EN BIT(1) +#define RCC_I2C7CFGR_I2C7LPEN BIT(2) + +/* RCC_I2C8CFGR register fields */ +#define RCC_I2C8CFGR_I2C8RST BIT(0) +#define RCC_I2C8CFGR_I2C8EN BIT(1) +#define RCC_I2C8CFGR_I2C8LPEN BIT(2) +#define RCC_I2C8CFGR_I2C8AMEN BIT(3) + +/* RCC_I2CxCFGR register fields */ +#define RCC_I2CxCFGR_I2CxRST BIT(0) +#define RCC_I2CxCFGR_I2CxEN BIT(1) +#define RCC_I2CxCFGR_I2CxLPEN BIT(2) +#define RCC_I2CxCFGR_I2CxAMEN BIT(3) + +/* RCC_SAI1CFGR register fields */ +#define RCC_SAI1CFGR_SAI1RST BIT(0) +#define RCC_SAI1CFGR_SAI1EN BIT(1) +#define RCC_SAI1CFGR_SAI1LPEN BIT(2) + +/* RCC_SAI2CFGR register fields */ +#define RCC_SAI2CFGR_SAI2RST BIT(0) +#define RCC_SAI2CFGR_SAI2EN BIT(1) +#define RCC_SAI2CFGR_SAI2LPEN BIT(2) + +/* RCC_SAI3CFGR register fields */ +#define RCC_SAI3CFGR_SAI3RST BIT(0) +#define RCC_SAI3CFGR_SAI3EN BIT(1) +#define RCC_SAI3CFGR_SAI3LPEN BIT(2) + +/* RCC_SAI4CFGR register fields */ +#define RCC_SAI4CFGR_SAI4RST BIT(0) +#define RCC_SAI4CFGR_SAI4EN BIT(1) +#define RCC_SAI4CFGR_SAI4LPEN BIT(2) + +/* RCC_SAIxCFGR register fields */ +#define RCC_SAIxCFGR_SAIxRST BIT(0) +#define RCC_SAIxCFGR_SAIxEN BIT(1) +#define RCC_SAIxCFGR_SAIxLPEN BIT(2) + +/* RCC_MDF1CFGR register fields */ +#define RCC_MDF1CFGR_MDF1RST BIT(0) +#define RCC_MDF1CFGR_MDF1EN BIT(1) +#define RCC_MDF1CFGR_MDF1LPEN BIT(2) + +/* RCC_ADF1CFGR register fields */ +#define RCC_ADF1CFGR_ADF1RST BIT(0) +#define RCC_ADF1CFGR_ADF1EN BIT(1) +#define RCC_ADF1CFGR_ADF1LPEN BIT(2) +#define RCC_ADF1CFGR_ADF1AMEN BIT(3) + +/* RCC_FDCANCFGR register fields */ +#define RCC_FDCANCFGR_FDCANRST BIT(0) +#define RCC_FDCANCFGR_FDCANEN BIT(1) +#define RCC_FDCANCFGR_FDCANLPEN BIT(2) + +/* RCC_HDPCFGR register fields */ +#define RCC_HDPCFGR_HDPRST BIT(0) +#define RCC_HDPCFGR_HDPEN BIT(1) + +/* RCC_ADC12CFGR register fields */ +#define RCC_ADC12CFGR_ADC12RST BIT(0) +#define RCC_ADC12CFGR_ADC12EN BIT(1) +#define RCC_ADC12CFGR_ADC12LPEN BIT(2) +#define RCC_ADC12CFGR_ADC12KERSEL BIT(12) + +/* RCC_ADC3CFGR register fields */ +#define RCC_ADC3CFGR_ADC3RST BIT(0) +#define RCC_ADC3CFGR_ADC3EN BIT(1) +#define RCC_ADC3CFGR_ADC3LPEN BIT(2) +#define RCC_ADC3CFGR_ADC3KERSEL_MASK GENMASK_32(13, 12) +#define RCC_ADC3CFGR_ADC3KERSEL_SHIFT 12 + +/* RCC_ETH1CFGR register fields */ +#define RCC_ETH1CFGR_ETH1RST BIT(0) +#define RCC_ETH1CFGR_ETH1MACEN BIT(1) +#define RCC_ETH1CFGR_ETH1MACLPEN BIT(2) +#define RCC_ETH1CFGR_ETH1STPEN BIT(4) +#define RCC_ETH1CFGR_ETH1EN BIT(5) +#define RCC_ETH1CFGR_ETH1LPEN BIT(6) +#define RCC_ETH1CFGR_ETH1TXEN BIT(8) +#define RCC_ETH1CFGR_ETH1TXLPEN BIT(9) +#define RCC_ETH1CFGR_ETH1RXEN BIT(10) +#define RCC_ETH1CFGR_ETH1RXLPEN BIT(11) + +/* RCC_ETH2CFGR register fields */ +#define RCC_ETH2CFGR_ETH2RST BIT(0) +#define RCC_ETH2CFGR_ETH2MACEN BIT(1) +#define RCC_ETH2CFGR_ETH2MACLPEN BIT(2) +#define RCC_ETH2CFGR_ETH2STPEN BIT(4) +#define RCC_ETH2CFGR_ETH2EN BIT(5) +#define RCC_ETH2CFGR_ETH2LPEN BIT(6) +#define RCC_ETH2CFGR_ETH2TXEN BIT(8) +#define RCC_ETH2CFGR_ETH2TXLPEN BIT(9) +#define RCC_ETH2CFGR_ETH2RXEN BIT(10) +#define RCC_ETH2CFGR_ETH2RXLPEN BIT(11) + +/* RCC_ETHxCFGR register fields */ +#define RCC_ETHxCFGR_ETHxRST BIT(0) +#define RCC_ETHxCFGR_ETHxMACEN BIT(1) +#define RCC_ETHxCFGR_ETHxMACLPEN BIT(2) +#define RCC_ETHxCFGR_ETHxSTPEN BIT(4) +#define RCC_ETHxCFGR_ETHxEN BIT(5) +#define RCC_ETHxCFGR_ETHxLPEN BIT(6) +#define RCC_ETHxCFGR_ETHxTXEN BIT(8) +#define RCC_ETHxCFGR_ETHxTXLPEN BIT(9) +#define RCC_ETHxCFGR_ETHxRXEN BIT(10) +#define RCC_ETHxCFGR_ETHxRXLPEN BIT(11) + +/* RCC_USB2CFGR register fields */ +#define RCC_USB2CFGR_USB2RST BIT(0) +#define RCC_USB2CFGR_USB2EN BIT(1) +#define RCC_USB2CFGR_USB2LPEN BIT(2) +#define RCC_USB2CFGR_USB2STPEN BIT(4) + +/* RCC_USB2PHY1CFGR register fields */ +#define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0) +#define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1) +#define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2) +#define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4) +#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15) + +/* RCC_USB2PHY2CFGR register fields */ +#define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0) +#define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1) +#define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2) +#define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4) +#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15) + +/* RCC_USB2PHYxCFGR register fields */ +#define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0) +#define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1) +#define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2) +#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4) +#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15) + +/* RCC_USB3DRDCFGR register fields */ +#define RCC_USB3DRDCFGR_USB3DRDRST BIT(0) +#define RCC_USB3DRDCFGR_USB3DRDEN BIT(1) +#define RCC_USB3DRDCFGR_USB3DRDLPEN BIT(2) +#define RCC_USB3DRDCFGR_USB3DRDSTPEN BIT(4) + +/* RCC_USB3PCIEPHYCFGR register fields */ +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYRST BIT(0) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYEN BIT(1) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYLPEN BIT(2) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYSTPEN BIT(4) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYCKREFSEL BIT(15) + +/* RCC_PCIECFGR register fields */ +#define RCC_PCIECFGR_PCIERST BIT(0) +#define RCC_PCIECFGR_PCIEEN BIT(1) +#define RCC_PCIECFGR_PCIELPEN BIT(2) +#define RCC_PCIECFGR_PCIESTPEN BIT(4) + +/* RCC_USBTCCFGR register fields */ +#define RCC_USBTCCFGR_USBTCRST BIT(0) +#define RCC_USBTCCFGR_USBTCEN BIT(1) +#define RCC_USBTCCFGR_USBTCLPEN BIT(2) + +/* RCC_ETHSWCFGR register fields */ +#define RCC_ETHSWCFGR_ETHSWRST BIT(0) +#define RCC_ETHSWCFGR_ETHSWMACEN BIT(1) +#define RCC_ETHSWCFGR_ETHSWMACLPEN BIT(2) +#define RCC_ETHSWCFGR_ETHSWEN BIT(5) +#define RCC_ETHSWCFGR_ETHSWLPEN BIT(6) +#define RCC_ETHSWCFGR_ETHSWREFEN BIT(21) +#define RCC_ETHSWCFGR_ETHSWREFLPEN BIT(22) + +/* RCC_ETHSWACMCFGR register fields */ +#define RCC_ETHSWACMCFGR_ETHSWACMEN BIT(1) +#define RCC_ETHSWACMCFGR_ETHSWACMLPEN BIT(2) + +/* RCC_ETHSWACMMSGCFGR register fields */ +#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGEN BIT(1) +#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGLPEN BIT(2) + +/* RCC_STGENCFGR register fields */ +#define RCC_STGENCFGR_STGENEN BIT(1) +#define RCC_STGENCFGR_STGENLPEN BIT(2) +#define RCC_STGENCFGR_STGENSTPEN BIT(4) + +/* RCC_SDMMC1CFGR register fields */ +#define RCC_SDMMC1CFGR_SDMMC1RST BIT(0) +#define RCC_SDMMC1CFGR_SDMMC1EN BIT(1) +#define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2) +#define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16) + +/* RCC_SDMMC2CFGR register fields */ +#define RCC_SDMMC2CFGR_SDMMC2RST BIT(0) +#define RCC_SDMMC2CFGR_SDMMC2EN BIT(1) +#define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2) +#define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16) + +/* RCC_SDMMC3CFGR register fields */ +#define RCC_SDMMC3CFGR_SDMMC3RST BIT(0) +#define RCC_SDMMC3CFGR_SDMMC3EN BIT(1) +#define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2) +#define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16) + +/* RCC_SDMMCxCFGR register fields */ +#define RCC_SDMMCxCFGR_SDMMC1RST BIT(0) +#define RCC_SDMMCxCFGR_SDMMC1EN BIT(1) +#define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2) +#define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16) + +/* RCC_GPUCFGR register fields */ +#define RCC_GPUCFGR_GPURST BIT(0) +#define RCC_GPUCFGR_GPUEN BIT(1) +#define RCC_GPUCFGR_GPULPEN BIT(2) + +/* RCC_LTDCCFGR register fields */ +#define RCC_LTDCCFGR_LTDCRST BIT(0) +#define RCC_LTDCCFGR_LTDCEN BIT(1) +#define RCC_LTDCCFGR_LTDCLPEN BIT(2) + +/* RCC_DSICFGR register fields */ +#define RCC_DSICFGR_DSIRST BIT(0) +#define RCC_DSICFGR_DSIEN BIT(1) +#define RCC_DSICFGR_DSILPEN BIT(2) +#define RCC_DSICFGR_DSIBLSEL BIT(12) +#define RCC_DSICFGR_DSIPHYCKREFSEL BIT(15) + +/* RCC_LVDSCFGR register fields */ +#define RCC_LVDSCFGR_LVDSRST BIT(0) +#define RCC_LVDSCFGR_LVDSEN BIT(1) +#define RCC_LVDSCFGR_LVDSLPEN BIT(2) +#define RCC_LVDSCFGR_LVDSPHYCKREFSEL BIT(15) + +/* RCC_CSI2CFGR register fields */ +#define RCC_CSI2CFGR_CSI2RST BIT(0) +#define RCC_CSI2CFGR_CSI2EN BIT(1) +#define RCC_CSI2CFGR_CSI2LPEN BIT(2) + +/* RCC_DCMIPPCFGR register fields */ +#define RCC_DCMIPPCFGR_DCMIPPRST BIT(0) +#define RCC_DCMIPPCFGR_DCMIPPEN BIT(1) +#define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2) + +/* RCC_CCICFGR register fields */ +#define RCC_CCICFGR_CCIRST BIT(0) +#define RCC_CCICFGR_CCIEN BIT(1) +#define RCC_CCICFGR_CCILPEN BIT(2) + +/* RCC_VDECCFGR register fields */ +#define RCC_VDECCFGR_VDECRST BIT(0) +#define RCC_VDECCFGR_VDECEN BIT(1) +#define RCC_VDECCFGR_VDECLPEN BIT(2) + +/* RCC_VENCCFGR register fields */ +#define RCC_VENCCFGR_VENCRST BIT(0) +#define RCC_VENCCFGR_VENCEN BIT(1) +#define RCC_VENCCFGR_VENCLPEN BIT(2) + +/* RCC_RNGCFGR register fields */ +#define RCC_RNGCFGR_RNGRST BIT(0) +#define RCC_RNGCFGR_RNGEN BIT(1) +#define RCC_RNGCFGR_RNGLPEN BIT(2) + +/* RCC_PKACFGR register fields */ +#define RCC_PKACFGR_PKARST BIT(0) +#define RCC_PKACFGR_PKAEN BIT(1) +#define RCC_PKACFGR_PKALPEN BIT(2) + +/* RCC_SAESCFGR register fields */ +#define RCC_SAESCFGR_SAESRST BIT(0) +#define RCC_SAESCFGR_SAESEN BIT(1) +#define RCC_SAESCFGR_SAESLPEN BIT(2) + +/* RCC_HASHCFGR register fields */ +#define RCC_HASHCFGR_HASHRST BIT(0) +#define RCC_HASHCFGR_HASHEN BIT(1) +#define RCC_HASHCFGR_HASHLPEN BIT(2) + +/* RCC_CRYP1CFGR register fields */ +#define RCC_CRYP1CFGR_CRYP1RST BIT(0) +#define RCC_CRYP1CFGR_CRYP1EN BIT(1) +#define RCC_CRYP1CFGR_CRYP1LPEN BIT(2) + +/* RCC_CRYP2CFGR register fields */ +#define RCC_CRYP2CFGR_CRYP2RST BIT(0) +#define RCC_CRYP2CFGR_CRYP2EN BIT(1) +#define RCC_CRYP2CFGR_CRYP2LPEN BIT(2) + +/* RCC_CRYPxCFGR register fields */ +#define RCC_CRYPxCFGR_CRYPxRST BIT(0) +#define RCC_CRYPxCFGR_CRYPxEN BIT(1) +#define RCC_CRYPxCFGR_CRYPxLPEN BIT(2) + +/* RCC_IWDG1CFGR register fields */ +#define RCC_IWDG1CFGR_IWDG1EN BIT(1) +#define RCC_IWDG1CFGR_IWDG1LPEN BIT(2) + +/* RCC_IWDG2CFGR register fields */ +#define RCC_IWDG2CFGR_IWDG2EN BIT(1) +#define RCC_IWDG2CFGR_IWDG2LPEN BIT(2) + +/* RCC_IWDG3CFGR register fields */ +#define RCC_IWDG3CFGR_IWDG3EN BIT(1) +#define RCC_IWDG3CFGR_IWDG3LPEN BIT(2) + +/* RCC_IWDG4CFGR register fields */ +#define RCC_IWDG4CFGR_IWDG4EN BIT(1) +#define RCC_IWDG4CFGR_IWDG4LPEN BIT(2) + +/* RCC_IWDGxCFGR register fields */ +#define RCC_IWDGxCFGR_IWDGxEN BIT(1) +#define RCC_IWDGxCFGR_IWDGxLPEN BIT(2) + +/* RCC_IWDG5CFGR register fields */ +#define RCC_IWDG5CFGR_IWDG5EN BIT(1) +#define RCC_IWDG5CFGR_IWDG5LPEN BIT(2) +#define RCC_IWDG5CFGR_IWDG5AMEN BIT(3) + +/* RCC_WWDG1CFGR register fields */ +#define RCC_WWDG1CFGR_WWDG1RST BIT(0) +#define RCC_WWDG1CFGR_WWDG1EN BIT(1) +#define RCC_WWDG1CFGR_WWDG1LPEN BIT(2) + +/* RCC_WWDG2CFGR register fields */ +#define RCC_WWDG2CFGR_WWDG2RST BIT(0) +#define RCC_WWDG2CFGR_WWDG2EN BIT(1) +#define RCC_WWDG2CFGR_WWDG2LPEN BIT(2) +#define RCC_WWDG2CFGR_WWDG2AMEN BIT(3) + +/* RCC_BUSPERFMCFGR register fields */ +#define RCC_BUSPERFMCFGR_BUSPERFMRST BIT(0) +#define RCC_BUSPERFMCFGR_BUSPERFMEN BIT(1) +#define RCC_BUSPERFMCFGR_BUSPERFMLPEN BIT(2) + +/* RCC_VREFCFGR register fields */ +#define RCC_VREFCFGR_VREFRST BIT(0) +#define RCC_VREFCFGR_VREFEN BIT(1) +#define RCC_VREFCFGR_VREFLPEN BIT(2) + +/* RCC_TMPSENSCFGR register fields */ +#define RCC_TMPSENSCFGR_TMPSENSRST BIT(0) +#define RCC_TMPSENSCFGR_TMPSENSEN BIT(1) +#define RCC_TMPSENSCFGR_TMPSENSLPEN BIT(2) +#define RCC_TMPSENSCFGR_TMPSENSKERSEL_MASK GENMASK_32(13, 12) +#define RCC_TMPSENSCFGR_TMPSENSKERSEL_SHIFT 12 + +/* RCC_CRCCFGR register fields */ +#define RCC_CRCCFGR_CRCRST BIT(0) +#define RCC_CRCCFGR_CRCEN BIT(1) +#define RCC_CRCCFGR_CRCLPEN BIT(2) + +/* RCC_SERCCFGR register fields */ +#define RCC_SERCCFGR_SERCRST BIT(0) +#define RCC_SERCCFGR_SERCEN BIT(1) +#define RCC_SERCCFGR_SERCLPEN BIT(2) + +/* RCC_OSPIIOMCFGR register fields */ +#define RCC_OSPIIOMCFGR_OSPIIOMRST BIT(0) +#define RCC_OSPIIOMCFGR_OSPIIOMEN BIT(1) +#define RCC_OSPIIOMCFGR_OSPIIOMLPEN BIT(2) + +/* RCC_GICV2MCFGR register fields */ +#define RCC_GICV2MCFGR_GICV2MEN BIT(1) +#define RCC_GICV2MCFGR_GICV2MLPEN BIT(2) + +/* RCC_I3C1CFGR register fields */ +#define RCC_I3C1CFGR_I3C1RST BIT(0) +#define RCC_I3C1CFGR_I3C1EN BIT(1) +#define RCC_I3C1CFGR_I3C1LPEN BIT(2) + +/* RCC_I3C2CFGR register fields */ +#define RCC_I3C2CFGR_I3C2RST BIT(0) +#define RCC_I3C2CFGR_I3C2EN BIT(1) +#define RCC_I3C2CFGR_I3C2LPEN BIT(2) + +/* RCC_I3C3CFGR register fields */ +#define RCC_I3C3CFGR_I3C3RST BIT(0) +#define RCC_I3C3CFGR_I3C3EN BIT(1) +#define RCC_I3C3CFGR_I3C3LPEN BIT(2) + +/* RCC_I3C4CFGR register fields */ +#define RCC_I3C4CFGR_I3C4RST BIT(0) +#define RCC_I3C4CFGR_I3C4EN BIT(1) +#define RCC_I3C4CFGR_I3C4LPEN BIT(2) +#define RCC_I3C4CFGR_I3C4AMEN BIT(3) + +/* RCC_I3CxCFGR register fields */ +#define RCC_I3CxCFGR_I3CxRST BIT(0) +#define RCC_I3CxCFGR_I3CxEN BIT(1) +#define RCC_I3CxCFGR_I3CxLPEN BIT(2) +#define RCC_I3CxCFGR_I3CxAMEN BIT(3) + +/* RCC_MUXSELCFGR register fields */ +#define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(1, 0) +#define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0 +#define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(5, 4) +#define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4 +#define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(9, 8) +#define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8 +#define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(13, 12) +#define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12 +#define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(17, 16) +#define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16 +#define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20) +#define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20 +#define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24) +#define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24 +#define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28) +#define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28 + +/* RCC_XBAR0CFGR register fields */ +#define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0 +#define RCC_XBAR0CFGR_XBAR0EN BIT(6) +#define RCC_XBAR0CFGR_XBAR0STS BIT(7) + +/* RCC_XBAR1CFGR register fields */ +#define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0 +#define RCC_XBAR1CFGR_XBAR1EN BIT(6) +#define RCC_XBAR1CFGR_XBAR1STS BIT(7) + +/* RCC_XBAR2CFGR register fields */ +#define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0 +#define RCC_XBAR2CFGR_XBAR2EN BIT(6) +#define RCC_XBAR2CFGR_XBAR2STS BIT(7) + +/* RCC_XBAR3CFGR register fields */ +#define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0 +#define RCC_XBAR3CFGR_XBAR3EN BIT(6) +#define RCC_XBAR3CFGR_XBAR3STS BIT(7) + +/* RCC_XBAR4CFGR register fields */ +#define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0 +#define RCC_XBAR4CFGR_XBAR4EN BIT(6) +#define RCC_XBAR4CFGR_XBAR4STS BIT(7) + +/* RCC_XBAR5CFGR register fields */ +#define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0 +#define RCC_XBAR5CFGR_XBAR5EN BIT(6) +#define RCC_XBAR5CFGR_XBAR5STS BIT(7) + +/* RCC_XBAR6CFGR register fields */ +#define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0 +#define RCC_XBAR6CFGR_XBAR6EN BIT(6) +#define RCC_XBAR6CFGR_XBAR6STS BIT(7) + +/* RCC_XBAR7CFGR register fields */ +#define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0 +#define RCC_XBAR7CFGR_XBAR7EN BIT(6) +#define RCC_XBAR7CFGR_XBAR7STS BIT(7) + +/* RCC_XBAR8CFGR register fields */ +#define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0 +#define RCC_XBAR8CFGR_XBAR8EN BIT(6) +#define RCC_XBAR8CFGR_XBAR8STS BIT(7) + +/* RCC_XBAR9CFGR register fields */ +#define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0 +#define RCC_XBAR9CFGR_XBAR9EN BIT(6) +#define RCC_XBAR9CFGR_XBAR9STS BIT(7) + +/* RCC_XBAR10CFGR register fields */ +#define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0 +#define RCC_XBAR10CFGR_XBAR10EN BIT(6) +#define RCC_XBAR10CFGR_XBAR10STS BIT(7) + +/* RCC_XBAR11CFGR register fields */ +#define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0 +#define RCC_XBAR11CFGR_XBAR11EN BIT(6) +#define RCC_XBAR11CFGR_XBAR11STS BIT(7) + +/* RCC_XBAR12CFGR register fields */ +#define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0 +#define RCC_XBAR12CFGR_XBAR12EN BIT(6) +#define RCC_XBAR12CFGR_XBAR12STS BIT(7) + +/* RCC_XBAR13CFGR register fields */ +#define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0 +#define RCC_XBAR13CFGR_XBAR13EN BIT(6) +#define RCC_XBAR13CFGR_XBAR13STS BIT(7) + +/* RCC_XBAR14CFGR register fields */ +#define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0 +#define RCC_XBAR14CFGR_XBAR14EN BIT(6) +#define RCC_XBAR14CFGR_XBAR14STS BIT(7) + +/* RCC_XBAR15CFGR register fields */ +#define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0 +#define RCC_XBAR15CFGR_XBAR15EN BIT(6) +#define RCC_XBAR15CFGR_XBAR15STS BIT(7) + +/* RCC_XBAR16CFGR register fields */ +#define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0 +#define RCC_XBAR16CFGR_XBAR16EN BIT(6) +#define RCC_XBAR16CFGR_XBAR16STS BIT(7) + +/* RCC_XBAR17CFGR register fields */ +#define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0 +#define RCC_XBAR17CFGR_XBAR17EN BIT(6) +#define RCC_XBAR17CFGR_XBAR17STS BIT(7) + +/* RCC_XBAR18CFGR register fields */ +#define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0 +#define RCC_XBAR18CFGR_XBAR18EN BIT(6) +#define RCC_XBAR18CFGR_XBAR18STS BIT(7) + +/* RCC_XBAR19CFGR register fields */ +#define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0 +#define RCC_XBAR19CFGR_XBAR19EN BIT(6) +#define RCC_XBAR19CFGR_XBAR19STS BIT(7) + +/* RCC_XBAR20CFGR register fields */ +#define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0 +#define RCC_XBAR20CFGR_XBAR20EN BIT(6) +#define RCC_XBAR20CFGR_XBAR20STS BIT(7) + +/* RCC_XBAR21CFGR register fields */ +#define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0 +#define RCC_XBAR21CFGR_XBAR21EN BIT(6) +#define RCC_XBAR21CFGR_XBAR21STS BIT(7) + +/* RCC_XBAR22CFGR register fields */ +#define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0 +#define RCC_XBAR22CFGR_XBAR22EN BIT(6) +#define RCC_XBAR22CFGR_XBAR22STS BIT(7) + +/* RCC_XBAR23CFGR register fields */ +#define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0 +#define RCC_XBAR23CFGR_XBAR23EN BIT(6) +#define RCC_XBAR23CFGR_XBAR23STS BIT(7) + +/* RCC_XBAR24CFGR register fields */ +#define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0 +#define RCC_XBAR24CFGR_XBAR24EN BIT(6) +#define RCC_XBAR24CFGR_XBAR24STS BIT(7) + +/* RCC_XBAR25CFGR register fields */ +#define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0 +#define RCC_XBAR25CFGR_XBAR25EN BIT(6) +#define RCC_XBAR25CFGR_XBAR25STS BIT(7) + +/* RCC_XBAR26CFGR register fields */ +#define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0 +#define RCC_XBAR26CFGR_XBAR26EN BIT(6) +#define RCC_XBAR26CFGR_XBAR26STS BIT(7) + +/* RCC_XBAR27CFGR register fields */ +#define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0 +#define RCC_XBAR27CFGR_XBAR27EN BIT(6) +#define RCC_XBAR27CFGR_XBAR27STS BIT(7) + +/* RCC_XBAR28CFGR register fields */ +#define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0 +#define RCC_XBAR28CFGR_XBAR28EN BIT(6) +#define RCC_XBAR28CFGR_XBAR28STS BIT(7) + +/* RCC_XBAR29CFGR register fields */ +#define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0 +#define RCC_XBAR29CFGR_XBAR29EN BIT(6) +#define RCC_XBAR29CFGR_XBAR29STS BIT(7) + +/* RCC_XBAR30CFGR register fields */ +#define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0 +#define RCC_XBAR30CFGR_XBAR30EN BIT(6) +#define RCC_XBAR30CFGR_XBAR30STS BIT(7) + +/* RCC_XBAR31CFGR register fields */ +#define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0 +#define RCC_XBAR31CFGR_XBAR31EN BIT(6) +#define RCC_XBAR31CFGR_XBAR31STS BIT(7) + +/* RCC_XBAR32CFGR register fields */ +#define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0 +#define RCC_XBAR32CFGR_XBAR32EN BIT(6) +#define RCC_XBAR32CFGR_XBAR32STS BIT(7) + +/* RCC_XBAR33CFGR register fields */ +#define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0 +#define RCC_XBAR33CFGR_XBAR33EN BIT(6) +#define RCC_XBAR33CFGR_XBAR33STS BIT(7) + +/* RCC_XBAR34CFGR register fields */ +#define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0 +#define RCC_XBAR34CFGR_XBAR34EN BIT(6) +#define RCC_XBAR34CFGR_XBAR34STS BIT(7) + +/* RCC_XBAR35CFGR register fields */ +#define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0 +#define RCC_XBAR35CFGR_XBAR35EN BIT(6) +#define RCC_XBAR35CFGR_XBAR35STS BIT(7) + +/* RCC_XBAR36CFGR register fields */ +#define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0 +#define RCC_XBAR36CFGR_XBAR36EN BIT(6) +#define RCC_XBAR36CFGR_XBAR36STS BIT(7) + +/* RCC_XBAR37CFGR register fields */ +#define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0 +#define RCC_XBAR37CFGR_XBAR37EN BIT(6) +#define RCC_XBAR37CFGR_XBAR37STS BIT(7) + +/* RCC_XBAR38CFGR register fields */ +#define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0 +#define RCC_XBAR38CFGR_XBAR38EN BIT(6) +#define RCC_XBAR38CFGR_XBAR38STS BIT(7) + +/* RCC_XBAR39CFGR register fields */ +#define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0 +#define RCC_XBAR39CFGR_XBAR39EN BIT(6) +#define RCC_XBAR39CFGR_XBAR39STS BIT(7) + +/* RCC_XBAR40CFGR register fields */ +#define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0 +#define RCC_XBAR40CFGR_XBAR40EN BIT(6) +#define RCC_XBAR40CFGR_XBAR40STS BIT(7) + +/* RCC_XBAR41CFGR register fields */ +#define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0 +#define RCC_XBAR41CFGR_XBAR41EN BIT(6) +#define RCC_XBAR41CFGR_XBAR41STS BIT(7) + +/* RCC_XBAR42CFGR register fields */ +#define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0 +#define RCC_XBAR42CFGR_XBAR42EN BIT(6) +#define RCC_XBAR42CFGR_XBAR42STS BIT(7) + +/* RCC_XBAR43CFGR register fields */ +#define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0 +#define RCC_XBAR43CFGR_XBAR43EN BIT(6) +#define RCC_XBAR43CFGR_XBAR43STS BIT(7) + +/* RCC_XBAR44CFGR register fields */ +#define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0 +#define RCC_XBAR44CFGR_XBAR44EN BIT(6) +#define RCC_XBAR44CFGR_XBAR44STS BIT(7) + +/* RCC_XBAR45CFGR register fields */ +#define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0 +#define RCC_XBAR45CFGR_XBAR45EN BIT(6) +#define RCC_XBAR45CFGR_XBAR45STS BIT(7) + +/* RCC_XBAR46CFGR register fields */ +#define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0 +#define RCC_XBAR46CFGR_XBAR46EN BIT(6) +#define RCC_XBAR46CFGR_XBAR46STS BIT(7) + +/* RCC_XBAR47CFGR register fields */ +#define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0 +#define RCC_XBAR47CFGR_XBAR47EN BIT(6) +#define RCC_XBAR47CFGR_XBAR47STS BIT(7) + +/* RCC_XBAR48CFGR register fields */ +#define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0 +#define RCC_XBAR48CFGR_XBAR48EN BIT(6) +#define RCC_XBAR48CFGR_XBAR48STS BIT(7) + +/* RCC_XBAR49CFGR register fields */ +#define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0 +#define RCC_XBAR49CFGR_XBAR49EN BIT(6) +#define RCC_XBAR49CFGR_XBAR49STS BIT(7) + +/* RCC_XBAR50CFGR register fields */ +#define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0 +#define RCC_XBAR50CFGR_XBAR50EN BIT(6) +#define RCC_XBAR50CFGR_XBAR50STS BIT(7) + +/* RCC_XBAR51CFGR register fields */ +#define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0 +#define RCC_XBAR51CFGR_XBAR51EN BIT(6) +#define RCC_XBAR51CFGR_XBAR51STS BIT(7) + +/* RCC_XBAR52CFGR register fields */ +#define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0 +#define RCC_XBAR52CFGR_XBAR52EN BIT(6) +#define RCC_XBAR52CFGR_XBAR52STS BIT(7) + +/* RCC_XBAR53CFGR register fields */ +#define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0 +#define RCC_XBAR53CFGR_XBAR53EN BIT(6) +#define RCC_XBAR53CFGR_XBAR53STS BIT(7) + +/* RCC_XBAR54CFGR register fields */ +#define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0 +#define RCC_XBAR54CFGR_XBAR54EN BIT(6) +#define RCC_XBAR54CFGR_XBAR54STS BIT(7) + +/* RCC_XBAR55CFGR register fields */ +#define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0 +#define RCC_XBAR55CFGR_XBAR55EN BIT(6) +#define RCC_XBAR55CFGR_XBAR55STS BIT(7) + +/* RCC_XBAR56CFGR register fields */ +#define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0 +#define RCC_XBAR56CFGR_XBAR56EN BIT(6) +#define RCC_XBAR56CFGR_XBAR56STS BIT(7) + +/* RCC_XBAR57CFGR register fields */ +#define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0 +#define RCC_XBAR57CFGR_XBAR57EN BIT(6) +#define RCC_XBAR57CFGR_XBAR57STS BIT(7) + +/* RCC_XBAR58CFGR register fields */ +#define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0 +#define RCC_XBAR58CFGR_XBAR58EN BIT(6) +#define RCC_XBAR58CFGR_XBAR58STS BIT(7) + +/* RCC_XBAR59CFGR register fields */ +#define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0 +#define RCC_XBAR59CFGR_XBAR59EN BIT(6) +#define RCC_XBAR59CFGR_XBAR59STS BIT(7) + +/* RCC_XBAR60CFGR register fields */ +#define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0 +#define RCC_XBAR60CFGR_XBAR60EN BIT(6) +#define RCC_XBAR60CFGR_XBAR60STS BIT(7) + +/* RCC_XBAR61CFGR register fields */ +#define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0 +#define RCC_XBAR61CFGR_XBAR61EN BIT(6) +#define RCC_XBAR61CFGR_XBAR61STS BIT(7) + +/* RCC_XBAR62CFGR register fields */ +#define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0 +#define RCC_XBAR62CFGR_XBAR62EN BIT(6) +#define RCC_XBAR62CFGR_XBAR62STS BIT(7) + +/* RCC_XBAR63CFGR register fields */ +#define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0 +#define RCC_XBAR63CFGR_XBAR63EN BIT(6) +#define RCC_XBAR63CFGR_XBAR63STS BIT(7) + +/* RCC_XBARxCFGR register fields */ +#define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0) +#define RCC_XBARxCFGR_XBARxSEL_SHIFT 0 +#define RCC_XBARxCFGR_XBARxEN BIT(6) +#define RCC_XBARxCFGR_XBARxSTS BIT(7) + +/* RCC_PREDIV0CFGR register fields */ +#define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0) +#define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0 + +/* RCC_PREDIV1CFGR register fields */ +#define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0) +#define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0 + +/* RCC_PREDIV2CFGR register fields */ +#define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0) +#define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0 + +/* RCC_PREDIV3CFGR register fields */ +#define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0) +#define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0 + +/* RCC_PREDIV4CFGR register fields */ +#define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0) +#define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0 + +/* RCC_PREDIV5CFGR register fields */ +#define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0) +#define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0 + +/* RCC_PREDIV6CFGR register fields */ +#define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0) +#define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0 + +/* RCC_PREDIV7CFGR register fields */ +#define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0) +#define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0 + +/* RCC_PREDIV8CFGR register fields */ +#define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0) +#define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0 + +/* RCC_PREDIV9CFGR register fields */ +#define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0) +#define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0 + +/* RCC_PREDIV10CFGR register fields */ +#define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0) +#define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0 + +/* RCC_PREDIV11CFGR register fields */ +#define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0) +#define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0 + +/* RCC_PREDIV12CFGR register fields */ +#define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0) +#define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0 + +/* RCC_PREDIV13CFGR register fields */ +#define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0) +#define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0 + +/* RCC_PREDIV14CFGR register fields */ +#define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0) +#define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0 + +/* RCC_PREDIV15CFGR register fields */ +#define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0) +#define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0 + +/* RCC_PREDIV16CFGR register fields */ +#define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0) +#define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0 + +/* RCC_PREDIV17CFGR register fields */ +#define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0) +#define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0 + +/* RCC_PREDIV18CFGR register fields */ +#define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0) +#define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0 + +/* RCC_PREDIV19CFGR register fields */ +#define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0) +#define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0 + +/* RCC_PREDIV20CFGR register fields */ +#define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0) +#define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0 + +/* RCC_PREDIV21CFGR register fields */ +#define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0) +#define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0 + +/* RCC_PREDIV22CFGR register fields */ +#define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0) +#define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0 + +/* RCC_PREDIV23CFGR register fields */ +#define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0) +#define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0 + +/* RCC_PREDIV24CFGR register fields */ +#define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0) +#define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0 + +/* RCC_PREDIV25CFGR register fields */ +#define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0) +#define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0 + +/* RCC_PREDIV26CFGR register fields */ +#define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0) +#define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0 + +/* RCC_PREDIV27CFGR register fields */ +#define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0) +#define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0 + +/* RCC_PREDIV28CFGR register fields */ +#define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0) +#define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0 + +/* RCC_PREDIV29CFGR register fields */ +#define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0) +#define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0 + +/* RCC_PREDIV30CFGR register fields */ +#define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0) +#define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0 + +/* RCC_PREDIV31CFGR register fields */ +#define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0) +#define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0 + +/* RCC_PREDIV32CFGR register fields */ +#define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0) +#define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0 + +/* RCC_PREDIV33CFGR register fields */ +#define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0) +#define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0 + +/* RCC_PREDIV34CFGR register fields */ +#define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0) +#define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0 + +/* RCC_PREDIV35CFGR register fields */ +#define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0) +#define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0 + +/* RCC_PREDIV36CFGR register fields */ +#define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0) +#define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0 + +/* RCC_PREDIV37CFGR register fields */ +#define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0) +#define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0 + +/* RCC_PREDIV38CFGR register fields */ +#define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0) +#define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0 + +/* RCC_PREDIV39CFGR register fields */ +#define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0) +#define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0 + +/* RCC_PREDIV40CFGR register fields */ +#define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0) +#define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0 + +/* RCC_PREDIV41CFGR register fields */ +#define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0) +#define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0 + +/* RCC_PREDIV42CFGR register fields */ +#define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0) +#define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0 + +/* RCC_PREDIV43CFGR register fields */ +#define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0) +#define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0 + +/* RCC_PREDIV44CFGR register fields */ +#define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0) +#define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0 + +/* RCC_PREDIV45CFGR register fields */ +#define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0) +#define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0 + +/* RCC_PREDIV46CFGR register fields */ +#define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0) +#define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0 + +/* RCC_PREDIV47CFGR register fields */ +#define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0) +#define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0 + +/* RCC_PREDIV48CFGR register fields */ +#define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0) +#define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0 + +/* RCC_PREDIV49CFGR register fields */ +#define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0) +#define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0 + +/* RCC_PREDIV50CFGR register fields */ +#define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0) +#define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0 + +/* RCC_PREDIV51CFGR register fields */ +#define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0) +#define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0 + +/* RCC_PREDIV52CFGR register fields */ +#define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0) +#define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0 + +/* RCC_PREDIV53CFGR register fields */ +#define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0) +#define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0 + +/* RCC_PREDIV54CFGR register fields */ +#define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0) +#define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0 + +/* RCC_PREDIV55CFGR register fields */ +#define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0) +#define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0 + +/* RCC_PREDIV56CFGR register fields */ +#define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0) +#define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0 + +/* RCC_PREDIV57CFGR register fields */ +#define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0) +#define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0 + +/* RCC_PREDIV58CFGR register fields */ +#define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0) +#define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0 + +/* RCC_PREDIV59CFGR register fields */ +#define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0) +#define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0 + +/* RCC_PREDIV60CFGR register fields */ +#define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0) +#define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0 + +/* RCC_PREDIV61CFGR register fields */ +#define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0) +#define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0 + +/* RCC_PREDIV62CFGR register fields */ +#define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0) +#define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0 + +/* RCC_PREDIV63CFGR register fields */ +#define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0) +#define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0 + +/* RCC_PREDIVxCFGR register fields */ +#define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0) +#define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0 + +/* RCC_FINDIV0CFGR register fields */ +#define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) +#define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0 +#define RCC_FINDIV0CFGR_FINDIV0EN BIT(6) + +/* RCC_FINDIV1CFGR register fields */ +#define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0) +#define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0 +#define RCC_FINDIV1CFGR_FINDIV1EN BIT(6) + +/* RCC_FINDIV2CFGR register fields */ +#define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0) +#define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0 +#define RCC_FINDIV2CFGR_FINDIV2EN BIT(6) + +/* RCC_FINDIV3CFGR register fields */ +#define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0) +#define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0 +#define RCC_FINDIV3CFGR_FINDIV3EN BIT(6) + +/* RCC_FINDIV4CFGR register fields */ +#define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0) +#define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0 +#define RCC_FINDIV4CFGR_FINDIV4EN BIT(6) + +/* RCC_FINDIV5CFGR register fields */ +#define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0) +#define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0 +#define RCC_FINDIV5CFGR_FINDIV5EN BIT(6) + +/* RCC_FINDIV6CFGR register fields */ +#define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0) +#define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0 +#define RCC_FINDIV6CFGR_FINDIV6EN BIT(6) + +/* RCC_FINDIV7CFGR register fields */ +#define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0) +#define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0 +#define RCC_FINDIV7CFGR_FINDIV7EN BIT(6) + +/* RCC_FINDIV8CFGR register fields */ +#define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0) +#define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0 +#define RCC_FINDIV8CFGR_FINDIV8EN BIT(6) + +/* RCC_FINDIV9CFGR register fields */ +#define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0) +#define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0 +#define RCC_FINDIV9CFGR_FINDIV9EN BIT(6) + +/* RCC_FINDIV10CFGR register fields */ +#define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0) +#define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0 +#define RCC_FINDIV10CFGR_FINDIV10EN BIT(6) + +/* RCC_FINDIV11CFGR register fields */ +#define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0) +#define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0 +#define RCC_FINDIV11CFGR_FINDIV11EN BIT(6) + +/* RCC_FINDIV12CFGR register fields */ +#define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0) +#define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0 +#define RCC_FINDIV12CFGR_FINDIV12EN BIT(6) + +/* RCC_FINDIV13CFGR register fields */ +#define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0) +#define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0 +#define RCC_FINDIV13CFGR_FINDIV13EN BIT(6) + +/* RCC_FINDIV14CFGR register fields */ +#define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0) +#define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0 +#define RCC_FINDIV14CFGR_FINDIV14EN BIT(6) + +/* RCC_FINDIV15CFGR register fields */ +#define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0) +#define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0 +#define RCC_FINDIV15CFGR_FINDIV15EN BIT(6) + +/* RCC_FINDIV16CFGR register fields */ +#define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0) +#define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0 +#define RCC_FINDIV16CFGR_FINDIV16EN BIT(6) + +/* RCC_FINDIV17CFGR register fields */ +#define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0) +#define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0 +#define RCC_FINDIV17CFGR_FINDIV17EN BIT(6) + +/* RCC_FINDIV18CFGR register fields */ +#define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0) +#define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0 +#define RCC_FINDIV18CFGR_FINDIV18EN BIT(6) + +/* RCC_FINDIV19CFGR register fields */ +#define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0) +#define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0 +#define RCC_FINDIV19CFGR_FINDIV19EN BIT(6) + +/* RCC_FINDIV20CFGR register fields */ +#define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0) +#define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0 +#define RCC_FINDIV20CFGR_FINDIV20EN BIT(6) + +/* RCC_FINDIV21CFGR register fields */ +#define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0) +#define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0 +#define RCC_FINDIV21CFGR_FINDIV21EN BIT(6) + +/* RCC_FINDIV22CFGR register fields */ +#define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0) +#define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0 +#define RCC_FINDIV22CFGR_FINDIV22EN BIT(6) + +/* RCC_FINDIV23CFGR register fields */ +#define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0) +#define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0 +#define RCC_FINDIV23CFGR_FINDIV23EN BIT(6) + +/* RCC_FINDIV24CFGR register fields */ +#define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0) +#define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0 +#define RCC_FINDIV24CFGR_FINDIV24EN BIT(6) + +/* RCC_FINDIV25CFGR register fields */ +#define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0) +#define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0 +#define RCC_FINDIV25CFGR_FINDIV25EN BIT(6) + +/* RCC_FINDIV26CFGR register fields */ +#define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0) +#define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0 +#define RCC_FINDIV26CFGR_FINDIV26EN BIT(6) + +/* RCC_FINDIV27CFGR register fields */ +#define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0) +#define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0 +#define RCC_FINDIV27CFGR_FINDIV27EN BIT(6) + +/* RCC_FINDIV28CFGR register fields */ +#define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0) +#define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0 +#define RCC_FINDIV28CFGR_FINDIV28EN BIT(6) + +/* RCC_FINDIV29CFGR register fields */ +#define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0) +#define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0 +#define RCC_FINDIV29CFGR_FINDIV29EN BIT(6) + +/* RCC_FINDIV30CFGR register fields */ +#define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0) +#define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0 +#define RCC_FINDIV30CFGR_FINDIV30EN BIT(6) + +/* RCC_FINDIV31CFGR register fields */ +#define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0) +#define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0 +#define RCC_FINDIV31CFGR_FINDIV31EN BIT(6) + +/* RCC_FINDIV32CFGR register fields */ +#define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0) +#define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0 +#define RCC_FINDIV32CFGR_FINDIV32EN BIT(6) + +/* RCC_FINDIV33CFGR register fields */ +#define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0) +#define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0 +#define RCC_FINDIV33CFGR_FINDIV33EN BIT(6) + +/* RCC_FINDIV34CFGR register fields */ +#define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0) +#define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0 +#define RCC_FINDIV34CFGR_FINDIV34EN BIT(6) + +/* RCC_FINDIV35CFGR register fields */ +#define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0) +#define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0 +#define RCC_FINDIV35CFGR_FINDIV35EN BIT(6) + +/* RCC_FINDIV36CFGR register fields */ +#define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0) +#define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0 +#define RCC_FINDIV36CFGR_FINDIV36EN BIT(6) + +/* RCC_FINDIV37CFGR register fields */ +#define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0) +#define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0 +#define RCC_FINDIV37CFGR_FINDIV37EN BIT(6) + +/* RCC_FINDIV38CFGR register fields */ +#define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0) +#define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0 +#define RCC_FINDIV38CFGR_FINDIV38EN BIT(6) + +/* RCC_FINDIV39CFGR register fields */ +#define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0) +#define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0 +#define RCC_FINDIV39CFGR_FINDIV39EN BIT(6) + +/* RCC_FINDIV40CFGR register fields */ +#define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0) +#define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0 +#define RCC_FINDIV40CFGR_FINDIV40EN BIT(6) + +/* RCC_FINDIV41CFGR register fields */ +#define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0) +#define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0 +#define RCC_FINDIV41CFGR_FINDIV41EN BIT(6) + +/* RCC_FINDIV42CFGR register fields */ +#define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0) +#define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0 +#define RCC_FINDIV42CFGR_FINDIV42EN BIT(6) + +/* RCC_FINDIV43CFGR register fields */ +#define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0) +#define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0 +#define RCC_FINDIV43CFGR_FINDIV43EN BIT(6) + +/* RCC_FINDIV44CFGR register fields */ +#define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0) +#define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0 +#define RCC_FINDIV44CFGR_FINDIV44EN BIT(6) + +/* RCC_FINDIV45CFGR register fields */ +#define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0) +#define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0 +#define RCC_FINDIV45CFGR_FINDIV45EN BIT(6) + +/* RCC_FINDIV46CFGR register fields */ +#define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0) +#define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0 +#define RCC_FINDIV46CFGR_FINDIV46EN BIT(6) + +/* RCC_FINDIV47CFGR register fields */ +#define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0) +#define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0 +#define RCC_FINDIV47CFGR_FINDIV47EN BIT(6) + +/* RCC_FINDIV48CFGR register fields */ +#define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0) +#define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0 +#define RCC_FINDIV48CFGR_FINDIV48EN BIT(6) + +/* RCC_FINDIV49CFGR register fields */ +#define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0) +#define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0 +#define RCC_FINDIV49CFGR_FINDIV49EN BIT(6) + +/* RCC_FINDIV50CFGR register fields */ +#define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0) +#define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0 +#define RCC_FINDIV50CFGR_FINDIV50EN BIT(6) + +/* RCC_FINDIV51CFGR register fields */ +#define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0) +#define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0 +#define RCC_FINDIV51CFGR_FINDIV51EN BIT(6) + +/* RCC_FINDIV52CFGR register fields */ +#define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0) +#define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0 +#define RCC_FINDIV52CFGR_FINDIV52EN BIT(6) + +/* RCC_FINDIV53CFGR register fields */ +#define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0) +#define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0 +#define RCC_FINDIV53CFGR_FINDIV53EN BIT(6) + +/* RCC_FINDIV54CFGR register fields */ +#define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0) +#define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0 +#define RCC_FINDIV54CFGR_FINDIV54EN BIT(6) + +/* RCC_FINDIV55CFGR register fields */ +#define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0) +#define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0 +#define RCC_FINDIV55CFGR_FINDIV55EN BIT(6) + +/* RCC_FINDIV56CFGR register fields */ +#define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0) +#define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0 +#define RCC_FINDIV56CFGR_FINDIV56EN BIT(6) + +/* RCC_FINDIV57CFGR register fields */ +#define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0) +#define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0 +#define RCC_FINDIV57CFGR_FINDIV57EN BIT(6) + +/* RCC_FINDIV58CFGR register fields */ +#define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0) +#define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0 +#define RCC_FINDIV58CFGR_FINDIV58EN BIT(6) + +/* RCC_FINDIV59CFGR register fields */ +#define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0) +#define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0 +#define RCC_FINDIV59CFGR_FINDIV59EN BIT(6) + +/* RCC_FINDIV60CFGR register fields */ +#define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0) +#define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0 +#define RCC_FINDIV60CFGR_FINDIV60EN BIT(6) + +/* RCC_FINDIV61CFGR register fields */ +#define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0) +#define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0 +#define RCC_FINDIV61CFGR_FINDIV61EN BIT(6) + +/* RCC_FINDIV62CFGR register fields */ +#define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0) +#define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0 +#define RCC_FINDIV62CFGR_FINDIV62EN BIT(6) + +/* RCC_FINDIV63CFGR register fields */ +#define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0) +#define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0 +#define RCC_FINDIV63CFGR_FINDIV63EN BIT(6) + +/* RCC_FINDIVxCFGR register fields */ +#define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0) +#define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0 +#define RCC_FINDIVxCFGR_FINDIVxEN BIT(6) + +/* RCC_FCALCOBS0CFGR register fields */ +#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0) +#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0 +#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) +#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8 +#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15) +#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16) +#define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17) +#define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18) +#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) +#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22 +#define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25) +#define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26) + +/* RCC_FCALCOBS1CFGR register fields */ +#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0) +#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0 +#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) +#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8 +#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16) +#define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18) +#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) +#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22 +#define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26) +#define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27) + +/* RCC_FCALCREFCFGR register fields */ +#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0) +#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0 + +/* RCC_FCALCCR1 register fields */ +#define RCC_FCALCCR1_FCALCRUN BIT(0) + +/* RCC_FCALCCR2 register fields */ +#define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3) +#define RCC_FCALCCR2_FCALCMD_SHIFT 3 +#define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11) +#define RCC_FCALCCR2_FCALCTWC_SHIFT 11 +#define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17) +#define RCC_FCALCCR2_FCALCTYP_SHIFT 17 + +/* RCC_FCALCSR register fields */ +#define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0) +#define RCC_FCALCSR_FVAL_SHIFT 0 +#define RCC_FCALCSR_FCALCSTS BIT(19) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_SSMODRST BIT(0) +#define RCC_PLL4CFGR1_PLLEN BIT(8) +#define RCC_PLL4CFGR1_PLLRDY BIT(24) +#define RCC_PLL4CFGR1_CKREFST BIT(28) + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL4CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL4CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL4CFGR3 register fields */ +#define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL4CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL4CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL4CFGR3_DACEN BIT(25) +#define RCC_PLL4CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL4CFGR4 register fields */ +#define RCC_PLL4CFGR4_DSMEN BIT(8) +#define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL4CFGR4_BYPASS BIT(10) + +/* RCC_PLL4CFGR5 register fields */ +#define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL4CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL4CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL4CFGR6 register fields */ +#define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL4CFGR7 register fields */ +#define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL5CFGR1 register fields */ +#define RCC_PLL5CFGR1_SSMODRST BIT(0) +#define RCC_PLL5CFGR1_PLLEN BIT(8) +#define RCC_PLL5CFGR1_PLLRDY BIT(24) +#define RCC_PLL5CFGR1_CKREFST BIT(28) + +/* RCC_PLL5CFGR2 register fields */ +#define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL5CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL5CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL5CFGR3 register fields */ +#define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL5CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL5CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL5CFGR3_DACEN BIT(25) +#define RCC_PLL5CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL5CFGR4 register fields */ +#define RCC_PLL5CFGR4_DSMEN BIT(8) +#define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL5CFGR4_BYPASS BIT(10) + +/* RCC_PLL5CFGR5 register fields */ +#define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL5CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL5CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL5CFGR6 register fields */ +#define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL5CFGR7 register fields */ +#define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL6CFGR1 register fields */ +#define RCC_PLL6CFGR1_SSMODRST BIT(0) +#define RCC_PLL6CFGR1_PLLEN BIT(8) +#define RCC_PLL6CFGR1_PLLRDY BIT(24) +#define RCC_PLL6CFGR1_CKREFST BIT(28) + +/* RCC_PLL6CFGR2 register fields */ +#define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL6CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL6CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL6CFGR3 register fields */ +#define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL6CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL6CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL6CFGR3_DACEN BIT(25) +#define RCC_PLL6CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL6CFGR4 register fields */ +#define RCC_PLL6CFGR4_DSMEN BIT(8) +#define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL6CFGR4_BYPASS BIT(10) + +/* RCC_PLL6CFGR5 register fields */ +#define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL6CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL6CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL6CFGR6 register fields */ +#define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL6CFGR7 register fields */ +#define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL7CFGR1 register fields */ +#define RCC_PLL7CFGR1_SSMODRST BIT(0) +#define RCC_PLL7CFGR1_PLLEN BIT(8) +#define RCC_PLL7CFGR1_PLLRDY BIT(24) +#define RCC_PLL7CFGR1_CKREFST BIT(28) + +/* RCC_PLL7CFGR2 register fields */ +#define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL7CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL7CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL7CFGR3 register fields */ +#define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL7CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL7CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL7CFGR3_DACEN BIT(25) +#define RCC_PLL7CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL7CFGR4 register fields */ +#define RCC_PLL7CFGR4_DSMEN BIT(8) +#define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL7CFGR4_BYPASS BIT(10) + +/* RCC_PLL7CFGR5 register fields */ +#define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL7CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL7CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL7CFGR6 register fields */ +#define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL7CFGR7 register fields */ +#define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL8CFGR1 register fields */ +#define RCC_PLL8CFGR1_SSMODRST BIT(0) +#define RCC_PLL8CFGR1_PLLEN BIT(8) +#define RCC_PLL8CFGR1_PLLRDY BIT(24) +#define RCC_PLL8CFGR1_CKREFST BIT(28) + +/* RCC_PLL8CFGR2 register fields */ +#define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL8CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL8CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL8CFGR3 register fields */ +#define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL8CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL8CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL8CFGR3_DACEN BIT(25) +#define RCC_PLL8CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL8CFGR4 register fields */ +#define RCC_PLL8CFGR4_DSMEN BIT(8) +#define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL8CFGR4_BYPASS BIT(10) + +/* RCC_PLL8CFGR5 register fields */ +#define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL8CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL8CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL8CFGR6 register fields */ +#define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL8CFGR7 register fields */ +#define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLLxCFGR1 register fields */ +#define RCC_PLLxCFGR1_SSMODRST BIT(0) +#define RCC_PLLxCFGR1_PLLEN BIT(8) +#define RCC_PLLxCFGR1_PLLRDY BIT(24) +#define RCC_PLLxCFGR1_CKREFST BIT(28) + +/* RCC_PLLxCFGR2 register fields */ +#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 +#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLLxCFGR2_FBDIV_SHIFT 16 + +/* RCC_PLLxCFGR3 register fields */ +#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLLxCFGR3_FRACIN_SHIFT 0 +#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) +#define RCC_PLLxCFGR3_DACEN BIT(25) +#define RCC_PLLxCFGR3_SSCGDIS BIT(26) + +/* RCC_PLLxCFGR4 register fields */ +#define RCC_PLLxCFGR4_DSMEN BIT(8) +#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLLxCFGR4_BYPASS BIT(10) + +/* RCC_PLLxCFGR5 register fields */ +#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 +#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLLxCFGR5_SPREAD_SHIFT 16 + +/* RCC_PLLxCFGR6 register fields */ +#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLLxCFGR7 register fields */ +#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK_32(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +#endif /* STM32MP2_RCC_H */ diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h index c7e0b6e6fb..61286b2244 100644 --- a/include/drivers/st/stm32mp_clkfunc.h +++ b/include/drivers/st/stm32mp_clkfunc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,18 +14,23 @@ #include <platform_def.h> int fdt_osc_read_freq(const char *name, uint32_t *freq); -bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name); -uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, +bool fdt_clk_read_bool(const char *node_label, const char *prop_name); +uint32_t fdt_clk_read_uint32_default(const char *node_label, const char *prop_name, uint32_t dflt_value); -int fdt_get_rcc_node(void *fdt); int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count, uint32_t *array); int fdt_rcc_subnode_offset(const char *name); const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp); -bool fdt_get_rcc_secure_status(void); +bool fdt_get_rcc_secure_state(void); int fdt_get_clock_id(int node); +unsigned long fdt_get_uart_clock_freq(uintptr_t instance); + +void stm32mp_stgen_config(unsigned long rate); +void stm32mp_stgen_restore_counter(unsigned long long value, + unsigned long long offset_in_ms); +unsigned long long stm32mp_stgen_get_counter(void); #endif /* STM32MP_CLKFUNC_H */ diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h new file mode 100644 index 0000000000..4535e3cb30 --- /dev/null +++ b/include/drivers/st/stm32mp_ddr.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32MP_DDR_H +#define STM32MP_DDR_H + +#include <platform_def.h> + +enum stm32mp_ddr_base_type { + DDR_BASE, + DDRPHY_BASE, + NONE_BASE +}; + +enum stm32mp_ddr_reg_type { + REG_REG, + REG_TIMING, + REG_PERF, + REG_MAP, + REGPHY_REG, + REGPHY_TIMING, + REG_TYPE_NB +}; + +struct stm32mp_ddr_reg_desc { + const char *name; + uint16_t offset; /* Offset for base address */ + uint8_t par_offset; /* Offset for parameter array */ +}; + +struct stm32mp_ddr_reg_info { + const char *name; + const struct stm32mp_ddr_reg_desc *desc; + uint8_t size; + enum stm32mp_ddr_base_type base; +}; + +struct stm32mp_ddr_size { + uint64_t base; + uint64_t size; +}; + +struct stm32mp_ddr_priv { + struct stm32mp_ddr_size info; + struct stm32mp_ddrctl *ctl; + struct stm32mp_ddrphy *phy; + uintptr_t pwr; + uintptr_t rcc; +}; + +struct stm32mp_ddr_info { + const char *name; + uint32_t speed; /* in kHz */ + size_t size; /* Memory size in byte = col * row * width */ +}; + +#define TIMEOUT_US_1S 1000000U + +void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type, + const void *param, const struct stm32mp_ddr_reg_info *ddr_registers); +void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl); +void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl); +void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl); +int stm32mp_board_ddr_power_init(enum ddr_type ddr_type); + +#endif /* STM32MP_DDR_H */ diff --git a/include/drivers/st/stm32mp_ddr_test.h b/include/drivers/st/stm32mp_ddr_test.h new file mode 100644 index 0000000000..cef5b486c3 --- /dev/null +++ b/include/drivers/st/stm32mp_ddr_test.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP_DDR_TEST_H +#define STM32MP_DDR_TEST_H + +#include <stdint.h> + +uintptr_t stm32mp_ddr_test_rw_access(void); +uintptr_t stm32mp_ddr_test_data_bus(void); +uintptr_t stm32mp_ddr_test_addr_bus(size_t size); +size_t stm32mp_ddr_check_size(void); + +#endif /* STM32MP_DDR_TEST_H */ diff --git a/include/drivers/st/stm32mp_ddrctrl_regs.h b/include/drivers/st/stm32mp_ddrctrl_regs.h new file mode 100644 index 0000000000..79de86b2a8 --- /dev/null +++ b/include/drivers/st/stm32mp_ddrctrl_regs.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32MP_DDRCTRL_REGS_H +#define STM32MP_DDRCTRL_REGS_H + +#include <cdefs.h> +#include <stdint.h> + +#include <lib/utils_def.h> + +/* DDR Controller (DDRCTRL) registers */ +struct stm32mp_ddrctl { + uint32_t mstr ; /* 0x0 Master */ + uint32_t stat; /* 0x4 Operating Mode Status */ + uint8_t reserved008[0x10 - 0x8]; + uint32_t mrctrl0; /* 0x10 Control 0 */ + uint32_t mrctrl1; /* 0x14 Control 1 */ + uint32_t mrstat; /* 0x18 Status */ + uint32_t mrctrl2; /* 0x1c Control 2 */ + uint32_t derateen; /* 0x20 Temperature Derate Enable */ + uint32_t derateint; /* 0x24 Temperature Derate Interval */ + uint32_t reserved028; + uint32_t deratectl; /* 0x2c Temperature Derate Control */ + uint32_t pwrctl; /* 0x30 Low Power Control */ + uint32_t pwrtmg; /* 0x34 Low Power Timing */ + uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */ + uint8_t reserved03c[0x50 - 0x3c]; + uint32_t rfshctl0; /* 0x50 Refresh Control 0 */ + uint32_t rfshctl1; /* 0x54 Refresh Control 1 */ + uint32_t reserved058; /* 0x58 Refresh Control 2 */ + uint32_t reserved05C; + uint32_t rfshctl3; /* 0x60 Refresh Control 0 */ + uint32_t rfshtmg; /* 0x64 Refresh Timing */ + uint32_t rfshtmg1; /* 0x68 Refresh Timing 1 */ + uint8_t reserved06c[0xc0 - 0x6c]; + uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */ + uint32_t crcparctl1; /* 0xc4 CRC Parity Control1 */ + uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */ + uint32_t crcparstat; /* 0xcc CRC Parity Status */ + uint32_t init0; /* 0xd0 SDRAM Initialization 0 */ + uint32_t init1; /* 0xd4 SDRAM Initialization 1 */ + uint32_t init2; /* 0xd8 SDRAM Initialization 2 */ + uint32_t init3; /* 0xdc SDRAM Initialization 3 */ + uint32_t init4; /* 0xe0 SDRAM Initialization 4 */ + uint32_t init5; /* 0xe4 SDRAM Initialization 5 */ + uint32_t init6; /* 0xe8 SDRAM Initialization 6 */ + uint32_t init7; /* 0xec SDRAM Initialization 7 */ + uint32_t dimmctl; /* 0xf0 DIMM Control */ + uint32_t rankctl; /* 0xf4 Rank Control */ + uint8_t reserved0f4[0x100 - 0xf8]; + uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */ + uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */ + uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */ + uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */ + uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */ + uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */ + uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */ + uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */ + uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */ + uint32_t dramtmg9; /* 0x124 SDRAM Timing 9 */ + uint32_t dramtmg10; /* 0x128 SDRAM Timing 10 */ + uint32_t dramtmg11; /* 0x12c SDRAM Timing 11 */ + uint32_t dramtmg12; /* 0x130 SDRAM Timing 12 */ + uint32_t dramtmg13; /* 0x134 SDRAM Timing 13 */ + uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */ + uint32_t dramtmg15; /* 0x13c SDRAM Timing 15 */ + uint8_t reserved140[0x180 - 0x140]; + uint32_t zqctl0; /* 0x180 ZQ Control 0 */ + uint32_t zqctl1; /* 0x184 ZQ Control 1 */ + uint32_t zqctl2; /* 0x188 ZQ Control 2 */ + uint32_t zqstat; /* 0x18c ZQ Status */ + uint32_t dfitmg0; /* 0x190 DFI Timing 0 */ + uint32_t dfitmg1; /* 0x194 DFI Timing 1 */ + uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */ + uint32_t dfilpcfg1; /* 0x19c DFI Low Power Configuration 1 */ + uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */ + uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */ + uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */ + uint32_t reserved1ac; + uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */ + uint32_t dfitmg2; /* 0x1b4 DFI Timing 2 */ + uint32_t dfitmg3; /* 0x1b8 DFI Timing 3 */ + uint32_t dfistat; /* 0x1bc DFI Status */ + uint32_t dbictl; /* 0x1c0 DM/DBI Control */ + uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */ + uint8_t reserved1c8[0x200 - 0x1c8]; + uint32_t addrmap0; /* 0x200 Address Map 0 */ + uint32_t addrmap1; /* 0x204 Address Map 1 */ + uint32_t addrmap2; /* 0x208 Address Map 2 */ + uint32_t addrmap3; /* 0x20c Address Map 3 */ + uint32_t addrmap4; /* 0x210 Address Map 4 */ + uint32_t addrmap5; /* 0x214 Address Map 5 */ + uint32_t addrmap6; /* 0x218 Address Map 6 */ + uint32_t addrmap7; /* 0x21c Address Map 7 */ + uint32_t addrmap8; /* 0x220 Address Map 8 */ + uint32_t addrmap9; /* 0x224 Address Map 9 */ + uint32_t addrmap10; /* 0x228 Address Map 10 */ + uint32_t addrmap11; /* 0x22C Address Map 11 */ + uint8_t reserved230[0x240 - 0x230]; + uint32_t odtcfg; /* 0x240 ODT Configuration */ + uint32_t odtmap; /* 0x244 ODT/Rank Map */ + uint8_t reserved248[0x250 - 0x248]; + uint32_t sched; /* 0x250 Scheduler Control */ + uint32_t sched1; /* 0x254 Scheduler Control 1 */ + uint32_t reserved258; + uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */ + uint32_t reserved260; + uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */ + uint32_t reserved268; + uint32_t perfwr1; /* 0x26c Write CAM 1 */ + uint8_t reserved27c[0x300 - 0x270]; + uint32_t dbg0; /* 0x300 Debug 0 */ + uint32_t dbg1; /* 0x304 Debug 1 */ + uint32_t dbgcam; /* 0x308 CAM Debug */ + uint32_t dbgcmd; /* 0x30c Command Debug */ + uint32_t dbgstat; /* 0x310 Status Debug */ + uint8_t reserved314[0x320 - 0x314]; + uint32_t swctl; /* 0x320 Software Programming Control Enable */ + uint32_t swstat; /* 0x324 Software Programming Control Status */ + uint8_t reserved328[0x36c - 0x328]; + uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */ + uint32_t poisonstat; /* 0x370 AXI Poison Status Register */ + uint8_t reserved374[0x3f0 - 0x374]; + uint32_t deratestat; /* 0x3f0 Temperature Derate Status */ + uint8_t reserved3f4[0x3fc - 0x3f4]; + + /* Multi Port registers */ + uint32_t pstat; /* 0x3fc Port Status */ + uint32_t pccfg; /* 0x400 Port Common Configuration */ + + /* PORT 0 */ + uint32_t pcfgr_0; /* 0x404 Configuration Read */ + uint32_t pcfgw_0; /* 0x408 Configuration Write */ + uint8_t reserved40c[0x490 - 0x40c]; + uint32_t pctrl_0; /* 0x490 Port Control Register */ + uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */ + uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */ + uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */ + uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */ + uint8_t reserved4a4[0x4b4 - 0x4a4]; + +#if STM32MP_DDR_DUAL_AXI_PORT + /* PORT 1 */ + uint32_t pcfgr_1; /* 0x4b4 Configuration Read */ + uint32_t pcfgw_1; /* 0x4b8 Configuration Write */ + uint8_t reserved4bc[0x540 - 0x4bc]; + uint32_t pctrl_1; /* 0x540 Port 2 Control Register */ + uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */ + uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */ + uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */ + uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */ +#endif + + uint8_t reserved554[0xff0 - 0x554]; + uint32_t umctl2_ver_number; /* 0xff0 UMCTL2 Version Number */ +} __packed; + +/* DDR Controller registers offsets */ +#define DDRCTRL_MSTR 0x000 +#define DDRCTRL_STAT 0x004 +#define DDRCTRL_MRCTRL0 0x010 +#define DDRCTRL_MRSTAT 0x018 +#define DDRCTRL_PWRCTL 0x030 +#define DDRCTRL_PWRTMG 0x034 +#define DDRCTRL_HWLPCTL 0x038 +#define DDRCTRL_RFSHCTL3 0x060 +#define DDRCTRL_RFSHTMG 0x064 +#define DDRCTRL_INIT0 0x0D0 +#define DDRCTRL_DFIMISC 0x1B0 +#define DDRCTRL_DBG1 0x304 +#define DDRCTRL_DBGCAM 0x308 +#define DDRCTRL_DBGCMD 0x30C +#define DDRCTRL_DBGSTAT 0x310 +#define DDRCTRL_SWCTL 0x320 +#define DDRCTRL_SWSTAT 0x324 +#define DDRCTRL_PSTAT 0x3FC +#define DDRCTRL_PCTRL_0 0x490 +#if STM32MP_DDR_DUAL_AXI_PORT +#define DDRCTRL_PCTRL_1 0x540 +#endif + +/* DDR Controller Register fields */ +#define DDRCTRL_MSTR_DDR3 BIT(0) +#define DDRCTRL_MSTR_LPDDR2 BIT(2) +#define DDRCTRL_MSTR_LPDDR3 BIT(3) +#define DDRCTRL_MSTR_DDR4 BIT(4) +#define DDRCTRL_MSTR_LPDDR4 BIT(5) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL 0 +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER BIT(13) +#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15) + +#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) +#define DDRCTRL_STAT_OPERATING_MODE_NORMAL BIT(0) +#define DDRCTRL_STAT_OPERATING_MODE_SR (BIT(0) | BIT(1)) +#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) +#define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5)) +#define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5) + +#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0) +/* Only one rank supported */ +#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRCTRL_MRCTRL0_MR_RANK_ALL \ + BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT) +#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12) +#define DDRCTRL_MRCTRL0_MR_WR BIT(31) + +#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) + +#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) +#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) +#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) + +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) + +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL BIT(1) + +#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) + +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16 + +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30) + +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) +#define DDRCTRL_DFIMISC_DFI_INIT_START BIT(5) + +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE BIT(0) + +#define DDRCTRL_DBG1_DIS_HIF BIT(1) + +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0) +#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \ + (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \ + DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY) +#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \ + (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \ + DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \ + DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH) + +#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0) + +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0) + +#define DDRCTRL_SWCTL_SW_DONE BIT(0) + +#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) + +#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) + +#endif /* STM32MP_DDRCTRL_REGS_H */ diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h index 984cd60143..303c571483 100644 --- a/include/drivers/st/stm32mp_pmic.h +++ b/include/drivers/st/stm32mp_pmic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,14 +20,6 @@ int dt_pmic_status(void); /* - * dt_pmic_configure_boot_on_regulators - Configure boot-on and always-on - * regulators from device tree configuration - * - * Returns 0 on success, and negative values on errors - */ -int dt_pmic_configure_boot_on_regulators(void); - -/* * initialize_pmic_i2c - Initialize I2C for the PMIC control * * Returns true if PMIC is available, false if not found, panics on errors @@ -41,6 +33,14 @@ bool initialize_pmic_i2c(void); */ void initialize_pmic(void); +#if DEBUG +void print_pmic_info_and_debug(void); +#else +static inline void print_pmic_info_and_debug(void) +{ +} +#endif + /* * pmic_ddr_power_init - Initialize regulators required for DDR * @@ -48,4 +48,11 @@ void initialize_pmic(void); */ int pmic_ddr_power_init(enum ddr_type ddr_type); +/* + * pmic_voltages_init - Update voltages for platform init + * + * Returns 0 on success, and negative values on errors + */ +int pmic_voltages_init(void); + #endif /* STM32MP_PMIC_H */ diff --git a/include/drivers/st/stm32mp_ram.h b/include/drivers/st/stm32mp_ram.h new file mode 100644 index 0000000000..6e1e21d572 --- /dev/null +++ b/include/drivers/st/stm32mp_ram.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef STM32MP_RAM_H +#define STM32MP_RAM_H + +#include <stdbool.h> + +#include <drivers/st/stm32mp_ddr.h> + +#define PARAM(x, y) \ + { \ + .name = x, \ + .offset = offsetof(struct stm32mp_ddr_config, y), \ + .size = sizeof(config.y) / sizeof(uint32_t), \ + } + +#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) +#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) + +struct stm32mp_ddr_param { + const char *name; /* Name in DT */ + const uint32_t offset; /* Offset in config struct */ + const uint32_t size; /* Size of parameters */ +}; + +int stm32mp_ddr_dt_get_info(void *fdt, int node, struct stm32mp_ddr_info *info); +int stm32mp_ddr_dt_get_param(void *fdt, int node, const struct stm32mp_ddr_param *param, + uint32_t param_size, uintptr_t config); + +#endif /* STM32MP_RAM_H */ diff --git a/include/drivers/st/stpmic1.h b/include/drivers/st/stpmic1.h index f7e293b189..2dfc7f8306 100644 --- a/include/drivers/st/stpmic1.h +++ b/include/drivers/st/stpmic1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -86,15 +86,15 @@ #define ITSOURCE4_REG 0xB3U /* Registers masks */ -#define LDO_VOLTAGE_MASK 0x7CU -#define BUCK_VOLTAGE_MASK 0xFCU +#define LDO_VOLTAGE_MASK GENMASK(6, 2) +#define BUCK_VOLTAGE_MASK GENMASK(7, 2) #define LDO_BUCK_VOLTAGE_SHIFT 2 -#define LDO_BUCK_ENABLE_MASK 0x01U -#define LDO_BUCK_HPLP_ENABLE_MASK 0x02U +#define LDO_BUCK_ENABLE_MASK BIT(0) +#define LDO_BUCK_HPLP_ENABLE_MASK BIT(1) #define LDO_BUCK_HPLP_SHIFT 1 -#define LDO_BUCK_RANK_MASK 0x01U -#define LDO_BUCK_RESET_MASK 0x01U -#define LDO_BUCK_PULL_DOWN_MASK 0x03U +#define LDO_BUCK_RANK_MASK BIT(0) +#define LDO_BUCK_RESET_MASK BIT(0) +#define LDO_BUCK_PULL_DOWN_MASK GENMASK(1, 0) /* Pull down register */ #define BUCK1_PULL_DOWN_SHIFT 0 @@ -103,6 +103,22 @@ #define BUCK4_PULL_DOWN_SHIFT 6 #define VREF_DDR_PULL_DOWN_SHIFT 4 +/* ICC register */ +#define BUCK1_ICC_SHIFT 0 +#define BUCK2_ICC_SHIFT 1 +#define BUCK3_ICC_SHIFT 2 +#define BUCK4_ICC_SHIFT 3 +#define PWR_SW1_ICC_SHIFT 4 +#define PWR_SW2_ICC_SHIFT 5 +#define BOOST_ICC_SHIFT 6 + +#define LDO1_ICC_SHIFT 0 +#define LDO2_ICC_SHIFT 1 +#define LDO3_ICC_SHIFT 2 +#define LDO4_ICC_SHIFT 3 +#define LDO5_ICC_SHIFT 4 +#define LDO6_ICC_SHIFT 5 + /* Buck Mask reset register */ #define BUCK1_MASK_RESET 0 #define BUCK2_MASK_RESET 1 @@ -118,6 +134,10 @@ #define LDO6_MASK_RESET 5 #define VREF_DDR_MASK_RESET 6 +/* LDO3 Special modes */ +#define LDO3_BYPASS BIT(7) +#define LDO3_DDR_SEL 31U + /* Main PMIC Control Register (MAIN_CONTROL_REG) */ #define ICC_EVENT_ENABLED BIT(4) #define PWRCTRL_POLARITY_HIGH BIT(3) @@ -135,19 +155,22 @@ /* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */ #define SWIN_DETECTOR_ENABLED BIT(7) #define SWOUT_DETECTOR_ENABLED BIT(6) -#define VINLOW_HYST_MASK 0x3 +#define VINLOW_HYST_MASK GENMASK(1, 0) #define VINLOW_HYST_SHIFT 4 -#define VINLOW_THRESHOLD_MASK 0x7 +#define VINLOW_THRESHOLD_MASK GENMASK(2, 0) #define VINLOW_THRESHOLD_SHIFT 1 -#define VINLOW_ENABLED 0x01 -#define VINLOW_CTRL_REG_MASK 0xFF +#define VINLOW_ENABLED BIT(0) +#define VINLOW_CTRL_REG_MASK GENMASK(7, 0) /* USB Control Register */ #define BOOST_OVP_DISABLED BIT(7) #define VBUS_OTG_DETECTION_DISABLED BIT(6) +#define SW_OUT_DISCHARGE BIT(5) +#define VBUS_OTG_DISCHARGE BIT(4) #define OCP_LIMIT_HIGH BIT(3) #define SWIN_SWOUT_ENABLED BIT(2) #define USBSW_OTG_SWITCH_ENABLED BIT(1) +#define BOOST_ENABLED BIT(0) int stpmic1_powerctrl_on(void); int stpmic1_switch_off(void); @@ -156,11 +179,17 @@ int stpmic1_register_write(uint8_t register_id, uint8_t value); int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask); int stpmic1_regulator_enable(const char *name); int stpmic1_regulator_disable(const char *name); -uint8_t stpmic1_is_regulator_enabled(const char *name); +bool stpmic1_is_regulator_enabled(const char *name); int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts); +int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels, + size_t *levels_count); int stpmic1_regulator_voltage_get(const char *name); int stpmic1_regulator_pull_down_set(const char *name); int stpmic1_regulator_mask_reset_set(const char *name); +int stpmic1_regulator_icc_set(const char *name); +int stpmic1_regulator_sink_mode_set(const char *name); +int stpmic1_regulator_bypass_mode_set(const char *name); +int stpmic1_active_discharge_mode_set(const char *name); void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr); int stpmic1_get_version(unsigned long *version); diff --git a/include/drivers/ufs.h b/include/drivers/ufs.h index 574c4ea0a5..2a63fd42e1 100644 --- a/include/drivers/ufs.h +++ b/include/drivers/ufs.h @@ -57,6 +57,21 @@ /* UTP Transfer Request Completion Status */ #define UFS_INT_UTRCS (1 << 0) +#define UFS_INT_FATAL (UFS_INT_DFES |\ + UFS_INT_HCFES |\ + UFS_INT_SBFES) +#define UFS_INT_ERR (UFS_INT_FATAL |\ + UFS_INT_UE) + +#define UFS_UIC_PA_ERROR_MASK 0x8000001F +#define UFS_UIC_DL_ERROR_MASK 0x8000FFFF +#define UFS_UIC_NL_ERROR_MASK 0x80000007 +#define UFS_UIC_TL_ERROR_MASK 0x8000007F +#define UFS_UIC_DME_ERROR_MASK 0x80000001 + +#define PA_INIT_ERR (1 << 13) +#define PA_LAYER_GEN_ERR (1 << 4) + /* Host Controller Status */ #define HCS 0x30 #define HCS_UPMCRS_MASK (7 << 8) @@ -69,6 +84,7 @@ /* Host Controller Enable */ #define HCE 0x34 #define HCE_ENABLE 1 +#define HCE_DISABLE 0 /* Host UIC Error Code PHY Adapter Layer */ #define UECPA 0x38 @@ -254,6 +270,31 @@ #define UFS_VENDOR_SKHYNIX U(0x1AD) #define MAX_MODEL_LEN 16 + +/* maximum number of retries for a general UIC command */ +#define UFS_UIC_COMMAND_RETRIES 3 + +/* maximum number of retries for a transfer command */ +#define UFS_CMD_RETRIES 3 + +/* maximum number of retries for reading UFS capacity */ +#define UFS_READ_CAPACITY_RETRIES 10 + +/* maximum number of link-startup retries */ +#define DME_LINKSTARTUP_RETRIES 10 + +#define HCE_ENABLE_OUTER_RETRIES 3 +#define HCE_ENABLE_INNER_RETRIES 50 +#define HCE_ENABLE_TIMEOUT_US 100 +#define HCE_DISABLE_TIMEOUT_US 1000 + +#define FDEVICEINIT_TIMEOUT_MS 1500 + +#define UIC_CMD_TIMEOUT_MS 500 +#define QUERY_REQ_TIMEOUT_MS 1500 +#define NOP_OUT_TIMEOUT_MS 50 +#define CMD_TIMEOUT_MS 5000 + /** * ufs_dev_desc - ufs device details from the device descriptor * @wmanufacturerid: card details @@ -498,7 +539,7 @@ typedef struct utp_utrd { uintptr_t prdt; size_t size_upiu; size_t size_resp_upiu; - size_t size_prdt; + size_t prdt_length; int task_tag; } utp_utrd_t; diff --git a/include/drivers/usb_device.h b/include/drivers/usb_device.h new file mode 100644 index 0000000000..d4c491c47e --- /dev/null +++ b/include/drivers/usb_device.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef USB_DEVICE_H +#define USB_DEVICE_H + +#include <stdbool.h> +#include <stdint.h> + +#include <lib/utils_def.h> + +#define USBD_MAX_NUM_INTERFACES 1U +#define USBD_MAX_NUM_CONFIGURATION 1U + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0AU +#define USB_LEN_DEV_DESC 0x12U +#define USB_LEN_CFG_DESC 0x09U +#define USB_LEN_IF_DESC 0x09U +#define USB_LEN_EP_DESC 0x07U +#define USB_LEN_OTG_DESC 0x03U +#define USB_LEN_LANGID_STR_DESC 0x04U +#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09U + +#define USBD_IDX_LANGID_STR 0x00U +#define USBD_IDX_MFC_STR 0x01U +#define USBD_IDX_PRODUCT_STR 0x02U +#define USBD_IDX_SERIAL_STR 0x03U +#define USBD_IDX_CONFIG_STR 0x04U +#define USBD_IDX_INTERFACE_STR 0x05U +#define USBD_IDX_USER0_STR 0x06U + +#define USB_REQ_TYPE_STANDARD 0x00U +#define USB_REQ_TYPE_CLASS 0x20U +#define USB_REQ_TYPE_VENDOR 0x40U +#define USB_REQ_TYPE_MASK 0x60U + +#define USB_REQ_RECIPIENT_DEVICE 0x00U +#define USB_REQ_RECIPIENT_INTERFACE 0x01U +#define USB_REQ_RECIPIENT_ENDPOINT 0x02U +#define USB_REQ_RECIPIENT_MASK 0x1FU + +#define USB_REQ_DIRECTION 0x80U + +#define USB_REQ_GET_STATUS 0x00U +#define USB_REQ_CLEAR_FEATURE 0x01U +#define USB_REQ_SET_FEATURE 0x03U +#define USB_REQ_SET_ADDRESS 0x05U +#define USB_REQ_GET_DESCRIPTOR 0x06U +#define USB_REQ_SET_DESCRIPTOR 0x07U +#define USB_REQ_GET_CONFIGURATION 0x08U +#define USB_REQ_SET_CONFIGURATION 0x09U +#define USB_REQ_GET_INTERFACE 0x0AU +#define USB_REQ_SET_INTERFACE 0x0BU +#define USB_REQ_SYNCH_FRAME 0x0CU + +#define USB_DESC_TYPE_DEVICE 0x01U +#define USB_DESC_TYPE_CONFIGURATION 0x02U +#define USB_DESC_TYPE_STRING 0x03U +#define USB_DESC_TYPE_INTERFACE 0x04U +#define USB_DESC_TYPE_ENDPOINT 0x05U +#define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07U +#define USB_DESC_TYPE_BOS 0x0FU + +#define USB_CONFIG_REMOTE_WAKEUP 2U +#define USB_CONFIG_SELF_POWERED 1U + +#define USB_MAX_EP0_SIZE 64U + +/* Device Status */ +#define USBD_STATE_DEFAULT 1U +#define USBD_STATE_ADDRESSED 2U +#define USBD_STATE_CONFIGURED 3U +#define USBD_STATE_SUSPENDED 4U + +/* EP0 State */ +#define USBD_EP0_IDLE 0U +#define USBD_EP0_SETUP 1U +#define USBD_EP0_DATA_IN 2U +#define USBD_EP0_DATA_OUT 3U +#define USBD_EP0_STATUS_IN 4U +#define USBD_EP0_STATUS_OUT 5U +#define USBD_EP0_STALL 6U + +#define USBD_EP_TYPE_CTRL 0U +#define USBD_EP_TYPE_ISOC 1U +#define USBD_EP_TYPE_BULK 2U +#define USBD_EP_TYPE_INTR 3U + +#define USBD_OUT_EPNUM_MASK GENMASK(15, 0) +#define USBD_OUT_COUNT_MASK GENMASK(31, 16) +#define USBD_OUT_COUNT_SHIFT 16U + +/* Number of EP supported, allow to reduce footprint: default max = 15 */ +#ifndef CONFIG_USBD_EP_NB +#define USBD_EP_NB 15U +#else +#define USBD_EP_NB CONFIG_USBD_EP_NB +#endif + +#define LOBYTE(x) ((uint8_t)((x) & 0x00FF)) +#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00) >> 8)) + +struct usb_setup_req { + uint8_t bm_request; + uint8_t b_request; + uint16_t value; + uint16_t index; + uint16_t length; +}; + +struct usb_handle; + +struct usb_class { + uint8_t (*init)(struct usb_handle *pdev, uint8_t cfgidx); + uint8_t (*de_init)(struct usb_handle *pdev, uint8_t cfgidx); + /* Control Endpoints */ + uint8_t (*setup)(struct usb_handle *pdev, struct usb_setup_req *req); + uint8_t (*ep0_tx_sent)(struct usb_handle *pdev); + uint8_t (*ep0_rx_ready)(struct usb_handle *pdev); + /* Class Specific Endpoints */ + uint8_t (*data_in)(struct usb_handle *pdev, uint8_t epnum); + uint8_t (*data_out)(struct usb_handle *pdev, uint8_t epnum); + uint8_t (*sof)(struct usb_handle *pdev); + uint8_t (*iso_in_incomplete)(struct usb_handle *pdev, uint8_t epnum); + uint8_t (*iso_out_incomplete)(struct usb_handle *pdev, uint8_t epnum); +}; + +/* Following USB Device status */ +enum usb_status { + USBD_OK = 0U, + USBD_BUSY, + USBD_FAIL, + USBD_TIMEOUT +}; + +/* Action to do after IT handling */ +enum usb_action { + USB_NOTHING = 0U, + USB_DATA_OUT, + USB_DATA_IN, + USB_SETUP, + USB_ENUM_DONE, + USB_READ_DATA_PACKET, + USB_READ_SETUP_PACKET, + USB_RESET, + USB_RESUME, + USB_SUSPEND, + USB_LPM, + USB_SOF, + USB_DISCONNECT, + USB_WRITE_EMPTY +}; + +/* USB Device descriptors structure */ +struct usb_desc { + uint8_t *(*get_device_desc)(uint16_t *length); + uint8_t *(*get_lang_id_desc)(uint16_t *length); + uint8_t *(*get_manufacturer_desc)(uint16_t *length); + uint8_t *(*get_product_desc)(uint16_t *length); + uint8_t *(*get_serial_desc)(uint16_t *length); + uint8_t *(*get_configuration_desc)(uint16_t *length); + uint8_t *(*get_interface_desc)(uint16_t *length); + uint8_t *(*get_usr_desc)(uint8_t index, uint16_t *length); + uint8_t *(*get_config_desc)(uint16_t *length); + uint8_t *(*get_device_qualifier_desc)(uint16_t *length); + /* optional: high speed capable device operating at its other speed */ + uint8_t *(*get_other_speed_config_desc)(uint16_t *length); +}; + +/* USB Device handle structure */ +struct usb_endpoint { + uint32_t status; + uint32_t total_length; + uint32_t rem_length; + uint32_t maxpacket; +}; + +/* + * EndPoint descriptor + * num : Endpoint number, between 0 and 15 (limited by USBD_EP_NB) + * is_in: Endpoint direction + * type : Endpoint type + * maxpacket: Endpoint Max packet size: between 0 and 64KB + * xfer_buff: Pointer to transfer buffer + * xfer_len: Current transfer lengt + * hxfer_count: Partial transfer length in case of multi packet transfer + */ +struct usbd_ep { + uint8_t num; + bool is_in; + uint8_t type; + uint32_t maxpacket; + uint8_t *xfer_buff; + uint32_t xfer_len; + uint32_t xfer_count; +}; + +enum pcd_lpm_state { + LPM_L0 = 0x00U, /* on */ + LPM_L1 = 0x01U, /* LPM L1 sleep */ + LPM_L2 = 0x02U, /* suspend */ + LPM_L3 = 0x03U, /* off */ +}; + +/* USB Device descriptors structure */ +struct usb_driver { + enum usb_status (*ep0_out_start)(void *handle); + enum usb_status (*ep_start_xfer)(void *handle, struct usbd_ep *ep); + enum usb_status (*ep0_start_xfer)(void *handle, struct usbd_ep *ep); + enum usb_status (*write_packet)(void *handle, uint8_t *src, + uint8_t ch_ep_num, uint16_t len); + void *(*read_packet)(void *handle, uint8_t *dest, uint16_t len); + enum usb_status (*ep_set_stall)(void *handle, struct usbd_ep *ep); + enum usb_status (*start_device)(void *handle); + enum usb_status (*stop_device)(void *handle); + enum usb_status (*set_address)(void *handle, uint8_t address); + enum usb_status (*write_empty_tx_fifo)(void *handle, + uint32_t epnum, uint32_t xfer_len, + uint32_t *xfer_count, + uint32_t maxpacket, + uint8_t **xfer_buff); + enum usb_action (*it_handler)(void *handle, uint32_t *param); +}; + +/* USB Peripheral Controller Drivers */ +struct pcd_handle { + void *instance; /* Register base address */ + struct usbd_ep in_ep[USBD_EP_NB]; /* IN endpoint parameters */ + struct usbd_ep out_ep[USBD_EP_NB]; /* OUT endpoint parameters */ + uint32_t setup[12]; /* Setup packet buffer */ + enum pcd_lpm_state lpm_state; /* LPM State */ +}; + +/* USB Device handle structure */ +struct usb_handle { + uint8_t id; + uint32_t dev_config; + uint32_t dev_config_status; + struct usb_endpoint ep_in[USBD_EP_NB]; + struct usb_endpoint ep_out[USBD_EP_NB]; + uint32_t ep0_state; + uint32_t ep0_data_len; + uint8_t dev_state; + uint8_t dev_old_state; + uint8_t dev_address; + uint32_t dev_remote_wakeup; + struct usb_setup_req request; + const struct usb_desc *desc; + struct usb_class *class; + void *class_data; + void *user_data; + struct pcd_handle *data; + const struct usb_driver *driver; +}; + +enum usb_status usb_core_handle_it(struct usb_handle *pdev); +enum usb_status usb_core_receive(struct usb_handle *pdev, uint8_t ep_addr, + uint8_t *p_buf, uint32_t len); +enum usb_status usb_core_transmit(struct usb_handle *pdev, uint8_t ep_addr, + uint8_t *p_buf, uint32_t len); +enum usb_status usb_core_receive_ep0(struct usb_handle *pdev, uint8_t *p_buf, + uint32_t len); +enum usb_status usb_core_transmit_ep0(struct usb_handle *pdev, uint8_t *p_buf, + uint32_t len); +void usb_core_ctl_error(struct usb_handle *pdev); +enum usb_status usb_core_start(struct usb_handle *pdev); +enum usb_status usb_core_stop(struct usb_handle *pdev); +enum usb_status register_usb_driver(struct usb_handle *pdev, + struct pcd_handle *pcd_handle, + const struct usb_driver *driver, + void *driver_handle); +enum usb_status register_platform(struct usb_handle *pdev, + const struct usb_desc *plat_call_back); + +#endif /* USB_DEVICE_H */ diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 67e66b23fd..0d25dedbbe 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -1,278 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. */ -#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ -#define _DT_BINDINGS_STM32MP1_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* Bus clocks */ -#define TIM2 6 -#define TIM3 7 -#define TIM4 8 -#define TIM5 9 -#define TIM6 10 -#define TIM7 11 -#define TIM12 12 -#define TIM13 13 -#define TIM14 14 -#define LPTIM1 15 -#define SPI2 16 -#define SPI3 17 -#define USART2 18 -#define USART3 19 -#define UART4 20 -#define UART5 21 -#define UART7 22 -#define UART8 23 -#define I2C1 24 -#define I2C2 25 -#define I2C3 26 -#define I2C5 27 -#define SPDIF 28 -#define CEC 29 -#define DAC12 30 -#define MDIO 31 -#define TIM1 32 -#define TIM8 33 -#define TIM15 34 -#define TIM16 35 -#define TIM17 36 -#define SPI1 37 -#define SPI4 38 -#define SPI5 39 -#define USART6 40 -#define SAI1 41 -#define SAI2 42 -#define SAI3 43 -#define DFSDM 44 -#define FDCAN 45 -#define LPTIM2 46 -#define LPTIM3 47 -#define LPTIM4 48 -#define LPTIM5 49 -#define SAI4 50 -#define SYSCFG 51 -#define VREF 52 -#define TMPSENS 53 -#define PMBCTRL 54 -#define HDP 55 -#define LTDC 56 -#define DSI 57 -#define IWDG2 58 -#define USBPHY 59 -#define STGENRO 60 -#define SPI6 61 -#define I2C4 62 -#define I2C6 63 -#define USART1 64 -#define RTCAPB 65 -#define TZC1 66 -#define TZPC 67 -#define IWDG1 68 -#define BSEC 69 -#define STGEN 70 -#define DMA1 71 -#define DMA2 72 -#define DMAMUX 73 -#define ADC12 74 -#define USBO 75 -#define SDMMC3 76 -#define DCMI 77 -#define CRYP2 78 -#define HASH2 79 -#define RNG2 80 -#define CRC2 81 -#define HSEM 82 -#define IPCC 83 -#define GPIOA 84 -#define GPIOB 85 -#define GPIOC 86 -#define GPIOD 87 -#define GPIOE 88 -#define GPIOF 89 -#define GPIOG 90 -#define GPIOH 91 -#define GPIOI 92 -#define GPIOJ 93 -#define GPIOK 94 -#define GPIOZ 95 -#define CRYP1 96 -#define HASH1 97 -#define RNG1 98 -#define BKPSRAM 99 -#define MDMA 100 -#define GPU 101 -#define ETHCK 102 -#define ETHTX 103 -#define ETHRX 104 -#define ETHMAC 105 -#define FMC 106 -#define QSPI 107 -#define SDMMC1 108 -#define SDMMC2 109 -#define CRC1 110 -#define USBH 111 -#define ETHSTP 112 -#define TZC2 113 - -/* Kernel clocks */ -#define SDMMC1_K 118 -#define SDMMC2_K 119 -#define SDMMC3_K 120 -#define FMC_K 121 -#define QSPI_K 122 -#define ETHCK_K 123 -#define RNG1_K 124 -#define RNG2_K 125 -#define GPU_K 126 -#define USBPHY_K 127 -#define STGEN_K 128 -#define SPDIF_K 129 -#define SPI1_K 130 -#define SPI2_K 131 -#define SPI3_K 132 -#define SPI4_K 133 -#define SPI5_K 134 -#define SPI6_K 135 -#define CEC_K 136 -#define I2C1_K 137 -#define I2C2_K 138 -#define I2C3_K 139 -#define I2C4_K 140 -#define I2C5_K 141 -#define I2C6_K 142 -#define LPTIM1_K 143 -#define LPTIM2_K 144 -#define LPTIM3_K 145 -#define LPTIM4_K 146 -#define LPTIM5_K 147 -#define USART1_K 148 -#define USART2_K 149 -#define USART3_K 150 -#define UART4_K 151 -#define UART5_K 152 -#define USART6_K 153 -#define UART7_K 154 -#define UART8_K 155 -#define DFSDM_K 156 -#define FDCAN_K 157 -#define SAI1_K 158 -#define SAI2_K 159 -#define SAI3_K 160 -#define SAI4_K 161 -#define ADC12_K 162 -#define DSI_K 163 -#define DSI_PX 164 -#define ADFSDM_K 165 -#define USBO_K 166 -#define LTDC_PX 167 -#define DAC12_K 168 -#define ETHPTP_K 169 - -/* PLL */ -#define PLL1 176 -#define PLL2 177 -#define PLL3 178 -#define PLL4 179 - -/* ODF */ -#define PLL1_P 180 -#define PLL1_Q 181 -#define PLL1_R 182 -#define PLL2_P 183 -#define PLL2_Q 184 -#define PLL2_R 185 -#define PLL3_P 186 -#define PLL3_Q 187 -#define PLL3_R 188 -#define PLL4_P 189 -#define PLL4_Q 190 -#define PLL4_R 191 - -/* AUX */ -#define RTC 192 - -/* MCLK */ -#define CK_PER 193 -#define CK_MPU 194 -#define CK_AXI 195 -#define CK_MCU 196 - -/* Time base */ -#define TIM2_K 197 -#define TIM3_K 198 -#define TIM4_K 199 -#define TIM5_K 200 -#define TIM6_K 201 -#define TIM7_K 202 -#define TIM12_K 203 -#define TIM13_K 204 -#define TIM14_K 205 -#define TIM1_K 206 -#define TIM8_K 207 -#define TIM15_K 208 -#define TIM16_K 209 -#define TIM17_K 210 - -/* MCO clocks */ -#define CK_MCO1 211 -#define CK_MCO2 212 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 214 -#define CK_TRACE 215 - -/* DDR */ -#define DDRC1 220 -#define DDRC1LP 221 -#define DDRC2 222 -#define DDRC2LP 223 -#define DDRPHYC 224 -#define DDRPHYCLP 225 -#define DDRCAPB 226 -#define DDRCAPBLP 227 -#define AXIDCG 228 -#define DDRPHYCAPB 229 -#define DDRPHYCAPBLP 230 -#define DDRPERFM 231 - -#define STM32MP1_LAST_CLK 232 - -/* SCMI clock identifiers */ -#define CK_SCMI0_HSE 0 -#define CK_SCMI0_HSI 1 -#define CK_SCMI0_CSI 2 -#define CK_SCMI0_LSE 3 -#define CK_SCMI0_LSI 4 -#define CK_SCMI0_PLL2_Q 5 -#define CK_SCMI0_PLL2_R 6 -#define CK_SCMI0_MPU 7 -#define CK_SCMI0_AXI 8 -#define CK_SCMI0_BSEC 9 -#define CK_SCMI0_CRYP1 10 -#define CK_SCMI0_GPIOZ 11 -#define CK_SCMI0_HASH1 12 -#define CK_SCMI0_I2C4 13 -#define CK_SCMI0_I2C6 14 -#define CK_SCMI0_IWDG1 15 -#define CK_SCMI0_RNG1 16 -#define CK_SCMI0_RTC 17 -#define CK_SCMI0_RTCAPB 18 -#define CK_SCMI0_SPI6 19 -#define CK_SCMI0_USART1 20 - -#define CK_SCMI1_PLL3_Q 0 -#define CK_SCMI1_PLL3_R 1 -#define CK_SCMI1_MCU 2 - -#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ +#if STM32MP13 +#include "stm32mp13-clks.h" +#endif +#if STM32MP15 +#include "stm32mp15-clks.h" +#endif diff --git a/include/dt-bindings/clock/stm32mp1-clksrc.h b/include/dt-bindings/clock/stm32mp1-clksrc.h index 818f4b7682..d02ddcd9a1 100644 --- a/include/dt-bindings/clock/stm32mp1-clksrc.h +++ b/include/dt-bindings/clock/stm32mp1-clksrc.h @@ -1,283 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved */ -#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ -#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ - -/* PLL output is enable when x=1, with x=p,q or r */ -#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) - -/* st,clksrc: mandatory clock source */ - -#define CLK_MPU_HSI 0x00000200 -#define CLK_MPU_HSE 0x00000201 -#define CLK_MPU_PLL1P 0x00000202 -#define CLK_MPU_PLL1P_DIV 0x00000203 - -#define CLK_AXI_HSI 0x00000240 -#define CLK_AXI_HSE 0x00000241 -#define CLK_AXI_PLL2P 0x00000242 - -#define CLK_MCU_HSI 0x00000480 -#define CLK_MCU_HSE 0x00000481 -#define CLK_MCU_CSI 0x00000482 -#define CLK_MCU_PLL3P 0x00000483 - -#define CLK_PLL12_HSI 0x00000280 -#define CLK_PLL12_HSE 0x00000281 - -#define CLK_PLL3_HSI 0x00008200 -#define CLK_PLL3_HSE 0x00008201 -#define CLK_PLL3_CSI 0x00008202 - -#define CLK_PLL4_HSI 0x00008240 -#define CLK_PLL4_HSE 0x00008241 -#define CLK_PLL4_CSI 0x00008242 -#define CLK_PLL4_I2SCKIN 0x00008243 - -#define CLK_RTC_DISABLED 0x00001400 -#define CLK_RTC_LSE 0x00001401 -#define CLK_RTC_LSI 0x00001402 -#define CLK_RTC_HSE 0x00001403 - -#define CLK_MCO1_HSI 0x00008000 -#define CLK_MCO1_HSE 0x00008001 -#define CLK_MCO1_CSI 0x00008002 -#define CLK_MCO1_LSI 0x00008003 -#define CLK_MCO1_LSE 0x00008004 -#define CLK_MCO1_DISABLED 0x0000800F - -#define CLK_MCO2_MPU 0x00008040 -#define CLK_MCO2_AXI 0x00008041 -#define CLK_MCO2_MCU 0x00008042 -#define CLK_MCO2_PLL4P 0x00008043 -#define CLK_MCO2_HSE 0x00008044 -#define CLK_MCO2_HSI 0x00008045 -#define CLK_MCO2_DISABLED 0x0000804F - -/* st,pkcs: peripheral kernel clock source */ - -#define CLK_I2C12_PCLK1 0x00008C00 -#define CLK_I2C12_PLL4R 0x00008C01 -#define CLK_I2C12_HSI 0x00008C02 -#define CLK_I2C12_CSI 0x00008C03 -#define CLK_I2C12_DISABLED 0x00008C07 - -#define CLK_I2C35_PCLK1 0x00008C40 -#define CLK_I2C35_PLL4R 0x00008C41 -#define CLK_I2C35_HSI 0x00008C42 -#define CLK_I2C35_CSI 0x00008C43 -#define CLK_I2C35_DISABLED 0x00008C47 - -#define CLK_I2C46_PCLK5 0x00000C00 -#define CLK_I2C46_PLL3Q 0x00000C01 -#define CLK_I2C46_HSI 0x00000C02 -#define CLK_I2C46_CSI 0x00000C03 -#define CLK_I2C46_DISABLED 0x00000C07 - -#define CLK_SAI1_PLL4Q 0x00008C80 -#define CLK_SAI1_PLL3Q 0x00008C81 -#define CLK_SAI1_I2SCKIN 0x00008C82 -#define CLK_SAI1_CKPER 0x00008C83 -#define CLK_SAI1_PLL3R 0x00008C84 -#define CLK_SAI1_DISABLED 0x00008C87 - -#define CLK_SAI2_PLL4Q 0x00008CC0 -#define CLK_SAI2_PLL3Q 0x00008CC1 -#define CLK_SAI2_I2SCKIN 0x00008CC2 -#define CLK_SAI2_CKPER 0x00008CC3 -#define CLK_SAI2_SPDIF 0x00008CC4 -#define CLK_SAI2_PLL3R 0x00008CC5 -#define CLK_SAI2_DISABLED 0x00008CC7 - -#define CLK_SAI3_PLL4Q 0x00008D00 -#define CLK_SAI3_PLL3Q 0x00008D01 -#define CLK_SAI3_I2SCKIN 0x00008D02 -#define CLK_SAI3_CKPER 0x00008D03 -#define CLK_SAI3_PLL3R 0x00008D04 -#define CLK_SAI3_DISABLED 0x00008D07 - -#define CLK_SAI4_PLL4Q 0x00008D40 -#define CLK_SAI4_PLL3Q 0x00008D41 -#define CLK_SAI4_I2SCKIN 0x00008D42 -#define CLK_SAI4_CKPER 0x00008D43 -#define CLK_SAI4_PLL3R 0x00008D44 -#define CLK_SAI4_DISABLED 0x00008D47 - -#define CLK_SPI2S1_PLL4P 0x00008D80 -#define CLK_SPI2S1_PLL3Q 0x00008D81 -#define CLK_SPI2S1_I2SCKIN 0x00008D82 -#define CLK_SPI2S1_CKPER 0x00008D83 -#define CLK_SPI2S1_PLL3R 0x00008D84 -#define CLK_SPI2S1_DISABLED 0x00008D87 - -#define CLK_SPI2S23_PLL4P 0x00008DC0 -#define CLK_SPI2S23_PLL3Q 0x00008DC1 -#define CLK_SPI2S23_I2SCKIN 0x00008DC2 -#define CLK_SPI2S23_CKPER 0x00008DC3 -#define CLK_SPI2S23_PLL3R 0x00008DC4 -#define CLK_SPI2S23_DISABLED 0x00008DC7 - -#define CLK_SPI45_PCLK2 0x00008E00 -#define CLK_SPI45_PLL4Q 0x00008E01 -#define CLK_SPI45_HSI 0x00008E02 -#define CLK_SPI45_CSI 0x00008E03 -#define CLK_SPI45_HSE 0x00008E04 -#define CLK_SPI45_DISABLED 0x00008E07 - -#define CLK_SPI6_PCLK5 0x00000C40 -#define CLK_SPI6_PLL4Q 0x00000C41 -#define CLK_SPI6_HSI 0x00000C42 -#define CLK_SPI6_CSI 0x00000C43 -#define CLK_SPI6_HSE 0x00000C44 -#define CLK_SPI6_PLL3Q 0x00000C45 -#define CLK_SPI6_DISABLED 0x00000C47 - -#define CLK_UART6_PCLK2 0x00008E40 -#define CLK_UART6_PLL4Q 0x00008E41 -#define CLK_UART6_HSI 0x00008E42 -#define CLK_UART6_CSI 0x00008E43 -#define CLK_UART6_HSE 0x00008E44 -#define CLK_UART6_DISABLED 0x00008E47 - -#define CLK_UART24_PCLK1 0x00008E80 -#define CLK_UART24_PLL4Q 0x00008E81 -#define CLK_UART24_HSI 0x00008E82 -#define CLK_UART24_CSI 0x00008E83 -#define CLK_UART24_HSE 0x00008E84 -#define CLK_UART24_DISABLED 0x00008E87 - -#define CLK_UART35_PCLK1 0x00008EC0 -#define CLK_UART35_PLL4Q 0x00008EC1 -#define CLK_UART35_HSI 0x00008EC2 -#define CLK_UART35_CSI 0x00008EC3 -#define CLK_UART35_HSE 0x00008EC4 -#define CLK_UART35_DISABLED 0x00008EC7 - -#define CLK_UART78_PCLK1 0x00008F00 -#define CLK_UART78_PLL4Q 0x00008F01 -#define CLK_UART78_HSI 0x00008F02 -#define CLK_UART78_CSI 0x00008F03 -#define CLK_UART78_HSE 0x00008F04 -#define CLK_UART78_DISABLED 0x00008F07 - -#define CLK_UART1_PCLK5 0x00000C80 -#define CLK_UART1_PLL3Q 0x00000C81 -#define CLK_UART1_HSI 0x00000C82 -#define CLK_UART1_CSI 0x00000C83 -#define CLK_UART1_PLL4Q 0x00000C84 -#define CLK_UART1_HSE 0x00000C85 -#define CLK_UART1_DISABLED 0x00000C87 - -#define CLK_SDMMC12_HCLK6 0x00008F40 -#define CLK_SDMMC12_PLL3R 0x00008F41 -#define CLK_SDMMC12_PLL4P 0x00008F42 -#define CLK_SDMMC12_HSI 0x00008F43 -#define CLK_SDMMC12_DISABLED 0x00008F47 - -#define CLK_SDMMC3_HCLK2 0x00008F80 -#define CLK_SDMMC3_PLL3R 0x00008F81 -#define CLK_SDMMC3_PLL4P 0x00008F82 -#define CLK_SDMMC3_HSI 0x00008F83 -#define CLK_SDMMC3_DISABLED 0x00008F87 - -#define CLK_ETH_PLL4P 0x00008FC0 -#define CLK_ETH_PLL3Q 0x00008FC1 -#define CLK_ETH_DISABLED 0x00008FC3 - -#define CLK_QSPI_ACLK 0x00009000 -#define CLK_QSPI_PLL3R 0x00009001 -#define CLK_QSPI_PLL4P 0x00009002 -#define CLK_QSPI_CKPER 0x00009003 - -#define CLK_FMC_ACLK 0x00009040 -#define CLK_FMC_PLL3R 0x00009041 -#define CLK_FMC_PLL4P 0x00009042 -#define CLK_FMC_CKPER 0x00009043 - -#define CLK_FDCAN_HSE 0x000090C0 -#define CLK_FDCAN_PLL3Q 0x000090C1 -#define CLK_FDCAN_PLL4Q 0x000090C2 -#define CLK_FDCAN_PLL4R 0x000090C3 - -#define CLK_SPDIF_PLL4P 0x00009140 -#define CLK_SPDIF_PLL3Q 0x00009141 -#define CLK_SPDIF_HSI 0x00009142 -#define CLK_SPDIF_DISABLED 0x00009143 - -#define CLK_CEC_LSE 0x00009180 -#define CLK_CEC_LSI 0x00009181 -#define CLK_CEC_CSI_DIV122 0x00009182 -#define CLK_CEC_DISABLED 0x00009183 - -#define CLK_USBPHY_HSE 0x000091C0 -#define CLK_USBPHY_PLL4R 0x000091C1 -#define CLK_USBPHY_HSE_DIV2 0x000091C2 -#define CLK_USBPHY_DISABLED 0x000091C3 - -#define CLK_USBO_PLL4R 0x800091C0 -#define CLK_USBO_USBPHY 0x800091C1 - -#define CLK_RNG1_CSI 0x00000CC0 -#define CLK_RNG1_PLL4R 0x00000CC1 -#define CLK_RNG1_LSE 0x00000CC2 -#define CLK_RNG1_LSI 0x00000CC3 - -#define CLK_RNG2_CSI 0x00009200 -#define CLK_RNG2_PLL4R 0x00009201 -#define CLK_RNG2_LSE 0x00009202 -#define CLK_RNG2_LSI 0x00009203 - -#define CLK_CKPER_HSI 0x00000D00 -#define CLK_CKPER_CSI 0x00000D01 -#define CLK_CKPER_HSE 0x00000D02 -#define CLK_CKPER_DISABLED 0x00000D03 - -#define CLK_STGEN_HSI 0x00000D40 -#define CLK_STGEN_HSE 0x00000D41 -#define CLK_STGEN_DISABLED 0x00000D43 - -#define CLK_DSI_DSIPLL 0x00009240 -#define CLK_DSI_PLL4P 0x00009241 - -#define CLK_ADC_PLL4R 0x00009280 -#define CLK_ADC_CKPER 0x00009281 -#define CLK_ADC_PLL3Q 0x00009282 -#define CLK_ADC_DISABLED 0x00009283 - -#define CLK_LPTIM45_PCLK3 0x000092C0 -#define CLK_LPTIM45_PLL4P 0x000092C1 -#define CLK_LPTIM45_PLL3Q 0x000092C2 -#define CLK_LPTIM45_LSE 0x000092C3 -#define CLK_LPTIM45_LSI 0x000092C4 -#define CLK_LPTIM45_CKPER 0x000092C5 -#define CLK_LPTIM45_DISABLED 0x000092C7 - -#define CLK_LPTIM23_PCLK3 0x00009300 -#define CLK_LPTIM23_PLL4Q 0x00009301 -#define CLK_LPTIM23_CKPER 0x00009302 -#define CLK_LPTIM23_LSE 0x00009303 -#define CLK_LPTIM23_LSI 0x00009304 -#define CLK_LPTIM23_DISABLED 0x00009307 - -#define CLK_LPTIM1_PCLK1 0x00009340 -#define CLK_LPTIM1_PLL4P 0x00009341 -#define CLK_LPTIM1_PLL3Q 0x00009342 -#define CLK_LPTIM1_LSE 0x00009343 -#define CLK_LPTIM1_LSI 0x00009344 -#define CLK_LPTIM1_CKPER 0x00009345 -#define CLK_LPTIM1_DISABLED 0x00009347 - -/* define for st,pll /csg */ -#define SSCG_MODE_CENTER_SPREAD 0 -#define SSCG_MODE_DOWN_SPREAD 1 - -/* define for st,drive */ -#define LSEDRV_LOWEST 0 -#define LSEDRV_MEDIUM_LOW 1 -#define LSEDRV_MEDIUM_HIGH 2 -#define LSEDRV_HIGHEST 3 - +#if STM32MP13 +#include "stm32mp13-clksrc.h" +#endif +#if STM32MP15 +#include "stm32mp15-clksrc.h" #endif diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h new file mode 100644 index 0000000000..1d5bb78381 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ +#define _DT_BINDINGS_STM32MP13_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* PLL */ +#define PLL1 6 +#define PLL2 7 +#define PLL3 8 +#define PLL4 9 + +/* ODF */ +#define PLL1_P 10 +#define PLL1_Q 11 +#define PLL1_R 12 +#define PLL2_P 13 +#define PLL2_Q 14 +#define PLL2_R 15 +#define PLL3_P 16 +#define PLL3_Q 17 +#define PLL3_R 18 +#define PLL4_P 19 +#define PLL4_Q 20 +#define PLL4_R 21 + +#define PCLK1 22 +#define PCLK2 23 +#define PCLK3 24 +#define PCLK4 25 +#define PCLK5 26 +#define PCLK6 27 + +/* SYSTEM CLOCK */ +#define CK_PER 28 +#define CK_MPU 29 +#define CK_AXI 30 +#define CK_MLAHB 31 + +/* BASE TIMER */ +#define CK_TIMG1 32 +#define CK_TIMG2 33 +#define CK_TIMG3 34 + +/* AUX */ +#define RTC 35 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 36 +#define CK_TRACE 37 + +/* MCO clocks */ +#define CK_MCO1 38 +#define CK_MCO2 39 + +/* IP clocks */ +#define SYSCFG 40 +#define VREF 41 +#define TMPSENS 42 +#define PMBCTRL 43 +#define HDP 44 +#define IWDG2 45 +#define STGENRO 46 +#define USART1 47 +#define RTCAPB 48 +#define TZC 49 +#define TZPC 50 +#define IWDG1 51 +#define BSEC 52 +#define DMA1 53 +#define DMA2 54 +#define DMAMUX1 55 +#define DMAMUX2 56 +#define GPIOA 57 +#define GPIOB 58 +#define GPIOC 59 +#define GPIOD 60 +#define GPIOE 61 +#define GPIOF 62 +#define GPIOG 63 +#define GPIOH 64 +#define GPIOI 65 +#define CRYP1 66 +#define HASH1 67 +#define BKPSRAM 68 +#define MDMA 69 +#define CRC1 70 +#define USBH 71 +#define DMA3 72 +#define TSC 73 +#define PKA 74 +#define AXIMC 75 +#define MCE 76 +#define ETH1TX 77 +#define ETH2TX 78 +#define ETH1RX 79 +#define ETH2RX 80 +#define ETH1MAC 81 +#define ETH2MAC 82 +#define ETH1STP 83 +#define ETH2STP 84 + +/* IP clocks with parents */ +#define SDMMC1_K 85 +#define SDMMC2_K 86 +#define ADC1_K 87 +#define ADC2_K 88 +#define FMC_K 89 +#define QSPI_K 90 +#define RNG1_K 91 +#define USBPHY_K 92 +#define STGEN_K 93 +#define SPDIF_K 94 +#define SPI1_K 95 +#define SPI2_K 96 +#define SPI3_K 97 +#define SPI4_K 98 +#define SPI5_K 99 +#define I2C1_K 100 +#define I2C2_K 101 +#define I2C3_K 102 +#define I2C4_K 103 +#define I2C5_K 104 +#define TIM2_K 105 +#define TIM3_K 106 +#define TIM4_K 107 +#define TIM5_K 108 +#define TIM6_K 109 +#define TIM7_K 110 +#define TIM12_K 111 +#define TIM13_K 112 +#define TIM14_K 113 +#define TIM1_K 114 +#define TIM8_K 115 +#define TIM15_K 116 +#define TIM16_K 117 +#define TIM17_K 118 +#define LPTIM1_K 119 +#define LPTIM2_K 120 +#define LPTIM3_K 121 +#define LPTIM4_K 122 +#define LPTIM5_K 123 +#define USART1_K 124 +#define USART2_K 125 +#define USART3_K 126 +#define UART4_K 127 +#define UART5_K 128 +#define USART6_K 129 +#define UART7_K 130 +#define UART8_K 131 +#define DFSDM_K 132 +#define FDCAN_K 133 +#define SAI1_K 134 +#define SAI2_K 135 +#define ADFSDM_K 136 +#define USBO_K 137 +#define LTDC_PX 138 +#define ETH1CK_K 139 +#define ETH1PTP_K 140 +#define ETH2CK_K 141 +#define ETH2PTP_K 142 +#define DCMIPP_K 143 +#define SAES_K 144 +#define DTS_K 145 + +/* DDR */ +#define DDRC1 146 +#define DDRC1LP 147 +#define DDRC2 148 +#define DDRC2LP 149 +#define DDRPHYC 150 +#define DDRPHYCLP 151 +#define DDRCAPB 152 +#define DDRCAPBLP 153 +#define AXIDCG 154 +#define DDRPHYCAPB 155 +#define DDRPHYCAPBLP 156 +#define DDRPERFM 157 + +#define ADC1 158 +#define ADC2 159 +#define SAI1 160 +#define SAI2 161 + +#define STM32MP1_LAST_CLK 162 + +/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_HSE_DIV2 5 +#define CK_SCMI0_PLL2_Q 6 +#define CK_SCMI0_PLL2_R 7 +#define CK_SCMI0_PLL3_P 8 +#define CK_SCMI0_PLL3_Q 9 +#define CK_SCMI0_PLL3_R 10 +#define CK_SCMI0_PLL4_P 11 +#define CK_SCMI0_PLL4_Q 12 +#define CK_SCMI0_PLL4_R 13 +#define CK_SCMI0_MPU 14 +#define CK_SCMI0_AXI 15 +#define CK_SCMI0_MLAHB 16 +#define CK_SCMI0_CKPER 17 +#define CK_SCMI0_PCLK1 18 +#define CK_SCMI0_PCLK2 19 +#define CK_SCMI0_PCLK3 20 +#define CK_SCMI0_PCLK4 21 +#define CK_SCMI0_PCLK5 22 +#define CK_SCMI0_PCLK6 23 +#define CK_SCMI0_CKTIMG1 24 +#define CK_SCMI0_CKTIMG2 25 +#define CK_SCMI0_CKTIMG3 26 +#define CK_SCMI0_RTC 27 +#define CK_SCMI0_RTCAPB 28 +#define CK_SCMI0_BSEC 29 + +#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp13-clksrc.h b/include/dt-bindings/clock/stm32mp13-clksrc.h new file mode 100644 index 0000000000..0d54ab98dd --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clksrc.h @@ -0,0 +1,394 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ + +#define CMD_DIV 0 +#define CMD_MUX 1 +#define CMD_CLK 2 +#define CMD_RESERVED1 3 + +#define CMD_SHIFT 26 +#define CMD_MASK 0xFC000000 +#define CMD_DATA_MASK 0x03FFFFFF + +#define DIV_ID_SHIFT 8 +#define DIV_ID_MASK 0x0000FF00 + +#define DIV_DIVN_SHIFT 0 +#define DIV_DIVN_MASK 0x000000FF + +#define MUX_ID_SHIFT 4 +#define MUX_ID_MASK 0x00000FF0 + +#define MUX_SEL_SHIFT 0 +#define MUX_SEL_MASK 0x0000000F + +#define CLK_ID_MASK GENMASK_32(19, 11) +#define CLK_ID_SHIFT 11 +#define CLK_ON_MASK 0x00000400 +#define CLK_ON_SHIFT 10 +#define CLK_DIV_MASK GENMASK_32(9, 4) +#define CLK_DIV_SHIFT 4 +#define CLK_SEL_MASK GENMASK_32(3, 0) +#define CLK_SEL_SHIFT 0 + +#define DIV_PLL1DIVP 0 +#define DIV_PLL2DIVP 1 +#define DIV_PLL2DIVQ 2 +#define DIV_PLL2DIVR 3 +#define DIV_PLL3DIVP 4 +#define DIV_PLL3DIVQ 5 +#define DIV_PLL3DIVR 6 +#define DIV_PLL4DIVP 7 +#define DIV_PLL4DIVQ 8 +#define DIV_PLL4DIVR 9 +#define DIV_MPU 10 +#define DIV_AXI 11 +#define DIV_MLAHB 12 +#define DIV_APB1 13 +#define DIV_APB2 14 +#define DIV_APB3 15 +#define DIV_APB4 16 +#define DIV_APB5 17 +#define DIV_APB6 18 +#define DIV_RTC 19 +#define DIV_MCO1 20 +#define DIV_MCO2 21 +#define DIV_HSI 22 +#define DIV_TRACE 23 +#define DIV_ETH1PTP 24 +#define DIV_ETH2PTP 25 +#define DIV_MAX 26 + +#define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ + ((div_id) << DIV_ID_SHIFT |\ + (div))) + +#define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ + ((mux_id) << MUX_ID_SHIFT |\ + (sel))) + +/* MCO output is enable */ +#define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\ + (((mco_id) << CLK_ID_SHIFT) |\ + (sel)) | CLK_ON_MASK) + +#define MCO_DISABLED(mco_id) ((CMD_CLK << CMD_SHIFT) |\ + ((mco_id) << CLK_ID_SHIFT)) + +/* CLK output is enable */ +#define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ + (((clk_id) << CLK_ID_SHIFT) |\ + (sel)) | CLK_ON_MASK) + +#define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\ + ((clk_id) << CLK_ID_SHIFT)) + +#define MUX_MPU 0 +#define MUX_AXI 1 +#define MUX_MLAHB 2 +#define MUX_PLL12 3 +#define MUX_PLL3 4 +#define MUX_PLL4 5 +#define MUX_RTC 6 +#define MUX_MCO1 7 +#define MUX_MCO2 8 +#define MUX_CKPER 9 +#define MUX_KERNEL_BEGIN 10 +#define MUX_ADC1 10 +#define MUX_ADC2 11 +#define MUX_DCMIPP 12 +#define MUX_ETH1 13 +#define MUX_ETH2 14 +#define MUX_FDCAN 15 +#define MUX_FMC 16 +#define MUX_I2C12 17 +#define MUX_I2C3 18 +#define MUX_I2C4 19 +#define MUX_I2C5 20 +#define MUX_LPTIM1 21 +#define MUX_LPTIM2 22 +#define MUX_LPTIM3 23 +#define MUX_LPTIM45 24 +#define MUX_QSPI 25 +#define MUX_RNG1 26 +#define MUX_SAES 27 +#define MUX_SAI1 28 +#define MUX_SAI2 29 +#define MUX_SDMMC1 30 +#define MUX_SDMMC2 31 +#define MUX_SPDIF 32 +#define MUX_SPI1 33 +#define MUX_SPI23 34 +#define MUX_SPI4 35 +#define MUX_SPI5 36 +#define MUX_STGEN 37 +#define MUX_UART1 38 +#define MUX_UART2 39 +#define MUX_UART35 40 +#define MUX_UART4 41 +#define MUX_UART6 42 +#define MUX_UART78 43 +#define MUX_USBO 44 +#define MUX_USBPHY 45 +#define MUX_MAX 46 + +#define CLK_MPU_HSI CLKSRC(MUX_MPU, 0) +#define CLK_MPU_HSE CLKSRC(MUX_MPU, 1) +#define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2) +#define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3) + +#define CLK_AXI_HSI CLKSRC(MUX_AXI, 0) +#define CLK_AXI_HSE CLKSRC(MUX_AXI, 1) +#define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2) + +#define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0) +#define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1) +#define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2) +#define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3) + +#define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0) +#define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1) + +#define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0) +#define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1) +#define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2) + +#define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0) +#define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1) +#define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2) + +#define CLK_RTC_DISABLED CLK_DISABLED(RTC) +#define CLK_RTC_LSE CLK_SRC(RTC, 1) +#define CLK_RTC_LSI CLK_SRC(RTC, 2) +#define CLK_RTC_HSE CLK_SRC(RTC, 3) + +#define CLK_MCO1_HSI CLK_SRC(CK_MCO1, 0) +#define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1) +#define CLK_MCO1_CSI CLK_SRC(CK_MCO1, 2) +#define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3) +#define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4) +#define CLK_MCO1_DISABLED CLK_DISABLED(CK_MCO1) + +#define CLK_MCO2_MPU CLK_SRC(CK_MCO2, 0) +#define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1) +#define CLK_MCO2_MLAHB CLK_SRC(CK_MCO2, 2) +#define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3) +#define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4) +#define CLK_MCO2_HSI CLK_SRC(CK_MCO2, 5) +#define CLK_MCO2_DISABLED CLK_DISABLED(CK_MCO2) + +#define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0) +#define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1) +#define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2) +#define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3) + +#define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0) +#define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1) +#define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2) +#define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3) + +#define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0) +#define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1) +#define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2) +#define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3) + +#define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0) +#define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1) +#define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2) +#define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3) + +#define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0) +#define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1) +#define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2) +#define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3) + +#define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0) +#define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1) +#define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2) +#define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3) +#define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4) + +#define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0) +#define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1) +#define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2) +#define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3) +#define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4) + +#define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0) +#define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1) +#define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2) +#define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3) +#define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4) +#define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5) + +#define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0) +#define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1) +#define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2) +#define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3) +#define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4) + +#define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0) +#define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1) +#define CLK_UART1_HSI CLKSRC(MUX_UART1, 2) +#define CLK_UART1_CSI CLKSRC(MUX_UART1, 3) +#define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4) +#define CLK_UART1_HSE CLKSRC(MUX_UART1, 5) + +#define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0) +#define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1) +#define CLK_UART2_HSI CLKSRC(MUX_UART2, 2) +#define CLK_UART2_CSI CLKSRC(MUX_UART2, 3) +#define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4) +#define CLK_UART2_HSE CLKSRC(MUX_UART2, 5) + +#define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0) +#define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1) +#define CLK_UART35_HSI CLKSRC(MUX_UART35, 2) +#define CLK_UART35_CSI CLKSRC(MUX_UART35, 3) +#define CLK_UART35_HSE CLKSRC(MUX_UART35, 4) + +#define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0) +#define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1) +#define CLK_UART4_HSI CLKSRC(MUX_UART4, 2) +#define CLK_UART4_CSI CLKSRC(MUX_UART4, 3) +#define CLK_UART4_HSE CLKSRC(MUX_UART4, 4) + +#define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0) +#define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1) +#define CLK_UART6_HSI CLKSRC(MUX_UART6, 2) +#define CLK_UART6_CSI CLKSRC(MUX_UART6, 3) +#define CLK_UART6_HSE CLKSRC(MUX_UART6, 4) + +#define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0) +#define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1) +#define CLK_UART78_HSI CLKSRC(MUX_UART78, 2) +#define CLK_UART78_CSI CLKSRC(MUX_UART78, 3) +#define CLK_UART78_HSE CLKSRC(MUX_UART78, 4) + +#define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0) +#define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1) +#define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2) +#define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3) +#define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4) +#define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5) + +#define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0) +#define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1) +#define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2) +#define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3) +#define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4) + +#define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0) +#define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1) +#define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2) +#define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3) +#define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4) + +#define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0) +#define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1) +#define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2) +#define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3) +#define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4) +#define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5) + +#define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0) +#define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1) +#define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2) +#define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3) +#define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4) + +#define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0) +#define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1) +#define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2) +#define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3) +#define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4) +#define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5) + +#define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0) +#define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1) +#define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2) +#define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3) + +#define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0) +#define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1) +#define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2) + +#define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0) +#define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1) +#define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2) + +#define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0) +#define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1) +#define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2) + +#define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0) +#define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1) +#define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2) +#define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3) + +#define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0) +#define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1) +#define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2) +#define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3) + +#define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0) +#define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1) + +#define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0) +#define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1) + +#define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0) +#define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1) +#define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2) + +#define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0) +#define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1) + +#define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0) +#define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1) +#define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2) +#define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3) + +#define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0) +#define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1) +#define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2) +#define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3) + +#define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0) +#define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1) +/* WARNING: POSITION 2 OF RNG1 MUX IS RESERVED */ +#define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3) + +#define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0) +#define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1) + +#define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0) +#define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1) +#define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2) +#define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3) + +#define CLK_SAES_AXI CLKSRC(MUX_SAES, 0) +#define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1) +#define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2) +#define CLK_SAES_LSI CLKSRC(MUX_SAES, 3) + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif /* _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ */ diff --git a/include/dt-bindings/clock/stm32mp15-clks.h b/include/dt-bindings/clock/stm32mp15-clks.h new file mode 100644 index 0000000000..bef1368ee7 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp15-clks.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ +#define _DT_BINDINGS_STM32MP1_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* Bus clocks */ +#define TIM2 6 +#define TIM3 7 +#define TIM4 8 +#define TIM5 9 +#define TIM6 10 +#define TIM7 11 +#define TIM12 12 +#define TIM13 13 +#define TIM14 14 +#define LPTIM1 15 +#define SPI2 16 +#define SPI3 17 +#define USART2 18 +#define USART3 19 +#define UART4 20 +#define UART5 21 +#define UART7 22 +#define UART8 23 +#define I2C1 24 +#define I2C2 25 +#define I2C3 26 +#define I2C5 27 +#define SPDIF 28 +#define CEC 29 +#define DAC12 30 +#define MDIO 31 +#define TIM1 32 +#define TIM8 33 +#define TIM15 34 +#define TIM16 35 +#define TIM17 36 +#define SPI1 37 +#define SPI4 38 +#define SPI5 39 +#define USART6 40 +#define SAI1 41 +#define SAI2 42 +#define SAI3 43 +#define DFSDM 44 +#define FDCAN 45 +#define LPTIM2 46 +#define LPTIM3 47 +#define LPTIM4 48 +#define LPTIM5 49 +#define SAI4 50 +#define SYSCFG 51 +#define VREF 52 +#define TMPSENS 53 +#define PMBCTRL 54 +#define HDP 55 +#define LTDC 56 +#define DSI 57 +#define IWDG2 58 +#define USBPHY 59 +#define STGENRO 60 +#define SPI6 61 +#define I2C4 62 +#define I2C6 63 +#define USART1 64 +#define RTCAPB 65 +#define TZC1 66 +#define TZPC 67 +#define IWDG1 68 +#define BSEC 69 +#define STGEN 70 +#define DMA1 71 +#define DMA2 72 +#define DMAMUX 73 +#define ADC12 74 +#define USBO 75 +#define SDMMC3 76 +#define DCMI 77 +#define CRYP2 78 +#define HASH2 79 +#define RNG2 80 +#define CRC2 81 +#define HSEM 82 +#define IPCC 83 +#define GPIOA 84 +#define GPIOB 85 +#define GPIOC 86 +#define GPIOD 87 +#define GPIOE 88 +#define GPIOF 89 +#define GPIOG 90 +#define GPIOH 91 +#define GPIOI 92 +#define GPIOJ 93 +#define GPIOK 94 +#define GPIOZ 95 +#define CRYP1 96 +#define HASH1 97 +#define RNG1 98 +#define BKPSRAM 99 +#define MDMA 100 +#define GPU 101 +#define ETHCK 102 +#define ETHTX 103 +#define ETHRX 104 +#define ETHMAC 105 +#define FMC 106 +#define QSPI 107 +#define SDMMC1 108 +#define SDMMC2 109 +#define CRC1 110 +#define USBH 111 +#define ETHSTP 112 +#define TZC2 113 + +/* Kernel clocks */ +#define SDMMC1_K 118 +#define SDMMC2_K 119 +#define SDMMC3_K 120 +#define FMC_K 121 +#define QSPI_K 122 +#define ETHCK_K 123 +#define RNG1_K 124 +#define RNG2_K 125 +#define GPU_K 126 +#define USBPHY_K 127 +#define STGEN_K 128 +#define SPDIF_K 129 +#define SPI1_K 130 +#define SPI2_K 131 +#define SPI3_K 132 +#define SPI4_K 133 +#define SPI5_K 134 +#define SPI6_K 135 +#define CEC_K 136 +#define I2C1_K 137 +#define I2C2_K 138 +#define I2C3_K 139 +#define I2C4_K 140 +#define I2C5_K 141 +#define I2C6_K 142 +#define LPTIM1_K 143 +#define LPTIM2_K 144 +#define LPTIM3_K 145 +#define LPTIM4_K 146 +#define LPTIM5_K 147 +#define USART1_K 148 +#define USART2_K 149 +#define USART3_K 150 +#define UART4_K 151 +#define UART5_K 152 +#define USART6_K 153 +#define UART7_K 154 +#define UART8_K 155 +#define DFSDM_K 156 +#define FDCAN_K 157 +#define SAI1_K 158 +#define SAI2_K 159 +#define SAI3_K 160 +#define SAI4_K 161 +#define ADC12_K 162 +#define DSI_K 163 +#define DSI_PX 164 +#define ADFSDM_K 165 +#define USBO_K 166 +#define LTDC_PX 167 +#define DAC12_K 168 +#define ETHPTP_K 169 + +/* PLL */ +#define PLL1 176 +#define PLL2 177 +#define PLL3 178 +#define PLL4 179 + +/* ODF */ +#define PLL1_P 180 +#define PLL1_Q 181 +#define PLL1_R 182 +#define PLL2_P 183 +#define PLL2_Q 184 +#define PLL2_R 185 +#define PLL3_P 186 +#define PLL3_Q 187 +#define PLL3_R 188 +#define PLL4_P 189 +#define PLL4_Q 190 +#define PLL4_R 191 + +/* AUX */ +#define RTC 192 + +/* MCLK */ +#define CK_PER 193 +#define CK_MPU 194 +#define CK_AXI 195 +#define CK_MCU 196 + +/* Time base */ +#define TIM2_K 197 +#define TIM3_K 198 +#define TIM4_K 199 +#define TIM5_K 200 +#define TIM6_K 201 +#define TIM7_K 202 +#define TIM12_K 203 +#define TIM13_K 204 +#define TIM14_K 205 +#define TIM1_K 206 +#define TIM8_K 207 +#define TIM15_K 208 +#define TIM16_K 209 +#define TIM17_K 210 + +/* MCO clocks */ +#define CK_MCO1 211 +#define CK_MCO2 212 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 214 +#define CK_TRACE 215 + +/* DDR */ +#define DDRC1 220 +#define DDRC1LP 221 +#define DDRC2 222 +#define DDRC2LP 223 +#define DDRPHYC 224 +#define DDRPHYCLP 225 +#define DDRCAPB 226 +#define DDRCAPBLP 227 +#define AXIDCG 228 +#define DDRPHYCAPB 229 +#define DDRPHYCAPBLP 230 +#define DDRPERFM 231 + +#define STM32MP1_LAST_CLK 232 + +/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_PLL2_Q 5 +#define CK_SCMI0_PLL2_R 6 +#define CK_SCMI0_MPU 7 +#define CK_SCMI0_AXI 8 +#define CK_SCMI0_BSEC 9 +#define CK_SCMI0_CRYP1 10 +#define CK_SCMI0_GPIOZ 11 +#define CK_SCMI0_HASH1 12 +#define CK_SCMI0_I2C4 13 +#define CK_SCMI0_I2C6 14 +#define CK_SCMI0_IWDG1 15 +#define CK_SCMI0_RNG1 16 +#define CK_SCMI0_RTC 17 +#define CK_SCMI0_RTCAPB 18 +#define CK_SCMI0_SPI6 19 +#define CK_SCMI0_USART1 20 + +#define CK_SCMI1_PLL3_Q 0 +#define CK_SCMI1_PLL3_R 1 +#define CK_SCMI1_MCU 2 + +#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp15-clksrc.h b/include/dt-bindings/clock/stm32mp15-clksrc.h new file mode 100644 index 0000000000..3a3792da3f --- /dev/null +++ b/include/dt-bindings/clock/stm32mp15-clksrc.h @@ -0,0 +1,282 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_ + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* st,clksrc: mandatory clock source */ +#define CLK_MPU_HSI 0x00000200 +#define CLK_MPU_HSE 0x00000201 +#define CLK_MPU_PLL1P 0x00000202 +#define CLK_MPU_PLL1P_DIV 0x00000203 + +#define CLK_AXI_HSI 0x00000240 +#define CLK_AXI_HSE 0x00000241 +#define CLK_AXI_PLL2P 0x00000242 + +#define CLK_MCU_HSI 0x00000480 +#define CLK_MCU_HSE 0x00000481 +#define CLK_MCU_CSI 0x00000482 +#define CLK_MCU_PLL3P 0x00000483 + +#define CLK_PLL12_HSI 0x00000280 +#define CLK_PLL12_HSE 0x00000281 + +#define CLK_PLL3_HSI 0x00008200 +#define CLK_PLL3_HSE 0x00008201 +#define CLK_PLL3_CSI 0x00008202 + +#define CLK_PLL4_HSI 0x00008240 +#define CLK_PLL4_HSE 0x00008241 +#define CLK_PLL4_CSI 0x00008242 +#define CLK_PLL4_I2SCKIN 0x00008243 + +#define CLK_RTC_DISABLED 0x00001400 +#define CLK_RTC_LSE 0x00001401 +#define CLK_RTC_LSI 0x00001402 +#define CLK_RTC_HSE 0x00001403 + +#define CLK_MCO1_HSI 0x00008000 +#define CLK_MCO1_HSE 0x00008001 +#define CLK_MCO1_CSI 0x00008002 +#define CLK_MCO1_LSI 0x00008003 +#define CLK_MCO1_LSE 0x00008004 +#define CLK_MCO1_DISABLED 0x0000800F + +#define CLK_MCO2_MPU 0x00008040 +#define CLK_MCO2_AXI 0x00008041 +#define CLK_MCO2_MCU 0x00008042 +#define CLK_MCO2_PLL4P 0x00008043 +#define CLK_MCO2_HSE 0x00008044 +#define CLK_MCO2_HSI 0x00008045 +#define CLK_MCO2_DISABLED 0x0000804F + +/* st,pkcs: peripheral kernel clock source */ + +#define CLK_I2C12_PCLK1 0x00008C00 +#define CLK_I2C12_PLL4R 0x00008C01 +#define CLK_I2C12_HSI 0x00008C02 +#define CLK_I2C12_CSI 0x00008C03 +#define CLK_I2C12_DISABLED 0x00008C07 + +#define CLK_I2C35_PCLK1 0x00008C40 +#define CLK_I2C35_PLL4R 0x00008C41 +#define CLK_I2C35_HSI 0x00008C42 +#define CLK_I2C35_CSI 0x00008C43 +#define CLK_I2C35_DISABLED 0x00008C47 + +#define CLK_I2C46_PCLK5 0x00000C00 +#define CLK_I2C46_PLL3Q 0x00000C01 +#define CLK_I2C46_HSI 0x00000C02 +#define CLK_I2C46_CSI 0x00000C03 +#define CLK_I2C46_DISABLED 0x00000C07 + +#define CLK_SAI1_PLL4Q 0x00008C80 +#define CLK_SAI1_PLL3Q 0x00008C81 +#define CLK_SAI1_I2SCKIN 0x00008C82 +#define CLK_SAI1_CKPER 0x00008C83 +#define CLK_SAI1_PLL3R 0x00008C84 +#define CLK_SAI1_DISABLED 0x00008C87 + +#define CLK_SAI2_PLL4Q 0x00008CC0 +#define CLK_SAI2_PLL3Q 0x00008CC1 +#define CLK_SAI2_I2SCKIN 0x00008CC2 +#define CLK_SAI2_CKPER 0x00008CC3 +#define CLK_SAI2_SPDIF 0x00008CC4 +#define CLK_SAI2_PLL3R 0x00008CC5 +#define CLK_SAI2_DISABLED 0x00008CC7 + +#define CLK_SAI3_PLL4Q 0x00008D00 +#define CLK_SAI3_PLL3Q 0x00008D01 +#define CLK_SAI3_I2SCKIN 0x00008D02 +#define CLK_SAI3_CKPER 0x00008D03 +#define CLK_SAI3_PLL3R 0x00008D04 +#define CLK_SAI3_DISABLED 0x00008D07 + +#define CLK_SAI4_PLL4Q 0x00008D40 +#define CLK_SAI4_PLL3Q 0x00008D41 +#define CLK_SAI4_I2SCKIN 0x00008D42 +#define CLK_SAI4_CKPER 0x00008D43 +#define CLK_SAI4_PLL3R 0x00008D44 +#define CLK_SAI4_DISABLED 0x00008D47 + +#define CLK_SPI2S1_PLL4P 0x00008D80 +#define CLK_SPI2S1_PLL3Q 0x00008D81 +#define CLK_SPI2S1_I2SCKIN 0x00008D82 +#define CLK_SPI2S1_CKPER 0x00008D83 +#define CLK_SPI2S1_PLL3R 0x00008D84 +#define CLK_SPI2S1_DISABLED 0x00008D87 + +#define CLK_SPI2S23_PLL4P 0x00008DC0 +#define CLK_SPI2S23_PLL3Q 0x00008DC1 +#define CLK_SPI2S23_I2SCKIN 0x00008DC2 +#define CLK_SPI2S23_CKPER 0x00008DC3 +#define CLK_SPI2S23_PLL3R 0x00008DC4 +#define CLK_SPI2S23_DISABLED 0x00008DC7 + +#define CLK_SPI45_PCLK2 0x00008E00 +#define CLK_SPI45_PLL4Q 0x00008E01 +#define CLK_SPI45_HSI 0x00008E02 +#define CLK_SPI45_CSI 0x00008E03 +#define CLK_SPI45_HSE 0x00008E04 +#define CLK_SPI45_DISABLED 0x00008E07 + +#define CLK_SPI6_PCLK5 0x00000C40 +#define CLK_SPI6_PLL4Q 0x00000C41 +#define CLK_SPI6_HSI 0x00000C42 +#define CLK_SPI6_CSI 0x00000C43 +#define CLK_SPI6_HSE 0x00000C44 +#define CLK_SPI6_PLL3Q 0x00000C45 +#define CLK_SPI6_DISABLED 0x00000C47 + +#define CLK_UART6_PCLK2 0x00008E40 +#define CLK_UART6_PLL4Q 0x00008E41 +#define CLK_UART6_HSI 0x00008E42 +#define CLK_UART6_CSI 0x00008E43 +#define CLK_UART6_HSE 0x00008E44 +#define CLK_UART6_DISABLED 0x00008E47 + +#define CLK_UART24_PCLK1 0x00008E80 +#define CLK_UART24_PLL4Q 0x00008E81 +#define CLK_UART24_HSI 0x00008E82 +#define CLK_UART24_CSI 0x00008E83 +#define CLK_UART24_HSE 0x00008E84 +#define CLK_UART24_DISABLED 0x00008E87 + +#define CLK_UART35_PCLK1 0x00008EC0 +#define CLK_UART35_PLL4Q 0x00008EC1 +#define CLK_UART35_HSI 0x00008EC2 +#define CLK_UART35_CSI 0x00008EC3 +#define CLK_UART35_HSE 0x00008EC4 +#define CLK_UART35_DISABLED 0x00008EC7 + +#define CLK_UART78_PCLK1 0x00008F00 +#define CLK_UART78_PLL4Q 0x00008F01 +#define CLK_UART78_HSI 0x00008F02 +#define CLK_UART78_CSI 0x00008F03 +#define CLK_UART78_HSE 0x00008F04 +#define CLK_UART78_DISABLED 0x00008F07 + +#define CLK_UART1_PCLK5 0x00000C80 +#define CLK_UART1_PLL3Q 0x00000C81 +#define CLK_UART1_HSI 0x00000C82 +#define CLK_UART1_CSI 0x00000C83 +#define CLK_UART1_PLL4Q 0x00000C84 +#define CLK_UART1_HSE 0x00000C85 +#define CLK_UART1_DISABLED 0x00000C87 + +#define CLK_SDMMC12_HCLK6 0x00008F40 +#define CLK_SDMMC12_PLL3R 0x00008F41 +#define CLK_SDMMC12_PLL4P 0x00008F42 +#define CLK_SDMMC12_HSI 0x00008F43 +#define CLK_SDMMC12_DISABLED 0x00008F47 + +#define CLK_SDMMC3_HCLK2 0x00008F80 +#define CLK_SDMMC3_PLL3R 0x00008F81 +#define CLK_SDMMC3_PLL4P 0x00008F82 +#define CLK_SDMMC3_HSI 0x00008F83 +#define CLK_SDMMC3_DISABLED 0x00008F87 + +#define CLK_ETH_PLL4P 0x00008FC0 +#define CLK_ETH_PLL3Q 0x00008FC1 +#define CLK_ETH_DISABLED 0x00008FC3 + +#define CLK_QSPI_ACLK 0x00009000 +#define CLK_QSPI_PLL3R 0x00009001 +#define CLK_QSPI_PLL4P 0x00009002 +#define CLK_QSPI_CKPER 0x00009003 + +#define CLK_FMC_ACLK 0x00009040 +#define CLK_FMC_PLL3R 0x00009041 +#define CLK_FMC_PLL4P 0x00009042 +#define CLK_FMC_CKPER 0x00009043 + +#define CLK_FDCAN_HSE 0x000090C0 +#define CLK_FDCAN_PLL3Q 0x000090C1 +#define CLK_FDCAN_PLL4Q 0x000090C2 +#define CLK_FDCAN_PLL4R 0x000090C3 + +#define CLK_SPDIF_PLL4P 0x00009140 +#define CLK_SPDIF_PLL3Q 0x00009141 +#define CLK_SPDIF_HSI 0x00009142 +#define CLK_SPDIF_DISABLED 0x00009143 + +#define CLK_CEC_LSE 0x00009180 +#define CLK_CEC_LSI 0x00009181 +#define CLK_CEC_CSI_DIV122 0x00009182 +#define CLK_CEC_DISABLED 0x00009183 + +#define CLK_USBPHY_HSE 0x000091C0 +#define CLK_USBPHY_PLL4R 0x000091C1 +#define CLK_USBPHY_HSE_DIV2 0x000091C2 +#define CLK_USBPHY_DISABLED 0x000091C3 + +#define CLK_USBO_PLL4R 0x800091C0 +#define CLK_USBO_USBPHY 0x800091C1 + +#define CLK_RNG1_CSI 0x00000CC0 +#define CLK_RNG1_PLL4R 0x00000CC1 +#define CLK_RNG1_LSE 0x00000CC2 +#define CLK_RNG1_LSI 0x00000CC3 + +#define CLK_RNG2_CSI 0x00009200 +#define CLK_RNG2_PLL4R 0x00009201 +#define CLK_RNG2_LSE 0x00009202 +#define CLK_RNG2_LSI 0x00009203 + +#define CLK_CKPER_HSI 0x00000D00 +#define CLK_CKPER_CSI 0x00000D01 +#define CLK_CKPER_HSE 0x00000D02 +#define CLK_CKPER_DISABLED 0x00000D03 + +#define CLK_STGEN_HSI 0x00000D40 +#define CLK_STGEN_HSE 0x00000D41 +#define CLK_STGEN_DISABLED 0x00000D43 + +#define CLK_DSI_DSIPLL 0x00009240 +#define CLK_DSI_PLL4P 0x00009241 + +#define CLK_ADC_PLL4R 0x00009280 +#define CLK_ADC_CKPER 0x00009281 +#define CLK_ADC_PLL3Q 0x00009282 +#define CLK_ADC_DISABLED 0x00009283 + +#define CLK_LPTIM45_PCLK3 0x000092C0 +#define CLK_LPTIM45_PLL4P 0x000092C1 +#define CLK_LPTIM45_PLL3Q 0x000092C2 +#define CLK_LPTIM45_LSE 0x000092C3 +#define CLK_LPTIM45_LSI 0x000092C4 +#define CLK_LPTIM45_CKPER 0x000092C5 +#define CLK_LPTIM45_DISABLED 0x000092C7 + +#define CLK_LPTIM23_PCLK3 0x00009300 +#define CLK_LPTIM23_PLL4Q 0x00009301 +#define CLK_LPTIM23_CKPER 0x00009302 +#define CLK_LPTIM23_LSE 0x00009303 +#define CLK_LPTIM23_LSI 0x00009304 +#define CLK_LPTIM23_DISABLED 0x00009307 + +#define CLK_LPTIM1_PCLK1 0x00009340 +#define CLK_LPTIM1_PLL4P 0x00009341 +#define CLK_LPTIM1_PLL3Q 0x00009342 +#define CLK_LPTIM1_LSE 0x00009343 +#define CLK_LPTIM1_LSI 0x00009344 +#define CLK_LPTIM1_CKPER 0x00009345 +#define CLK_LPTIM1_DISABLED 0x00009347 + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif diff --git a/include/dt-bindings/clock/stm32mp25-clks.h b/include/dt-bindings/clock/stm32mp25-clks.h new file mode 100644 index 0000000000..c4ff9cfcef --- /dev/null +++ b/include/dt-bindings/clock/stm32mp25-clks.h @@ -0,0 +1,494 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_ +#define _DT_BINDINGS_STM32MP25_CLKS_H_ + +/* INTERNAL/EXTERNAL OSCILLATORS */ +#define HSI_CK 0 +#define HSE_CK 1 +#define MSI_CK 2 +#define LSI_CK 3 +#define LSE_CK 4 +#define I2S_CK 5 +#define RTC_CK 6 +#define SPDIF_CK_SYMB 7 + +/* PLL CLOCKS */ +#define PLL1_CK 8 +#define PLL2_CK 9 +#define PLL3_CK 10 +#define PLL4_CK 11 +#define PLL5_CK 12 +#define PLL6_CK 13 +#define PLL7_CK 14 +#define PLL8_CK 15 + +#define CK_CPU1 16 + +/* APB DIV CLOCKS */ +#define CK_ICN_APB1 17 +#define CK_ICN_APB2 18 +#define CK_ICN_APB3 19 +#define CK_ICN_APB4 20 +#define CK_ICN_APBDBG 21 + +/* GLOBAL TIMER */ +#define TIMG1_CK 22 +#define TIMG2_CK 23 + +/* FLEXGEN CLOCKS */ +#define CK_ICN_HS_MCU 24 +#define CK_ICN_SDMMC 25 +#define CK_ICN_DDR 26 +#define CK_ICN_DISPLAY 27 +#define CK_ICN_HSL 28 +#define CK_ICN_NIC 29 +#define CK_ICN_VID 30 +#define CK_FLEXGEN_07 31 +#define CK_FLEXGEN_08 32 +#define CK_FLEXGEN_09 33 +#define CK_FLEXGEN_10 34 +#define CK_FLEXGEN_11 35 +#define CK_FLEXGEN_12 36 +#define CK_FLEXGEN_13 37 +#define CK_FLEXGEN_14 38 +#define CK_FLEXGEN_15 39 +#define CK_FLEXGEN_16 40 +#define CK_FLEXGEN_17 41 +#define CK_FLEXGEN_18 42 +#define CK_FLEXGEN_19 43 +#define CK_FLEXGEN_20 44 +#define CK_FLEXGEN_21 45 +#define CK_FLEXGEN_22 46 +#define CK_FLEXGEN_23 47 +#define CK_FLEXGEN_24 48 +#define CK_FLEXGEN_25 49 +#define CK_FLEXGEN_26 50 +#define CK_FLEXGEN_27 51 +#define CK_FLEXGEN_28 52 +#define CK_FLEXGEN_29 53 +#define CK_FLEXGEN_30 54 +#define CK_FLEXGEN_31 55 +#define CK_FLEXGEN_32 56 +#define CK_FLEXGEN_33 57 +#define CK_FLEXGEN_34 58 +#define CK_FLEXGEN_35 59 +#define CK_FLEXGEN_36 60 +#define CK_FLEXGEN_37 61 +#define CK_FLEXGEN_38 62 +#define CK_FLEXGEN_39 63 +#define CK_FLEXGEN_40 64 +#define CK_FLEXGEN_41 65 +#define CK_FLEXGEN_42 66 +#define CK_FLEXGEN_43 67 +#define CK_FLEXGEN_44 68 +#define CK_FLEXGEN_45 69 +#define CK_FLEXGEN_46 70 +#define CK_FLEXGEN_47 71 +#define CK_FLEXGEN_48 72 +#define CK_FLEXGEN_49 73 +#define CK_FLEXGEN_50 74 +#define CK_FLEXGEN_51 75 +#define CK_FLEXGEN_52 76 +#define CK_FLEXGEN_53 77 +#define CK_FLEXGEN_54 78 +#define CK_FLEXGEN_55 79 +#define CK_FLEXGEN_56 80 +#define CK_FLEXGEN_57 81 +#define CK_FLEXGEN_58 82 +#define CK_FLEXGEN_59 83 +#define CK_FLEXGEN_60 84 +#define CK_FLEXGEN_61 85 +#define CK_FLEXGEN_62 86 +#define CK_FLEXGEN_63 87 + +/* LOW SPEED MCU CLOCK */ +#define CK_ICN_LS_MCU 88 + +#define CK_BUS_STM500 89 +#define CK_BUS_FMC 90 +#define CK_BUS_GPU 91 +#define CK_BUS_ETH1 92 +#define CK_BUS_ETH2 93 +#define CK_BUS_PCIE 94 +#define CK_BUS_DDRPHYC 95 +#define CK_BUS_SYSCPU1 96 +#define CK_BUS_ETHSW 97 +#define CK_BUS_HPDMA1 98 +#define CK_BUS_HPDMA2 99 +#define CK_BUS_HPDMA3 100 +#define CK_BUS_ADC12 101 +#define CK_BUS_ADC3 102 +#define CK_BUS_IPCC1 103 +#define CK_BUS_CCI 104 +#define CK_BUS_CRC 105 +#define CK_BUS_MDF1 106 +#define CK_BUS_OSPIIOM 107 +#define CK_BUS_BKPSRAM 108 +#define CK_BUS_HASH 109 +#define CK_BUS_RNG 110 +#define CK_BUS_CRYP1 111 +#define CK_BUS_CRYP2 112 +#define CK_BUS_SAES 113 +#define CK_BUS_PKA 114 +#define CK_BUS_GPIOA 115 +#define CK_BUS_GPIOB 116 +#define CK_BUS_GPIOC 117 +#define CK_BUS_GPIOD 118 +#define CK_BUS_GPIOE 119 +#define CK_BUS_GPIOF 120 +#define CK_BUS_GPIOG 121 +#define CK_BUS_GPIOH 122 +#define CK_BUS_GPIOI 123 +#define CK_BUS_GPIOJ 124 +#define CK_BUS_GPIOK 125 +#define CK_BUS_LPSRAM1 126 +#define CK_BUS_LPSRAM2 127 +#define CK_BUS_LPSRAM3 128 +#define CK_BUS_GPIOZ 129 +#define CK_BUS_LPDMA 130 +#define CK_BUS_HSEM 131 +#define CK_BUS_IPCC2 132 +#define CK_BUS_RTC 133 +#define CK_BUS_SPI8 134 +#define CK_BUS_LPUART1 135 +#define CK_BUS_I2C8 136 +#define CK_BUS_LPTIM3 137 +#define CK_BUS_LPTIM4 138 +#define CK_BUS_LPTIM5 139 +#define CK_BUS_IWDG5 140 +#define CK_BUS_WWDG2 141 +#define CK_BUS_I3C4 142 +#define CK_BUS_TIM2 143 +#define CK_BUS_TIM3 144 +#define CK_BUS_TIM4 145 +#define CK_BUS_TIM5 146 +#define CK_BUS_TIM6 147 +#define CK_BUS_TIM7 148 +#define CK_BUS_TIM10 149 +#define CK_BUS_TIM11 150 +#define CK_BUS_TIM12 151 +#define CK_BUS_TIM13 152 +#define CK_BUS_TIM14 153 +#define CK_BUS_LPTIM1 154 +#define CK_BUS_LPTIM2 155 +#define CK_BUS_SPI2 156 +#define CK_BUS_SPI3 157 +#define CK_BUS_SPDIFRX 158 +#define CK_BUS_USART2 159 +#define CK_BUS_USART3 160 +#define CK_BUS_UART4 161 +#define CK_BUS_UART5 162 +#define CK_BUS_I2C1 163 +#define CK_BUS_I2C2 164 +#define CK_BUS_I2C3 165 +#define CK_BUS_I2C4 166 +#define CK_BUS_I2C5 167 +#define CK_BUS_I2C6 168 +#define CK_BUS_I2C7 169 +#define CK_BUS_I3C1 170 +#define CK_BUS_I3C2 171 +#define CK_BUS_I3C3 172 +#define CK_BUS_TIM1 173 +#define CK_BUS_TIM8 174 +#define CK_BUS_TIM15 175 +#define CK_BUS_TIM16 176 +#define CK_BUS_TIM17 177 +#define CK_BUS_TIM20 178 +#define CK_BUS_SAI1 179 +#define CK_BUS_SAI2 180 +#define CK_BUS_SAI3 181 +#define CK_BUS_SAI4 182 +#define CK_BUS_USART1 183 +#define CK_BUS_USART6 184 +#define CK_BUS_UART7 185 +#define CK_BUS_UART8 186 +#define CK_BUS_UART9 187 +#define CK_BUS_FDCAN 188 +#define CK_BUS_SPI1 189 +#define CK_BUS_SPI4 190 +#define CK_BUS_SPI5 191 +#define CK_BUS_SPI6 192 +#define CK_BUS_SPI7 193 +#define CK_BUS_BSEC 194 +#define CK_BUS_IWDG1 195 +#define CK_BUS_IWDG2 196 +#define CK_BUS_IWDG3 197 +#define CK_BUS_IWDG4 198 +#define CK_BUS_WWDG1 199 +#define CK_BUS_VREF 200 +#define CK_BUS_DTS 201 +#define CK_BUS_SERC 202 +#define CK_BUS_HDP 203 +#define CK_BUS_IS2M 204 +#define CK_BUS_DSI 205 +#define CK_BUS_LTDC 206 +#define CK_BUS_CSI 207 +#define CK_BUS_DCMIPP 208 +#define CK_BUS_DDRC 209 +#define CK_BUS_DDRCFG 210 +#define CK_BUS_GICV2M 211 +#define CK_BUS_USBTC 212 +#define CK_BUS_BUSPERFM 213 +#define CK_BUS_USB3PCIEPHY 214 +#define CK_BUS_STGEN 215 +#define CK_BUS_VDEC 216 +#define CK_BUS_VENC 217 +#define CK_SYSDBG 218 +#define CK_KER_TIM2 219 +#define CK_KER_TIM3 220 +#define CK_KER_TIM4 221 +#define CK_KER_TIM5 222 +#define CK_KER_TIM6 223 +#define CK_KER_TIM7 224 +#define CK_KER_TIM10 225 +#define CK_KER_TIM11 226 +#define CK_KER_TIM12 227 +#define CK_KER_TIM13 228 +#define CK_KER_TIM14 229 +#define CK_KER_TIM1 230 +#define CK_KER_TIM8 231 +#define CK_KER_TIM15 232 +#define CK_KER_TIM16 233 +#define CK_KER_TIM17 234 +#define CK_KER_TIM20 235 +#define CK_BUS_SYSRAM 236 +#define CK_BUS_VDERAM 237 +#define CK_BUS_RETRAM 238 +#define CK_BUS_OSPI1 239 +#define CK_BUS_OSPI2 240 +#define CK_BUS_OTFD1 241 +#define CK_BUS_OTFD2 242 +#define CK_BUS_SRAM1 243 +#define CK_BUS_SRAM2 244 +#define CK_BUS_SDMMC1 245 +#define CK_BUS_SDMMC2 246 +#define CK_BUS_SDMMC3 247 +#define CK_BUS_DDR 248 +#define CK_BUS_RISAF4 249 +#define CK_BUS_USB2OHCI 250 +#define CK_BUS_USB2EHCI 251 +#define CK_BUS_USB3DRD 252 +#define CK_KER_LPTIM1 253 +#define CK_KER_LPTIM2 254 +#define CK_KER_USART2 255 +#define CK_KER_UART4 256 +#define CK_KER_USART3 257 +#define CK_KER_UART5 258 +#define CK_KER_SPI2 259 +#define CK_KER_SPI3 260 +#define CK_KER_SPDIFRX 261 +#define CK_KER_I2C1 262 +#define CK_KER_I2C2 263 +#define CK_KER_I3C1 264 +#define CK_KER_I3C2 265 +#define CK_KER_I2C3 266 +#define CK_KER_I2C5 267 +#define CK_KER_I3C3 268 +#define CK_KER_I2C4 269 +#define CK_KER_I2C6 270 +#define CK_KER_I2C7 271 +#define CK_KER_SPI1 272 +#define CK_KER_SPI4 273 +#define CK_KER_SPI5 274 +#define CK_KER_SPI6 275 +#define CK_KER_SPI7 276 +#define CK_KER_USART1 277 +#define CK_KER_USART6 278 +#define CK_KER_UART7 279 +#define CK_KER_UART8 280 +#define CK_KER_UART9 281 +#define CK_KER_MDF1 282 +#define CK_KER_SAI1 283 +#define CK_KER_SAI2 284 +#define CK_KER_SAI3 285 +#define CK_KER_SAI4 286 +#define CK_KER_FDCAN 287 +#define CK_KER_DSIBLANE 288 +#define CK_KER_DSIPHY 289 +#define CK_KER_CSI 290 +#define CK_KER_CSITXESC 291 +#define CK_KER_CSIPHY 292 +#define CK_KER_LVDSPHY 293 +#define CK_KER_STGEN 294 +#define CK_KER_USB3PCIEPHY 295 +#define CK_KER_USB2PHY2EN 296 +#define CK_KER_I3C4 297 +#define CK_KER_SPI8 298 +#define CK_KER_I2C8 299 +#define CK_KER_LPUART1 300 +#define CK_KER_LPTIM3 301 +#define CK_KER_LPTIM4 302 +#define CK_KER_LPTIM5 303 +#define CK_KER_TSDBG 304 +#define CK_KER_TPIU 305 +#define CK_BUS_ETR 306 +#define CK_BUS_SYSATB 307 +#define CK_KER_ADC12 308 +#define CK_KER_ADC3 309 +#define CK_KER_OSPI1 310 +#define CK_KER_OSPI2 311 +#define CK_KER_FMC 312 +#define CK_KER_SDMMC1 313 +#define CK_KER_SDMMC2 314 +#define CK_KER_SDMMC3 315 +#define CK_KER_ETH1 316 +#define CK_KER_ETH2 317 +#define CK_KER_ETH1PTP 318 +#define CK_KER_ETH2PTP 319 +#define CK_KER_USB2PHY1 320 +#define CK_KER_USB2PHY2 321 +#define CK_KER_ETHSW 322 +#define CK_KER_ETHSWREF 323 +#define CK_MCO1 324 +#define CK_MCO2 325 +#define CK_KER_DTS 326 +#define CK_ETH1_RX 327 +#define CK_ETH1_TX 328 +#define CK_ETH1_MAC 329 +#define CK_ETH2_RX 330 +#define CK_ETH2_TX 331 +#define CK_ETH2_MAC 332 +#define CK_ETH1_STP 333 +#define CK_ETH2_STP 334 +#define CK_KER_USBTC 335 +#define CK_BUS_ADF1 336 +#define CK_KER_ADF1 337 +#define CK_BUS_LVDS 338 +#define CK_KER_LTDC 339 +#define CK_KER_GPU 340 +#define CK_BUS_ETHSWACMCFG 341 +#define CK_BUS_ETHSWACMMSG 342 +#define HSE_DIV2_CK 343 + +#define STM32MP25_LAST_CLK 344 + +#define CK_SCMI_ICN_HS_MCU 0 +#define CK_SCMI_ICN_SDMMC 1 +#define CK_SCMI_ICN_DDR 2 +#define CK_SCMI_ICN_DISPLAY 3 +#define CK_SCMI_ICN_HSL 4 +#define CK_SCMI_ICN_NIC 5 +#define CK_SCMI_ICN_VID 6 +#define CK_SCMI_FLEXGEN_07 7 +#define CK_SCMI_FLEXGEN_08 8 +#define CK_SCMI_FLEXGEN_09 9 +#define CK_SCMI_FLEXGEN_10 10 +#define CK_SCMI_FLEXGEN_11 11 +#define CK_SCMI_FLEXGEN_12 12 +#define CK_SCMI_FLEXGEN_13 13 +#define CK_SCMI_FLEXGEN_14 14 +#define CK_SCMI_FLEXGEN_15 15 +#define CK_SCMI_FLEXGEN_16 16 +#define CK_SCMI_FLEXGEN_17 17 +#define CK_SCMI_FLEXGEN_18 18 +#define CK_SCMI_FLEXGEN_19 19 +#define CK_SCMI_FLEXGEN_20 20 +#define CK_SCMI_FLEXGEN_21 21 +#define CK_SCMI_FLEXGEN_22 22 +#define CK_SCMI_FLEXGEN_23 23 +#define CK_SCMI_FLEXGEN_24 24 +#define CK_SCMI_FLEXGEN_25 25 +#define CK_SCMI_FLEXGEN_26 26 +#define CK_SCMI_FLEXGEN_27 27 +#define CK_SCMI_FLEXGEN_28 28 +#define CK_SCMI_FLEXGEN_29 29 +#define CK_SCMI_FLEXGEN_30 30 +#define CK_SCMI_FLEXGEN_31 31 +#define CK_SCMI_FLEXGEN_32 32 +#define CK_SCMI_FLEXGEN_33 33 +#define CK_SCMI_FLEXGEN_34 34 +#define CK_SCMI_FLEXGEN_35 35 +#define CK_SCMI_FLEXGEN_36 36 +#define CK_SCMI_FLEXGEN_37 37 +#define CK_SCMI_FLEXGEN_38 38 +#define CK_SCMI_FLEXGEN_39 39 +#define CK_SCMI_FLEXGEN_40 40 +#define CK_SCMI_FLEXGEN_41 41 +#define CK_SCMI_FLEXGEN_42 42 +#define CK_SCMI_FLEXGEN_43 43 +#define CK_SCMI_FLEXGEN_44 44 +#define CK_SCMI_FLEXGEN_45 45 +#define CK_SCMI_FLEXGEN_46 46 +#define CK_SCMI_FLEXGEN_47 47 +#define CK_SCMI_FLEXGEN_48 48 +#define CK_SCMI_FLEXGEN_49 49 +#define CK_SCMI_FLEXGEN_50 50 +#define CK_SCMI_FLEXGEN_51 51 +#define CK_SCMI_FLEXGEN_52 52 +#define CK_SCMI_FLEXGEN_53 53 +#define CK_SCMI_FLEXGEN_54 54 +#define CK_SCMI_FLEXGEN_55 55 +#define CK_SCMI_FLEXGEN_56 56 +#define CK_SCMI_FLEXGEN_57 57 +#define CK_SCMI_FLEXGEN_58 58 +#define CK_SCMI_FLEXGEN_59 59 +#define CK_SCMI_FLEXGEN_60 60 +#define CK_SCMI_FLEXGEN_61 61 +#define CK_SCMI_FLEXGEN_62 62 +#define CK_SCMI_FLEXGEN_63 63 +#define CK_SCMI_ICN_LS_MCU 64 +#define CK_SCMI_HSE 65 +#define CK_SCMI_LSE 66 +#define CK_SCMI_HSI 67 +#define CK_SCMI_LSI 68 +#define CK_SCMI_MSI 69 +#define CK_SCMI_HSE_DIV2 70 +#define CK_SCMI_CPU1 71 +#define CK_SCMI_SYSCPU1 72 +#define CK_SCMI_PLL2 73 +#define CK_SCMI_PLL3 74 +#define CK_SCMI_RTC 75 +#define CK_SCMI_RTCCK 76 +#define CK_SCMI_ICN_APB1 77 +#define CK_SCMI_ICN_APB2 78 +#define CK_SCMI_ICN_APB3 79 +#define CK_SCMI_ICN_APB4 80 +#define CK_SCMI_ICN_APBDBG 81 +#define CK_SCMI_TIMG1 82 +#define CK_SCMI_TIMG2 83 +#define CK_SCMI_BKPSRAM 84 +#define CK_SCMI_BSEC 85 +#define CK_SCMI_BUSPERFM 86 +#define CK_SCMI_ETR 87 +#define CK_SCMI_FMC 88 +#define CK_SCMI_GPIOA 89 +#define CK_SCMI_GPIOB 90 +#define CK_SCMI_GPIOC 91 +#define CK_SCMI_GPIOD 92 +#define CK_SCMI_GPIOE 93 +#define CK_SCMI_GPIOF 94 +#define CK_SCMI_GPIOG 95 +#define CK_SCMI_GPIOH 96 +#define CK_SCMI_GPIOI 97 +#define CK_SCMI_GPIOJ 98 +#define CK_SCMI_GPIOK 99 +#define CK_SCMI_GPIOZ 100 +#define CK_SCMI_HPDMA1 101 +#define CK_SCMI_HPDMA2 102 +#define CK_SCMI_HPDMA3 103 +#define CK_SCMI_HSEM 104 +#define CK_SCMI_IPCC1 105 +#define CK_SCMI_IPCC2 106 +#define CK_SCMI_LPDMA 107 +#define CK_SCMI_RETRAM 108 +#define CK_SCMI_SRAM1 109 +#define CK_SCMI_SRAM2 110 +#define CK_SCMI_LPSRAM1 111 +#define CK_SCMI_LPSRAM2 112 +#define CK_SCMI_LPSRAM3 113 +#define CK_SCMI_VDERAM 114 +#define CK_SCMI_SYSRAM 115 +#define CK_SCMI_OSPI1 116 +#define CK_SCMI_OSPI2 117 +#define CK_SCMI_TPIU 118 +#define CK_SCMI_SYSDBG 119 +#define CK_SCMI_SYSATB 120 +#define CK_SCMI_TSDBG 121 +#define CK_SCMI_STM500 122 + +#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp25-clksrc.h b/include/dt-bindings/clock/stm32mp25-clksrc.h new file mode 100644 index 0000000000..e6f7154b77 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp25-clksrc.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ + +#define CMD_DIV 0 +#define CMD_MUX 1 +#define CMD_CLK 2 +#define CMD_FLEXGEN 3 + +#define CMD_ADDR_BIT 0x80000000 + +#define CMD_SHIFT 26 +#define CMD_MASK 0xFC000000 +#define CMD_DATA_MASK 0x03FFFFFF + +#define DIV_ID_SHIFT 8 +#define DIV_ID_MASK 0x0000FF00 + +#define DIV_DIVN_SHIFT 0 +#define DIV_DIVN_MASK 0x000000FF + +#define MUX_ID_SHIFT 4 +#define MUX_ID_MASK 0x00000FF0 + +#define MUX_SEL_SHIFT 0 +#define MUX_SEL_MASK 0x0000000F + +/* CLK define */ +#define CLK_ON_MASK BIT(21) +#define CLK_ON_SHIFT 21 + +#define CLK_ID_MASK GENMASK_32(20, 12) +#define CLK_ID_SHIFT 12 + +#define CLK_NO_DIV_MASK 0x0000080 +#define CLK_DIV_MASK GENMASK_32(10, 5) +#define CLK_DIV_SHIFT 5 + +#define CLK_NO_SEL_MASK 0x00000010 +#define CLK_SEL_MASK GENMASK_32(3, 0) +#define CLK_SEL_SHIFT 0 + +#define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ + ((state) << CLK_ON_SHIFT) |\ + ((clk_id) << CLK_ID_SHIFT) |\ + ((div) << CLK_DIV_SHIFT) |\ + ((sel) << CLK_SEL_SHIFT)) + +#define CLK_OFF 0 +#define CLK_ON 1 +#define CLK_NODIV 0x00000040 +#define CLK_NOMUX 0x00000010 + +/* Flexgen define */ +#define FLEX_ID_SHIFT 13 +#define FLEX_SEL_SHIFT 9 +#define FLEX_PDIV_SHIFT 6 +#define FLEX_FDIV_SHIFT 0 + +#define FLEX_ID_MASK GENMASK_32(18, 13) +#define FLEX_SEL_MASK GENMASK_32(12, 9) +#define FLEX_PDIV_MASK GENMASK_32(8, 6) +#define FLEX_FDIV_MASK GENMASK_32(5, 0) + +#define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ + ((div_id) << DIV_ID_SHIFT |\ + (div))) + +#define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ + ((mux_id) << MUX_ID_SHIFT |\ + (sel))) + +#define CLK_ADDR_SHIFT 16 +#define CLK_ADDR_MASK 0x7FFF0000 +#define CLK_ADDR_VAL_MASK 0xFFFF + +#define DIV_LSMCU 0 +#define DIV_APB1 1 +#define DIV_APB2 2 +#define DIV_APB3 3 +#define DIV_APB4 4 +#define DIV_APBDBG 5 +#define DIV_RTC 6 +#define DIV_NB 7 + +#define MUX_MUXSEL0 0 +#define MUX_MUXSEL1 1 +#define MUX_MUXSEL2 2 +#define MUX_MUXSEL3 3 +#define MUX_MUXSEL4 4 +#define MUX_MUXSEL5 5 +#define MUX_MUXSEL6 6 +#define MUX_MUXSEL7 7 +#define MUX_XBARSEL 8 +#define MUX_RTC 9 +#define MUX_MCO1 10 +#define MUX_MCO2 11 +#define MUX_ADC12 12 +#define MUX_ADC3 13 +#define MUX_USB2PHY1 14 +#define MUX_USB2PHY2 15 +#define MUX_USB3PCIEPHY 16 +#define MUX_DSIBLANE 17 +#define MUX_DSIPHY 18 +#define MUX_LVDSPHY 19 +#define MUX_DTS 20 +#define MUX_CPU1 21 +#define MUX_D3PER 22 +#define MUX_NB 23 + +#define MUXSEL_HSI 0 +#define MUXSEL_HSE 1 +#define MUXSEL_MSI 2 + +/* KERNEL source clocks */ +#define MUX_RTC_DISABLED 0x0 +#define MUX_RTC_LSE 0x1 +#define MUX_RTC_LSI 0x2 +#define MUX_RTC_HSE 0x3 + +#define MUX_MCO1_FLEX61 0x0 +#define MUX_MCO1_OBSER0 0x1 + +#define MUX_MCO2_FLEX62 0x0 +#define MUX_MCO2_OBSER1 0x1 + +#define MUX_ADC12_FLEX46 0x0 +#define MUX_ADC12_LSMCU 0x1 + +#define MUX_ADC3_FLEX47 0x0 +#define MUX_ADC3_LSMCU 0x1 +#define MUX_ADC3_FLEX46 0x2 + +#define MUX_USB2PHY1_FLEX57 0x0 +#define MUX_USB2PHY1_HSE 0x1 + +#define MUX_USB2PHY2_FLEX58 0x0 +#define MUX_USB2PHY2_HSE 0x1 + +#define MUX_USB3PCIEPHY_FLEX34 0x0 +#define MUX_USB3PCIEPHY_HSE 0x1 + +#define MUX_DSIBLANE_FLEX28 0x0 +#define MUX_DSIBLANE_FLEX27 0x1 + +#define MUX_DSIPHY_FLEX28 0x0 +#define MUX_DSIPHY_HSE 0x1 + +#define MUX_LVDSPHY_FLEX32 0x0 +#define MUX_LVDSPHY_HSE 0x1 + +#define MUX_DTS_HSI 0x0 +#define MUX_DTS_HSE 0x1 +#define MUX_DTS_MSI 0x2 + +#define MUX_D3PER_MSI 0x0 +#define MUX_D3PER_LSI 0x1 +#define MUX_D3PER_LSE 0x2 + +/* PLLs source clocks */ +#define PLL_SRC_HSI 0x0 +#define PLL_SRC_HSE 0x1 +#define PLL_SRC_MSI 0x2 +#define PLL_SRC_DISABLED 0x3 + +/* XBAR source clocks */ +#define XBAR_SRC_PLL4 0x0 +#define XBAR_SRC_PLL5 0x1 +#define XBAR_SRC_PLL6 0x2 +#define XBAR_SRC_PLL7 0x3 +#define XBAR_SRC_PLL8 0x4 +#define XBAR_SRC_HSI 0x5 +#define XBAR_SRC_HSE 0x6 +#define XBAR_SRC_MSI 0x7 +#define XBAR_SRC_HSI_KER 0x8 +#define XBAR_SRC_HSE_KER 0x9 +#define XBAR_SRC_MSI_KER 0xA +#define XBAR_SRC_SPDIF_SYMB 0xB +#define XBAR_SRC_I2S 0xC +#define XBAR_SRC_LSI 0xD +#define XBAR_SRC_LSE 0xE + +/* + * Configure a XBAR channel with its clock source + * channel_nb: XBAR channel number from 0 to 63 + * channel_src: one of the 15 previous XBAR source clocks defines + * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register + * can be either 1, 2, 4 or 1024 + * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register + * from 1 to 64 + */ + +#define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ + ((ch) << FLEX_ID_SHIFT) |\ + ((sel) << FLEX_SEL_SHIFT) |\ + ((pdiv) << FLEX_PDIV_SHIFT) |\ + ((fdiv) << FLEX_FDIV_SHIFT)) + +/* Register addresses of MCO1 & MCO2 */ +#define MCO1 0x494 +#define MCO2 0x498 + +#define MCO_OFF 0 +#define MCO_ON 1 +#define MCO_STATUS_SHIFT 8 + +#define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ + ((addr) << CLK_ADDR_SHIFT) |\ + ((status) << MCO_STATUS_SHIFT) |\ + (sel)) + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */ diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h index fbe07da986..803cd9cd34 100644 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: MIT * @@ -9,21 +9,18 @@ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H +#include <dt-bindings/interrupt-controller/irq.h> + /* interrupt specifier cell 0 */ #define GIC_SPI 0 #define GIC_PPI 1 -#define IRQ_TYPE_NONE 0 -#define IRQ_TYPE_EDGE_RISING 1 -#define IRQ_TYPE_EDGE_FALLING 2 -#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 4 -#define IRQ_TYPE_LEVEL_LOW 8 - /* * Interrupt specifier cell 2. + * The flags in irq.h are valid, plus those below. */ #define GIC_CPU_MASK_RAW(x) ((x) << 8) +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) #endif diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h new file mode 100644 index 0000000000..94e7f95e55 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irq.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * This header provides constants for most IRQ bindings. + * + * Most IRQ bindings include a flags cell as part of the IRQ specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#endif diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index bc71924faa..d40b1a24ab 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -1,121 +1,11 @@ -/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. + * Copyright (C) 2020-2022, STMicroelectronics - All Rights Reserved */ -#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ -#define _DT_BINDINGS_STM32MP1_RESET_H_ - -#define LTDC_R 3072 -#define DSI_R 3076 -#define DDRPERFM_R 3080 -#define USBPHY_R 3088 -#define SPI6_R 3136 -#define I2C4_R 3138 -#define I2C6_R 3139 -#define USART1_R 3140 -#define STGEN_R 3156 -#define GPIOZ_R 3200 -#define CRYP1_R 3204 -#define HASH1_R 3205 -#define RNG1_R 3206 -#define AXIM_R 3216 -#define GPU_R 3269 -#define ETHMAC_R 3274 -#define FMC_R 3276 -#define QSPI_R 3278 -#define SDMMC1_R 3280 -#define SDMMC2_R 3281 -#define CRC1_R 3284 -#define USBH_R 3288 -#define MDMA_R 3328 -#define MCU_R 8225 -#define TIM2_R 19456 -#define TIM3_R 19457 -#define TIM4_R 19458 -#define TIM5_R 19459 -#define TIM6_R 19460 -#define TIM7_R 19461 -#define TIM12_R 16462 -#define TIM13_R 16463 -#define TIM14_R 16464 -#define LPTIM1_R 19465 -#define SPI2_R 19467 -#define SPI3_R 19468 -#define USART2_R 19470 -#define USART3_R 19471 -#define UART4_R 19472 -#define UART5_R 19473 -#define UART7_R 19474 -#define UART8_R 19475 -#define I2C1_R 19477 -#define I2C2_R 19478 -#define I2C3_R 19479 -#define I2C5_R 19480 -#define SPDIF_R 19482 -#define CEC_R 19483 -#define DAC12_R 19485 -#define MDIO_R 19847 -#define TIM1_R 19520 -#define TIM8_R 19521 -#define TIM15_R 19522 -#define TIM16_R 19523 -#define TIM17_R 19524 -#define SPI1_R 19528 -#define SPI4_R 19529 -#define SPI5_R 19530 -#define USART6_R 19533 -#define SAI1_R 19536 -#define SAI2_R 19537 -#define SAI3_R 19538 -#define DFSDM_R 19540 -#define FDCAN_R 19544 -#define LPTIM2_R 19584 -#define LPTIM3_R 19585 -#define LPTIM4_R 19586 -#define LPTIM5_R 19587 -#define SAI4_R 19592 -#define SYSCFG_R 19595 -#define VREF_R 19597 -#define TMPSENS_R 19600 -#define PMBCTRL_R 19601 -#define DMA1_R 19648 -#define DMA2_R 19649 -#define DMAMUX_R 19650 -#define ADC12_R 19653 -#define USBO_R 19656 -#define SDMMC3_R 19664 -#define CAMITF_R 19712 -#define CRYP2_R 19716 -#define HASH2_R 19717 -#define RNG2_R 19718 -#define CRC2_R 19719 -#define HSEM_R 19723 -#define MBOX_R 19724 -#define GPIOA_R 19776 -#define GPIOB_R 19777 -#define GPIOC_R 19778 -#define GPIOD_R 19779 -#define GPIOE_R 19780 -#define GPIOF_R 19781 -#define GPIOG_R 19782 -#define GPIOH_R 19783 -#define GPIOI_R 19784 -#define GPIOJ_R 19785 -#define GPIOK_R 19786 - -/* SCMI reset domain identifiers */ -#define RST_SCMI0_SPI6 0 -#define RST_SCMI0_I2C4 1 -#define RST_SCMI0_I2C6 2 -#define RST_SCMI0_USART1 3 -#define RST_SCMI0_STGEN 4 -#define RST_SCMI0_GPIOZ 5 -#define RST_SCMI0_CRYP1 6 -#define RST_SCMI0_HASH1 7 -#define RST_SCMI0_RNG1 8 -#define RST_SCMI0_MDMA 9 -#define RST_SCMI0_MCU 10 - -#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ +#if STM32MP13 +#include "stm32mp13-resets.h" +#endif +#if STM32MP15 +#include "stm32mp15-resets.h" +#endif diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h new file mode 100644 index 0000000000..8a0f80e3c1 --- /dev/null +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ +#define _DT_BINDINGS_STM32MP13_RESET_H_ + +#define TIM2_R 13568 +#define TIM3_R 13569 +#define TIM4_R 13570 +#define TIM5_R 13571 +#define TIM6_R 13572 +#define TIM7_R 13573 +#define LPTIM1_R 13577 +#define SPI2_R 13579 +#define SPI3_R 13580 +#define USART3_R 13583 +#define UART4_R 13584 +#define UART5_R 13585 +#define UART7_R 13586 +#define UART8_R 13587 +#define I2C1_R 13589 +#define I2C2_R 13590 +#define SPDIF_R 13594 +#define TIM1_R 13632 +#define TIM8_R 13633 +#define SPI1_R 13640 +#define USART6_R 13645 +#define SAI1_R 13648 +#define SAI2_R 13649 +#define DFSDM_R 13652 +#define FDCAN_R 13656 +#define LPTIM2_R 13696 +#define LPTIM3_R 13697 +#define LPTIM4_R 13698 +#define LPTIM5_R 13699 +#define SYSCFG_R 13707 +#define VREF_R 13709 +#define DTS_R 13712 +#define PMBCTRL_R 13713 +#define LTDC_R 13760 +#define DCMIPP_R 13761 +#define DDRPERFM_R 13768 +#define USBPHY_R 13776 +#define STGEN_R 13844 +#define USART1_R 13888 +#define USART2_R 13889 +#define SPI4_R 13890 +#define SPI5_R 13891 +#define I2C3_R 13892 +#define I2C4_R 13893 +#define I2C5_R 13894 +#define TIM12_R 13895 +#define TIM13_R 13896 +#define TIM14_R 13897 +#define TIM15_R 13898 +#define TIM16_R 13899 +#define TIM17_R 13900 +#define DMA1_R 13952 +#define DMA2_R 13953 +#define DMAMUX1_R 13954 +#define DMA3_R 13955 +#define DMAMUX2_R 13956 +#define ADC1_R 13957 +#define ADC2_R 13958 +#define USBO_R 13960 +#define GPIOA_R 14080 +#define GPIOB_R 14081 +#define GPIOC_R 14082 +#define GPIOD_R 14083 +#define GPIOE_R 14084 +#define GPIOF_R 14085 +#define GPIOG_R 14086 +#define GPIOH_R 14087 +#define GPIOI_R 14088 +#define TSC_R 14095 +#define PKA_R 14146 +#define SAES_R 14147 +#define CRYP1_R 14148 +#define HASH1_R 14149 +#define RNG1_R 14150 +#define AXIMC_R 14160 +#define MDMA_R 14208 +#define MCE_R 14209 +#define ETH1MAC_R 14218 +#define FMC_R 14220 +#define QSPI_R 14222 +#define SDMMC1_R 14224 +#define SDMMC2_R 14225 +#define CRC1_R 14228 +#define USBH_R 14232 +#define ETH2MAC_R 14238 + +#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ diff --git a/include/dt-bindings/reset/stm32mp15-resets.h b/include/dt-bindings/reset/stm32mp15-resets.h new file mode 100644 index 0000000000..2b34864869 --- /dev/null +++ b/include/dt-bindings/reset/stm32mp15-resets.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP15_RESET_H_ +#define _DT_BINDINGS_STM32MP15_RESET_H_ + +#define MCU_HOLD_BOOT_R 2144 +#define LTDC_R 3072 +#define DSI_R 3076 +#define DDRPERFM_R 3080 +#define USBPHY_R 3088 +#define SPI6_R 3136 +#define I2C4_R 3138 +#define I2C6_R 3139 +#define USART1_R 3140 +#define STGEN_R 3156 +#define GPIOZ_R 3200 +#define CRYP1_R 3204 +#define HASH1_R 3205 +#define RNG1_R 3206 +#define AXIM_R 3216 +#define GPU_R 3269 +#define ETHMAC_R 3274 +#define FMC_R 3276 +#define QSPI_R 3278 +#define SDMMC1_R 3280 +#define SDMMC2_R 3281 +#define CRC1_R 3284 +#define USBH_R 3288 +#define MDMA_R 3328 +#define MCU_R 8225 +#define TIM2_R 19456 +#define TIM3_R 19457 +#define TIM4_R 19458 +#define TIM5_R 19459 +#define TIM6_R 19460 +#define TIM7_R 19461 +#define TIM12_R 16462 +#define TIM13_R 16463 +#define TIM14_R 16464 +#define LPTIM1_R 19465 +#define SPI2_R 19467 +#define SPI3_R 19468 +#define USART2_R 19470 +#define USART3_R 19471 +#define UART4_R 19472 +#define UART5_R 19473 +#define UART7_R 19474 +#define UART8_R 19475 +#define I2C1_R 19477 +#define I2C2_R 19478 +#define I2C3_R 19479 +#define I2C5_R 19480 +#define SPDIF_R 19482 +#define CEC_R 19483 +#define DAC12_R 19485 +#define MDIO_R 19847 +#define TIM1_R 19520 +#define TIM8_R 19521 +#define TIM15_R 19522 +#define TIM16_R 19523 +#define TIM17_R 19524 +#define SPI1_R 19528 +#define SPI4_R 19529 +#define SPI5_R 19530 +#define USART6_R 19533 +#define SAI1_R 19536 +#define SAI2_R 19537 +#define SAI3_R 19538 +#define DFSDM_R 19540 +#define FDCAN_R 19544 +#define LPTIM2_R 19584 +#define LPTIM3_R 19585 +#define LPTIM4_R 19586 +#define LPTIM5_R 19587 +#define SAI4_R 19592 +#define SYSCFG_R 19595 +#define VREF_R 19597 +#define TMPSENS_R 19600 +#define PMBCTRL_R 19601 +#define DMA1_R 19648 +#define DMA2_R 19649 +#define DMAMUX_R 19650 +#define ADC12_R 19653 +#define USBO_R 19656 +#define SDMMC3_R 19664 +#define CAMITF_R 19712 +#define CRYP2_R 19716 +#define HASH2_R 19717 +#define RNG2_R 19718 +#define CRC2_R 19719 +#define HSEM_R 19723 +#define MBOX_R 19724 +#define GPIOA_R 19776 +#define GPIOB_R 19777 +#define GPIOC_R 19778 +#define GPIOD_R 19779 +#define GPIOE_R 19780 +#define GPIOF_R 19781 +#define GPIOG_R 19782 +#define GPIOH_R 19783 +#define GPIOI_R 19784 +#define GPIOJ_R 19785 +#define GPIOK_R 19786 + +/* SCMI reset domain identifiers */ +#define RST_SCMI0_SPI6 0 +#define RST_SCMI0_I2C4 1 +#define RST_SCMI0_I2C6 2 +#define RST_SCMI0_USART1 3 +#define RST_SCMI0_STGEN 4 +#define RST_SCMI0_GPIOZ 5 +#define RST_SCMI0_CRYP1 6 +#define RST_SCMI0_HASH1 7 +#define RST_SCMI0_RNG1 8 +#define RST_SCMI0_MDMA 9 +#define RST_SCMI0_MCU 10 +#define RST_SCMI0_MCU_HOLD_BOOT 11 + +#endif /* _DT_BINDINGS_STM32MP15_RESET_H_ */ diff --git a/include/dt-bindings/reset/stm32mp25-resets.h b/include/dt-bindings/reset/stm32mp25-resets.h new file mode 100644 index 0000000000..c34fe2aec1 --- /dev/null +++ b/include/dt-bindings/reset/stm32mp25-resets.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP25_RESET_H_ +#define _DT_BINDINGS_STM32MP25_RESET_H_ + +#define SYS_R 8192 +#define C1_R 8224 +#define C1P1POR_R 8256 +#define C1P1_R 8257 +#define C2_R 8288 +#define C2_HOLDBOOT_R 8608 +#define C1_HOLDBOOT_R 8609 +#define VSW_R 8703 +#define C1MS_R 8808 +#define IWDG2_KER_R 9074 +#define IWDG4_KER_R 9202 +#define C3_R 9312 +#define DDRCP_R 9856 +#define DDRCAPB_R 9888 +#define DDRPHYCAPB_R 9920 +#define DDRCFG_R 9984 +#define DDR_R 10016 +#define OSPI1_R 10400 +#define OSPI1DLL_R 10416 +#define OSPI2_R 10432 +#define OSPI2DLL_R 10448 +#define FMC_R 10464 +#define DBG_R 10508 +#define GPIOA_R 10592 +#define GPIOB_R 10624 +#define GPIOC_R 10656 +#define GPIOD_R 10688 +#define GPIOE_R 10720 +#define GPIOF_R 10752 +#define GPIOG_R 10784 +#define GPIOH_R 10816 +#define GPIOI_R 10848 +#define GPIOJ_R 10880 +#define GPIOK_R 10912 +#define GPIOZ_R 10944 +#define HPDMA1_R 10976 +#define HPDMA2_R 11008 +#define HPDMA3_R 11040 +#define LPDMA_R 11072 +#define HSEM_R 11104 +#define IPCC1_R 11136 +#define IPCC2_R 11168 +#define IS2M_R 11360 +#define SSMOD_R 11392 +#define TIM1_R 14336 +#define TIM2_R 14368 +#define TIM3_R 14400 +#define TIM4_R 14432 +#define TIM5_R 14464 +#define TIM6_R 14496 +#define TIM7_R 14528 +#define TIM8_R 14560 +#define TIM10_R 14592 +#define TIM11_R 14624 +#define TIM12_R 14656 +#define TIM13_R 14688 +#define TIM14_R 14720 +#define TIM15_R 14752 +#define TIM16_R 14784 +#define TIM17_R 14816 +#define TIM20_R 14848 +#define LPTIM1_R 14880 +#define LPTIM2_R 14912 +#define LPTIM3_R 14944 +#define LPTIM4_R 14976 +#define LPTIM5_R 15008 +#define SPI1_R 15040 +#define SPI2_R 15072 +#define SPI3_R 15104 +#define SPI4_R 15136 +#define SPI5_R 15168 +#define SPI6_R 15200 +#define SPI7_R 15232 +#define SPI8_R 15264 +#define SPDIFRX_R 15296 +#define USART1_R 15328 +#define USART2_R 15360 +#define USART3_R 15392 +#define UART4_R 15424 +#define UART5_R 15456 +#define USART6_R 15488 +#define UART7_R 15520 +#define UART8_R 15552 +#define UART9_R 15584 +#define LPUART1_R 15616 +#define I2C1_R 15648 +#define I2C2_R 15680 +#define I2C3_R 15712 +#define I2C4_R 15744 +#define I2C5_R 15776 +#define I2C6_R 15808 +#define I2C7_R 15840 +#define I2C8_R 15872 +#define SAI1_R 15904 +#define SAI2_R 15936 +#define SAI3_R 15968 +#define SAI4_R 16000 +#define MDF1_R 16064 +#define MDF2_R 16096 +#define FDCAN_R 16128 +#define HDP_R 16160 +#define ADC12_R 16192 +#define ADC3_R 16224 +#define ETH1_R 16256 +#define ETH2_R 16288 +#define USB2_R 16352 +#define USB2PHY1_R 16384 +#define USB2PHY2_R 16416 +#define USB3DRD_R 16448 +#define USB3PCIEPHY_R 16480 +#define PCIE_R 16512 +#define USBTC_R 16544 +#define ETHSW_R 16576 +#define SDMMC1_R 16768 +#define SDMMC1DLL_R 16784 +#define SDMMC2_R 16800 +#define SDMMC2DLL_R 16816 +#define SDMMC3_R 16832 +#define SDMMC3DLL_R 16848 +#define GPU_R 16864 +#define LTDC_R 16896 +#define DSI_R 16928 +#define LVDS_R 17024 +#define CSI_R 17088 +#define DCMIPP_R 17120 +#define CCI_R 17152 +#define VDEC_R 17184 +#define VENC_R 17216 +#define RNG_R 17280 +#define PKA_R 17312 +#define SAES_R 17344 +#define HASH_R 17376 +#define CRYP1_R 17408 +#define CRYP2_R 17440 +#define WWDG1_R 17632 +#define WWDG2_R 17664 +#define BUSPERFM_R 17696 +#define VREF_R 17728 +#define DTS_R 17760 +#define CRC_R 17824 +#define SERC_R 17856 +#define OSPIIOM_R 17888 +#define I3C1_R 17984 +#define I3C2_R 18016 +#define I3C3_R 18048 +#define I3C4_R 18080 + +#define RST_SCMI_C1_R 0 +#define RST_SCMI_C2_R 1 +#define RST_SCMI_C1_HOLDBOOT_R 2 +#define RST_SCMI_C2_HOLDBOOT_R 3 +#define RST_SCMI_FMC 4 +#define RST_SCMI_PCIE 5 + +#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */ diff --git a/include/dt-bindings/soc/stm32mp13-tzc400.h b/include/dt-bindings/soc/stm32mp13-tzc400.h new file mode 100644 index 0000000000..1cb2326ed9 --- /dev/null +++ b/include/dt-bindings/soc/stm32mp13-tzc400.h @@ -0,0 +1,35 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + * + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#ifndef _DT_BINDINGS_STM32MP13_TZC400_H +#define _DT_BINDINGS_STM32MP13_TZC400_H + +#include <drivers/arm/tzc_common.h> + +#define STM32MP1_TZC_A7_ID U(0) +#define STM32MP1_TZC_LCD_ID U(3) +#define STM32MP1_TZC_MDMA_ID U(5) +#define STM32MP1_TZC_DMA_ID U(6) +#define STM32MP1_TZC_USB_HOST_ID U(7) +#define STM32MP1_TZC_USB_OTG_ID U(8) +#define STM32MP1_TZC_SDMMC_ID U(9) +#define STM32MP1_TZC_ETH_ID U(10) +#define STM32MP1_TZC_DCMIPP_ID U(11) +#define STM32MP1_TZC_DAP_ID U(15) + +#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \ + (TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DCMIPP_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)) + +#endif /* _DT_BINDINGS_STM32MP13_TZC400_H */ diff --git a/include/dt-bindings/soc/stm32mp15-tzc400.h b/include/dt-bindings/soc/stm32mp15-tzc400.h new file mode 100644 index 0000000000..54cd90224a --- /dev/null +++ b/include/dt-bindings/soc/stm32mp15-tzc400.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + */ + +#ifndef _DT_BINDINGS_STM32MP15_TZC400_H +#define _DT_BINDINGS_STM32MP15_TZC400_H + +#include <drivers/arm/tzc_common.h> + +#define STM32MP1_TZC_A7_ID U(0) +#define STM32MP1_TZC_M4_ID U(1) +#define STM32MP1_TZC_LCD_ID U(3) +#define STM32MP1_TZC_GPU_ID U(4) +#define STM32MP1_TZC_MDMA_ID U(5) +#define STM32MP1_TZC_DMA_ID U(6) +#define STM32MP1_TZC_USB_HOST_ID U(7) +#define STM32MP1_TZC_USB_OTG_ID U(8) +#define STM32MP1_TZC_SDMMC_ID U(9) +#define STM32MP1_TZC_ETH_ID U(10) +#define STM32MP1_TZC_DAP_ID U(15) + +#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \ + (TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \ + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)) + +#endif /* _DT_BINDINGS_STM32MP15_TZC400_H */ diff --git a/include/export/common/bl_common_exp.h b/include/export/common/bl_common_exp.h index 8f0901765d..2cc7c54b2f 100644 --- a/include/export/common/bl_common_exp.h +++ b/include/export/common/bl_common_exp.h @@ -39,8 +39,8 @@ *****************************************************************************/ typedef struct image_info { param_header_t h; - uintptr_t image_base; /* physical address of base of image */ - uint32_t image_size; /* bytes read from image file */ + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ uint32_t image_max_size; } image_info_t; diff --git a/include/export/common/ep_info_exp.h b/include/export/common/ep_info_exp.h index 9d2969f3fb..a5bd10ac8a 100644 --- a/include/export/common/ep_info_exp.h +++ b/include/export/common/ep_info_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,11 +24,23 @@ #define ENTRY_POINT_INFO_ARGS_OFFSET U(0x14) #endif -/* Security state of the image. */ -#define EP_SECURITY_MASK UL(0x1) +/* + * Security state of the image. Bit 0 and + * bit 5 are used to determine the security + * state of the image as follows: + * + * --------------------------------- + * Bit 5 | Bit 0 | Security state + * --------------------------------- + * 0 0 EP_SECURE + * 0 1 EP_NON_SECURE + * 1 1 EP_REALM + */ +#define EP_SECURITY_MASK UL(0x21) #define EP_SECURITY_SHIFT UL(0) #define EP_SECURE UL(0x0) #define EP_NON_SECURE UL(0x1) +#define EP_REALM UL(0x21) /* Endianness of the image. */ #define EP_EE_MASK U(0x2) diff --git a/include/export/common/tbbr/tbbr_img_def_exp.h b/include/export/common/tbbr/tbbr_img_def_exp.h index 18f0125137..ce17b4afb6 100644 --- a/include/export/common/tbbr/tbbr_img_def_exp.h +++ b/include/export/common/tbbr/tbbr_img_def_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,19 +79,44 @@ /* NT_FW_CONFIG */ #define NT_FW_CONFIG_ID U(27) -/* GPT Partition */ +/* GPT primary header and entries */ #define GPT_IMAGE_ID U(28) +/* GPT backup header and entries */ +#define BKUP_GPT_IMAGE_ID U(29) + /* Binary with STM32 header */ -#define STM32_IMAGE_ID U(29) +#define STM32_IMAGE_ID U(30) /* Encrypted image identifier */ -#define ENC_IMAGE_ID U(30) +#define ENC_IMAGE_ID U(31) /* FW_CONFIG */ -#define FW_CONFIG_ID U(31) +#define FW_CONFIG_ID U(32) + +/* + * Primary FWU metadata image ID + */ +#define FWU_METADATA_IMAGE_ID U(33) + +/* + * Backup FWU metadata image ID + */ +#define BKUP_FWU_METADATA_IMAGE_ID U(34) + +/* Realm Monitor Manager (RMM) */ +#define RMM_IMAGE_ID U(35) + +/* CCA Content Certificate ID */ +#define CCA_CONTENT_CERT_ID U(36) + +/* Core SWD Key Certificate ID */ +#define CORE_SWD_KEY_CERT_ID U(37) + +/* Platform Key Certificate ID */ +#define PLAT_KEY_CERT_ID U(38) /* Max Images */ -#define MAX_IMAGE_IDS U(32) +#define MAX_IMAGE_IDS U(39) #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */ diff --git a/include/export/drivers/gpio_exp.h b/include/export/drivers/gpio_exp.h index a37f190727..e4112a939e 100644 --- a/include/export/drivers/gpio_exp.h +++ b/include/export/drivers/gpio_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,5 +18,6 @@ #define ARM_TF_GPIO_PULL_NONE 0 #define ARM_TF_GPIO_PULL_UP 1 #define ARM_TF_GPIO_PULL_DOWN 2 +#define ARM_TF_GPIO_PULL_REPEATER 3 #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_DRIVERS_GPIO_EXP_H */ diff --git a/include/export/lib/bl_aux_params/bl_aux_params_exp.h b/include/export/lib/bl_aux_params/bl_aux_params_exp.h index 7391dec351..5ae1d64c58 100644 --- a/include/export/lib/bl_aux_params/bl_aux_params_exp.h +++ b/include/export/lib/bl_aux_params/bl_aux_params_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h index d4a4a85dd4..8c58cbb41e 100644 --- a/include/export/lib/utils_def_exp.h +++ b/include/export/lib/utils_def_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,10 +27,14 @@ #else # define U_(_x) (_x##U) # define U(_x) U_(_x) -# define UL(_x) (_x##UL) -# define ULL(_x) (_x##ULL) -# define L(_x) (_x##L) -# define LL(_x) (_x##LL) +# define UL_(_x) (_x##UL) +# define UL(_x) UL_(_x) +# define ULL_(_x) (_x##ULL) +# define ULL(_x) ULL_(_x) +# define L_(_x) (_x##L) +# define L(_x) L_(_x) +# define LL_(_x) (_x##LL) +# define LL(_x) LL_(_x) #endif diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h index 1fece01afd..5d165c90a2 100644 --- a/include/lib/bakery_lock.h +++ b/include/lib/bakery_lock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -96,7 +96,7 @@ static inline void bakery_lock_init(bakery_lock_t *bakery) {} void bakery_lock_get(bakery_lock_t *bakery); void bakery_lock_release(bakery_lock_t *bakery); -#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name __section("bakery_lock") +#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name __section(".bakery_lock") #define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name diff --git a/include/lib/bl_aux_params/bl_aux_params.h b/include/lib/bl_aux_params/bl_aux_params.h index f6ce8024bf..c2da96cf8d 100644 --- a/include/lib/bl_aux_params/bl_aux_params.h +++ b/include/lib/bl_aux_params/bl_aux_params.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,7 @@ /* * Handler function that handles an individual aux parameter. Return true if - * the parameter was handled, and flase if bl_aux_params_parse() should make its + * the parameter was handled, and false if bl_aux_params_parse() should make its * own attempt at handling it (for generic parameters). */ typedef bool (*bl_aux_param_handler_t)(struct bl_aux_param_header *param); diff --git a/include/lib/bootmarker_capture.h b/include/lib/bootmarker_capture.h new file mode 100644 index 0000000000..31fe048048 --- /dev/null +++ b/include/lib/bootmarker_capture.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOOTMARKER_CAPTURE_H +#define BOOTMARKER_CAPTURE_H + +#define BL1_ENTRY U(0) +#define BL1_EXIT U(1) +#define BL2_ENTRY U(2) +#define BL2_EXIT U(3) +#define BL31_ENTRY U(4) +#define BL31_EXIT U(5) +#define BL_TOTAL_IDS U(6) + +#ifdef __ASSEMBLER__ +PMF_DECLARE_CAPTURE_TIMESTAMP(bl_svc) +#endif /*__ASSEMBLER__*/ + +#endif /*BOOTMARKER_CAPTURE_H*/ diff --git a/include/lib/cassert.h b/include/lib/cassert.h index bbfdfdb2ed..512a2ad365 100644 --- a/include/lib/cassert.h +++ b/include/lib/cassert.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h index 0aa65791dd..c8e1b2d1fe 100644 --- a/include/lib/coreboot.h +++ b/include/lib/coreboot.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,5 +41,6 @@ typedef enum { coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size); void coreboot_table_setup(void *base); +void coreboot_get_table_location(uint64_t *address, uint32_t *size); #endif /* COREBOOT_H */ diff --git a/include/lib/cpus/aarch32/aem_generic.h b/include/lib/cpus/aarch32/aem_generic.h index 1d40cec2eb..f631f263c8 100644 --- a/include/lib/cpus/aarch32/aem_generic.h +++ b/include/lib/cpus/aarch32/aem_generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a12.h b/include/lib/cpus/aarch32/cortex_a12.h index abacdbad54..789b4cf56f 100644 --- a/include/lib/cpus/aarch32/cortex_a12.h +++ b/include/lib/cpus/aarch32/cortex_a12.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h index 9526a9cef7..aca4d34ed7 100644 --- a/include/lib/cpus/aarch32/cortex_a15.h +++ b/include/lib/cpus/aarch32/cortex_a15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h index 89a8eb6107..b9e754a426 100644 --- a/include/lib/cpus/aarch32/cortex_a17.h +++ b/include/lib/cpus/aarch32/cortex_a17.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h index 6ddd53380e..841898ab72 100644 --- a/include/lib/cpus/aarch32/cortex_a32.h +++ b/include/lib/cpus/aarch32/cortex_a32.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a5.h b/include/lib/cpus/aarch32/cortex_a5.h index 76703b72ac..c0763f9d36 100644 --- a/include/lib/cpus/aarch32/cortex_a5.h +++ b/include/lib/cpus/aarch32/cortex_a5.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h index 8dd0192e68..b9bb3109bc 100644 --- a/include/lib/cpus/aarch32/cortex_a53.h +++ b/include/lib/cpus/aarch32/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index ffabd61acd..bb977ffadc 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a7.h b/include/lib/cpus/aarch32/cortex_a7.h index 730fdb5cff..16fbfaadd6 100644 --- a/include/lib/cpus/aarch32/cortex_a7.h +++ b/include/lib/cpus/aarch32/cortex_a7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index 4b1af61ca3..0a3a23ab21 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,16 +37,21 @@ #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) +#define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 +#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) +#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) + #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h index a8c978a8b3..337bad9fc4 100644 --- a/include/lib/cpus/aarch32/cortex_a9.h +++ b/include/lib/cpus/aarch32/cortex_a9.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S index a5ae6a486f..096e0b14fc 100644 --- a/include/lib/cpus/aarch32/cpu_macros.S +++ b/include/lib/cpus/aarch32/cpu_macros.S @@ -1,81 +1,13 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef CPU_MACROS_S #define CPU_MACROS_S -#include <arch.h> -#include <lib/cpus/errata_report.h> - -#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3) -#define IMAGE_AT_EL3 -#endif - -#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ - (MIDR_PN_MASK << MIDR_PN_SHIFT) - -/* The number of CPU operations allowed */ -#define CPU_MAX_PWR_DWN_OPS 2 - -/* Special constant to specify that CPU has no reset function */ -#define CPU_NO_RESET_FUNC 0 - -/* Word size for 32-bit CPUs */ -#define CPU_WORD_SIZE 4 - -/* - * Whether errata status needs reporting. Errata status is printed in debug - * builds for both BL1 and BL32 images. - */ -#if (defined(IMAGE_BL1) || defined(IMAGE_BL32)) && DEBUG -# define REPORT_ERRATA 1 -#else -# define REPORT_ERRATA 0 -#endif - - - .equ CPU_MIDR_SIZE, CPU_WORD_SIZE - .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS - .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE - -#ifndef IMAGE_AT_EL3 - .equ CPU_RESET_FUNC_SIZE, 0 -#endif - -/* The power down core and cluster is needed only in BL32 */ -#ifndef IMAGE_BL32 - .equ CPU_PWR_DWN_OPS_SIZE, 0 -#endif - -/* Fields required to print errata status */ -#if !REPORT_ERRATA - .equ CPU_ERRATA_FUNC_SIZE, 0 -#endif - -/* Only BL32 requires mutual exclusion and printed flag. */ -#if !(REPORT_ERRATA && defined(IMAGE_BL32)) - .equ CPU_ERRATA_LOCK_SIZE, 0 - .equ CPU_ERRATA_PRINTED_SIZE, 0 -#endif - - -/* - * Define the offsets to the fields in cpu_ops structure. - * Every offset is defined based on the offset and size of the previous - * field. - */ - .equ CPU_MIDR, 0 - .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE - .equ CPU_PWR_DWN_OPS, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE - .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE - .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE - .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE - .equ CPU_OPS_SIZE, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE +#include <lib/cpus/cpu_ops.h> +#include <lib/cpus/errata.h> /* * Write given expressions as words @@ -129,7 +61,7 @@ */ .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ _power_down_ops:vararg - .section cpu_ops, "a" + .section .cpu_ops, "a" .align 2 .type cpu_ops_\_name, %object .word \_midr @@ -141,6 +73,29 @@ fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops #endif + /* + * It is possible (although unlikely) that a cpu may have no errata in + * code. In that case the start label will not be defined. The list is + * inteded to be used in a loop, so define it as zero-length for + * predictable behaviour. Since this macro is always called at the end + * of the cpu file (after all errata have been parsed) we can be sure + * that we are at the end of the list. Some cpus call the macro twice, + * so only do this once. + */ + .pushsection .rodata.errata_entries + .ifndef \_name\()_errata_list_start + \_name\()_errata_list_start: + .endif + /* some call this multiple times, so only do this once */ + .ifndef \_name\()_errata_list_end + \_name\()_errata_list_end: + .endif + .popsection + + /* and now put them in cpu_ops */ + .word \_name\()_errata_list_start + .word \_name\()_errata_list_end + #if REPORT_ERRATA .ifndef \_name\()_cpu_str /* @@ -165,6 +120,7 @@ * this class. */ .word \_name\()_errata_report + .word \_name\()_cpu_str #ifdef IMAGE_BL32 /* Pointers to errata lock and reported flag */ @@ -227,4 +183,77 @@ beq \_label .endm +/* + * NOTE an erratum and CVE id could clash. However, both numbers are very large + * and the probablity is minuscule. Working around this makes code very + * complicated and extremely difficult to read so it is not considered. In the + * unlikely event that this does happen, prepending the CVE id with a 0 should + * resolve the conflict + */ + +/* + * Add an entry for this erratum to the errata framework + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with the previous field with the + * ERRATUM or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * _special: + * The special non-standard name of an erratum + */ +.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _special + .pushsection .rodata.errata_entries + .align 2 + .ifndef \_cpu\()_errata_list_start + \_cpu\()_errata_list_start: + .endif + + /* unused on AArch32, maintain for portability */ + .word 0 + /* TODO(errata ABI): this prevents all checker functions from + * being optimised away. Can be done away with unless the ABI + * needs them */ + .ifnb \_special + .word check_errata_\_special + .elseif \_cve + .word check_errata_cve_\_cve\()_\_id + .else + .word check_errata_\_id + .endif + /* Will fit CVEs with up to 10 character in the ID field */ + .word \_id + .hword \_cve + .byte \_chosen + /* TODO(errata ABI): mitigated field for known but unmitigated + * errata*/ + .byte 0x1 + .popsection +.endm + +/* + * Maintain compatibility with the old scheme of "each cpu has its own reporter". + * TODO remove entirely once all cpus have been converted. This includes the + * cpu_ops entry, as print_errata_status can call this directly for all cpus + */ +.macro errata_report_shim _cpu:req + #if REPORT_ERRATA + func \_cpu\()_errata_report + push {r12, lr} + + bl generic_errata_report + + pop {r12, lr} + bx lr + endfunc \_cpu\()_errata_report + #endif +.endm #endif /* CPU_MACROS_S */ diff --git a/include/lib/cpus/aarch64/a64fx.h b/include/lib/cpus/aarch64/a64fx.h new file mode 100644 index 0000000000..b7342b0fc4 --- /dev/null +++ b/include/lib/cpus/aarch64/a64fx.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, Fujitsu Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef A64FX_H +#define A64FX_H + +#include <lib/utils_def.h> + +/* A64FX midr for revision 0 */ +#define A64FX_MIDR U(0x461f0010) + +#endif /* A64FX_H */ diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h index 6bb30a275b..acb6adb4a8 100644 --- a/include/lib/cpus/aarch64/aem_generic.h +++ b/include/lib/cpus/aarch64/aem_generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h index 5421478d20..c82b4eb03e 100644 --- a/include/lib/cpus/aarch64/cortex_a35.h +++ b/include/lib/cpus/aarch64/cortex_a35.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,9 @@ /* Cortex-A35 Main ID register for revision 0 */ #define CORTEX_A35_MIDR U(0x410FD040) +/* L2 Extended Control Register */ +#define CORTEX_A35_L2ECTLR_EL1 S3_1_C11_C0_3 + /******************************************************************************* * CPU Extended Control register specific definitions. * CPUECTLR_EL1 is an implementation-specific register. diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h index 6a4cfdfe33..337aac3ef0 100644 --- a/include/lib/cpus/aarch64/cortex_a510.h +++ b/include/lib/cpus/aarch64/cortex_a510.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,14 @@ * CPU Extended Control register specific definitions ******************************************************************************/ #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1) +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) +#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) +#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3) /******************************************************************************* * CPU Power Control register specific definitions @@ -20,4 +28,28 @@ #define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +/******************************************************************************* + * Complex auxiliary control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25) +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2) + +/******************************************************************************* + * Auxiliary control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) +#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1) + #endif /* CORTEX_A510_H */ diff --git a/include/lib/cpus/aarch64/cortex_a520.h b/include/lib/cpus/aarch64/cortex_a520.h new file mode 100644 index 0000000000..619a15d1c8 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a520.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A520_H +#define CORTEX_A520_H + +#define CORTEX_A520_MIDR U(0x410FD800) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register 1 specific definitions. + ******************************************************************************/ +#define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A520_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A520_H */ diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 6fe67a9f3d..18796eea34 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -52,6 +52,8 @@ #define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) #define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT U(13) +#define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT) /******************************************************************************* * L2 Auxiliary Control register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index 60ed957df2..0a1593a590 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index dc40e31adf..19ac513db2 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h index 44c540c72d..9df8d471b1 100644 --- a/include/lib/cpus/aarch64/cortex_a710.h +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,10 +9,14 @@ #define CORTEX_A710_MIDR U(0x410FD470) +/* Cortex-A710 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A710_BHB_LOOP_COUNT U(32) + /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) /******************************************************************************* * CPU Power Control register specific definitions @@ -20,4 +24,47 @@ #define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) +#define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUACTLR3_EL1 S3_0_C15_C1_2 + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) +#define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) +#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) + +/******************************************************************************* + * CPU Selected Instruction Private register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 + #endif /* CORTEX_A710_H */ diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h new file mode 100644 index 0000000000..c7f50db349 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a715.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A715_H +#define CORTEX_A715_H + +#define CORTEX_A715_MIDR U(0x410FD4D0) + +/* Cortex-A715 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A715_BHB_LOOP_COUNT U(38) + +/******************************************************************************* + * CPU Auxiliary Control register 1 specific definitions. + ******************************************************************************/ +#define CORTEX_A715_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1 + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4 + +#define CORTEX_A715_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A715_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A715_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A715_CPUPMR_EL3 S3_6_C15_C8_3 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A715_H */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 28b440e19d..a00f6d6dd5 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,9 @@ /* Cortex-A72 midr for revision 0 */ #define CORTEX_A72_MIDR U(0x410FD080) +/* Cortex-A72 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A72_BHB_LOOP_COUNT U(8) + /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ @@ -37,6 +40,7 @@ #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) +#define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31) /******************************************************************************* * L2 Auxiliary Control register specific definitions. @@ -57,6 +61,9 @@ ******************************************************************************/ #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 +#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) +#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) + #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) #define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) @@ -65,6 +72,7 @@ #define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) #define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) diff --git a/include/lib/cpus/aarch64/cortex_a720.h b/include/lib/cpus/aarch64/cortex_a720.h new file mode 100644 index 0000000000..fb27f79123 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a720.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A720_H +#define CORTEX_A720_H + +#define CORTEX_A720_MIDR U(0x410FD810) + +/* Cortex A720 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A720_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Auxiliary Control register 1 specific definitions. + ******************************************************************************/ +#define CORTEX_A720_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1 + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A720_H */ diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 271a33348c..ede76d1128 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h index e5ca1ba313..ca79991e52 100644 --- a/include/lib/cpus/aarch64/cortex_a75.h +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index a61825f1b9..b2ec8aa560 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,38 +10,42 @@ #include <lib/utils_def.h> /* Cortex-A76 MIDR for revision 0 */ -#define CORTEX_A76_MIDR U(0x410fd0b0) +#define CORTEX_A76_MIDR U(0x410fd0b0) + +/* Cortex-A76 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A76_BHB_LOOP_COUNT U(24) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 -#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) -#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) +#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) +#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) -#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) +#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) -#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) -#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 -#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) +#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ -#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) +#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) #endif /* CORTEX_A76_H */ diff --git a/include/lib/cpus/aarch64/cortex_a76ae.h b/include/lib/cpus/aarch64/cortex_a76ae.h index 9e34efba4c..0d30f70ab8 100644 --- a/include/lib/cpus/aarch64/cortex_a76ae.h +++ b/include/lib/cpus/aarch64/cortex_a76ae.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,9 @@ /* Cortex-A76AE MIDR for revision 0 */ #define CORTEX_A76AE_MIDR U(0x410FD0E0) +/* Cortex-A76 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A76AE_BHB_LOOP_COUNT U(24) + /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h index 0a42a5d77e..39717a3fe2 100644 --- a/include/lib/cpus/aarch64/cortex_a77.h +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,11 +12,15 @@ /* Cortex-A77 MIDR */ #define CORTEX_A77_MIDR U(0x410FD0D0) +/* Cortex-A77 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A77_BHB_LOOP_COUNT U(24) + /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) /******************************************************************************* * CPU Power Control register specific definitions. @@ -24,6 +28,13 @@ #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1) + #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 #define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index caa512046c..2984f82a82 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,11 +11,17 @@ #define CORTEX_A78_MIDR U(0x410FD410) +/* Cortex-A78 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A78_BHB_LOOP_COUNT U(32) + /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions @@ -29,7 +35,14 @@ #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0) #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) +#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40) + +#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2 + +#define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0 /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h index 24ae7eeacd..4ada845068 100644 --- a/include/lib/cpus/aarch64/cortex_a78_ae.h +++ b/include/lib/cpus/aarch64/cortex_a78_ae.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +10,22 @@ #include <cortex_a78.h> -#define CORTEX_A78_AE_MIDR U(0x410FD420) +#define CORTEX_A78_AE_MIDR U(0x410FD420) + +/* Cortex-A78AE loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A78_AE_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1 +#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8 + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1 +#define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0 +#define CORTEX_A78_AE_ACTLR2_EL1_BIT_40 CORTEX_A78_ACTLR2_EL1_BIT_40 #endif /* CORTEX_A78_AE_H */ diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h index adb13bc92e..d600ecab53 100644 --- a/include/lib/cpus/aarch64/cortex_a78c.h +++ b/include/lib/cpus/aarch64/cortex_a78c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,23 @@ #define CORTEX_A78C_MIDR U(0x410FD4B1) +/* Cortex-A76 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A78C_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + * ****************************************************************************/ +#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) +#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) +#define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53) /******************************************************************************* * CPU Power Control register specific definitions @@ -21,4 +34,22 @@ #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2 + +/******************************************************************************* + * CPU Implementation Specific Selected Instruction registers + ******************************************************************************/ +#define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define CORTEX_A78C_ACTLR5_EL1 S3_0_C15_C9_0 + #endif /* CORTEX_A78C_H */ diff --git a/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h b/include/lib/cpus/aarch64/cortex_blackhawk.h index a0d788e39f..bfb303950b 100644 --- a/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h +++ b/include/lib/cpus/aarch64/cortex_blackhawk.h @@ -1,23 +1,23 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_MAKALU_ELP_ARM_H -#define CORTEX_MAKALU_ELP_ARM_H +#ifndef CORTEX_BLACKHAWK_H +#define CORTEX_BLACKHAWK_H -#define CORTEX_MAKALU_ELP_ARM_MIDR U(0x410FD4E0) +#define CORTEX_BLACKHAWK_MIDR U(0x410FD850) /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ -#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_BLACKHAWK_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define CORTEX_BLACKHAWK_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* CORTEX_MAKALU_ELP_ARM_H */ +#endif /* CORTEX_BLACKHAWK_H */ diff --git a/include/lib/cpus/aarch64/cortex_chaberton.h b/include/lib/cpus/aarch64/cortex_chaberton.h new file mode 100644 index 0000000000..8f10b6876b --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_chaberton.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_CHABERTON_H +#define CORTEX_CHABERTON_H + +#define CORTEX_CHABERTON_MIDR U(0x410FD870) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_CHABERTON_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_CHABERTON_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_CHABERTON_H */ diff --git a/include/lib/cpus/aarch64/cortex_gelas.h b/include/lib/cpus/aarch64/cortex_gelas.h new file mode 100644 index 0000000000..90bb78feeb --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_gelas.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_GELAS_H +#define CORTEX_GELAS_H + +#include <lib/utils_def.h> + +#define CORTEX_GELAS_MIDR U(0x410FD8B0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_GELAS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * SME Control registers + ******************************************************************************/ +#define CORTEX_GELAS_SVCRSM S0_3_C4_C2_3 +#define CORTEX_GELAS_SVCRZA S0_3_C4_C4_3 + +#endif /* CORTEX_GELAS_H */ diff --git a/include/lib/cpus/aarch64/cortex_x1.h b/include/lib/cpus/aarch64/cortex_x1.h new file mode 100644 index 0000000000..e3661a882c --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x1.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2022, Google LLC. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X1_H +#define CORTEX_X1_H + +/* Cortex-X1 MIDR for r1p0 */ +#define CORTEX_X1_MIDR U(0x411fd440) + +/* Cortex-X1 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X1_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1) + +#endif /* CORTEX_X1_H */ diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h index 9ce1223c8b..0f97b1e115 100644 --- a/include/lib/cpus/aarch64/cortex_x2.h +++ b/include/lib/cpus/aarch64/cortex_x2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,10 +9,28 @@ #define CORTEX_X2_MIDR U(0x410FD480) +/* Cortex-X2 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X2_BHB_LOOP_COUNT U(32) + /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) + +/******************************************************************************* + * CPU Extended Control register 2 specific definitions + ******************************************************************************/ +#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5 + +#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11) +#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR3_EL1 S3_0_C15_C1_2 /******************************************************************************* * CPU Power Control register specific definitions @@ -20,4 +38,30 @@ #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +/******************************************************************************* + * CPU Auxiliary Control Register definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) + +/******************************************************************************* + * CPU Auxiliary Control Register 2 definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + +/******************************************************************************* + * CPU Auxiliary Control Register 5 definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) + +/******************************************************************************* + * CPU Implementation Specific Selected Instruction registers + ******************************************************************************/ +#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 + #endif /* CORTEX_X2_H */ diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h new file mode 100644 index 0000000000..c5f820cf4d --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X3_H +#define CORTEX_X3_H + +#define CORTEX_X3_MIDR U(0x410FD4E0) + +/* Cortex-X3 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X3_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4) +#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) +#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) + +/******************************************************************************* + * CPU Auxiliary Control register 6 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR6_EL1 S3_0_C15_C8_1 + +/******************************************************************************* + * CPU Extended Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5 + +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) + +#endif /* CORTEX_X3_H */ diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h new file mode 100644 index 0000000000..17d07c8b17 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x4.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X4_H +#define CORTEX_X4_H + +#define CORTEX_X4_MIDR U(0x410FD821) + +/* Cortex X4 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X4_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_X4_H */ diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index 92891ce38b..6faef5db9f 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -1,92 +1,14 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef CPU_MACROS_S #define CPU_MACROS_S -#include <arch.h> #include <assert_macros.S> -#include <lib/cpus/errata_report.h> - -#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ - (MIDR_PN_MASK << MIDR_PN_SHIFT) - -/* The number of CPU operations allowed */ -#define CPU_MAX_PWR_DWN_OPS 2 - -/* Special constant to specify that CPU has no reset function */ -#define CPU_NO_RESET_FUNC 0 - -#define CPU_NO_EXTRA1_FUNC 0 -#define CPU_NO_EXTRA2_FUNC 0 - -/* Word size for 64-bit CPUs */ -#define CPU_WORD_SIZE 8 - -/* - * Whether errata status needs reporting. Errata status is printed in debug - * builds for both BL1 and BL31 images. - */ -#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG -# define REPORT_ERRATA 1 -#else -# define REPORT_ERRATA 0 -#endif - - - .equ CPU_MIDR_SIZE, CPU_WORD_SIZE - .equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS - .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE - .equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE - -#ifndef IMAGE_AT_EL3 - .equ CPU_RESET_FUNC_SIZE, 0 -#endif - -/* The power down core and cluster is needed only in BL31 */ -#ifndef IMAGE_BL31 - .equ CPU_PWR_DWN_OPS_SIZE, 0 -#endif - -/* Fields required to print errata status. */ -#if !REPORT_ERRATA - .equ CPU_ERRATA_FUNC_SIZE, 0 -#endif - -/* Only BL31 requieres mutual exclusion and printed flag. */ -#if !(REPORT_ERRATA && defined(IMAGE_BL31)) - .equ CPU_ERRATA_LOCK_SIZE, 0 - .equ CPU_ERRATA_PRINTED_SIZE, 0 -#endif - -#if !defined(IMAGE_BL31) || !CRASH_REPORTING - .equ CPU_REG_DUMP_SIZE, 0 -#endif - -/* - * Define the offsets to the fields in cpu_ops structure. - * Every offset is defined based in the offset and size of the previous - * field. - */ - .equ CPU_MIDR, 0 - .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE - .equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE - .equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE - .equ CPU_E_HANDLER_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE - .equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE - .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE - .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE - .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE - .equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE - .equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE +#include <lib/cpus/cpu_ops.h> +#include <lib/cpus/errata.h> /* * Write given expressions as quad words @@ -134,9 +56,13 @@ * some CPUs use this entry to set a test function to determine if * the workaround for CVE-2017-5715 needs to be applied or not. * _extra2: - * This is a placeholder for future per CPU operations. Currently + * This is a placeholder for future per CPU operations. Currently * some CPUs use this entry to set a function to disable the * workaround for CVE-2018-3639. + * _extra3: + * This is a placeholder for future per CPU operations. Currently, + * some CPUs use this entry to set a test function to determine if + * the workaround for CVE-2022-23960 needs to be applied or not. * _e_handler: * This is a placeholder for future per CPU exception handlers. * _power_down_ops: @@ -149,8 +75,8 @@ * used to handle power down at subsequent levels */ .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \ - _extra1:req, _extra2:req, _e_handler:req, _power_down_ops:vararg - .section cpu_ops, "a" + _extra1:req, _extra2:req, _extra3:req, _e_handler:req, _power_down_ops:vararg + .section .cpu_ops, "a" .align 3 .type cpu_ops_\_name, %object .quad \_midr @@ -159,11 +85,33 @@ #endif .quad \_extra1 .quad \_extra2 + .quad \_extra3 .quad \_e_handler #ifdef IMAGE_BL31 /* Insert list of functions */ fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops #endif + /* + * It is possible (although unlikely) that a cpu may have no errata in + * code. In that case the start label will not be defined. The list is + * intended to be used in a loop, so define it as zero-length for + * predictable behaviour. Since this macro is always called at the end + * of the cpu file (after all errata have been parsed) we can be sure + * that we are at the end of the list. Some cpus call declare_cpu_ops + * twice, so only do this once. + */ + .pushsection .rodata.errata_entries + .ifndef \_name\()_errata_list_start + \_name\()_errata_list_start: + .endif + .ifndef \_name\()_errata_list_end + \_name\()_errata_list_end: + .endif + .popsection + + /* and now put them in cpu_ops */ + .quad \_name\()_errata_list_start + .quad \_name\()_errata_list_end #if REPORT_ERRATA .ifndef \_name\()_cpu_str @@ -184,18 +132,20 @@ .popsection .endif + /* * Mandatory errata status printing function for CPUs of * this class. */ .quad \_name\()_errata_report + .quad \_name\()_cpu_str #ifdef IMAGE_BL31 /* Pointers to errata lock and reported flag */ .quad \_name\()_errata_lock .quad \_name\()_errata_reported -#endif -#endif +#endif /* IMAGE_BL31 */ +#endif /* REPORT_ERRATA */ #if defined(IMAGE_BL31) && CRASH_REPORTING .quad \_name\()_cpu_reg_dump @@ -204,23 +154,24 @@ .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ _power_down_ops:vararg - declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, \ + declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, \ \_power_down_ops .endm .macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \ _e_handler:req, _power_down_ops:vararg declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ - 0, 0, \_e_handler, \_power_down_ops + 0, 0, 0, \_e_handler, \_power_down_ops .endm .macro declare_cpu_ops_wa _name:req, _midr:req, \ _resetfunc:req, _extra1:req, _extra2:req, \ - _power_down_ops:vararg + _extra3:req, _power_down_ops:vararg declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ - \_extra1, \_extra2, 0, \_power_down_ops + \_extra1, \_extra2, \_extra3, 0, \_power_down_ops .endm +/* TODO can be deleted once all CPUs have been converted */ #if REPORT_ERRATA /* * Print status of a CPU errata @@ -303,4 +254,383 @@ b.eq \_label .endm + +/* + * Workaround wrappers for errata that apply at reset or runtime. Reset errata + * will be applied automatically + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * _apply_at_reset: + * Whether the erratum should be automatically applied at reset + */ +.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req + .pushsection .rodata.errata_entries + .align 3 + .ifndef \_cpu\()_errata_list_start + \_cpu\()_errata_list_start: + .endif + + /* check if unused and compile out if no references */ + .if \_apply_at_reset && \_chosen + .quad erratum_\_cpu\()_\_id\()_wa + .else + .quad 0 + .endif + /* TODO(errata ABI): this prevents all checker functions from + * being optimised away. Can be done away with unless the ABI + * needs them */ + .quad check_erratum_\_cpu\()_\_id + /* Will fit CVEs with up to 10 character in the ID field */ + .word \_id + .hword \_cve + .byte \_chosen + /* TODO(errata ABI): mitigated field for known but unmitigated + * errata */ + .byte 0x1 + .popsection +.endm + +.macro _workaround_start _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req + add_erratum_entry \_cpu, \_cve, \_id, \_chosen, \_apply_at_reset + + func erratum_\_cpu\()_\_id\()_wa + mov x8, x30 + + /* save rev_var for workarounds that might need it but don't + * restore to x0 because few will care */ + mov x7, x0 + bl check_erratum_\_cpu\()_\_id + cbz x0, erratum_\_cpu\()_\_id\()_skip +.endm + +.macro _workaround_end _cpu:req, _id:req + erratum_\_cpu\()_\_id\()_skip: + ret x8 + endfunc erratum_\_cpu\()_\_id\()_wa +.endm + +/******************************************************************************* + * Errata workaround wrappers + ******************************************************************************/ +/* + * Workaround wrappers for errata that apply at reset or runtime. Reset errata + * will be applied automatically + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * in body: + * clobber x0 to x7 (please only use those) + * argument x7 - cpu_rev_var + * + * _wa clobbers: x0-x8 (PCS compliant) + */ +.macro workaround_reset_start _cpu:req, _cve:req, _id:req, _chosen:req + _workaround_start \_cpu, \_cve, \_id, \_chosen, 1 +.endm + +/* + * See `workaround_reset_start` for usage info. Additional arguments: + * + * _midr: + * Check if CPU's MIDR matches the CPU it's meant for. Must be specified + * for errata applied in generic code + */ +.macro workaround_runtime_start _cpu:req, _cve:req, _id:req, _chosen:req, _midr + /* + * Let errata specify if they need MIDR checking. Sadly, storing the + * MIDR in an .equ to retrieve automatically blows up as it stores some + * brackets in the symbol + */ + .ifnb \_midr + jump_if_cpu_midr \_midr, 1f + b erratum_\_cpu\()_\_id\()_skip + + 1: + .endif + _workaround_start \_cpu, \_cve, \_id, \_chosen, 0 +.endm + +/* + * Usage and arguments identical to `workaround_reset_start`. The _cve argument + * is kept here so the same #define can be used as that macro + */ +.macro workaround_reset_end _cpu:req, _cve:req, _id:req + _workaround_end \_cpu, \_id +.endm + +/* + * See `workaround_reset_start` for usage info. The _cve argument is kept here + * so the same #define can be used as that macro. Additional arguments: + * + * _no_isb: + * Optionally do not include the trailing isb. Please disable with the + * NO_ISB macro + */ +.macro workaround_runtime_end _cpu:req, _cve:req, _id:req, _no_isb + /* + * Runtime errata do not have a reset function to call the isb for them + * and missing the isb could be very problematic. It is also likely as + * they tend to be scattered in generic code. + */ + .ifb \_no_isb + isb + .endif + _workaround_end \_cpu, \_id +.endm + +/******************************************************************************* + * Errata workaround helpers + ******************************************************************************/ +/* + * Set a bit in a system register. Can set multiple bits but is limited by the + * way the ORR instruction encodes them. + * + * _reg: + * Register to write to + * + * _bit: + * Bit to set. Please use a descriptive #define + * + * _assert: + * Optionally whether to read back and assert that the bit has been + * written. Please disable with NO_ASSERT macro + * + * clobbers: x1 + */ +.macro sysreg_bit_set _reg:req, _bit:req, _assert=1 + mrs x1, \_reg + orr x1, x1, #\_bit + msr \_reg, x1 +.endm + +/* + * Clear a bit in a system register. Can clear multiple bits but is limited by + * the way the BIC instrucion encodes them. + * + * see sysreg_bit_set for usage + */ +.macro sysreg_bit_clear _reg:req, _bit:req + mrs x1, \_reg + bic x1, x1, #\_bit + msr \_reg, x1 +.endm + +.macro override_vector_table _table:req + adr x1, \_table + msr vbar_el3, x1 +.endm + +/* + * BFI : Inserts bitfield into a system register. + * + * BFI{cond} Rd, Rn, #lsb, #width + */ +.macro sysreg_bitfield_insert _reg:req, _src:req, _lsb:req, _width:req + /* Source value for BFI */ + mov x1, #\_src + mrs x0, \_reg + bfi x0, x1, #\_lsb, #\_width + msr \_reg, x0 +.endm + +/* + * Apply erratum + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * _get_rev: + * Optional parameter that determines whether to insert a call to the CPU revision fetching + * procedure. Stores the result of this in the temporary register x10. + * + * clobbers: x0-x10 (PCS compliant) + */ +.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req, _get_rev=GET_CPU_REV + .if (\_chosen & \_get_rev) + mov x9, x30 + bl cpu_get_rev_var + mov x10, x0 + .elseif (\_chosen) + mov x9, x30 + mov x0, x10 + .endif + + .if \_chosen + bl erratum_\_cpu\()_\_id\()_wa + mov x30, x9 + .endif +.endm + +/* + * Helpers to select which revisions errata apply to. Don't leave a link + * register as the cpu_rev_var_*** will call the ret and we can save on one. + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _rev_num: + * Revision to apply to + * + * in body: + * clobber: x0 to x4 + * argument: x0 - cpu_rev_var + */ +.macro check_erratum_ls _cpu:req, _cve:req, _id:req, _rev_num:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num + b cpu_rev_var_ls + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_hs _cpu:req, _cve:req, _id:req, _rev_num:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num + b cpu_rev_var_hs + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_range _cpu:req, _cve:req, _id:req, _rev_num_lo:req, _rev_num_hi:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num_lo + mov x2, #\_rev_num_hi + b cpu_rev_var_range + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_chosen _cpu:req, _cve:req, _id:req, _chosen:req + func check_erratum_\_cpu\()_\_id + .if \_chosen + mov x0, #ERRATA_APPLIES + .else + mov x0, #ERRATA_MISSING + .endif + ret + endfunc check_erratum_\_cpu\()_\_id +.endm + +/* provide a shorthand for the name format for annoying errata */ +.macro check_erratum_custom_start _cpu:req, _cve:req, _id:req + func check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_custom_end _cpu:req, _cve:req, _id:req + endfunc check_erratum_\_cpu\()_\_id +.endm + + +/******************************************************************************* + * CPU reset function wrapper + ******************************************************************************/ + +/* + * Wrapper to automatically apply all reset-time errata. Will end with an isb. + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * in body: + * clobber x8 to x14 + * argument x14 - cpu_rev_var + */ +.macro cpu_reset_func_start _cpu:req + func \_cpu\()_reset_func + mov x15, x30 + bl cpu_get_rev_var + mov x14, x0 + + /* short circuit the location to avoid searching the list */ + adrp x12, \_cpu\()_errata_list_start + add x12, x12, :lo12:\_cpu\()_errata_list_start + adrp x13, \_cpu\()_errata_list_end + add x13, x13, :lo12:\_cpu\()_errata_list_end + + errata_begin: + /* if head catches up with end of list, exit */ + cmp x12, x13 + b.eq errata_end + + ldr x10, [x12, #ERRATUM_WA_FUNC] + /* TODO(errata ABI): check mitigated and checker function fields + * for 0 */ + ldrb w11, [x12, #ERRATUM_CHOSEN] + + /* skip if not chosen */ + cbz x11, 1f + /* skip if runtime erratum */ + cbz x10, 1f + + /* put cpu revision in x0 and call workaround */ + mov x0, x14 + blr x10 + 1: + add x12, x12, #ERRATUM_ENTRY_SIZE + b errata_begin + errata_end: +.endm + +.macro cpu_reset_func_end _cpu:req + isb + ret x15 + endfunc \_cpu\()_reset_func +.endm + +/* + * Maintain compatibility with the old scheme of each cpu has its own reporting. + * TODO remove entirely once all cpus have been converted. This includes the + * cpu_ops entry, as print_errata_status can call this directly for all cpus + */ +.macro errata_report_shim _cpu:req + #if REPORT_ERRATA + func \_cpu\()_errata_report + /* normal stack frame for pretty debugging */ + stp x29, x30, [sp, #-16]! + mov x29, sp + + bl generic_errata_report + + ldp x29, x30, [sp], #16 + ret + endfunc \_cpu\()_errata_report + #endif +.endm #endif /* CPU_MACROS_S */ diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h index 463f890fd0..cb004bfdd2 100644 --- a/include/lib/cpus/aarch64/cpuamu.h +++ b/include/lib/cpus/aarch64/cpuamu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index 24b6a870c7..84ab6bb438 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h index 0969acf53b..577de61995 100644 --- a/include/lib/cpus/aarch64/dsu_def.h +++ b/include/lib/cpus/aarch64/dsu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,6 +32,7 @@ #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 #define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15) +#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15) /******************************************************************** * Masks applied for DSU errata workarounds diff --git a/include/lib/cpus/aarch64/generic.h b/include/lib/cpus/aarch64/generic.h index 53df587618..dd71554d0f 100644 --- a/include/lib/cpus/aarch64/generic.h +++ b/include/lib/cpus/aarch64/generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserverd. + * Copyright (c) 2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h index 96b4661dbe..6e784f6f53 100644 --- a/include/lib/cpus/aarch64/neoverse_e1.h +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/neoverse_hermes.h b/include/lib/cpus/aarch64/neoverse_hermes.h new file mode 100644 index 0000000000..22492c3d54 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_hermes.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_HERMES_H +#define NEOVERSE_HERMES_H + +#define NEOVERSE_HERMES_MIDR U(0x410FD8E0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_HERMES_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_HERMES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* NEOVERSE_HERMES_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index b50befa8d8..0ba5ad1007 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,58 +10,61 @@ #include <lib/utils_def.h> /* Neoverse N1 MIDR for revision 0 */ -#define NEOVERSE_N1_MIDR U(0x410fd0c0) +#define NEOVERSE_N1_MIDR U(0x410fd0c0) + +/* Neoverse N1 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_N1_BHB_LOOP_COUNT U(24) /* Exception Syndrome register EC code for IC Trap */ -#define NEOVERSE_N1_EC_IC_TRAP U(0x1f) +#define NEOVERSE_N1_EC_IC_TRAP U(0x1f) /******************************************************************************* * CPU Power Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ -#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) +#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) -#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) +#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) -#define NEOVERSE_N1_AMU_NR_COUNTERS U(5) -#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) +#define NEOVERSE_N1_AMU_NR_COUNTERS U(5) +#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 -#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) +#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 -#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) -#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) -#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) -#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) -#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) -#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) -#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) -#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) -#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 -#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) +#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) /* Instruction patching registers */ -#define CPUPSELR_EL3 S3_6_C15_C8_0 -#define CPUPCR_EL3 S3_6_C15_C8_1 -#define CPUPOR_EL3 S3_6_C15_C8_2 -#define CPUPMR_EL3 S3_6_C15_C8_3 +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 #endif /* NEOVERSE_N1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index 7cbd8c17b9..b379faba64 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,24 +8,65 @@ #define NEOVERSE_N2_H /* Neoverse N2 ID register for revision r0p0 */ -#define NEOVERSE_N2_MIDR U(0x410FD490) +#define NEOVERSE_N2_MIDR U(0x410FD490) + +/* Neoverse N2 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_N2_BHB_LOOP_COUNT U(32) /******************************************************************************* * CPU Power control register ******************************************************************************/ -#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 -#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) +#define CPUECTLR2_EL1_TXREQ_LSB U(0) +#define CPUECTLR2_EL1_TXREQ_WIDTH U(3) #endif /* NEOVERSE_N2_H */ diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h index 650eb4d418..1e2d7eaf95 100644 --- a/include/lib/cpus/aarch64/neoverse_v1.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,10 +9,22 @@ #define NEOVERSE_V1_MIDR U(0x410FD400) +/* Neoverse V1 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_V1_BHB_LOOP_COUNT U(32) + /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0 +#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2 +#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3 +#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1 +#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) +#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions @@ -20,4 +32,21 @@ #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1) +#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) +#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40) + +#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47) + +#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0 +#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55) +#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56) +#define NEOVERSE_V1_ACTLR5_EL1_BIT_61 (ULL(1) << 61) + #endif /* NEOVERSE_V1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h new file mode 100644 index 0000000000..39a6607132 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_v2.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_V2_H +#define NEOVERSE_V2_H + +#define NEOVERSE_V2_MIDR U(0x410FD4F0) + +/* Neoverse V2 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_V2_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT U(4) +#define NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH U(3) +#define NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT U(7) +#define NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH U(3) + +/******************************************************************************* + * CPU Extended Control register 2 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) +#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0) +#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) +#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) + +#endif /* NEOVERSE_V2_H */ diff --git a/include/lib/cpus/aarch64/neoverse_v3.h b/include/lib/cpus/aarch64/neoverse_v3.h new file mode 100644 index 0000000000..e5f75ba9b3 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_v3.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_V3_H +#define NEOVERSE_V3_H + + +#define NEOVERSE_V3_VNAE_MIDR U(0x410FD830) +#define NEOVERSE_V3_MIDR U(0x410FD840) + +/* Neoverse V3 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_V3_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* NEOVERSE_V3_H */ diff --git a/include/lib/cpus/aarch64/cortex_makalu.h b/include/lib/cpus/aarch64/nevis.h index 4e0dc86251..7006a29d43 100644 --- a/include/lib/cpus/aarch64/cortex_makalu.h +++ b/include/lib/cpus/aarch64/nevis.h @@ -1,23 +1,23 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_MAKALU_H -#define CORTEX_MAKALU_H +#ifndef NEVIS_H +#define NEVIS_H -#define CORTEX_MAKALU_MIDR U(0x410FD4D0) +#define NEVIS_MIDR U(0x410FD8A0) /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ -#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEVIS_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define NEVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) -#endif /* CORTEX_MAKALU_H */ +#endif /* NEVIS_H */ diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h index 14da170398..58923d2261 100644 --- a/include/lib/cpus/aarch64/qemu_max.h +++ b/include/lib/cpus/aarch64/qemu_max.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/aarch64/travis.h b/include/lib/cpus/aarch64/travis.h new file mode 100644 index 0000000000..a8a255673c --- /dev/null +++ b/include/lib/cpus/aarch64/travis.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRAVIS_H +#define TRAVIS_H + +#define TRAVIS_MIDR U(0x410FD8C0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define TRAVIS_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define TRAVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +/******************************************************************************* + * SME Control registers + ******************************************************************************/ +#define TRAVIS_SVCRSM S0_3_C4_C2_3 +#define TRAVIS_SVCRZA S0_3_C4_C4_3 + +#endif /* TRAVIS_H */ diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h new file mode 100644 index 0000000000..8b36ff1240 --- /dev/null +++ b/include/lib/cpus/cpu_ops.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CPU_OPS_H +#define CPU_OPS_H + +#include <arch.h> + +#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ + (MIDR_PN_MASK << MIDR_PN_SHIFT) + +/* Hardcode to keep compatible with assembly. sizeof(uintptr_t) */ +#if __aarch64__ +#define CPU_WORD_SIZE 8 +#else +#define CPU_WORD_SIZE 4 +#endif /* __aarch64__ */ + +/* The number of CPU operations allowed */ +#define CPU_MAX_PWR_DWN_OPS 2 +/* Special constant to specify that CPU has no reset function */ +#define CPU_NO_RESET_FUNC 0 + +#if __aarch64__ +#define CPU_NO_EXTRA1_FUNC 0 +#define CPU_NO_EXTRA2_FUNC 0 +#define CPU_NO_EXTRA3_FUNC 0 +#endif /* __aarch64__ */ + + +/* + * Define the sizes of the fields in the cpu_ops structure. Word size is set per + * Aarch so keep these definitions the same and each can include whatever it + * needs. + */ +#define CPU_MIDR_SIZE CPU_WORD_SIZE +#ifdef IMAGE_AT_EL3 +#define CPU_RESET_FUNC_SIZE CPU_WORD_SIZE +#else +#define CPU_RESET_FUNC_SIZE 0 +#endif /* IMAGE_AT_EL3 */ +#define CPU_EXTRA1_FUNC_SIZE CPU_WORD_SIZE +#define CPU_EXTRA2_FUNC_SIZE CPU_WORD_SIZE +#define CPU_EXTRA3_FUNC_SIZE CPU_WORD_SIZE +#define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE +/* The power down core and cluster is needed only in BL31 and BL32 */ +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) +#define CPU_PWR_DWN_OPS_SIZE CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS +#else +#define CPU_PWR_DWN_OPS_SIZE 0 +#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ + +#define CPU_ERRATA_LIST_START_SIZE CPU_WORD_SIZE +#define CPU_ERRATA_LIST_END_SIZE CPU_WORD_SIZE +/* Fields required to print errata status */ +#if REPORT_ERRATA +#define CPU_ERRATA_FUNC_SIZE CPU_WORD_SIZE +#define CPU_CPU_STR_SIZE CPU_WORD_SIZE +/* BL1 doesn't require mutual exclusion and printed flag. */ +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) +#define CPU_ERRATA_LOCK_SIZE CPU_WORD_SIZE +#define CPU_ERRATA_PRINTED_SIZE CPU_WORD_SIZE +#else +#define CPU_ERRATA_LOCK_SIZE 0 +#define CPU_ERRATA_PRINTED_SIZE 0 +#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ +#else +#define CPU_ERRATA_FUNC_SIZE 0 +#define CPU_CPU_STR_SIZE 0 +#define CPU_ERRATA_LOCK_SIZE 0 +#define CPU_ERRATA_PRINTED_SIZE 0 +#endif /* REPORT_ERRATA */ + +#if defined(IMAGE_BL31) && CRASH_REPORTING +#define CPU_REG_DUMP_SIZE CPU_WORD_SIZE +#else +#define CPU_REG_DUMP_SIZE 0 +#endif /* defined(IMAGE_BL31) && CRASH_REPORTING */ + + +/* + * Define the offsets to the fields in cpu_ops structure. Every offset is + * defined based on the offset and size of the previous field. + */ +#define CPU_MIDR 0 +#define CPU_RESET_FUNC CPU_MIDR + CPU_MIDR_SIZE +#if __aarch64__ +#define CPU_EXTRA1_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE +#define CPU_EXTRA2_FUNC CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE +#define CPU_EXTRA3_FUNC CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE +#define CPU_E_HANDLER_FUNC CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE +#define CPU_PWR_DWN_OPS CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE +#else +#define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE +#endif /* __aarch64__ */ +#define CPU_ERRATA_LIST_START CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE +#define CPU_ERRATA_LIST_END CPU_ERRATA_LIST_START + CPU_ERRATA_LIST_START_SIZE +#define CPU_ERRATA_FUNC CPU_ERRATA_LIST_END + CPU_ERRATA_LIST_END_SIZE +#define CPU_CPU_STR CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE +#define CPU_ERRATA_LOCK CPU_CPU_STR + CPU_CPU_STR_SIZE +#define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE +#if __aarch64__ +#define CPU_REG_DUMP CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE +#define CPU_OPS_SIZE CPU_REG_DUMP + CPU_REG_DUMP_SIZE +#else +#define CPU_OPS_SIZE CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE +#endif /* __aarch64__ */ + +#ifndef __ASSEMBLER__ +#include <lib/cassert.h> +#include <lib/spinlock.h> + +struct cpu_ops { + unsigned long midr; +#ifdef IMAGE_AT_EL3 + void (*reset_func)(void); +#endif /* IMAGE_AT_EL3 */ +#if __aarch64__ + void (*extra1_func)(void); + void (*extra2_func)(void); + void (*extra3_func)(void); + void (*e_handler_func)(long es); +#endif /* __aarch64__ */ +#if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS + void (*pwr_dwn_ops[CPU_MAX_PWR_DWN_OPS])(void); +#endif /* (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS */ + void *errata_list_start; + void *errata_list_end; +#if REPORT_ERRATA + void (*errata_func)(void); + char *cpu_str; +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) + spinlock_t *errata_lock; + unsigned int *errata_reported; +#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ +#endif /* REPORT_ERRATA */ +#if defined(IMAGE_BL31) && CRASH_REPORTING + void (*reg_dump)(void); +#endif /* defined(IMAGE_BL31) && CRASH_REPORTING */ +} __packed; + +CASSERT(sizeof(struct cpu_ops) == CPU_OPS_SIZE, + assert_cpu_ops_asm_c_different_sizes); + +long cpu_get_rev_var(void); +void *get_cpu_ops_ptr(void); + +#endif /* __ASSEMBLER__ */ +#endif /* CPU_OPS_H */ diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h new file mode 100644 index 0000000000..20808989a5 --- /dev/null +++ b/include/lib/cpus/errata.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ERRATA_REPORT_H +#define ERRATA_REPORT_H + +#include <lib/cpus/cpu_ops.h> + + +#define ERRATUM_WA_FUNC_SIZE CPU_WORD_SIZE +#define ERRATUM_CHECK_FUNC_SIZE CPU_WORD_SIZE +#define ERRATUM_ID_SIZE 4 +#define ERRATUM_CVE_SIZE 2 +#define ERRATUM_CHOSEN_SIZE 1 +#define ERRATUM_MITIGATED_SIZE 1 + +#define ERRATUM_WA_FUNC 0 +#define ERRATUM_CHECK_FUNC ERRATUM_WA_FUNC + ERRATUM_WA_FUNC_SIZE +#define ERRATUM_ID ERRATUM_CHECK_FUNC + ERRATUM_CHECK_FUNC_SIZE +#define ERRATUM_CVE ERRATUM_ID + ERRATUM_ID_SIZE +#define ERRATUM_CHOSEN ERRATUM_CVE + ERRATUM_CVE_SIZE +#define ERRATUM_MITIGATED ERRATUM_CHOSEN + ERRATUM_CHOSEN_SIZE +#define ERRATUM_ENTRY_SIZE ERRATUM_MITIGATED + ERRATUM_MITIGATED_SIZE + +#ifndef __ASSEMBLER__ +#include <lib/cassert.h> + +void print_errata_status(void); +void errata_print_msg(unsigned int status, const char *cpu, const char *id); + +/* + * NOTE that this structure will be different on AArch32 and AArch64. The + * uintptr_t will reflect the change and the alignment will be correct in both. + */ +struct erratum_entry { + uintptr_t (*wa_func)(uint64_t cpu_rev); + uintptr_t (*check_func)(uint64_t cpu_rev); + /* Will fit CVEs with up to 10 character in the ID field */ + uint32_t id; + /* Denote CVEs with their year or errata with 0 */ + uint16_t cve; + uint8_t chosen; + /* TODO(errata ABI): placeholder for the mitigated field */ + uint8_t _mitigated; +} __packed; + +CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE, + assert_erratum_entry_asm_c_different_sizes); +#else + +/* + * errata framework macro helpers + * + * NOTE an erratum and CVE id could clash. However, both numbers are very large + * and the probablity is minuscule. Working around this makes code very + * complicated and extremely difficult to read so it is not considered. In the + * unlikely event that this does happen, prepending the CVE id with a 0 should + * resolve the conflict + */ +#define ERRATUM(id) 0, id +#define CVE(year, id) year, id +#define NO_ISB 1 +#define NO_ASSERT 0 +#define NO_APPLY_AT_RESET 0 +#define APPLY_AT_RESET 1 +#define GET_CPU_REV 1 +#define NO_GET_CPU_REV 0 + +/* useful for errata that end up always being worked around */ +#define ERRATUM_ALWAYS_CHOSEN 1 + +#endif /* __ASSEMBLER__ */ + +/* Errata status */ +#define ERRATA_NOT_APPLIES 0 +#define ERRATA_APPLIES 1 +#define ERRATA_MISSING 2 + +/* Macro to get CPU revision code for checking errata version compatibility. */ +#define CPU_REV(r, p) ((r << 4) | p) + +#endif /* ERRATA_REPORT_H */ diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h deleted file mode 100644 index efdedf0aaa..0000000000 --- a/include/lib/cpus/errata_report.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef ERRATA_REPORT_H -#define ERRATA_REPORT_H - -#ifndef __ASSEMBLER__ - -#include <arch.h> -#include <arch_helpers.h> -#include <lib/spinlock.h> -#include <lib/utils_def.h> - -#if DEBUG -void print_errata_status(void); -#else -static inline void print_errata_status(void) {} -#endif - -void errata_print_msg(unsigned int status, const char *cpu, const char *id); -int errata_needs_reporting(spinlock_t *lock, uint32_t *reported); - -#endif /* __ASSEMBLER__ */ - -/* Errata status */ -#define ERRATA_NOT_APPLIES 0 -#define ERRATA_APPLIES 1 -#define ERRATA_MISSING 2 - -/* Macro to get CPU revision code for checking errata version compatibility. */ -#define CPU_REV(r, p) ((r << 4) | p) - -#endif /* ERRATA_REPORT_H */ diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h index 940fc659e6..2ad56e1790 100644 --- a/include/lib/cpus/wa_cve_2017_5715.h +++ b/include/lib/cpus/wa_cve_2017_5715.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h index e37db377e3..5a7c9bf2c9 100644 --- a/include/lib/cpus/wa_cve_2018_3639.h +++ b/include/lib/cpus/wa_cve_2018_3639.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h new file mode 100644 index 0000000000..50c0f76c76 --- /dev/null +++ b/include/lib/cpus/wa_cve_2022_23960.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef WA_CVE_2022_23960_H +#define WA_CVE_2022_23960_H + +int check_smccc_arch_wa3_applies(void); + +#endif /* WA_CVE_2022_23960_H */ diff --git a/include/lib/dice/dice.h b/include/lib/dice/dice.h new file mode 100644 index 0000000000..cf549422e3 --- /dev/null +++ b/include/lib/dice/dice.h @@ -0,0 +1,166 @@ +// Copyright 2020 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); you may not +// use this file except in compliance with the License. You may obtain a copy of +// the License at +// +// https://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +// License for the specific language governing permissions and limitations under +// the License. + +#ifndef DICE_DICE_H_ +#define DICE_DICE_H_ + +#include <stddef.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define DICE_CDI_SIZE 32 +#define DICE_HASH_SIZE 64 +#define DICE_HIDDEN_SIZE 64 +#define DICE_INLINE_CONFIG_SIZE 64 +#define DICE_PRIVATE_KEY_SEED_SIZE 32 +#define DICE_ID_SIZE 20 + +typedef enum { + kDiceResultOk, + kDiceResultInvalidInput, + kDiceResultBufferTooSmall, + kDiceResultPlatformError, +} DiceResult; + +typedef enum { + kDiceModeNotInitialized, + kDiceModeNormal, + kDiceModeDebug, + kDiceModeMaintenance, +} DiceMode; + +typedef enum { + kDiceConfigTypeInline, + kDiceConfigTypeDescriptor, +} DiceConfigType; + +// Contains a full set of input values describing the target program or system. +// See the Open Profile for DICE specification for a detailed explanation of +// these inputs. +// +// Fields: +// code_hash: A hash or similar representation of the target code. +// code_descriptor: An optional descriptor to be included in the certificate. +// This descriptor is opaque to the DICE flow and is included verbatim +// in the certificate with no validation. May be null. +// code_descriptor_size: The size in bytes of |code_descriptor|. +// config_type: Indicates how to interpret the remaining config-related +// fields. If the type is 'inline', then the 64 byte configuration input +// value must be provided in |config_value| and |config_descriptor| is +// ignored. If the type is 'descriptor', then |config_descriptor| is +// hashed to get the configuration input value and |config_value| is +// ignored. +// config_value: A 64-byte configuration input value when |config_type| is +// kDiceConfigTypeInline. Otherwise, this field is ignored. +// config_descriptor: A descriptor to be hashed for the configuration input +// value when |config_type| is kDiceConfigTypeDescriptor. Otherwise, +// this field is ignored and may be null. +// config_descriptor_size: The size in bytes of |config_descriptor|. +// authority_hash: A hash or similar representation of the authority used to +// verify the target code. If the code is not verified or the authority +// is implicit, for example hard coded as part of the code currently +// executing, then this value should be set to all zero bytes. +// authority_descriptor: An optional descriptor to be included in the +// certificate. This descriptor is opaque to the DICE flow and is +// included verbatim in the certificate with no validation. May be null. +// authority_descriptor_size: The size in bytes of |authority_descriptor|. +// mode: The current operating mode. +// hidden: Additional input which will not appear in certificates. If this is +// not used it should be set to all zero bytes. +typedef struct DiceInputValues_ { + uint8_t code_hash[DICE_HASH_SIZE]; + const uint8_t* code_descriptor; + size_t code_descriptor_size; + DiceConfigType config_type; + uint8_t config_value[DICE_INLINE_CONFIG_SIZE]; + const uint8_t* config_descriptor; + size_t config_descriptor_size; + uint8_t authority_hash[DICE_HASH_SIZE]; + const uint8_t* authority_descriptor; + size_t authority_descriptor_size; + DiceMode mode; + uint8_t hidden[DICE_HIDDEN_SIZE]; +} DiceInputValues; + +// Derives a |cdi_private_key_seed| from a |cdi_attest| value. On success +// populates |cdi_private_key_seed| and returns kDiceResultOk. +DiceResult DiceDeriveCdiPrivateKeySeed( + void* context, const uint8_t cdi_attest[DICE_CDI_SIZE], + uint8_t cdi_private_key_seed[DICE_PRIVATE_KEY_SEED_SIZE]); + +// Derives an |id| from a |cdi_public_key| value. Because public keys can vary +// in length depending on the algorithm, the |cdi_public_key_size| in bytes must +// be provided. When interpreted as an integer, |id| is big-endian. On success +// populates |id| and returns kDiceResultOk. +DiceResult DiceDeriveCdiCertificateId(void* context, + const uint8_t* cdi_public_key, + size_t cdi_public_key_size, + uint8_t id[DICE_ID_SIZE]); + +// Executes the main DICE flow. +// +// Given a full set of input values and the current CDI values, computes the +// next CDI values and a matching certificate. See the Open Profile for DICE +// specification for a detailed explanation of this flow. +// In certain cases, the caller may not need to generate the CDI certificate. +// The caller should signal this by setting the certificate parameters to +// null/zero values appropriately. +// +// Parameters: +// context: Context provided by the caller that is opaque to this library +// but is passed through to the integration-provided operations in +// dice/ops.h. The value is, therefore, integration-specific and may be +// null. +// current_cdi_attest, current_cdi_seal: The current CDI values as produced +// by a previous DICE flow. If this is the first DICE flow in a system, +// the Unique Device Secret (UDS) should be used for both of these +// arguments. +// input_values: A set of input values describing the target program or +// system. +// next_cdi_certificate_buffer_size: The size in bytes of the buffer pointed +// to by the |next_cdi_certificate| argument. This should be set to zero +// if next CDI certificate should not be computed. +// next_cdi_certificate: On success, will be populated with the generated +// certificate, up to |next_cdi_certificate_buffer_size| in size. If the +// certificate cannot fit in the buffer, |next_cdi_certificate_size| is +// populated with the required size and kDiceResultBufferTooSmall is +// returned. This should be set to NULL if next CDI certificate should +// not be computed. +// next_cdi_certificate_actual_size: On success, will be populated with the +// size, in bytes, of the certificate data written to +// |next_cdi_certificate|. If kDiceResultBufferTooSmall is returned, will +// be populated with the required buffer size. This should be set to NULL +// if next CDI certificate should not be computed. +// next_cdi_attest: On success, will be populated with the next CDI value for +// attestation. +// next_cdi_seal: On success, will be populated with the next CDI value for +// sealing. +DiceResult DiceMainFlow(void* context, + const uint8_t current_cdi_attest[DICE_CDI_SIZE], + const uint8_t current_cdi_seal[DICE_CDI_SIZE], + const DiceInputValues* input_values, + size_t next_cdi_certificate_buffer_size, + uint8_t* next_cdi_certificate, + size_t* next_cdi_certificate_actual_size, + uint8_t next_cdi_attest[DICE_CDI_SIZE], + uint8_t next_cdi_seal[DICE_CDI_SIZE]); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // DICE_DICE_H_ diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h index 5604c8e502..3b698e3f72 100644 --- a/include/lib/el3_runtime/aarch32/context.h +++ b/include/lib/el3_runtime/aarch32/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,7 +62,7 @@ typedef struct cpu_context { * ensure that the assembler and the compiler view of the offsets of * the structure members is the same. */ -CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), \ +CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), assert_core_context_regs_offset_mismatch); #endif /* __ASSEMBLER__ */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 9d9f9d3325..fbaa008f1d 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef CONTEXT_H #define CONTEXT_H +#include <lib/el3_runtime/context_el2.h> +#include <lib/el3_runtime/cpu_data.h> #include <lib/utils_def.h> /******************************************************************************* @@ -61,7 +63,22 @@ #define CTX_ELR_EL3 U(0x20) #define CTX_PMCR_EL0 U(0x28) #define CTX_IS_IN_EL3 U(0x30) -#define CTX_EL3STATE_END U(0x40) /* Align to the next 16 byte boundary */ +/* Constants required in supporting nested exception in EL3 */ +#define CTX_SAVED_ELR_EL3 U(0x38) +/* + * General purpose flag, to save various EL3 states + * FFH mode : Used to identify if handling nested exception + * KFH mode : Used as counter value + */ +#define CTX_NESTED_EA_FLAG U(0x40) +#if FFH_SUPPORT + #define CTX_SAVED_ESR_EL3 U(0x48) + #define CTX_SAVED_SPSR_EL3 U(0x50) + #define CTX_SAVED_GPREG_LR U(0x58) + #define CTX_EL3STATE_END U(0x60) /* Align to the next 16 byte boundary */ +#else + #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ +#endif /* FFH_SUPPORT */ /******************************************************************************* * Constants that allow assembler code to access members of and the @@ -124,7 +141,7 @@ #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END #endif /* NS_TIMER_SWITCH */ -#if CTX_INCLUDE_MTE_REGS +#if ENABLE_FEAT_MTE2 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) @@ -134,112 +151,18 @@ #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) #else #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END -#endif /* CTX_INCLUDE_MTE_REGS */ +#endif /* ENABLE_FEAT_MTE2 */ /* * End of system registers. */ #define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END -/* - * EL2 register set - */ - -#if CTX_INCLUDE_EL2_REGS -/* For later discussion - * ICH_AP0R<n>_EL2 - * ICH_AP1R<n>_EL2 - * AMEVCNTVOFF0<n>_EL2 - * AMEVCNTVOFF1<n>_EL2 - * ICH_LR<n>_EL2 - */ -#define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) - -#define CTX_ACTLR_EL2 U(0x0) -#define CTX_AFSR0_EL2 U(0x8) -#define CTX_AFSR1_EL2 U(0x10) -#define CTX_AMAIR_EL2 U(0x18) -#define CTX_CNTHCTL_EL2 U(0x20) -#define CTX_CNTVOFF_EL2 U(0x28) -#define CTX_CPTR_EL2 U(0x30) -#define CTX_DBGVCR32_EL2 U(0x38) -#define CTX_ELR_EL2 U(0x40) -#define CTX_ESR_EL2 U(0x48) -#define CTX_FAR_EL2 U(0x50) -#define CTX_HACR_EL2 U(0x58) -#define CTX_HCR_EL2 U(0x60) -#define CTX_HPFAR_EL2 U(0x68) -#define CTX_HSTR_EL2 U(0x70) -#define CTX_ICC_SRE_EL2 U(0x78) -#define CTX_ICH_HCR_EL2 U(0x80) -#define CTX_ICH_VMCR_EL2 U(0x88) -#define CTX_MAIR_EL2 U(0x90) -#define CTX_MDCR_EL2 U(0x98) -#define CTX_PMSCR_EL2 U(0xa0) -#define CTX_SCTLR_EL2 U(0xa8) -#define CTX_SPSR_EL2 U(0xb0) -#define CTX_SP_EL2 U(0xb8) -#define CTX_TCR_EL2 U(0xc0) -#define CTX_TPIDR_EL2 U(0xc8) -#define CTX_TTBR0_EL2 U(0xd0) -#define CTX_VBAR_EL2 U(0xd8) -#define CTX_VMPIDR_EL2 U(0xe0) -#define CTX_VPIDR_EL2 U(0xe8) -#define CTX_VTCR_EL2 U(0xf0) -#define CTX_VTTBR_EL2 U(0xf8) - -// Only if MTE registers in use -#define CTX_TFSR_EL2 U(0x100) - -// Only if ENABLE_MPAM_FOR_LOWER_ELS==1 -#define CTX_MPAM2_EL2 U(0x108) -#define CTX_MPAMHCR_EL2 U(0x110) -#define CTX_MPAMVPM0_EL2 U(0x118) -#define CTX_MPAMVPM1_EL2 U(0x120) -#define CTX_MPAMVPM2_EL2 U(0x128) -#define CTX_MPAMVPM3_EL2 U(0x130) -#define CTX_MPAMVPM4_EL2 U(0x138) -#define CTX_MPAMVPM5_EL2 U(0x140) -#define CTX_MPAMVPM6_EL2 U(0x148) -#define CTX_MPAMVPM7_EL2 U(0x150) -#define CTX_MPAMVPMV_EL2 U(0x158) - -// Starting with Armv8.6 -#define CTX_HAFGRTR_EL2 U(0x160) -#define CTX_HDFGRTR_EL2 U(0x168) -#define CTX_HDFGWTR_EL2 U(0x170) -#define CTX_HFGITR_EL2 U(0x178) -#define CTX_HFGRTR_EL2 U(0x180) -#define CTX_HFGWTR_EL2 U(0x188) -#define CTX_CNTPOFF_EL2 U(0x190) - -// Starting with Armv8.4 -#define CTX_CONTEXTIDR_EL2 U(0x198) -#define CTX_SDER32_EL2 U(0x1a0) -#define CTX_TTBR1_EL2 U(0x1a8) -#define CTX_VDISR_EL2 U(0x1b0) -#define CTX_VNCR_EL2 U(0x1b8) -#define CTX_VSESR_EL2 U(0x1c0) -#define CTX_VSTCR_EL2 U(0x1c8) -#define CTX_VSTTBR_EL2 U(0x1d0) -#define CTX_TRFCR_EL2 U(0x1d8) - -// Starting with Armv8.5 -#define CTX_SCXTNUM_EL2 U(0x1e0) -/* Align to the next 16 byte boundary */ -#define CTX_EL2_SYSREGS_END U(0x1f0) - -#endif /* CTX_INCLUDE_EL2_REGS */ - /******************************************************************************* * Constants that allow assembler code to access members of and the 'fp_regs' * structure at their correct offsets. ******************************************************************************/ -#if CTX_INCLUDE_EL2_REGS -# define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END) -#else # define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) -#endif #if CTX_INCLUDE_FPREGS #define CTX_FP_Q0 U(0x0) #define CTX_FP_Q1 U(0x10) @@ -280,10 +203,10 @@ #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ #else #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ -#endif +#endif /* CTX_INCLUDE_AARCH32_REGS */ #else #define CTX_FPREGS_END U(0) -#endif +#endif /* CTX_INCLUDE_FPREGS */ /******************************************************************************* * Registers related to CVE-2018-3639 @@ -312,6 +235,35 @@ #define CTX_PAUTH_REGS_END U(0) #endif /* CTX_INCLUDE_PAUTH_REGS */ +/******************************************************************************* + * Registers related to ARMv8.2-MPAM. + ******************************************************************************/ +#define CTX_MPAM_REGS_OFFSET (CTX_PAUTH_REGS_OFFSET + CTX_PAUTH_REGS_END) +#if CTX_INCLUDE_MPAM_REGS +#define CTX_MPAM2_EL2 U(0x0) +#define CTX_MPAMHCR_EL2 U(0x8) +#define CTX_MPAMVPM0_EL2 U(0x10) +#define CTX_MPAMVPM1_EL2 U(0x18) +#define CTX_MPAMVPM2_EL2 U(0x20) +#define CTX_MPAMVPM3_EL2 U(0x28) +#define CTX_MPAMVPM4_EL2 U(0x30) +#define CTX_MPAMVPM5_EL2 U(0x38) +#define CTX_MPAMVPM6_EL2 U(0x40) +#define CTX_MPAMVPM7_EL2 U(0x48) +#define CTX_MPAMVPMV_EL2 U(0x50) +#define CTX_MPAM_REGS_END U(0x60) +#else +#define CTX_MPAM_REGS_END U(0x0) +#endif /* CTX_INCLUDE_MPAM_REGS */ + +/******************************************************************************* + * Registers initialised in a per-world context. + ******************************************************************************/ +#define CTX_CPTR_EL3 U(0x0) +#define CTX_ZCR_EL3 U(0x8) +#define CTX_MPAM3_EL3 U(0x10) +#define CTX_PERWORLD_EL3STATE_END U(0x18) + #ifndef __ASSEMBLER__ #include <stdint.h> @@ -331,9 +283,7 @@ /* Constants to determine the size of individual context structures */ #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) #define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT) -#if CTX_INCLUDE_EL2_REGS -# define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT) -#endif + #if CTX_INCLUDE_FPREGS # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) #endif @@ -342,6 +292,9 @@ #if CTX_INCLUDE_PAUTH_REGS # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) #endif +#if CTX_INCLUDE_MPAM_REGS +# define CTX_MPAM_REGS_ALL (CTX_MPAM_REGS_END >> DWORD_SHIFT) +#endif /* * AArch64 general purpose register context structure. Usually x0-x18, @@ -358,15 +311,6 @@ DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); */ DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL); - -/* - * AArch64 EL2 system register context structure for preserving the - * architectural state during world switches. - */ -#if CTX_INCLUDE_EL2_REGS -DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL); -#endif - /* * AArch64 floating point register context structure for preserving * the floating point state during switches from one security state to @@ -390,6 +334,11 @@ DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); #endif +/* Registers associated to ARMv8.2 MPAM */ +#if CTX_INCLUDE_MPAM_REGS +DEFINE_REG_STRUCT(mpam, CTX_MPAM_REGS_ALL); +#endif + /* * Macros to access members of any of the above structures using their * offsets @@ -399,30 +348,49 @@ DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); = (uint64_t) (val)) /* - * Top-level context structure which is used by EL3 firmware to - * preserve the state of a core at EL1 in one of the two security - * states and save enough EL3 meta data to be able to return to that - * EL and security state. The context management library will be used - * to ensure that SP_EL3 always points to an instance of this - * structure at exception entry and exit. Each instance will - * correspond to either the secure or the non-secure state. + * Top-level context structure which is used by EL3 firmware to preserve + * the state of a core at the next lower EL in a given security state and + * save enough EL3 meta data to be able to return to that EL and security + * state. The context management library will be used to ensure that + * SP_EL3 always points to an instance of this structure at exception + * entry and exit. */ typedef struct cpu_context { gp_regs_t gpregs_ctx; el3_state_t el3state_ctx; el1_sysregs_t el1_sysregs_ctx; -#if CTX_INCLUDE_EL2_REGS - el2_sysregs_t el2_sysregs_ctx; -#endif + #if CTX_INCLUDE_FPREGS fp_regs_t fpregs_ctx; #endif cve_2018_3639_t cve_2018_3639_ctx; + #if CTX_INCLUDE_PAUTH_REGS pauth_t pauth_ctx; #endif + +#if CTX_INCLUDE_MPAM_REGS + mpam_t mpam_ctx; +#endif + +#if CTX_INCLUDE_EL2_REGS + el2_sysregs_t el2_sysregs_ctx; +#endif + } cpu_context_t; +/* + * Per-World Context. + * It stores registers whose values can be shared across CPUs. + */ +typedef struct per_world_context { + uint64_t ctx_cptr_el3; + uint64_t ctx_zcr_el3; + uint64_t ctx_mpam3_el3; +} per_world_context_t; + +extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; + /* Macros to access members of the 'cpu_context_t' structure */ #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) #if CTX_INCLUDE_FPREGS @@ -437,32 +405,41 @@ typedef struct cpu_context { #if CTX_INCLUDE_PAUTH_REGS # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) #endif +#if CTX_INCLUDE_MPAM_REGS +# define get_mpam_ctx(h) (&((cpu_context_t *) h)->mpam_ctx) +#endif /* * Compile time assertions related to the 'cpu_context' structure to * ensure that the assembler and the compiler view of the offsets of * the structure members is the same. */ -CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ +CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), assert_core_context_gp_offset_mismatch); -CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), \ + +CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), + assert_core_context_el3state_offset_mismatch); + +CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), assert_core_context_el1_sys_offset_mismatch); -#if CTX_INCLUDE_EL2_REGS -CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), \ - assert_core_context_el2_sys_offset_mismatch); -#endif + #if CTX_INCLUDE_FPREGS -CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ +CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), assert_core_context_fp_offset_mismatch); -#endif -CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ - assert_core_context_el3state_offset_mismatch); -CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \ +#endif /* CTX_INCLUDE_FPREGS */ + +CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), assert_core_context_cve_2018_3639_offset_mismatch); + #if CTX_INCLUDE_PAUTH_REGS -CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \ +CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), assert_core_context_pauth_offset_mismatch); -#endif +#endif /* CTX_INCLUDE_PAUTH_REGS */ + +#if CTX_INCLUDE_MPAM_REGS +CASSERT(CTX_MPAM_REGS_OFFSET == __builtin_offsetof(cpu_context_t, mpam_ctx), + assert_core_context_mpam_offset_mismatch); +#endif /* CTX_INCLUDE_MPAM_REGS */ /* * Helper macro to set the general purpose registers that correspond to @@ -503,14 +480,6 @@ CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \ /******************************************************************************* * Function prototypes ******************************************************************************/ -void el1_sysregs_context_save(el1_sysregs_t *regs); -void el1_sysregs_context_restore(el1_sysregs_t *regs); - -#if CTX_INCLUDE_EL2_REGS -void el2_sysregs_context_save(el2_sysregs_t *regs); -void el2_sysregs_context_restore(el2_sysregs_t *regs); -#endif - #if CTX_INCLUDE_FPREGS void fpregs_context_save(fp_regs_t *regs); void fpregs_context_restore(fp_regs_t *regs); diff --git a/include/lib/el3_runtime/context_debug.h b/include/lib/el3_runtime/context_debug.h new file mode 100644 index 0000000000..51e77482df --- /dev/null +++ b/include/lib/el3_runtime/context_debug.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef CONTEXT_DEBUG_H +#define CONTEXT_DEBUG_H + +#if PLATFORM_REPORT_CTX_MEM_USE && defined(__aarch64__) +/******************************************************************************** + * Reports the allocated memory for every security state and then reports the + * total system-wide allocated memory. + *******************************************************************************/ +void report_ctx_memory_usage(void); +#else +static inline void report_ctx_memory_usage(void) {} +#endif /* PLATFORM_REPORT_CTX_MEM_USE */ + +#endif /* CONTEXT_DEBUG_H */ diff --git a/include/lib/el3_runtime/context_el2.h b/include/lib/el3_runtime/context_el2.h new file mode 100644 index 0000000000..4ad96349d4 --- /dev/null +++ b/include/lib/el3_runtime/context_el2.h @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CONTEXT_EL2_H +#define CONTEXT_EL2_H + +#ifndef __ASSEMBLER__ +/******************************************************************************* + * EL2 Registers: + * AArch64 EL2 system register context structure for preserving the + * architectural state during world switches. + ******************************************************************************/ +#if CTX_INCLUDE_EL2_REGS +typedef struct el2_common_regs { + uint64_t actlr_el2; + uint64_t afsr0_el2; + uint64_t afsr1_el2; + uint64_t amair_el2; + uint64_t cnthctl_el2; + uint64_t cntvoff_el2; + uint64_t cptr_el2; + uint64_t dbgvcr32_el2; + uint64_t elr_el2; + uint64_t esr_el2; + uint64_t far_el2; + uint64_t hacr_el2; + uint64_t hcr_el2; + uint64_t hpfar_el2; + uint64_t hstr_el2; + uint64_t icc_sre_el2; + uint64_t ich_hcr_el2; + uint64_t ich_vmcr_el2; + uint64_t mair_el2; + uint64_t mdcr_el2; + uint64_t pmscr_el2; + uint64_t sctlr_el2; + uint64_t spsr_el2; + uint64_t sp_el2; + uint64_t tcr_el2; + uint64_t tpidr_el2; + uint64_t ttbr0_el2; + uint64_t vbar_el2; + uint64_t vmpidr_el2; + uint64_t vpidr_el2; + uint64_t vtcr_el2; + uint64_t vttbr_el2; +} el2_common_regs_t; + +typedef struct el2_mte_regs { + uint64_t tfsr_el2; +} el2_mte_regs_t; + +typedef struct el2_fgt_regs { + uint64_t hdfgrtr_el2; + uint64_t hafgrtr_el2; + uint64_t hdfgwtr_el2; + uint64_t hfgitr_el2; + uint64_t hfgrtr_el2; + uint64_t hfgwtr_el2; +} el2_fgt_regs_t; + +typedef struct el2_ecv_regs { + uint64_t cntpoff_el2; +} el2_ecv_regs_t; + +typedef struct el2_vhe_regs { + uint64_t contextidr_el2; + uint64_t ttbr1_el2; +} el2_vhe_regs_t; + +typedef struct el2_ras_regs { + uint64_t vdisr_el2; + uint64_t vsesr_el2; +} el2_ras_regs_t; + +typedef struct el2_neve_regs { + uint64_t vncr_el2; +} el2_neve_regs_t; + +typedef struct el2_trf_regs { + uint64_t trfcr_el2; +} el2_trf_regs_t; + +typedef struct el2_csv2_regs { + uint64_t scxtnum_el2; +} el2_csv2_regs_t; + +typedef struct el2_hcx_regs { + uint64_t hcrx_el2; +} el2_hcx_regs_t; + +typedef struct el2_tcr2_regs { + uint64_t tcr2_el2; +} el2_tcr2_regs_t; + +typedef struct el2_sxpoe_regs { + uint64_t por_el2; +} el2_sxpoe_regs_t; + +typedef struct el2_sxpie_regs { + uint64_t pire0_el2; + uint64_t pir_el2; +} el2_sxpie_regs_t; + +typedef struct el2_s2pie_regs { + uint64_t s2pir_el2; +} el2_s2pie_regs_t; + +typedef struct el2_gcs_regs { + uint64_t gcscr_el2; + uint64_t gcspr_el2; +} el2_gcs_regs_t; + +typedef struct el2_sysregs { + + el2_common_regs_t common; + +#if ENABLE_FEAT_MTE + el2_mte_regs_t mte; +#endif + +#if ENABLE_FEAT_FGT + el2_fgt_regs_t fgt; +#endif + +#if ENABLE_FEAT_ECV + el2_ecv_regs_t ecv; +#endif + +#if ENABLE_FEAT_VHE + el2_vhe_regs_t vhe; +#endif + +#if ENABLE_FEAT_RAS + el2_ras_regs_t ras; +#endif + +#if CTX_INCLUDE_NEVE_REGS + el2_neve_regs_t neve; +#endif + +#if ENABLE_TRF_FOR_NS + el2_trf_regs_t trf; +#endif + +#if ENABLE_FEAT_CSV2_2 + el2_csv2_regs_t csv2; +#endif + +#if ENABLE_FEAT_HCX + el2_hcx_regs_t hcx; +#endif + +#if ENABLE_FEAT_TCR2 + el2_tcr2_regs_t tcr2; +#endif + +#if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) + el2_sxpoe_regs_t sxpoe; +#endif + +#if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) + el2_sxpie_regs_t sxpie; +#endif + +#if ENABLE_FEAT_S2PIE + el2_s2pie_regs_t s2pie; +#endif + +#if ENABLE_FEAT_GCS + el2_gcs_regs_t gcs; +#endif + +} el2_sysregs_t; + +/* + * Macros to access members related to individual features of the el2_sysregs_t + * structures. + */ +#define read_el2_ctx_common(ctx, reg) (((ctx)->common).reg) + +#define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ + = (uint64_t) (val)) + +#if ENABLE_FEAT_MTE +#define read_el2_ctx_mte(ctx, reg) (((ctx)->mte).reg) +#define write_el2_ctx_mte(ctx, reg, val) ((((ctx)->mte).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_mte(ctx, reg) ULL(0) +#define write_el2_ctx_mte(ctx, reg, val) +#endif /* ENABLE_FEAT_MTE */ + +#if ENABLE_FEAT_FGT +#define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg) +#define write_el2_ctx_fgt(ctx, reg, val) ((((ctx)->fgt).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_fgt(ctx, reg) ULL(0) +#define write_el2_ctx_fgt(ctx, reg, val) +#endif /* ENABLE_FEAT_FGT */ + +#if ENABLE_FEAT_ECV +#define read_el2_ctx_ecv(ctx, reg) (((ctx)->ecv).reg) +#define write_el2_ctx_ecv(ctx, reg, val) ((((ctx)->ecv).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_ecv(ctx, reg) ULL(0) +#define write_el2_ctx_ecv(ctx, reg, val) +#endif /* ENABLE_FEAT_ECV */ + +#if ENABLE_FEAT_VHE +#define read_el2_ctx_vhe(ctx, reg) (((ctx)->vhe).reg) +#define write_el2_ctx_vhe(ctx, reg, val) ((((ctx)->vhe).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_vhe(ctx, reg) ULL(0) +#define write_el2_ctx_vhe(ctx, reg, val) +#endif /* ENABLE_FEAT_VHE */ + +#if ENABLE_FEAT_RAS +#define read_el2_ctx_ras(ctx, reg) (((ctx)->ras).reg) +#define write_el2_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_ras(ctx, reg) ULL(0) +#define write_el2_ctx_ras(ctx, reg, val) +#endif /* ENABLE_FEAT_RAS */ + +#if CTX_INCLUDE_NEVE_REGS +#define read_el2_ctx_neve(ctx, reg) (((ctx)->neve).reg) +#define write_el2_ctx_neve(ctx, reg, val) ((((ctx)->neve).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_neve(ctx, reg) ULL(0) +#define write_el2_ctx_neve(ctx, reg, val) +#endif /* CTX_INCLUDE_NEVE_REGS */ + +#if ENABLE_TRF_FOR_NS +#define read_el2_ctx_trf(ctx, reg) (((ctx)->trf).reg) +#define write_el2_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_trf(ctx, reg) ULL(0) +#define write_el2_ctx_trf(ctx, reg, val) +#endif /* ENABLE_TRF_FOR_NS */ + +#if ENABLE_FEAT_CSV2_2 +#define read_el2_ctx_csv2_2(ctx, reg) (((ctx)->csv2).reg) +#define write_el2_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_csv2_2(ctx, reg) ULL(0) +#define write_el2_ctx_csv2_2(ctx, reg, val) +#endif /* ENABLE_FEAT_CSV2_2 */ + +#if ENABLE_FEAT_HCX +#define read_el2_ctx_hcx(ctx, reg) (((ctx)->hcx).reg) +#define write_el2_ctx_hcx(ctx, reg, val) ((((ctx)->hcx).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_hcx(ctx, reg) ULL(0) +#define write_el2_ctx_hcx(ctx, reg, val) +#endif /* ENABLE_FEAT_HCX */ + +#if ENABLE_FEAT_TCR2 +#define read_el2_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) +#define write_el2_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_tcr2(ctx, reg) ULL(0) +#define write_el2_ctx_tcr2(ctx, reg, val) +#endif /* ENABLE_FEAT_TCR2 */ + +#if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) +#define read_el2_ctx_sxpoe(ctx, reg) (((ctx)->sxpoe).reg) +#define write_el2_ctx_sxpoe(ctx, reg, val) ((((ctx)->sxpoe).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_sxpoe(ctx, reg) ULL(0) +#define write_el2_ctx_sxpoe(ctx, reg, val) +#endif /*(ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) */ + +#if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) +#define read_el2_ctx_sxpie(ctx, reg) (((ctx)->sxpie).reg) +#define write_el2_ctx_sxpie(ctx, reg, val) ((((ctx)->sxpie).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_sxpie(ctx, reg) ULL(0) +#define write_el2_ctx_sxpie(ctx, reg, val) +#endif /*(ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) */ + +#if ENABLE_FEAT_S2PIE +#define read_el2_ctx_s2pie(ctx, reg) (((ctx)->s2pie).reg) +#define write_el2_ctx_s2pie(ctx, reg, val) ((((ctx)->s2pie).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_s2pie(ctx, reg) ULL(0) +#define write_el2_ctx_s2pie(ctx, reg, val) +#endif /* ENABLE_FEAT_S2PIE */ + +#if ENABLE_FEAT_GCS +#define read_el2_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) +#define write_el2_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ + = (uint64_t) (val)) +#else +#define read_el2_ctx_gcs(ctx, reg) ULL(0) +#define write_el2_ctx_gcs(ctx, reg, val) +#endif /* ENABLE_FEAT_GCS */ + +#endif /* CTX_INCLUDE_EL2_REGS */ +/******************************************************************************/ + +#endif /* __ASSEMBLER__ */ + +#endif /* CONTEXT_EL2_H */ diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index 2090687ee8..f631125f06 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,8 +34,15 @@ void cm_init_context_by_index(unsigned int cpu_idx, const struct entry_point_info *ep); void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep); void cm_prepare_el3_exit(uint32_t security_state); +void cm_prepare_el3_exit_ns(void); #ifdef __aarch64__ +#if IMAGE_BL31 +void cm_manage_extensions_el3(void); +void manage_extensions_nonsecure_per_world(void); +void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx); +#endif + #if CTX_INCLUDE_EL2_REGS void cm_el2_sysregs_context_save(uint32_t security_state); void cm_el2_sysregs_context_restore(uint32_t security_state); @@ -83,6 +90,8 @@ static inline void cm_set_next_context(void *context) #else void *cm_get_next_context(void); void cm_set_next_context(void *context); +static inline void cm_manage_extensions_el3(void) {} +static inline void manage_extensions_nonsecure_per_world(void) {} #endif /* __aarch64__ */ #endif /* CONTEXT_MGMT_H */ diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h index 54261358eb..2c7b619670 100644 --- a/include/lib/el3_runtime/cpu_data.h +++ b/include/lib/el3_runtime/cpu_data.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,16 +19,25 @@ /* 8-bytes aligned size of psci_cpu_data structure */ #define PSCI_CPU_DATA_SIZE_ALIGNED ((PSCI_CPU_DATA_SIZE + 7) & ~7) +#if ENABLE_RME +/* Size of cpu_context array */ +#define CPU_DATA_CONTEXT_NUM 3 /* Offset of cpu_ops_ptr, size 8 bytes */ +#define CPU_DATA_CPU_OPS_PTR 0x18 +#else /* ENABLE_RME */ +#define CPU_DATA_CONTEXT_NUM 2 #define CPU_DATA_CPU_OPS_PTR 0x10 +#endif /* ENABLE_RME */ #if ENABLE_PAUTH /* 8-bytes aligned offset of apiakey[2], size 16 bytes */ -#define CPU_DATA_APIAKEY_OFFSET (0x18 + PSCI_CPU_DATA_SIZE_ALIGNED) -#define CPU_DATA_CRASH_BUF_OFFSET (CPU_DATA_APIAKEY_OFFSET + 0x10) -#else -#define CPU_DATA_CRASH_BUF_OFFSET (0x18 + PSCI_CPU_DATA_SIZE_ALIGNED) -#endif /* ENABLE_PAUTH */ +#define CPU_DATA_APIAKEY_OFFSET (0x8 + PSCI_CPU_DATA_SIZE_ALIGNED \ + + CPU_DATA_CPU_OPS_PTR) +#define CPU_DATA_CRASH_BUF_OFFSET (0x10 + CPU_DATA_APIAKEY_OFFSET) +#else /* ENABLE_PAUTH */ +#define CPU_DATA_CRASH_BUF_OFFSET (0x8 + PSCI_CPU_DATA_SIZE_ALIGNED \ + + CPU_DATA_CPU_OPS_PTR) +#endif /* ENABLE_PAUTH */ /* need enough space in crash buffer to save 8 registers */ #define CPU_DATA_CRASH_BUF_SIZE 64 @@ -65,11 +74,14 @@ #ifndef __ASSEMBLER__ +#include <assert.h> +#include <stdint.h> + #include <arch_helpers.h> #include <lib/cassert.h> #include <lib/psci/psci.h> + #include <platform_def.h> -#include <stdint.h> /* Offsets for the cpu_data structure */ #define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\ @@ -80,27 +92,34 @@ (cpu_data_t, platform_cpu_data) #endif +typedef enum context_pas { + CPU_CONTEXT_SECURE = 0, + CPU_CONTEXT_NS, +#if ENABLE_RME + CPU_CONTEXT_REALM, +#endif + CPU_CONTEXT_NUM +} context_pas_t; + /******************************************************************************* * Function & variable prototypes ******************************************************************************/ /******************************************************************************* * Cache of frequently used per-cpu data: - * Pointers to non-secure and secure security state contexts + * Pointers to non-secure, realm, and secure security state contexts * Address of the crash stack * It is aligned to the cache line boundary to allow efficient concurrent * manipulation of these pointers on different cpus * - * TODO: Add other commonly used variables to this (tf_issues#90) - * * The data structure and the _cpu_data accessors should not be used directly * by components that have per-cpu members. The member access macros should be * used for this. ******************************************************************************/ typedef struct cpu_data { #ifdef __aarch64__ - void *cpu_context[2]; -#endif + void *cpu_context[CPU_DATA_CONTEXT_NUM]; +#endif /* __aarch64__ */ uintptr_t cpu_ops_ptr; struct psci_cpu_data psci_svc_cpu_data; #if ENABLE_PAUTH @@ -122,10 +141,15 @@ typedef struct cpu_data { extern cpu_data_t percpu_data[PLATFORM_CORE_COUNT]; +#ifdef __aarch64__ +CASSERT(CPU_DATA_CONTEXT_NUM == CPU_CONTEXT_NUM, + assert_cpu_data_context_num_mismatch); +#endif + #if ENABLE_PAUTH CASSERT(CPU_DATA_APIAKEY_OFFSET == __builtin_offsetof (cpu_data_t, apiakey), - assert_cpu_data_crash_stack_offset_mismatch); + assert_cpu_data_pauth_stack_offset_mismatch); #endif #if CRASH_REPORTING @@ -160,6 +184,31 @@ static inline struct cpu_data *_cpu_data(void) struct cpu_data *_cpu_data(void); #endif +/* + * Returns the index of the cpu_context array for the given security state. + * All accesses to cpu_context should be through this helper to make sure + * an access is not out-of-bounds. The function assumes security_state is + * valid. + */ +static inline context_pas_t get_cpu_context_index(uint32_t security_state) +{ + if (security_state == SECURE) { + return CPU_CONTEXT_SECURE; + } else { +#if ENABLE_RME + if (security_state == NON_SECURE) { + return CPU_CONTEXT_NS; + } else { + assert(security_state == REALM); + return CPU_CONTEXT_REALM; + } +#else + assert(security_state == NON_SECURE); + return CPU_CONTEXT_NS; +#endif + } +} + /************************************************************************** * APIs for initialising and accessing per-cpu data *************************************************************************/ diff --git a/include/lib/el3_runtime/pubsub.h b/include/lib/el3_runtime/pubsub.h index 64fe5ccb4d..cbd8ecc057 100644 --- a/include/lib/el3_runtime/pubsub.h +++ b/include/lib/el3_runtime/pubsub.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ /* For the linker ... */ #define __pubsub_start_sym(event) __pubsub_##event##_start #define __pubsub_end_sym(event) __pubsub_##event##_end -#define __pubsub_section(event) __pubsub_##event +#define __pubsub_section(event) .__pubsub_##event /* * REGISTER_PUBSUB_EVENT has a different definition between linker and compiler @@ -54,7 +54,7 @@ #define __pubsub_end_sym(event) __pubsub_##event##_end #endif -#define __pubsub_section(event) __section("__pubsub_" #event) +#define __pubsub_section(event) __section(".__pubsub_" #event) /* * In compiler context, REGISTER_PUBSUB_EVENT declares the per-event symbols diff --git a/include/lib/el3_runtime/pubsub_events.h b/include/lib/el3_runtime/pubsub_events.h index 50120826d9..d0c0502a0a 100644 --- a/include/lib/el3_runtime/pubsub_events.h +++ b/include/lib/el3_runtime/pubsub_events.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h index 3a70e4ffef..a396b99181 100644 --- a/include/lib/extensions/amu.h +++ b/include/lib/extensions/amu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,100 +10,63 @@ #include <stdbool.h> #include <stdint.h> -#include <lib/cassert.h> -#include <lib/utils_def.h> +#include <context.h> #include <platform_def.h> -/* All group 0 counters */ -#define AMU_GROUP0_COUNTERS_MASK U(0xf) -#define AMU_GROUP0_NR_COUNTERS U(4) - -#ifdef PLAT_AMU_GROUP1_COUNTERS_MASK -#define AMU_GROUP1_COUNTERS_MASK PLAT_AMU_GROUP1_COUNTERS_MASK +#if ENABLE_FEAT_AMU +#if __aarch64__ +void amu_enable(cpu_context_t *ctx); +void amu_init_el3(void); +void amu_init_el2_unused(void); +void amu_enable_per_world(per_world_context_t *per_world_ctx); #else -#define AMU_GROUP1_COUNTERS_MASK U(0) -#endif +void amu_enable(bool el2_unused); +#endif /* __aarch64__ */ -/* Calculate number of group 1 counters */ -#if (AMU_GROUP1_COUNTERS_MASK & (1 << 15)) -#define AMU_GROUP1_NR_COUNTERS 16U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14)) -#define AMU_GROUP1_NR_COUNTERS 15U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13)) -#define AMU_GROUP1_NR_COUNTERS 14U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12)) -#define AMU_GROUP1_NR_COUNTERS 13U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11)) -#define AMU_GROUP1_NR_COUNTERS 12U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10)) -#define AMU_GROUP1_NR_COUNTERS 11U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9)) -#define AMU_GROUP1_NR_COUNTERS 10U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8)) -#define AMU_GROUP1_NR_COUNTERS 9U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7)) -#define AMU_GROUP1_NR_COUNTERS 8U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6)) -#define AMU_GROUP1_NR_COUNTERS 7U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5)) -#define AMU_GROUP1_NR_COUNTERS 6U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4)) -#define AMU_GROUP1_NR_COUNTERS 5U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3)) -#define AMU_GROUP1_NR_COUNTERS 4U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2)) -#define AMU_GROUP1_NR_COUNTERS 3U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1)) -#define AMU_GROUP1_NR_COUNTERS 2U -#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0)) -#define AMU_GROUP1_NR_COUNTERS 1U #else -#define AMU_GROUP1_NR_COUNTERS 0U -#endif - -CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask); - -struct amu_ctx { - uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS]; #if __aarch64__ - /* Architected event counter 1 does not have an offset register. */ - uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1]; -#endif +void amu_enable(cpu_context_t *ctx) +{ +} +void amu_init_el3(void) +{ +} +void amu_init_el2_unused(void) +{ +} +void amu_enable_per_world(per_world_context_t *per_world_ctx) +{ +} +#else +static inline void amu_enable(bool el2_unused) +{ +} +#endif /*__aarch64__ */ +#endif /* ENABLE_FEAT_AMU */ -#if AMU_GROUP1_NR_COUNTERS - uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS]; -#if __aarch64__ - uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS]; -#endif -#endif +#if ENABLE_AMU_AUXILIARY_COUNTERS +/* + * AMU data for a single core. + */ +struct amu_core { + uint16_t enable; /* Mask of auxiliary counters to enable */ }; -unsigned int amu_get_version(void); -void amu_enable(bool el2_unused); - -/* Group 0 configuration helpers */ -uint64_t amu_group0_cnt_read(unsigned int idx); -void amu_group0_cnt_write(unsigned int idx, uint64_t val); - -#if __aarch64__ -uint64_t amu_group0_voffset_read(unsigned int idx); -void amu_group0_voffset_write(unsigned int idx, uint64_t val); -#endif - -#if AMU_GROUP1_NR_COUNTERS -bool amu_group1_supported(void); - -/* Group 1 configuration helpers */ -uint64_t amu_group1_cnt_read(unsigned int idx); -void amu_group1_cnt_write(unsigned int idx, uint64_t val); -void amu_group1_set_evtype(unsigned int idx, unsigned int val); - -#if __aarch64__ -uint64_t amu_group1_voffset_read(unsigned int idx); -void amu_group1_voffset_write(unsigned int idx, uint64_t val); -#endif +/* + * Topological platform data specific to the AMU. + */ +struct amu_topology { + struct amu_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */ +}; -#endif +#if !ENABLE_AMU_FCONF +/* + * Retrieve the platform's AMU topology. A `NULL` return value is treated as a + * non-fatal error, in which case no auxiliary counters will be enabled. + */ +const struct amu_topology *plat_amu_topology(void); +#endif /* ENABLE_AMU_FCONF */ +#endif /* ENABLE_AMU_AUXILIARY_COUNTERS */ #endif /* AMU_H */ diff --git a/include/lib/extensions/amu_private.h b/include/lib/extensions/amu_private.h deleted file mode 100644 index 3b4b47ca3a..0000000000 --- a/include/lib/extensions/amu_private.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AMU_PRIVATE_H -#define AMU_PRIVATE_H - -#include <stdint.h> - -uint64_t amu_group0_cnt_read_internal(unsigned int idx); -void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val); - -uint64_t amu_group1_cnt_read_internal(unsigned int idx); -void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val); -void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val); - -#if __aarch64__ -uint64_t amu_group0_voffset_read_internal(unsigned int idx); -void amu_group0_voffset_write_internal(unsigned int idx, uint64_t val); - -uint64_t amu_group1_voffset_read_internal(unsigned int idx); -void amu_group1_voffset_write_internal(unsigned int idx, uint64_t val); -#endif - -#endif /* AMU_PRIVATE_H */ diff --git a/include/lib/extensions/brbe.h b/include/lib/extensions/brbe.h new file mode 100644 index 0000000000..194efba703 --- /dev/null +++ b/include/lib/extensions/brbe.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BRBE_H +#define BRBE_H + +#if ENABLE_BRBE_FOR_NS +void brbe_init_el3(void); +#else +static inline void brbe_init_el3(void) +{ +} +#endif /* ENABLE_BRBE_FOR_NS */ + +#endif /* BRBE_H */ diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h index ac8c00a43b..3dd5652651 100644 --- a/include/lib/extensions/mpam.h +++ b/include/lib/extensions/mpam.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,18 @@ #include <stdbool.h> -bool mpam_supported(void); -void mpam_enable(bool el2_unused); +#include <context.h> + +#if ENABLE_FEAT_MPAM +void mpam_enable_per_world(per_world_context_t *per_world_ctx); +void mpam_init_el2_unused(void); +#else +static inline void mpam_enable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void mpam_init_el2_unused(void) +{ +} +#endif /* ENABLE_FEAT_MPAM */ #endif /* MPAM_H */ diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h index 2e780dec2a..dbc22267b5 100644 --- a/include/lib/extensions/pauth.h +++ b/include/lib/extensions/pauth.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/extensions/pmuv3.h b/include/lib/extensions/pmuv3.h new file mode 100644 index 0000000000..62fee7b60c --- /dev/null +++ b/include/lib/extensions/pmuv3.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMUV3_H +#define PMUV3_H + +#include <context.h> + +void pmuv3_init_el3(void); + +#ifdef __aarch64__ +void pmuv3_enable(cpu_context_t *ctx); +void pmuv3_init_el2_unused(void); +#endif /* __aarch64__ */ + +#endif /* PMUV3_H */ diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h index 793ab9fac6..6997da0335 100644 --- a/include/lib/extensions/ras.h +++ b/include/lib/extensions/ras.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h index 55760b06b6..e0aee50e6e 100644 --- a/include/lib/extensions/ras_arch.h +++ b/include/lib/extensions/ras_arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/include/lib/extensions/sme.h b/include/lib/extensions/sme.h new file mode 100644 index 0000000000..bd7948e63a --- /dev/null +++ b/include/lib/extensions/sme.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SME_H +#define SME_H + +#include <stdbool.h> +#include <context.h> + +/* + * Maximum value of LEN field in SMCR_ELx. This is different than the maximum + * supported value which is platform dependent. In the first version of SME the + * LEN field is limited to 4 bits but will be expanded in future iterations. + * To support different versions, the code that discovers the supported vector + * lengths will write the max value into SMCR_ELx then read it back to see how + * many bits are implemented. + */ +#define SME_SMCR_LEN_MAX U(0x1FF) + +#if ENABLE_SME_FOR_NS +void sme_init_el3(void); +void sme_init_el2_unused(void); +void sme_enable(cpu_context_t *context); +void sme_disable(cpu_context_t *context); +void sme_enable_per_world(per_world_context_t *per_world_ctx); +void sme_disable_per_world(per_world_context_t *per_world_ctx); +#else +static inline void sme_init_el3(void) +{ +} +static inline void sme_init_el2_unused(void) +{ +} +static inline void sme_enable(cpu_context_t *context) +{ +} +static inline void sme_disable(cpu_context_t *context) +{ +} +static inline void sme_enable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void sme_disable_per_world(per_world_context_t *per_world_ctx) +{ +} +#endif /* ENABLE_SME_FOR_NS */ + +#endif /* SME_H */ diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h index d4b925fe4f..7b390378c3 100644 --- a/include/lib/extensions/spe.h +++ b/include/lib/extensions/spe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,20 @@ #include <stdbool.h> -bool spe_supported(void); -void spe_enable(bool el2_unused); +#if ENABLE_SPE_FOR_NS +void spe_init_el3(void); +void spe_init_el2_unused(void); void spe_disable(void); +#else +static inline void spe_init_el3(void) +{ +} +static inline void spe_init_el2_unused(void) +{ +} +static inline void spe_disable(void) +{ +} +#endif /* ENABLE_SPE_FOR_NS */ #endif /* SPE_H */ diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h index 83df1775e5..947c905bd0 100644 --- a/include/lib/extensions/sve.h +++ b/include/lib/extensions/sve.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,9 +7,22 @@ #ifndef SVE_H #define SVE_H -#include <stdbool.h> +#include <context.h> -bool sve_supported(void); -void sve_enable(bool el2_unused); +#if (ENABLE_SME_FOR_NS || ENABLE_SVE_FOR_NS) +void sve_init_el2_unused(void); +void sve_enable_per_world(per_world_context_t *per_world_ctx); +void sve_disable_per_world(per_world_context_t *per_world_ctx); +#else +static inline void sve_init_el2_unused(void) +{ +} +static inline void sve_enable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void sve_disable_per_world(per_world_context_t *per_world_ctx) +{ +} +#endif /* ( ENABLE_SME_FOR_NS | ENABLE_SVE_FOR_NS ) */ #endif /* SVE_H */ diff --git a/include/lib/extensions/sys_reg_trace.h b/include/lib/extensions/sys_reg_trace.h new file mode 100644 index 0000000000..7004267178 --- /dev/null +++ b/include/lib/extensions/sys_reg_trace.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SYS_REG_TRACE_H +#define SYS_REG_TRACE_H + +#include <context.h> + +#if ENABLE_SYS_REG_TRACE_FOR_NS + +#if __aarch64__ +void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx); +void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx); +void sys_reg_trace_init_el2_unused(void); +#else +void sys_reg_trace_init_el3(void); +#endif /* __aarch64__ */ + +#else /* !ENABLE_SYS_REG_TRACE_FOR_NS */ + +#if __aarch64__ +static inline void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void sys_reg_trace_init_el2_unused(void) +{ +} +#else +static inline void sys_reg_trace_init_el3(void) +{ +} +#endif /* __aarch64__ */ + +#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ + +#endif /* SYS_REG_TRACE_H */ diff --git a/include/lib/extensions/trbe.h b/include/lib/extensions/trbe.h new file mode 100644 index 0000000000..0bed433722 --- /dev/null +++ b/include/lib/extensions/trbe.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRBE_H +#define TRBE_H + +#if ENABLE_TRBE_FOR_NS +void trbe_init_el3(void); +void trbe_init_el2_unused(void); +#else +static inline void trbe_init_el3(void) +{ +} +static inline void trbe_init_el2_unused(void) +{ +} +#endif /* ENABLE_TRBE_FOR_NS */ + +#endif /* TRBE_H */ diff --git a/include/lib/extensions/trf.h b/include/lib/extensions/trf.h new file mode 100644 index 0000000000..1ac7cda4b4 --- /dev/null +++ b/include/lib/extensions/trf.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRF_H +#define TRF_H + +#if ENABLE_TRF_FOR_NS +void trf_init_el3(void); +void trf_init_el2_unused(void); +#else +static inline void trf_init_el3(void) +{ +} +static inline void trf_init_el2_unused(void) +{ +} +#endif /* ENABLE_TRF_FOR_NS */ + +#endif /* TRF_H */ diff --git a/include/lib/extensions/twed.h b/include/lib/extensions/twed.h deleted file mode 100644 index eac4aa3149..0000000000 --- a/include/lib/extensions/twed.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TWED_H -#define TWED_H - -#include <stdint.h> - -#define TWED_DISABLED U(0xFFFFFFFF) - -uint32_t plat_arm_set_twedel_scr_el3(void); - -#endif /* TWEDE_H */ diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h index 917e053bd5..5b54c049a8 100644 --- a/include/lib/fconf/fconf.h +++ b/include/lib/fconf/fconf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef FCONF_H #define FCONF_H +#include <stddef.h> #include <stdint.h> /* Public API */ @@ -20,7 +21,7 @@ */ #define FCONF_REGISTER_POPULATOR(config, name, callback) \ __attribute__((used, section(".fconf_populator"))) \ - const struct fconf_populator (name##__populator) = { \ + static const struct fconf_populator (name##__populator) = { \ .config_type = (#config), \ .info = (#name), \ .populate = (callback) \ diff --git a/include/lib/fconf/fconf_amu_getter.h b/include/lib/fconf/fconf_amu_getter.h new file mode 100644 index 0000000000..2faee73b4b --- /dev/null +++ b/include/lib/fconf/fconf_amu_getter.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_AMU_GETTER_H +#define FCONF_AMU_GETTER_H + +#include <lib/extensions/amu.h> + +#define amu__config_getter(id) fconf_amu_config.id + +struct fconf_amu_config { + const struct amu_topology *topology; +}; + +extern struct fconf_amu_config fconf_amu_config; + +#endif /* FCONF_AMU_GETTER_H */ diff --git a/include/lib/fconf/fconf_dyn_cfg_getter.h b/include/lib/fconf/fconf_dyn_cfg_getter.h index 6f8da0d787..35546734d5 100644 --- a/include/lib/fconf/fconf_dyn_cfg_getter.h +++ b/include/lib/fconf/fconf_dyn_cfg_getter.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,8 @@ #include <lib/fconf/fconf.h> +#define FCONF_INVALID_IDX 0xFFFFFFFFU + /* Dynamic configuration related getter */ #define dyn_cfg__dtb_getter(id) dyn_cfg_dtb_info_getter(id) @@ -16,13 +18,21 @@ struct dyn_cfg_dtb_info_t { uintptr_t config_addr; uint32_t config_max_size; unsigned int config_id; + /* + * A platform uses this address to copy the configuration + * to another location during the boot-flow. + * - e.g. HW_CONFIG + */ + uintptr_t secondary_config_addr; }; +unsigned int dyn_cfg_dtb_info_get_index(unsigned int config_id); struct dyn_cfg_dtb_info_t *dyn_cfg_dtb_info_getter(unsigned int config_id); int fconf_populate_dtb_registry(uintptr_t config); /* Set config information in global DTB array */ -void set_config_info(uintptr_t config_addr, uint32_t config_max_size, - unsigned int config_id); +void set_config_info(uintptr_t config_addr, uintptr_t secondary_config_addr, + uint32_t config_max_size, + unsigned int config_id); #endif /* FCONF_DYN_CFG_GETTER_H */ diff --git a/include/lib/fconf/fconf_mpmm_getter.h b/include/lib/fconf/fconf_mpmm_getter.h new file mode 100644 index 0000000000..50d991a2fd --- /dev/null +++ b/include/lib/fconf/fconf_mpmm_getter.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_MPMM_GETTER_H +#define FCONF_MPMM_GETTER_H + +#include <lib/mpmm/mpmm.h> + +#define mpmm__config_getter(id) fconf_mpmm_config.id + +struct fconf_mpmm_config { + const struct mpmm_topology *topology; +}; + +extern struct fconf_mpmm_config fconf_mpmm_config; + +#endif /* FCONF_MPMM_GETTER_H */ diff --git a/include/lib/fconf/fconf_tbbr_getter.h b/include/lib/fconf/fconf_tbbr_getter.h index 6066af6df6..541a396a85 100644 --- a/include/lib/fconf/fconf_tbbr_getter.h +++ b/include/lib/fconf/fconf_tbbr_getter.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,9 +23,6 @@ struct tbbr_dyn_config_t { uint32_t disable_auth; void *mbedtls_heap_addr; size_t mbedtls_heap_size; -#if MEASURED_BOOT - uint8_t bl2_hash_data[TCG_DIGEST_SIZE]; -#endif }; extern struct tbbr_dyn_config_t tbbr_dyn_config; diff --git a/include/lib/gpt_rme/gpt_rme.h b/include/lib/gpt_rme/gpt_rme.h new file mode 100644 index 0000000000..94a88b0d5b --- /dev/null +++ b/include/lib/gpt_rme/gpt_rme.h @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GPT_RME_H +#define GPT_RME_H + +#include <stdint.h> + +#include <arch.h> + +/******************************************************************************/ +/* GPT helper macros and definitions */ +/******************************************************************************/ + +/* + * Structure for specifying a mapping range and it's properties. This should not + * be manually initialized, using the MAP_GPT_REGION_x macros is recommended as + * to avoid potential incompatibilities in the future. + */ +typedef struct pas_region { + uintptr_t base_pa; /* Base address for PAS. */ + size_t size; /* Size of the PAS. */ + unsigned int attrs; /* PAS GPI and entry type. */ +} pas_region_t; + +/* GPT GPI definitions */ +#define GPT_GPI_NO_ACCESS U(0x0) +#define GPT_GPI_SECURE U(0x8) +#define GPT_GPI_NS U(0x9) +#define GPT_GPI_ROOT U(0xA) +#define GPT_GPI_REALM U(0xB) +#define GPT_GPI_ANY U(0xF) +#define GPT_GPI_VAL_MASK UL(0xF) + +#define GPT_NSE_SECURE U(0b00) +#define GPT_NSE_ROOT U(0b01) +#define GPT_NSE_NS U(0b10) +#define GPT_NSE_REALM U(0b11) + +#define GPT_NSE_SHIFT U(62) + +/* PAS attribute GPI definitions. */ +#define GPT_PAS_ATTR_GPI_SHIFT U(0) +#define GPT_PAS_ATTR_GPI_MASK U(0xF) +#define GPT_PAS_ATTR_GPI(_attrs) (((_attrs) \ + >> GPT_PAS_ATTR_GPI_SHIFT) \ + & GPT_PAS_ATTR_GPI_MASK) + +/* PAS attribute mapping type definitions */ +#define GPT_PAS_ATTR_MAP_TYPE_BLOCK U(0x0) +#define GPT_PAS_ATTR_MAP_TYPE_GRANULE U(0x1) +#define GPT_PAS_ATTR_MAP_TYPE_SHIFT U(4) +#define GPT_PAS_ATTR_MAP_TYPE_MASK U(0x1) +#define GPT_PAS_ATTR_MAP_TYPE(_attrs) (((_attrs) \ + >> GPT_PAS_ATTR_MAP_TYPE_SHIFT) \ + & GPT_PAS_ATTR_MAP_TYPE_MASK) + +/* + * Macro to initialize the attributes field in the pas_region_t structure. + * [31:5] Reserved + * [4] Mapping type (GPT_PAS_ATTR_MAP_TYPE_x definitions) + * [3:0] PAS GPI type (GPT_GPI_x definitions) + */ +#define GPT_PAS_ATTR(_type, _gpi) \ + ((((_type) & GPT_PAS_ATTR_MAP_TYPE_MASK) \ + << GPT_PAS_ATTR_MAP_TYPE_SHIFT) | \ + (((_gpi) & GPT_PAS_ATTR_GPI_MASK) \ + << GPT_PAS_ATTR_GPI_SHIFT)) + +/* + * Macro to create a GPT entry for this PAS range as a block descriptor. If this + * region does not fit the requirements for a block descriptor then GPT + * initialization will fail. + */ +#define GPT_MAP_REGION_BLOCK(_pa, _sz, _gpi) \ + { \ + .base_pa = (_pa), \ + .size = (_sz), \ + .attrs = GPT_PAS_ATTR(GPT_PAS_ATTR_MAP_TYPE_BLOCK, (_gpi)), \ + } + +/* + * Macro to create a GPT entry for this PAS range as a table descriptor. If this + * region does not fit the requirements for a table descriptor then GPT + * initialization will fail. + */ +#define GPT_MAP_REGION_GRANULE(_pa, _sz, _gpi) \ + { \ + .base_pa = (_pa), \ + .size = (_sz), \ + .attrs = GPT_PAS_ATTR(GPT_PAS_ATTR_MAP_TYPE_GRANULE, (_gpi)), \ + } + +/******************************************************************************/ +/* GPT register field definitions */ +/******************************************************************************/ + +/* + * Least significant address bits protected by each entry in level 0 GPT. This + * field is read-only. + */ +#define GPCCR_L0GPTSZ_SHIFT U(20) +#define GPCCR_L0GPTSZ_MASK U(0xF) + +typedef enum { + GPCCR_L0GPTSZ_30BITS = U(0x0), + GPCCR_L0GPTSZ_34BITS = U(0x4), + GPCCR_L0GPTSZ_36BITS = U(0x6), + GPCCR_L0GPTSZ_39BITS = U(0x9) +} gpccr_l0gptsz_e; + +/* Granule protection check priority bit definitions */ +#define GPCCR_GPCP_SHIFT U(17) +#define GPCCR_GPCP_BIT (ULL(1) << GPCCR_EL3_GPCP_SHIFT) + +/* Granule protection check bit definitions */ +#define GPCCR_GPC_SHIFT U(16) +#define GPCCR_GPC_BIT (ULL(1) << GPCCR_GPC_SHIFT) + +/* Physical granule size bit definitions */ +#define GPCCR_PGS_SHIFT U(14) +#define GPCCR_PGS_MASK U(0x3) +#define SET_GPCCR_PGS(x) (((x) & GPCCR_PGS_MASK) << GPCCR_PGS_SHIFT) + +typedef enum { + GPCCR_PGS_4K = U(0x0), + GPCCR_PGS_64K = U(0x1), + GPCCR_PGS_16K = U(0x2) +} gpccr_pgs_e; + +/* GPT fetch shareability attribute bit definitions */ +#define GPCCR_SH_SHIFT U(12) +#define GPCCR_SH_MASK U(0x3) +#define SET_GPCCR_SH(x) (((x) & GPCCR_SH_MASK) << GPCCR_SH_SHIFT) + +typedef enum { + GPCCR_SH_NS = U(0x0), + GPCCR_SH_OS = U(0x2), + GPCCR_SH_IS = U(0x3) +} gpccr_sh_e; + +/* GPT fetch outer cacheability attribute bit definitions */ +#define GPCCR_ORGN_SHIFT U(10) +#define GPCCR_ORGN_MASK U(0x3) +#define SET_GPCCR_ORGN(x) (((x) & GPCCR_ORGN_MASK) << GPCCR_ORGN_SHIFT) + +typedef enum { + GPCCR_ORGN_NC = U(0x0), + GPCCR_ORGN_WB_RA_WA = U(0x1), + GPCCR_ORGN_WT_RA_NWA = U(0x2), + GPCCR_ORGN_WB_RA_NWA = U(0x3) +} gpccr_orgn_e; + +/* GPT fetch inner cacheability attribute bit definitions */ +#define GPCCR_IRGN_SHIFT U(8) +#define GPCCR_IRGN_MASK U(0x3) +#define SET_GPCCR_IRGN(x) (((x) & GPCCR_IRGN_MASK) << GPCCR_IRGN_SHIFT) + +typedef enum { + GPCCR_IRGN_NC = U(0x0), + GPCCR_IRGN_WB_RA_WA = U(0x1), + GPCCR_IRGN_WT_RA_NWA = U(0x2), + GPCCR_IRGN_WB_RA_NWA = U(0x3) +} gpccr_irgn_e; + +/* Protected physical address size bit definitions */ +#define GPCCR_PPS_SHIFT U(0) +#define GPCCR_PPS_MASK U(0x7) +#define SET_GPCCR_PPS(x) (((x) & GPCCR_PPS_MASK) << GPCCR_PPS_SHIFT) + +typedef enum { + GPCCR_PPS_4GB = U(0x0), + GPCCR_PPS_64GB = U(0x1), + GPCCR_PPS_1TB = U(0x2), + GPCCR_PPS_4TB = U(0x3), + GPCCR_PPS_16TB = U(0x4), + GPCCR_PPS_256TB = U(0x5), + GPCCR_PPS_4PB = U(0x6) +} gpccr_pps_e; + +/* Base Address for the GPT bit definitions */ +#define GPTBR_BADDR_SHIFT U(0) +#define GPTBR_BADDR_VAL_SHIFT U(12) +#define GPTBR_BADDR_MASK ULL(0xffffffffff) + +/******************************************************************************/ +/* GPT public APIs */ +/******************************************************************************/ + +/* + * Public API that initializes the entire protected space to GPT_GPI_ANY using + * the L0 tables (block descriptors). Ideally, this function is invoked prior + * to DDR discovery and initialization. The MMU must be initialized before + * calling this function. + * + * Parameters + * pps PPS value to use for table generation + * l0_mem_base Base address of L0 tables in memory. + * l0_mem_size Total size of memory available for L0 tables. + * + * Return + * Negative Linux error code in the event of a failure, 0 for success. + */ +int gpt_init_l0_tables(gpccr_pps_e pps, + uintptr_t l0_mem_base, + size_t l0_mem_size); + +/* + * Public API that carves out PAS regions from the L0 tables and builds any L1 + * tables that are needed. This function ideally is run after DDR discovery and + * initialization. The L0 tables must have already been initialized to GPI_ANY + * when this function is called. + * + * Parameters + * pgs PGS value to use for table generation. + * l1_mem_base Base address of memory used for L1 tables. + * l1_mem_size Total size of memory available for L1 tables. + * *pas_regions Pointer to PAS regions structure array. + * pas_count Total number of PAS regions. + * + * Return + * Negative Linux error code in the event of a failure, 0 for success. + */ +int gpt_init_pas_l1_tables(gpccr_pgs_e pgs, + uintptr_t l1_mem_base, + size_t l1_mem_size, + pas_region_t *pas_regions, + unsigned int pas_count); + +/* + * Public API to initialize the runtime gpt_config structure based on the values + * present in the GPTBR_EL3 and GPCCR_EL3 registers. GPT initialization + * typically happens in a bootloader stage prior to setting up the EL3 runtime + * environment for the granule transition service so this function detects the + * initialization from a previous stage. Granule protection checks must be + * enabled already or this function will return an error. + * + * Return + * Negative Linux error code in the event of a failure, 0 for success. + */ +int gpt_runtime_init(void); + +/* + * Public API to enable granule protection checks once the tables have all been + * initialized. This function is called at first initialization and then again + * later during warm boots of CPU cores. + * + * Return + * Negative Linux error code in the event of a failure, 0 for success. + */ +int gpt_enable(void); + +/* + * Public API to disable granule protection checks. + */ +void gpt_disable(void); + +/* + * This function is the core of the granule transition service. When a granule + * transition request occurs it is routed to this function where the request is + * validated then fulfilled if possible. + * + * TODO: implement support for transitioning multiple granules at once. + * + * Parameters + * base: Base address of the region to transition, must be aligned to granule + * size. + * size: Size of region to transition, must be aligned to granule size. + * src_sec_state: Security state of the originating SMC invoking the API. + * + * Return + * Negative Linux error code in the event of a failure, 0 for success. + */ +int gpt_delegate_pas(uint64_t base, size_t size, unsigned int src_sec_state); +int gpt_undelegate_pas(uint64_t base, size_t size, unsigned int src_sec_state); + +#endif /* GPT_RME_H */ diff --git a/include/lib/libc/aarch32/endian_.h b/include/lib/libc/aarch32/endian_.h index 0cf2c755f2..edca4966f8 100644 --- a/include/lib/libc/aarch32/endian_.h +++ b/include/lib/libc/aarch32/endian_.h @@ -32,7 +32,7 @@ * $FreeBSD$ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/aarch32/float.h b/include/lib/libc/aarch32/float.h new file mode 100644 index 0000000000..857d76ea57 --- /dev/null +++ b/include/lib/libc/aarch32/float.h @@ -0,0 +1,100 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)float.h 7.1 (Berkeley) 5/8/90 + * $FreeBSD$ + */ + +#ifndef _MACHINE_FLOAT_H_ +#define _MACHINE_FLOAT_H_ 1 + +#include <sys/cdefs.h> + +__BEGIN_DECLS +extern int __flt_rounds(void); +__END_DECLS + +#define FLT_RADIX 2 /* b */ +#ifndef _ARM_HARD_FLOAT +#define FLT_ROUNDS __flt_rounds() +#else +#define FLT_ROUNDS (-1) +#endif +#if __ISO_C_VISIBLE >= 1999 +#define FLT_EVAL_METHOD 0 +#define DECIMAL_DIG 17 /* max precision in decimal digits */ +#endif + +#define FLT_MANT_DIG 24 /* p */ +#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ +#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ +#define FLT_MIN_EXP (-125) /* emin */ +#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ +#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ +#define FLT_MAX_EXP 128 /* emax */ +#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ +#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ +#if __ISO_C_VISIBLE >= 2011 +#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ +#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ +#define FLT_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define DBL_MANT_DIG 53 +#define DBL_EPSILON 2.2204460492503131E-16 +#define DBL_DIG 15 +#define DBL_MIN_EXP (-1021) +#define DBL_MIN 2.2250738585072014E-308 +#define DBL_MIN_10_EXP (-307) +#define DBL_MAX_EXP 1024 +#define DBL_MAX 1.7976931348623157E+308 +#define DBL_MAX_10_EXP 308 +#if __ISO_C_VISIBLE >= 2011 +#define DBL_TRUE_MIN 4.9406564584124654E-324 +#define DBL_DECIMAL_DIG 17 +#define DBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define LDBL_MANT_DIG DBL_MANT_DIG +#define LDBL_EPSILON ((long double)DBL_EPSILON) +#define LDBL_DIG DBL_DIG +#define LDBL_MIN_EXP DBL_MIN_EXP +#define LDBL_MIN ((long double)DBL_MIN) +#define LDBL_MIN_10_EXP DBL_MIN_10_EXP +#define LDBL_MAX_EXP DBL_MAX_EXP +#define LDBL_MAX ((long double)DBL_MAX) +#define LDBL_MAX_10_EXP DBL_MAX_10_EXP +#if __ISO_C_VISIBLE >= 2011 +#define LDBL_TRUE_MIN ((long double)DBL_TRUE_MIN) +#define LDBL_DECIMAL_DIG DBL_DECIMAL_DIG +#define LDBL_HAS_SUBNORM DBL_HAS_SUBNORM +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#endif /* _MACHINE_FLOAT_H_ */ diff --git a/include/lib/libc/aarch32/inttypes_.h b/include/lib/libc/aarch32/inttypes_.h new file mode 100644 index 0000000000..0888bf0066 --- /dev/null +++ b/include/lib/libc/aarch32/inttypes_.h @@ -0,0 +1,28 @@ +/* + * Copyright 2020 Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* + * Portions copyright (c) 2020, Arm Limited and Contributors. + * All rights reserved. + */ + +#ifndef INTTYPES__H +#define INTTYPES__H + +#define PRId64 "lld" /* int64_t */ +#define PRIi64 "lli" /* int64_t */ +#define PRIo64 "llo" /* int64_t */ +#define PRIu64 "llu" /* uint64_t */ +#define PRIx64 "llx" /* uint64_t */ +#define PRIX64 "llX" /* uint64_t */ + +#define PRIdPTR "d" /* intptr_t */ +#define PRIiPTR "i" /* intptr_t */ +#define PRIoPTR "o" /* intptr_t */ +#define PRIuPTR "u" /* uintptr_t */ +#define PRIxPTR "x" /* uintptr_t */ +#define PRIXPTR "X" /* uintptr_t */ + +#endif /* INTTYPES__H */ diff --git a/include/lib/libc/aarch32/limits_.h b/include/lib/libc/aarch32/limits_.h index 26cec1723a..5b0516a826 100644 --- a/include/lib/libc/aarch32/limits_.h +++ b/include/lib/libc/aarch32/limits_.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #define SCHAR_MAX 0x7F -#define SCHAR_MIN (-SCHAR_MIN - 1) +#define SCHAR_MIN (-SCHAR_MAX - 1) #define CHAR_MAX 0x7F #define CHAR_MIN (-CHAR_MAX - 1) #define UCHAR_MAX 0xFFU diff --git a/include/lib/libc/aarch32/stddef_.h b/include/lib/libc/aarch32/stddef_.h index 36dc20bd40..14ed094c8d 100644 --- a/include/lib/libc/aarch32/stddef_.h +++ b/include/lib/libc/aarch32/stddef_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h new file mode 100644 index 0000000000..6e2deedc98 --- /dev/null +++ b/include/lib/libc/aarch32/stdint_.h @@ -0,0 +1,28 @@ +/* + * Copyright 2020 Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* + * Portions copyright (c) 2020, Arm Limited and Contributors. + * All rights reserved. + */ + +#ifndef STDINT__H +#define STDINT__H + +#define INT64_MAX LLONG_MAX +#define INT64_MIN LLONG_MIN +#define UINT64_MAX ULLONG_MAX + +#define INT64_C(x) x ## LL +#define UINT64_C(x) x ## ULL + +typedef long long int64_t; +typedef unsigned long long uint64_t; +typedef long long int64_least_t; +typedef unsigned long long uint64_least_t; +typedef long long int64_fast_t; +typedef unsigned long long uint64_fast_t; + +#endif diff --git a/include/lib/libc/aarch32/stdio_.h b/include/lib/libc/aarch32/stdio_.h index 5e49425cbb..7042664c04 100644 --- a/include/lib/libc/aarch32/stdio_.h +++ b/include/lib/libc/aarch32/stdio_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/libc/aarch64/endian_.h b/include/lib/libc/aarch64/endian_.h index 7c79fd43bf..58273d784d 100644 --- a/include/lib/libc/aarch64/endian_.h +++ b/include/lib/libc/aarch64/endian_.h @@ -32,7 +32,7 @@ * $FreeBSD$ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/aarch64/float.h b/include/lib/libc/aarch64/float.h new file mode 100644 index 0000000000..0829f6f52a --- /dev/null +++ b/include/lib/libc/aarch64/float.h @@ -0,0 +1,94 @@ +/*- + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)float.h 7.1 (Berkeley) 5/8/90 + * $FreeBSD$ + */ + +#ifndef _MACHINE_FLOAT_H_ +#define _MACHINE_FLOAT_H_ + +#include <sys/cdefs.h> + +__BEGIN_DECLS +extern int __flt_rounds(void); +__END_DECLS + +#define FLT_RADIX 2 /* b */ +#define FLT_ROUNDS __flt_rounds() +#if __ISO_C_VISIBLE >= 1999 +#define FLT_EVAL_METHOD 0 +#define DECIMAL_DIG 17 /* max precision in decimal digits */ +#endif + +#define FLT_MANT_DIG 24 /* p */ +#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ +#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ +#define FLT_MIN_EXP (-125) /* emin */ +#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ +#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ +#define FLT_MAX_EXP 128 /* emax */ +#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ +#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ +#if __ISO_C_VISIBLE >= 2011 +#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ +#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ +#define FLT_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define DBL_MANT_DIG 53 +#define DBL_EPSILON 2.2204460492503131E-16 +#define DBL_DIG 15 +#define DBL_MIN_EXP (-1021) +#define DBL_MIN 2.2250738585072014E-308 +#define DBL_MIN_10_EXP (-307) +#define DBL_MAX_EXP 1024 +#define DBL_MAX 1.7976931348623157E+308 +#define DBL_MAX_10_EXP 308 +#if __ISO_C_VISIBLE >= 2011 +#define DBL_TRUE_MIN 4.9406564584124654E-324 +#define DBL_DECIMAL_DIG 17 +#define DBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define LDBL_MANT_DIG 113 +#define LDBL_EPSILON 1.925929944387235853055977942584927319E-34L +#define LDBL_DIG 33 +#define LDBL_MIN_EXP (-16381) +#define LDBL_MIN 3.362103143112093506262677817321752603E-4932L +#define LDBL_MIN_10_EXP (-4931) +#define LDBL_MAX_EXP (+16384) +#define LDBL_MAX 1.189731495357231765085759326628007016E+4932L +#define LDBL_MAX_10_EXP (+4932) +#if __ISO_C_VISIBLE >= 2011 +#define LDBL_TRUE_MIN 6.475175119438025110924438958227646552E-4966L +#define LDBL_DECIMAL_DIG 36 +#define LDBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#endif /* _MACHINE_FLOAT_H_ */ diff --git a/include/lib/libc/aarch64/inttypes_.h b/include/lib/libc/aarch64/inttypes_.h new file mode 100644 index 0000000000..61090842ea --- /dev/null +++ b/include/lib/libc/aarch64/inttypes_.h @@ -0,0 +1,28 @@ +/* + * Copyright 2020 Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* + * Portions copyright (c) 2020, Arm Limited and Contributors. + * All rights reserved. + */ + +#ifndef INTTYPES__H +#define INTTYPES__H + +#define PRId64 "ld" /* int64_t */ +#define PRIi64 "li" /* int64_t */ +#define PRIo64 "lo" /* int64_t */ +#define PRIu64 "lu" /* uint64_t */ +#define PRIx64 "lx" /* uint64_t */ +#define PRIX64 "lX" /* uint64_t */ + +#define PRIdPTR "ld" /* intptr_t */ +#define PRIiPTR "li" /* intptr_t */ +#define PRIoPTR "lo" /* intptr_t */ +#define PRIuPTR "lu" /* uintptr_t */ +#define PRIxPTR "lx" /* uintptr_t */ +#define PRIXPTR "lX" /* uintptr_t */ + +#endif /* INTTYPES__H */ diff --git a/include/lib/libc/aarch64/limits_.h b/include/lib/libc/aarch64/limits_.h index e36cfe7dc2..834439efba 100644 --- a/include/lib/libc/aarch64/limits_.h +++ b/include/lib/libc/aarch64/limits_.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #define SCHAR_MAX 0x7F -#define SCHAR_MIN (-SCHAR_MIN - 1) +#define SCHAR_MIN (-SCHAR_MAX - 1) #define CHAR_MAX 0x7F #define CHAR_MIN (-CHAR_MAX - 1) #define UCHAR_MAX 0xFFU diff --git a/include/lib/libc/aarch64/setjmp_.h b/include/lib/libc/aarch64/setjmp_.h index f880a17b7b..a7d0b5cbb0 100644 --- a/include/lib/libc/aarch64/setjmp_.h +++ b/include/lib/libc/aarch64/setjmp_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/libc/aarch64/stddef_.h b/include/lib/libc/aarch64/stddef_.h index 6ecc6067c8..963048e730 100644 --- a/include/lib/libc/aarch64/stddef_.h +++ b/include/lib/libc/aarch64/stddef_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h new file mode 100644 index 0000000000..34a75ece14 --- /dev/null +++ b/include/lib/libc/aarch64/stdint_.h @@ -0,0 +1,31 @@ +/* + * Copyright 2020 Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* + * Portions copyright (c) 2020, Arm Limited and Contributors. + * All rights reserved. + */ + +#ifndef STDINT__H +#define STDINT__H + +#define INT64_MAX LONG_MAX +#define INT64_MIN LONG_MIN +#define UINT64_MAX ULONG_MAX + +#define INT64_C(x) x ## L +#define UINT64_C(x) x ## UL + +typedef long int64_t; +typedef unsigned long uint64_t; +typedef long int64_least_t; +typedef unsigned long uint64_least_t; +typedef long int64_fast_t; +typedef unsigned long uint64_fast_t; + +typedef __int128 int128_t; +typedef unsigned __int128 uint128_t; + +#endif diff --git a/include/lib/libc/aarch64/stdio_.h b/include/lib/libc/aarch64/stdio_.h index afaeadc218..331bcaa037 100644 --- a/include/lib/libc/aarch64/stdio_.h +++ b/include/lib/libc/aarch64/stdio_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/libc/arm_acle.h b/include/lib/libc/arm_acle.h index eb08552db7..d1bc0f9344 100644 --- a/include/lib/libc/arm_acle.h +++ b/include/lib/libc/arm_acle.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 ARM Limited + * Copyright (c) 2021 Arm Limited * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h index 486bbc2904..acfd14732a 100644 --- a/include/lib/libc/assert.h +++ b/include/lib/libc/assert.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,6 @@ #include <cdefs.h> -#include <platform_def.h> - #include <common/debug.h> #ifndef PLAT_LOG_LEVEL_ASSERT @@ -18,9 +16,7 @@ #endif #if ENABLE_ASSERTIONS -# if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE -# define assert(e) ((e) ? (void)0 : __assert(__FILE__, __LINE__, #e)) -# elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO +# if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO # define assert(e) ((e) ? (void)0 : __assert(__FILE__, __LINE__)) # else # define assert(e) ((e) ? (void)0 : __assert()) @@ -29,10 +25,7 @@ #define assert(e) ((void)0) #endif /* ENABLE_ASSERTIONS */ -#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE -void __dead2 __assert(const char *file, unsigned int line, - const char *assertion); -#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO +#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO void __dead2 __assert(const char *file, unsigned int line); #else void __dead2 __assert(void); diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h index 0d0072254a..b11d0727dc 100644 --- a/include/lib/libc/cdefs.h +++ b/include/lib/libc/cdefs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,8 +12,10 @@ #define __packed __attribute__((__packed__)) #define __used __attribute__((__used__)) #define __unused __attribute__((__unused__)) +#define __maybe_unused __attribute__((__unused__)) #define __aligned(x) __attribute__((__aligned__(x))) #define __section(x) __attribute__((__section__(x))) +#define __fallthrough __attribute__((__fallthrough__)) #if RECLAIM_INIT_CODE /* * Add each function to a section that is unique so the functions can still diff --git a/include/lib/libc/endian.h b/include/lib/libc/endian.h index 4100f57371..9c9fd58682 100644 --- a/include/lib/libc/endian.h +++ b/include/lib/libc/endian.h @@ -28,7 +28,7 @@ * $FreeBSD$ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/errno.h b/include/lib/libc/errno.h index 029912f61b..b536fe929d 100644 --- a/include/lib/libc/errno.h +++ b/include/lib/libc/errno.h @@ -37,7 +37,7 @@ * $FreeBSD$ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/inttypes.h b/include/lib/libc/inttypes.h new file mode 100644 index 0000000000..344b71c524 --- /dev/null +++ b/include/lib/libc/inttypes.h @@ -0,0 +1,41 @@ +/* + * Copyright 2020 Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* + * Portions copyright (c) 2020, Arm Limited and Contributors. + * All rights reserved. + */ + +#ifndef INTTYPES_H +#define INTTYPES_H + +#include <inttypes_.h> +#include <stdint.h> + +#define PRId8 "d" /* int8_t */ +#define PRId16 "d" /* int16_t */ +#define PRId32 "d" /* int32_t */ + +#define PRIi8 "i" /* int8_t */ +#define PRIi16 "i" /* int16_t */ +#define PRIi32 "i" /* int32_t */ + +#define PRIo8 "o" /* int8_t */ +#define PRIo16 "o" /* int16_t */ +#define PRIo32 "o" /* int32_t */ + +#define PRIu8 "u" /* uint8_t */ +#define PRIu16 "u" /* uint16_t */ +#define PRIu32 "u" /* uint32_t */ + +#define PRIx8 "x" /* uint8_t */ +#define PRIx16 "x" /* uint16_t */ +#define PRIx32 "x" /* uint32_t */ + +#define PRIX8 "X" /* uint8_t */ +#define PRIX16 "X" /* uint16_t */ +#define PRIX32 "X" /* uint32_t */ + +#endif diff --git a/include/lib/libc/limits.h b/include/lib/libc/limits.h index 41bb658481..c5c8764075 100644 --- a/include/lib/libc/limits.h +++ b/include/lib/libc/limits.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/setjmp.h b/include/lib/libc/setjmp.h index be8e2c01ad..871c868858 100644 --- a/include/lib/libc/setjmp.h +++ b/include/lib/libc/setjmp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/libc/stdarg.h b/include/lib/libc/stdarg.h index e260b9b501..2d1f78503d 100644 --- a/include/lib/libc/stdarg.h +++ b/include/lib/libc/stdarg.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h index b58334cd0d..c2c9b22295 100644 --- a/include/lib/libc/stdbool.h +++ b/include/lib/libc/stdbool.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/libc/stddef.h b/include/lib/libc/stddef.h index 58a519e523..aaad673aad 100644 --- a/include/lib/libc/stddef.h +++ b/include/lib/libc/stddef.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h index 818870e164..88502e7a35 100644 --- a/include/lib/libc/stdint.h +++ b/include/lib/libc/stdint.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */ @@ -12,6 +12,7 @@ #define STDINT_H #include <limits.h> +#include <stdint_.h> #define INT8_MAX CHAR_MAX #define INT8_MIN CHAR_MIN @@ -25,10 +26,6 @@ #define INT32_MIN INT_MIN #define UINT32_MAX UINT_MAX -#define INT64_MAX LLONG_MAX -#define INT64_MIN LLONG_MIN -#define UINT64_MAX ULLONG_MAX - #define INT_LEAST8_MIN INT8_MIN #define INT_LEAST8_MAX INT8_MAX #define UINT_LEAST8_MAX UINT8_MAX @@ -77,12 +74,10 @@ #define INT8_C(x) x #define INT16_C(x) x #define INT32_C(x) x -#define INT64_C(x) x ## LL #define UINT8_C(x) x #define UINT16_C(x) x #define UINT32_C(x) x ## U -#define UINT64_C(x) x ## ULL #define INTMAX_C(x) x ## LL #define UINTMAX_C(x) x ## ULL @@ -90,32 +85,26 @@ typedef signed char int8_t; typedef short int16_t; typedef int int32_t; -typedef long long int64_t; typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; typedef signed char int8_least_t; typedef short int16_least_t; typedef int int32_least_t; -typedef long long int64_least_t; typedef unsigned char uint8_least_t; typedef unsigned short uint16_least_t; typedef unsigned int uint32_least_t; -typedef unsigned long long uint64_least_t; typedef int int8_fast_t; typedef int int16_fast_t; typedef int int32_fast_t; -typedef long long int64_fast_t; typedef unsigned int uint8_fast_t; typedef unsigned int uint16_fast_t; typedef unsigned int uint32_fast_t; -typedef unsigned long long uint64_fast_t; typedef long intptr_t; typedef unsigned long uintptr_t; @@ -130,9 +119,4 @@ typedef unsigned long long uintmax_t; typedef long register_t; typedef unsigned long u_register_t; -#ifdef __aarch64__ -typedef __int128 int128_t; -typedef unsigned __int128 uint128_t; -#endif /* __aarch64__ */ - #endif /* STDINT_H */ diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h index ba13683e69..5ceaf68f3b 100644 --- a/include/lib/libc/stdio.h +++ b/include/lib/libc/stdio.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h index 4641e566e7..4e5a824faf 100644 --- a/include/lib/libc/stdlib.h +++ b/include/lib/libc/stdlib.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h index 9894483183..8129404185 100644 --- a/include/lib/libc/string.h +++ b/include/lib/libc/string.h @@ -4,7 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2020, ARM Limited and Contributors. + * Portions copyright (c) 2018-2020, Arm Limited and Contributors. + * Portions copyright (c) 2023, Intel Corporation. All rights reserved. * All rights reserved. */ @@ -14,6 +15,7 @@ #include <stddef.h> void *memcpy(void *dst, const void *src, size_t len); +int memcpy_s(void *dst, size_t dsize, void *src, size_t ssize); void *memmove(void *dst, const void *src, size_t len); int memcmp(const void *s1, const void *s2, size_t len); int strcmp(const char *s1, const char *s2); diff --git a/include/lib/libc/sys/cdefs.h b/include/lib/libc/sys/cdefs.h new file mode 100644 index 0000000000..1ace5fbee7 --- /dev/null +++ b/include/lib/libc/sys/cdefs.h @@ -0,0 +1,922 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_CDEFS_H_ +#define _SYS_CDEFS_H_ + +#if defined(_KERNEL) && defined(_STANDALONE) +#error "_KERNEL and _STANDALONE are mutually exclusive" +#endif + +/* + * Testing against Clang-specific extensions. + */ +#ifndef __has_attribute +#define __has_attribute(x) 0 +#endif +#ifndef __has_extension +#define __has_extension __has_feature +#endif +#ifndef __has_feature +#define __has_feature(x) 0 +#endif +#ifndef __has_include +#define __has_include(x) 0 +#endif +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +#if defined(__cplusplus) +#define __BEGIN_DECLS extern "C" { +#define __END_DECLS } +#else +#define __BEGIN_DECLS +#define __END_DECLS +#endif + +/* + * This code has been put in place to help reduce the addition of + * compiler specific defines in FreeBSD code. It helps to aid in + * having a compiler-agnostic source tree. + */ + +#if defined(__GNUC__) + +#if __GNUC__ >= 3 +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS +#else +#define __GNUCLIKE_ASM 2 +#endif +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___SECTION 1 + +#define __GNUCLIKE_CTOR_SECTION_HANDLING 1 + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 + +#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) +#define __GNUCLIKE_BUILTIN_VARARGS 1 +#define __GNUCLIKE_BUILTIN_STDARG 1 +#define __GNUCLIKE_BUILTIN_VAALIST 1 +#endif + +#define __GNUC_VA_LIST_COMPATIBILITY 1 + +/* + * Compiler memory barriers, specific to gcc and clang. + */ +#define __compiler_membar() __asm __volatile(" " : : : "memory") + +#define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +#define __GNUCLIKE_MATH_BUILTIN_RELOPS + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + +/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 + +#endif /* __GNUC__ */ + +/* + * Macro to test if we're using a specific version of gcc or later. + */ +#if defined(__GNUC__) +#define __GNUC_PREREQ__(ma, mi) \ + (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) +#else +#define __GNUC_PREREQ__(ma, mi) 0 +#endif + +/* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI + * mode -- there must be no spaces between its arguments, and for nested + * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also + * concatenate double-quoted strings produced by the __STRING macro, but + * this only works with ANSI C. + * + * __XSTRING is like __STRING, but it expands any macros in its argument + * first. It is only available with ANSI C. + */ +#if defined(__STDC__) || defined(__cplusplus) +#define __P(protos) protos /* full-blown ANSI C */ +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x /* stringify without expanding x */ +#define __XSTRING(x) __STRING(x) /* expand x, then stringify */ + +#define __const const /* define reserved names to standard */ +#define __signed signed +#define __volatile volatile +#if defined(__cplusplus) +#define __inline inline /* convert to C++ keyword */ +#else +#if !(defined(__CC_SUPPORTS___INLINE)) +#define __inline /* delete GCC keyword */ +#endif /* ! __CC_SUPPORTS___INLINE */ +#endif /* !__cplusplus */ + +#else /* !(__STDC__ || __cplusplus) */ +#define __P(protos) () /* traditional C preprocessor */ +#define __CONCAT(x,y) x/**/y +#define __STRING(x) "x" + +#if !defined(__CC_SUPPORTS___INLINE) +#define __const /* delete pseudo-ANSI C keywords */ +#define __inline +#define __signed +#define __volatile +/* + * In non-ANSI C environments, new programs will want ANSI-only C keywords + * deleted from the program and old programs will want them left alone. + * When using a compiler other than gcc, programs using the ANSI C keywords + * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. + * When using "gcc -traditional", we assume that this is the intent; if + * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. + */ +#ifndef NO_ANSI_KEYWORDS +#define const /* delete ANSI C keywords */ +#define inline +#define signed +#define volatile +#endif /* !NO_ANSI_KEYWORDS */ +#endif /* !__CC_SUPPORTS___INLINE */ +#endif /* !(__STDC__ || __cplusplus) */ + +/* + * Compiler-dependent macros to help declare dead (non-returning) and + * pure (no side effects) functions, and unused variables. They are + * null except for versions of gcc that are known to support the features + * properly (old versions of gcc-2 supported the dead and pure features + * in a different (wrong) way). If we do not provide an implementation + * for a given compiler, let the compile fail if it is told to use + * a feature that we cannot live without. + */ +#define __weak_symbol __attribute__((__weak__)) +#if !__GNUC_PREREQ__(2, 5) +#define __dead2 +#define __pure2 +#define __unused +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused +/* XXX Find out what to do for __packed, __aligned and __section */ +#endif +#if __GNUC_PREREQ__(2, 7) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#if __GNUC_PREREQ__(4, 3) || __has_attribute(__alloc_size__) +#define __alloc_size(x) __attribute__((__alloc_size__(x))) +#define __alloc_size2(n, x) __attribute__((__alloc_size__(n, x))) +#else +#define __alloc_size(x) +#define __alloc_size2(n, x) +#endif +#if __GNUC_PREREQ__(4, 9) || __has_attribute(__alloc_align__) +#define __alloc_align(x) __attribute__((__alloc_align__(x))) +#else +#define __alloc_align(x) +#endif + +#if !__GNUC_PREREQ__(2, 95) +#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) +#endif + +/* + * Keywords added in C11. + */ + +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 201112L + +#if !__has_extension(c_alignas) +#if (defined(__cplusplus) && __cplusplus >= 201103L) || \ + __has_extension(cxx_alignas) +#define _Alignas(x) alignas(x) +#else +/* XXX: Only emulates _Alignas(constant-expression); not _Alignas(type-name). */ +#define _Alignas(x) __aligned(x) +#endif +#endif + +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Alignof(x) alignof(x) +#else +#define _Alignof(x) __alignof(x) +#endif + +#if !defined(__cplusplus) && !__has_extension(c_atomic) && \ + !__has_extension(cxx_atomic) && !__GNUC_PREREQ__(4, 7) +/* + * No native support for _Atomic(). Place object in structure to prevent + * most forms of direct non-atomic access. + */ +#define _Atomic(T) struct { T volatile __val; } +#endif + +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Noreturn [[noreturn]] +#else +#define _Noreturn __dead2 +#endif + +#if !__has_extension(c_static_assert) +#if (defined(__cplusplus) && __cplusplus >= 201103L) || \ + __has_extension(cxx_static_assert) +#define _Static_assert(x, y) static_assert(x, y) +#elif __GNUC_PREREQ__(4,6) && !defined(__cplusplus) +/* Nothing, gcc 4.6 and higher has _Static_assert built-in */ +#elif defined(__COUNTER__) +#define _Static_assert(x, y) __Static_assert(x, __COUNTER__) +#define __Static_assert(x, y) ___Static_assert(x, y) +#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] \ + __unused +#else +#define _Static_assert(x, y) struct __hack +#endif +#endif + +#if !__has_extension(c_thread_local) +/* + * XXX: Some compilers (Clang 3.3, GCC 4.7) falsely announce C++11 mode + * without actually supporting the thread_local keyword. Don't check for + * the presence of C++11 when defining _Thread_local. + */ +#if /* (defined(__cplusplus) && __cplusplus >= 201103L) || */ \ + __has_extension(cxx_thread_local) +#define _Thread_local thread_local +#else +#define _Thread_local __thread +#endif +#endif + +#endif /* __STDC_VERSION__ || __STDC_VERSION__ < 201112L */ + +/* + * Emulation of C11 _Generic(). Unlike the previously defined C11 + * keywords, it is not possible to implement this using exactly the same + * syntax. Therefore implement something similar under the name + * __generic(). Unlike _Generic(), this macro can only distinguish + * between a single type, so it requires nested invocations to + * distinguish multiple cases. + */ + +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \ + __has_extension(c_generic_selections) +#define __generic(expr, t, yes, no) \ + _Generic(expr, t: yes, default: no) +#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) +#define __generic(expr, t, yes, no) \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof(expr), t), yes, no) +#endif + +/* + * C99 Static array indices in function parameter declarations. Syntax such as: + * void bar(int myArray[static 10]); + * is allowed in C99 but not in C++. Define __min_size appropriately so + * headers using it can be compiled in either language. Use like this: + * void bar(int myArray[__min_size(10)]); + */ +#if !defined(__cplusplus) && \ + (defined(__clang__) || __GNUC_PREREQ__(4, 6)) && \ + (!defined(__STDC_VERSION__) || (__STDC_VERSION__ >= 199901)) +#define __min_size(x) static (x) +#else +#define __min_size(x) (x) +#endif + +#if __GNUC_PREREQ__(2, 96) +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) +#else +#define __malloc_like +#define __pure +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __always_inline __attribute__((__always_inline__)) +#else +#define __always_inline +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __noinline __attribute__ ((__noinline__)) +#else +#define __noinline +#endif + +#if __GNUC_PREREQ__(3, 4) +#define __fastcall __attribute__((__fastcall__)) +#define __result_use_check __attribute__((__warn_unused_result__)) +#else +#define __fastcall +#define __result_use_check +#endif + +#if __GNUC_PREREQ__(4, 1) +#define __returns_twice __attribute__((__returns_twice__)) +#else +#define __returns_twice +#endif + +#if __GNUC_PREREQ__(4, 6) || __has_builtin(__builtin_unreachable) +#define __unreachable() __builtin_unreachable() +#else +#define __unreachable() ((void)0) +#endif + +/* XXX: should use `#if __STDC_VERSION__ < 199901'. */ +#if !__GNUC_PREREQ__(2, 7) +#define __func__ NULL +#endif + +#if (defined(__GNUC__) && __GNUC__ >= 2) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 +#define __LONG_LONG_SUPPORTED +#endif + +/* C++11 exposes a load of C99 stuff */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __LONG_LONG_SUPPORTED +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif +#ifndef __STDC_CONSTANT_MACROS +#define __STDC_CONSTANT_MACROS +#endif +#endif + +/* + * GCC 2.95 provides `__restrict' as an extension to C90 to support the + * C99-specific `restrict' type qualifier. We happen to use `__restrict' as + * a way to define the `restrict' type qualifier without disturbing older + * software that is unaware of C99 keywords. + */ +#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 +#define __restrict +#else +#define __restrict restrict +#endif +#endif + +/* + * GNU C version 2.96 adds explicit branch prediction so that + * the CPU back-end can hint the processor and also so that + * code blocks can be reordered such that the predicted path + * sees a more linear flow, thus improving cache behavior, etc. + * + * The following two macros provide us with a way to utilize this + * compiler feature. Use __predict_true() if you expect the expression + * to evaluate to true, and __predict_false() if you expect the + * expression to evaluate to false. + * + * A few notes about usage: + * + * * Generally, __predict_false() error condition checks (unless + * you have some _strong_ reason to do otherwise, in which case + * document it), and/or __predict_true() `no-error' condition + * checks, assuming you want to optimize for the no-error case. + * + * * Other than that, if you don't know the likelihood of a test + * succeeding from empirical or other `hard' evidence, don't + * make predictions. + * + * * These are meant to be used in places that are run `a lot'. + * It is wasteful to make predictions in code that is run + * seldomly (e.g. at subsystem initialization time) as the + * basic block reordering that this affects can often generate + * larger code. + */ +#if __GNUC_PREREQ__(2, 96) +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) +#else +#define __predict_true(exp) (exp) +#define __predict_false(exp) (exp) +#endif + +#if __GNUC_PREREQ__(4, 0) +#define __null_sentinel __attribute__((__sentinel__)) +#define __exported __attribute__((__visibility__("default"))) +#define __hidden __attribute__((__visibility__("hidden"))) +#else +#define __null_sentinel +#define __exported +#define __hidden +#endif + +/* + * We define this here since <stddef.h>, <sys/queue.h>, and <sys/types.h> + * require it. + */ +#if __GNUC_PREREQ__(4, 1) +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#ifndef __cplusplus +#define __offsetof(type, field) \ + ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) +#else +#define __offsetof(type, field) \ + (__offsetof__ (reinterpret_cast <__size_t> \ + (&reinterpret_cast <const volatile char &> \ + (static_cast<type *> (0)->field)))) +#endif +#endif +#define __rangeof(type, start, end) \ + (__offsetof(type, end) - __offsetof(type, start)) + +/* + * Given the pointer x to the member m of the struct s, return + * a pointer to the containing structure. When using GCC, we first + * assign pointer x to a local variable, to check that its type is + * compatible with member m. + */ +#if __GNUC_PREREQ__(3, 1) +#define __containerof(x, s, m) ({ \ + const volatile __typeof(((s *)0)->m) *__x = (x); \ + __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ +}) +#else +#define __containerof(x, s, m) \ + __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) +#endif + +/* + * Compiler-dependent macros to declare that functions take printf-like + * or scanf-like arguments. They are null except for versions of gcc + * that are known to support the features properly (old versions of gcc-2 + * didn't permit keeping the keywords out of the application namespace). + */ +#if !__GNUC_PREREQ__(2, 7) +#define __printflike(fmtarg, firstvararg) +#define __scanflike(fmtarg, firstvararg) +#define __format_arg(fmtarg) +#define __strfmonlike(fmtarg, firstvararg) +#define __strftimelike(fmtarg, firstvararg) +#else +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) +#define __scanflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) +#define __strftimelike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +#endif + +/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ +#if defined(__FreeBSD_cc_version) && __FreeBSD_cc_version >= 300001 && \ + defined(__GNUC__) +#define __printf0like(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) +#else +#define __printf0like(fmtarg, firstvararg) +#endif + +#if defined(__GNUC__) +#define __strong_reference(sym,aliassym) \ + extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) +#ifdef __STDC__ +#define __weak_reference(sym,alias) \ + __asm__(".weak " #alias); \ + __asm__(".equ " #alias ", " #sym) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." #sym); \ + __asm__(".asciz \"" msg "\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@" #verid) +#define __sym_default(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@@@" #verid) +#else +#define __weak_reference(sym,alias) \ + __asm__(".weak alias"); \ + __asm__(".equ alias, sym") +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning.sym"); \ + __asm__(".asciz \"msg\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver impl, sym@verid") +#define __sym_default(impl,sym,verid) \ + __asm__(".symver impl, sym@@@verid") +#endif /* __STDC__ */ +#endif /* __GNUC__ */ + +#define __GLOBL(sym) __asm__(".globl " __XSTRING(sym)) +#define __WEAK(sym) __asm__(".weak " __XSTRING(sym)) + +#if defined(__GNUC__) +#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") +#else +/* + * The following definition might not work well if used in header files, + * but it should be better than nothing. If you want a "do nothing" + * version, then it should generate some harmless declaration, such as: + * #define __IDSTRING(name,string) struct __hack + */ +#define __IDSTRING(name,string) static const char name[] __unused = string +#endif + +/* + * Embed the rcs id of a source file in the resulting library. Note that in + * more recent ELF binutils, we use .ident allowing the ID to be stripped. + * Usage: + * __FBSDID("$FreeBSD$"); + */ +#ifndef __FBSDID +#if !defined(STRIP_FBSDID) +#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __FBSDID(s) struct __hack +#endif +#endif + +#ifndef __RCSID +#ifndef NO__RCSID +#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __RCSID(s) struct __hack +#endif +#endif + +#ifndef __RCSID_SOURCE +#ifndef NO__RCSID_SOURCE +#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) +#else +#define __RCSID_SOURCE(s) struct __hack +#endif +#endif + +#ifndef __SCCSID +#ifndef NO__SCCSID +#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) +#else +#define __SCCSID(s) struct __hack +#endif +#endif + +#ifndef __COPYRIGHT +#ifndef NO__COPYRIGHT +#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) +#else +#define __COPYRIGHT(s) struct __hack +#endif +#endif + +#ifndef __DECONST +#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) +#endif + +#ifndef __DEVOLATILE +#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) +#endif + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) +#endif + +/*- + * The following definitions are an extension of the behavior originally + * implemented in <sys/_posix.h>, but with a different level of granularity. + * POSIX.1 requires that the macros we test be defined before any standard + * header file is included. + * + * Here's a quick run-down of the versions (and some informal names) + * defined(_POSIX_SOURCE) 1003.1-1988 + * encoded as 198808 below + * _POSIX_C_SOURCE == 1 1003.1-1990 + * encoded as 199009 below + * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option + * encoded as 199209 below + * _POSIX_C_SOURCE == 199309 1003.1b-1993 + * (1003.1 Issue 4, Single Unix Spec v1, Unix 93) + * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, + * and the omnibus ISO/IEC 9945-1: 1996 + * (1003.1 Issue 5, Single Unix Spec v2, Unix 95) + * _POSIX_C_SOURCE == 200112 1003.1-2001 (1003.1 Issue 6, Unix 03) + * _POSIX_C_SOURCE == 200809 1003.1-2008 (1003.1 Issue 7) + * IEEE Std 1003.1-2017 (Rev of 1003.1-2008) is + * 1003.1-2008 with two TCs applied with + * _POSIX_C_SOURCE=200809 and _XOPEN_SOURCE=700 + * + * In addition, the X/Open Portability Guide, which is now the Single UNIX + * Specification, defines a feature-test macro which indicates the version of + * that specification, and which subsumes _POSIX_C_SOURCE. + * + * Our macros begin with two underscores to avoid namespace screwage. + */ + +/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 +#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ +#define _POSIX_C_SOURCE 199009 +#endif + +/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199209 +#endif + +/* Deal with various X/Open Portability Guides and Single UNIX Spec. */ +#ifdef _XOPEN_SOURCE +#if _XOPEN_SOURCE - 0 >= 700 +#define __XSI_VISIBLE 700 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809 +#elif _XOPEN_SOURCE - 0 >= 600 +#define __XSI_VISIBLE 600 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200112 +#elif _XOPEN_SOURCE - 0 >= 500 +#define __XSI_VISIBLE 500 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199506 +#endif +#endif + +/* + * Deal with all versions of POSIX. The ordering relative to the tests above is + * important. + */ +#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 198808 +#endif +#ifdef _POSIX_C_SOURCE +#if _POSIX_C_SOURCE >= 200809 +#define __POSIX_VISIBLE 200809 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 200112 +#define __POSIX_VISIBLE 200112 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 199506 +#define __POSIX_VISIBLE 199506 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199309 +#define __POSIX_VISIBLE 199309 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199209 +#define __POSIX_VISIBLE 199209 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199009 +#define __POSIX_VISIBLE 199009 +#define __ISO_C_VISIBLE 1990 +#else +#define __POSIX_VISIBLE 198808 +#define __ISO_C_VISIBLE 0 +#endif /* _POSIX_C_SOURCE */ +/* + * Both glibc and OpenBSD enable c11 features when _ISOC11_SOURCE is defined, or + * when compiling with -stdc=c11. A strict reading of the standard would suggest + * doing it only for the former. However, a strict reading also requires C99 + * mode only, so building with C11 is already undefined. Follow glibc's and + * OpenBSD's lead for this non-standard configuration for maximum compatibility. + */ +#if _ISOC11_SOURCE || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) +#undef __ISO_C_VISIBLE +#define __ISO_C_VISIBLE 2011 +#endif +#else +/*- + * Deal with _ANSI_SOURCE: + * If it is defined, and no other compilation environment is explicitly + * requested, then define our internal feature-test macros to zero. This + * makes no difference to the preprocessor (undefined symbols in preprocessing + * expressions are defined to have value zero), but makes it more convenient for + * a test program to print out the values. + * + * If a program mistakenly defines _ANSI_SOURCE and some other macro such as + * _POSIX_C_SOURCE, we will assume that it wants the broader compilation + * environment (and in fact we will never get here). + */ +#if defined(_ANSI_SOURCE) /* Hide almost everything. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1990 +#define __EXT1_VISIBLE 0 +#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1999 +#define __EXT1_VISIBLE 0 +#elif defined(_C11_SOURCE) /* Localism to specify strict C11 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 2011 +#define __EXT1_VISIBLE 0 +#else /* Default environment: show everything. */ +#define __POSIX_VISIBLE 200809 +#define __XSI_VISIBLE 700 +#define __BSD_VISIBLE 1 +#define __ISO_C_VISIBLE 2011 +#define __EXT1_VISIBLE 1 +#endif +#endif + +/* User override __EXT1_VISIBLE */ +#if defined(__STDC_WANT_LIB_EXT1__) +#undef __EXT1_VISIBLE +#if __STDC_WANT_LIB_EXT1__ +#define __EXT1_VISIBLE 1 +#else +#define __EXT1_VISIBLE 0 +#endif +#endif /* __STDC_WANT_LIB_EXT1__ */ + +/* + * Old versions of GCC use non-standard ARM arch symbols; acle-compat.h + * translates them to __ARM_ARCH and the modern feature symbols defined by ARM. + */ +#if defined(__arm__) && !defined(__ARM_ARCH) +#include <machine/acle-compat.h> +#endif + +/* + * Nullability qualifiers: currently only supported by Clang. + */ +#if !(defined(__clang__) && __has_feature(nullability)) +#define _Nonnull +#define _Nullable +#define _Null_unspecified +#define __NULLABILITY_PRAGMA_PUSH +#define __NULLABILITY_PRAGMA_POP +#else +#define __NULLABILITY_PRAGMA_PUSH _Pragma("clang diagnostic push") \ + _Pragma("clang diagnostic ignored \"-Wnullability-completeness\"") +#define __NULLABILITY_PRAGMA_POP _Pragma("clang diagnostic pop") +#endif + +/* + * Type Safety Checking + * + * Clang provides additional attributes to enable checking type safety + * properties that cannot be enforced by the C type system. + */ + +#if __has_attribute(__argument_with_type_tag__) && \ + __has_attribute(__type_tag_for_datatype__) +#define __arg_type_tag(arg_kind, arg_idx, type_tag_idx) \ + __attribute__((__argument_with_type_tag__(arg_kind, arg_idx, type_tag_idx))) +#define __datatype_type_tag(kind, type) \ + __attribute__((__type_tag_for_datatype__(kind, type))) +#else +#define __arg_type_tag(arg_kind, arg_idx, type_tag_idx) +#define __datatype_type_tag(kind, type) +#endif + +/* + * Lock annotations. + * + * Clang provides support for doing basic thread-safety tests at + * compile-time, by marking which locks will/should be held when + * entering/leaving a functions. + * + * Furthermore, it is also possible to annotate variables and structure + * members to enforce that they are only accessed when certain locks are + * held. + */ + +#if __has_extension(c_thread_safety_attributes) +#define __lock_annotate(x) __attribute__((x)) +#else +#define __lock_annotate(x) +#endif + +/* Structure implements a lock. */ +#define __lockable __lock_annotate(lockable) + +/* Function acquires an exclusive or shared lock. */ +#define __locks_exclusive(...) \ + __lock_annotate(exclusive_lock_function(__VA_ARGS__)) +#define __locks_shared(...) \ + __lock_annotate(shared_lock_function(__VA_ARGS__)) + +/* Function attempts to acquire an exclusive or shared lock. */ +#define __trylocks_exclusive(...) \ + __lock_annotate(exclusive_trylock_function(__VA_ARGS__)) +#define __trylocks_shared(...) \ + __lock_annotate(shared_trylock_function(__VA_ARGS__)) + +/* Function releases a lock. */ +#define __unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__)) + +/* Function asserts that an exclusive or shared lock is held. */ +#define __asserts_exclusive(...) \ + __lock_annotate(assert_exclusive_lock(__VA_ARGS__)) +#define __asserts_shared(...) \ + __lock_annotate(assert_shared_lock(__VA_ARGS__)) + +/* Function requires that an exclusive or shared lock is or is not held. */ +#define __requires_exclusive(...) \ + __lock_annotate(exclusive_locks_required(__VA_ARGS__)) +#define __requires_shared(...) \ + __lock_annotate(shared_locks_required(__VA_ARGS__)) +#define __requires_unlocked(...) \ + __lock_annotate(locks_excluded(__VA_ARGS__)) + +/* Function should not be analyzed. */ +#define __no_lock_analysis __lock_annotate(no_thread_safety_analysis) + +/* + * Function or variable should not be sanitized, e.g., by AddressSanitizer. + * GCC has the nosanitize attribute, but as a function attribute only, and + * warns on use as a variable attribute. + */ +#if __has_attribute(no_sanitize) && defined(__clang__) +#ifdef _KERNEL +#define __nosanitizeaddress __attribute__((no_sanitize("kernel-address"))) +#define __nosanitizememory __attribute__((no_sanitize("kernel-memory"))) +#else +#define __nosanitizeaddress __attribute__((no_sanitize("address"))) +#define __nosanitizememory __attribute__((no_sanitize("memory"))) +#endif +#define __nosanitizethread __attribute__((no_sanitize("thread"))) +#else +#define __nosanitizeaddress +#define __nosanitizememory +#define __nosanitizethread +#endif + +/* Guard variables and structure members by lock. */ +#define __guarded_by(x) __lock_annotate(guarded_by(x)) +#define __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x)) + +/* Alignment builtins for better type checking and improved code generation. */ +/* Provide fallback versions for other compilers (GCC/Clang < 10): */ +#if !__has_builtin(__builtin_is_aligned) +#define __builtin_is_aligned(x, align) \ + (((__uintptr_t)x & ((align) - 1)) == 0) +#endif +#if !__has_builtin(__builtin_align_up) +#define __builtin_align_up(x, align) \ + ((__typeof__(x))(((__uintptr_t)(x)+((align)-1))&(~((align)-1)))) +#endif +#if !__has_builtin(__builtin_align_down) +#define __builtin_align_down(x, align) \ + ((__typeof__(x))((x)&(~((align)-1)))) +#endif + +#define __align_up(x, y) __builtin_align_up(x, y) +#define __align_down(x, y) __builtin_align_down(x, y) +#define __is_aligned(x, y) __builtin_is_aligned(x, y) + +#endif /* !_SYS_CDEFS_H_ */ diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h index c1c95e5863..e1eb2a501f 100644 --- a/include/lib/libc/time.h +++ b/include/lib/libc/time.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */ diff --git a/include/lib/libfdt/fdt.h b/include/lib/libfdt/fdt.h index eb9edb72f5..c9acc0cb07 100644 --- a/include/lib/libfdt/fdt.h +++ b/include/lib/libfdt/fdt.h @@ -35,14 +35,14 @@ struct fdt_reserve_entry { struct fdt_node_header { fdt32_t tag; - char name[0]; + char name[]; }; struct fdt_property { fdt32_t tag; fdt32_t len; fdt32_t nameoff; - char data[0]; + char data[]; }; #endif /* !__ASSEMBLER__*/ diff --git a/include/lib/libfdt/libfdt.h b/include/lib/libfdt/libfdt.h index 544d3efff5..d0a2ed2741 100644 --- a/include/lib/libfdt/libfdt.h +++ b/include/lib/libfdt/libfdt.h @@ -14,6 +14,7 @@ extern "C" { #endif #define FDT_FIRST_SUPPORTED_VERSION 0x02 +#define FDT_LAST_COMPATIBLE_VERSION 0x10 #define FDT_LAST_SUPPORTED_VERSION 0x11 /* Error codes: informative error codes */ @@ -101,7 +102,11 @@ extern "C" { /* FDT_ERR_BADFLAGS: The function was passed a flags field that * contains invalid flags or an invalid combination of flags. */ -#define FDT_ERR_MAX 18 +#define FDT_ERR_ALIGNMENT 19 + /* FDT_ERR_ALIGNMENT: The device tree base address is not 8-byte + * aligned. */ + +#define FDT_ERR_MAX 19 /* constants */ #define FDT_MAX_PHANDLE 0xfffffffe @@ -122,11 +127,16 @@ static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); /* - * Alignment helpers: - * These helpers access words from a device tree blob. They're - * built to work even with unaligned pointers on platforms (ike - * ARM) that don't like unaligned loads and stores + * External helpers to access words from a device tree blob. They're built + * to work even with unaligned pointers on platforms (such as ARMv5) that don't + * like unaligned loads and stores. */ +static inline uint16_t fdt16_ld(const fdt16_t *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint16_t)bp[0] << 8) | bp[1]; +} static inline uint32_t fdt32_ld(const fdt32_t *p) { @@ -184,23 +194,23 @@ int fdt_next_node(const void *fdt, int offset, int *depth); /** * fdt_first_subnode() - get offset of first direct subnode - * * @fdt: FDT blob * @offset: Offset of node to check - * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + * + * Return: offset of first subnode, or -FDT_ERR_NOTFOUND if there is none */ int fdt_first_subnode(const void *fdt, int offset); /** * fdt_next_subnode() - get offset of next direct subnode + * @fdt: FDT blob + * @offset: Offset of previous subnode * * After first calling fdt_first_subnode(), call this function repeatedly to * get direct subnodes of a parent node. * - * @fdt: FDT blob - * @offset: Offset of previous subnode - * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more - * subnodes + * Return: offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes */ int fdt_next_subnode(const void *fdt, int offset); @@ -225,7 +235,6 @@ int fdt_next_subnode(const void *fdt, int offset); * Note that this is implemented as a macro and @node is used as * iterator in the loop. The parent variable be constant or even a * literal. - * */ #define fdt_for_each_subnode(node, fdt, parent) \ for (node = fdt_first_subnode(fdt, parent); \ @@ -269,17 +278,21 @@ fdt_set_hdr_(size_dt_struct); /** * fdt_header_size - return the size of the tree's header * @fdt: pointer to a flattened device tree + * + * Return: size of DTB header in bytes */ size_t fdt_header_size(const void *fdt); /** - * fdt_header_size_ - internal function which takes a version number + * fdt_header_size_ - internal function to get header size from a version number + * @version: devicetree version number + * + * Return: size of DTB header in bytes */ size_t fdt_header_size_(uint32_t version); /** * fdt_check_header - sanity check a device tree header - * @fdt: pointer to data which might be a flattened device tree * * fdt_check_header() checks that the given buffer contains what @@ -404,8 +417,7 @@ static inline uint32_t fdt_get_max_phandle(const void *fdt) * highest phandle value in the device tree blob) will be returned in the * @phandle parameter. * - * Returns: - * 0 on success or a negative error-code on failure + * Return: 0 on success or a negative error-code on failure */ int fdt_generate_phandle(const void *fdt, uint32_t *phandle); @@ -425,9 +437,11 @@ int fdt_num_mem_rsv(const void *fdt); /** * fdt_get_mem_rsv - retrieve one memory reserve map entry * @fdt: pointer to the device tree blob - * @address, @size: pointers to 64-bit variables + * @n: index of reserve map entry + * @address: pointer to 64-bit variable to hold the start address + * @size: pointer to 64-bit variable to hold the size of the entry * - * On success, *address and *size will contain the address and size of + * On success, @address and @size will contain the address and size of * the n-th reserve map entry from the device tree blob, in * native-endian format. * @@ -450,6 +464,8 @@ int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); * namelen characters of name for matching the subnode name. This is * useful for finding subnodes based on a portion of a larger string, * such as a full path. + * + * Return: offset of the subnode or -FDT_ERR_NOTFOUND if name not found. */ #ifndef SWIG /* Not available in Python */ int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, @@ -489,6 +505,8 @@ int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); * * Identical to fdt_path_offset(), but only consider the first namelen * characters of path as the path name. + * + * Return: offset of the node or negative libfdt error value otherwise */ #ifndef SWIG /* Not available in Python */ int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); @@ -588,9 +606,9 @@ int fdt_next_property_offset(const void *fdt, int offset); /** * fdt_for_each_property_offset - iterate over all properties of a node * - * @property_offset: property offset (int, lvalue) - * @fdt: FDT blob (const void *) - * @node: node offset (int) + * @property: property offset (int, lvalue) + * @fdt: FDT blob (const void *) + * @node: node offset (int) * * This is actually a wrapper around a for loop and would be used like so: * @@ -642,6 +660,13 @@ int fdt_next_property_offset(const void *fdt, int offset); const struct fdt_property *fdt_get_property_by_offset(const void *fdt, int offset, int *lenp); +static inline struct fdt_property *fdt_get_property_by_offset_w(void *fdt, + int offset, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property_by_offset(fdt, offset, lenp); +} /** * fdt_get_property_namelen - find a property based on substring @@ -653,6 +678,9 @@ const struct fdt_property *fdt_get_property_by_offset(const void *fdt, * * Identical to fdt_get_property(), but only examine the first namelen * characters of name for matching the property name. + * + * Return: pointer to the structure representing the property, or NULL + * if not found */ #ifndef SWIG /* Not available in Python */ const struct fdt_property *fdt_get_property_namelen(const void *fdt, @@ -745,6 +773,8 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, * * Identical to fdt_getprop(), but only examine the first namelen * characters of name for matching the property name. + * + * Return: pointer to the property's value or NULL on error */ #ifndef SWIG /* Not available in Python */ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, @@ -766,10 +796,10 @@ static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, * @lenp: pointer to an integer variable (will be overwritten) or NULL * * fdt_getprop() retrieves a pointer to the value of the property - * named 'name' of the node at offset nodeoffset (this will be a + * named @name of the node at offset @nodeoffset (this will be a * pointer to within the device blob itself, not a copy of the value). - * If lenp is non-NULL, the length of the property value is also - * returned, in the integer pointed to by lenp. + * If @lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by @lenp. * * returns: * pointer to the property's value @@ -814,8 +844,11 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); * @name: name of the alias th look up * @namelen: number of characters of name to consider * - * Identical to fdt_get_alias(), but only examine the first namelen - * characters of name for matching the alias name. + * Identical to fdt_get_alias(), but only examine the first @namelen + * characters of @name for matching the alias name. + * + * Return: a pointer to the expansion of the alias named @name, if it exists, + * NULL otherwise */ #ifndef SWIG /* Not available in Python */ const char *fdt_get_alias_namelen(const void *fdt, @@ -828,7 +861,7 @@ const char *fdt_get_alias_namelen(const void *fdt, * @name: name of the alias th look up * * fdt_get_alias() retrieves the value of a given alias. That is, the - * value of the property named 'name' in the node /aliases. + * value of the property named @name in the node /aliases. * * returns: * a pointer to the expansion of the alias named 'name', if it exists @@ -1004,14 +1037,13 @@ int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); /** - * fdt_node_check_compatible: check a node's compatible property + * fdt_node_check_compatible - check a node's compatible property * @fdt: pointer to the device tree blob * @nodeoffset: offset of a tree node * @compatible: string to match against * - * * fdt_node_check_compatible() returns 0 if the given node contains a - * 'compatible' property with the given string as one of its elements, + * @compatible property with the given string as one of its elements, * it returns non-zero otherwise, or on error. * * returns: @@ -1075,7 +1107,7 @@ int fdt_node_offset_by_compatible(const void *fdt, int startoffset, * one or more strings, each terminated by \0, as is found in a device tree * "compatible" property. * - * @return: 1 if the string is found in the list, 0 not found, or invalid list + * Return: 1 if the string is found in the list, 0 not found, or invalid list */ int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); @@ -1084,7 +1116,8 @@ int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); * @fdt: pointer to the device tree blob * @nodeoffset: offset of a tree node * @property: name of the property containing the string list - * @return: + * + * Return: * the number of strings in the given property * -FDT_ERR_BADVALUE if the property value is not NUL-terminated * -FDT_ERR_NOTFOUND if the property does not exist @@ -1104,7 +1137,7 @@ int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); * small-valued cell properties, such as #address-cells, when searching for * the empty string. * - * @return: + * return: * the index of the string in the list of strings * -FDT_ERR_BADVALUE if the property value is not NUL-terminated * -FDT_ERR_NOTFOUND if the property does not exist or does not contain @@ -1128,7 +1161,7 @@ int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, * If non-NULL, the length of the string (on success) or a negative error-code * (on failure) will be stored in the integer pointer to by lenp. * - * @return: + * Return: * A pointer to the string at the given index in the string list or NULL on * failure. On success the length of the string will be stored in the memory * location pointed to by the lenp parameter, if non-NULL. On failure one of @@ -1217,6 +1250,8 @@ int fdt_size_cells(const void *fdt, int nodeoffset); * starting from the given index, and using only the first characters * of the name. It is useful when you want to manipulate only one value of * an array and you have a string that doesn't end with \0. + * + * Return: 0 on success, negative libfdt error value otherwise */ #ifndef SWIG /* Not available in Python */ int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, @@ -1330,8 +1365,13 @@ static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, /** * fdt_setprop_inplace_cell - change the value of a single-cell property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node containing the property + * @name: name of the property to change the value of + * @val: new value of the 32-bit cell * * This is an alternative name for fdt_setprop_inplace_u32() + * Return: 0 on success, negative libfdt error number otherwise. */ static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, const char *name, uint32_t val) @@ -1403,7 +1443,7 @@ int fdt_nop_node(void *fdt, int nodeoffset); /** * fdt_create_with_flags - begin creation of a new fdt - * @fdt: pointer to memory allocated where fdt will be created + * @buf: pointer to memory allocated where fdt will be created * @bufsize: size of the memory space at fdt * @flags: a valid combination of FDT_CREATE_FLAG_ flags, or 0. * @@ -1421,7 +1461,7 @@ int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags); /** * fdt_create - begin creation of a new fdt - * @fdt: pointer to memory allocated where fdt will be created + * @buf: pointer to memory allocated where fdt will be created * @bufsize: size of the memory space at fdt * * fdt_create() is equivalent to fdt_create_with_flags() with flags=0. @@ -1486,7 +1526,8 @@ int fdt_pack(void *fdt); /** * fdt_add_mem_rsv - add one memory reserve map entry * @fdt: pointer to the device tree blob - * @address, @size: 64-bit values (native endian) + * @address: 64-bit start address of the reserve map entry + * @size: 64-bit size of the reserved region * * Adds a reserve map entry to the given blob reserving a region at * address address of length size. @@ -1691,8 +1732,14 @@ static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, /** * fdt_setprop_cell - set a property to a single cell value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) * * This is an alternative name for fdt_setprop_u32() + * + * Return: 0 on success, negative libfdt error value otherwise. */ static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, uint32_t val) @@ -1863,8 +1910,14 @@ static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, /** * fdt_appendprop_cell - append a single cell value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) * * This is an alternative name for fdt_appendprop_u32() + * + * Return: 0 on success, negative libfdt error value otherwise. */ static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, const char *name, uint32_t val) @@ -1967,13 +2020,16 @@ int fdt_delprop(void *fdt, int nodeoffset, const char *name); * fdt_add_subnode_namelen - creates a new node based on substring * @fdt: pointer to the device tree blob * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate + * @name: name of the subnode to create * @namelen: number of characters of name to consider * - * Identical to fdt_add_subnode(), but use only the first namelen - * characters of name as the name of the new node. This is useful for + * Identical to fdt_add_subnode(), but use only the first @namelen + * characters of @name as the name of the new node. This is useful for * creating subnodes based on a portion of a larger string, such as a * full path. + * + * Return: structure block offset of the created subnode (>=0), + * negative libfdt error value otherwise */ #ifndef SWIG /* Not available in Python */ int fdt_add_subnode_namelen(void *fdt, int parentoffset, @@ -1992,7 +2048,7 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset, * * This function will insert data into the blob, and will therefore * change the offsets of some existing nodes. - + * * returns: * structure block offset of the created nodeequested subnode (>=0), on * success @@ -2067,6 +2123,24 @@ int fdt_del_node(void *fdt, int nodeoffset); */ int fdt_overlay_apply(void *fdt, void *fdto); +/** + * fdt_overlay_target_offset - retrieves the offset of a fragment's target + * @fdt: Base device tree blob + * @fdto: Device tree overlay blob + * @fragment_offset: node offset of the fragment in the overlay + * @pathp: pointer which receives the path of the target (or NULL) + * + * fdt_overlay_target_offset() retrieves the target offset in the base + * device tree of a fragment, no matter how the actual targeting is + * done (through a phandle or a path) + * + * returns: + * the targeted node offset in the base device tree + * Negative error code on error + */ +int fdt_overlay_target_offset(const void *fdt, const void *fdto, + int fragment_offset, char const **pathp); + /**********************************************************************/ /* Debugging / informational functions */ /**********************************************************************/ diff --git a/include/lib/mmio.h b/include/lib/mmio.h index 3242a7cc55..591d7b6cb0 100644 --- a/include/lib/mmio.h +++ b/include/lib/mmio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/mpmm/mpmm.h b/include/lib/mpmm/mpmm.h new file mode 100644 index 0000000000..955c530e83 --- /dev/null +++ b/include/lib/mpmm/mpmm.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MPMM_H +#define MPMM_H + +#include <stdbool.h> + +#include <platform_def.h> + +/* + * Enable the Maximum Power Mitigation Mechanism. + * + * This function will enable MPMM for the current core. The AMU counters + * representing the MPMM gears must have been configured and enabled prior to + * calling this function. + */ +void mpmm_enable(void); + +/* + * MPMM core data. + * + * This structure represents per-core data retrieved from the hardware + * configuration device tree. + */ +struct mpmm_core { + /* + * Whether MPMM is supported. + * + * Cores with support for MPMM offer one or more auxiliary AMU counters + * representing MPMM gears. + */ + bool supported; +}; + +/* + * MPMM topology. + * + * This topology structure describes the system-wide representation of the + * information retrieved from the hardware configuration device tree. + */ +struct mpmm_topology { + struct mpmm_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */ +}; + +#if !ENABLE_MPMM_FCONF +/* + * Retrieve the platform's MPMM topology. A `NULL` return value is treated as a + * non-fatal error, in which case MPMM will not be enabled for any core. + */ +const struct mpmm_topology *plat_mpmm_topology(void); +#endif /* ENABLE_MPMM_FCONF */ + +#endif /* MPMM_H */ diff --git a/include/lib/object_pool.h b/include/lib/object_pool.h index 66e8c4780c..49584ebdaf 100644 --- a/include/lib/object_pool.h +++ b/include/lib/object_pool.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/optee_utils.h b/include/lib/optee_utils.h index 6067caff42..e1e9d803a8 100644 --- a/include/lib/optee_utils.h +++ b/include/lib/optee_utils.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +7,50 @@ #ifndef OPTEE_UTILS_H #define OPTEE_UTILS_H +#include <stdbool.h> + #include <common/bl_common.h> +bool optee_header_is_valid(uintptr_t header_base); + int parse_optee_header(entry_point_info_t *header_ep, image_info_t *pager_image_info, image_info_t *paged_image_info); +/* + * load_addr_hi and load_addr_lo: image load address. + * image_id: 0 - pager, 1 - paged + * size: image size in bytes. + */ +typedef struct optee_image { + uint32_t load_addr_hi; + uint32_t load_addr_lo; + uint32_t image_id; + uint32_t size; +} optee_image_t; + +#define OPTEE_PAGER_IMAGE_ID 0 +#define OPTEE_PAGED_IMAGE_ID 1 + +#define OPTEE_MAX_NUM_IMAGES 2u + +#define TEE_MAGIC_NUM_OPTEE 0x4554504f +/* + * magic: header magic number. + * version: OPTEE header version: + * 1 - not supported + * 2 - supported + * arch: OPTEE os architecture type: 0 - AARCH32, 1 - AARCH64. + * flags: unused currently. + * nb_images: number of images. + */ +typedef struct optee_header { + uint32_t magic; + uint8_t version; + uint8_t arch; + uint16_t flags; + uint32_t nb_images; + optee_image_t optee_image_list[]; +} optee_header_t; + #endif /* OPTEE_UTILS_H */ diff --git a/include/lib/pmf/aarch64/pmf_asm_macros.S b/include/lib/pmf/aarch64/pmf_asm_macros.S index 5f3e6b7ecc..792ede9132 100644 --- a/include/lib/pmf/aarch64/pmf_asm_macros.S +++ b/include/lib/pmf/aarch64/pmf_asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index fa990d2e54..9d901e202f 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index b49c6da09e..f5f040ba56 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -154,7 +154,7 @@ typedef struct pmf_svc_desc { extern unsigned long long pmf_ts_mem_ ## _name[_total_id]; \ unsigned long long pmf_ts_mem_ ## _name[_total_id] \ __aligned(CACHE_WRITEBACK_GRANULE) \ - __section("pmf_timestamp_array") \ + __section(".pmf_timestamp_array") \ __used; /* @@ -225,7 +225,7 @@ typedef struct pmf_svc_desc { #define PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \ _init, _getts_by_mpidr) \ static const pmf_svc_desc_t __pmf_desc_ ## _name \ - __section("pmf_svc_descs") __used = { \ + __section(".pmf_svc_descs") __used = { \ .h.type = PARAM_EP, \ .h.version = VERSION_1, \ .h.size = sizeof(pmf_svc_desc_t), \ diff --git a/include/lib/psa/delegated_attestation.h b/include/lib/psa/delegated_attestation.h new file mode 100644 index 0000000000..7aaceb3e3d --- /dev/null +++ b/include/lib/psa/delegated_attestation.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file describes the Delegated Attestation API */ + +#ifndef DELEGATED_ATTESTATION_H +#define DELEGATED_ATTESTATION_H + +#include <stddef.h> +#include <stdint.h> + +#include "psa/error.h" + +/* RSS Delegated Attestation message types that distinguish its services. */ +#define RSS_DELEGATED_ATTEST_GET_DELEGATED_KEY 1001U +#define RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN 1002U + +/** + * The aim of these APIs to get a derived signing key (private only) for the + * delegated attestation model and obtain the corresponding platform attestation + * token. In the delegated attestation model the final token consist of more + * than one subtokens which are signed by different entities. There is a + * cryptographical binding between the tokens. The derived delegated attestation + * key is bind to the platform token (details below). + * + * Expected usage model: + * - First rss_delegated_attest_get_delegated_key() API need to be called to + * obtain the private part of the delegated attestation key. The public part + * of key is computed by the cryptographic library when the key is + * registered. + * - Secondly the rss_delegated_attest_get_token() must be called to obtain + * platform attestation token. The hash of the public key (computed by + * the hash_algo indicated in the rss_delegated_attest_get_delegated_key() + * call) must be the input of this call. This ensures that nothing but the + * previously derived delegated key is bindable to the platform token. + */ + +/** + * Get a delegated attestation key (DAK). + * + * The aim of the delegated attestation key is to enable other SW components + * within the system to sign an attestation token which is different than the + * initial/platform token. The initial attestation token MUST contain the hash + * of the public delegated key to make a cryptographical binding (hash lock) + * between the key and the token. + * The initial attestation token has two roles in this scenario: + * - Attest the device boot status and security lifecycle. + * - Attest the delegated attestation key. + * The delegated attestation key is derived from a preprovisioned seed. The + * input for the key derivation is the platform boot status. The system can be + * attestated with the two tokens together. + * + * ecc_curve The type of the elliptic curve to which the requested + * attestation key belongs. Please check the note section for + * limitations. + * key_bits The size of the requested attestation key, in bits. + * key_buf Pointer to the buffer where the delegated attestation key will + * be stored. + * key_buf_size Size of allocated buffer for the key, in bytes. + * key_size Size of the key that has been returned, in bytes. + * hash_algo The hash algorithm that will be used later by the owner of the + * requested delegated key for binding it to the platform + * attestation token. + * + * Returns error code as specified in psa_status_t. + * + * Notes: + * - Currently, only the PSA_ECC_FAMILY_SECP_R1 curve type is supported. + * - The delegated attestation key must be derived before requesting for the + * platform attestation token as they are cryptographically linked together. + */ +psa_status_t +rss_delegated_attest_get_delegated_key(uint8_t ecc_curve, + uint32_t key_bits, + uint8_t *key_buf, + size_t key_buf_size, + size_t *key_size, + uint32_t hash_algo); + +/** + * Get platform attestation token + * + * dak_pub_hash Pointer to buffer where the hash of the public DAK is + * stored. + * dak_pub_hash_size Size of the hash value, in bytes. + * token_buf Pointer to the buffer where the platform attestation token + * will be stored. + * token_buf_size Size of allocated buffer for token, in bytes. + * token_size Size of the token that has been returned, in bytes. + * + * Returns error code as specified in psa_status_t. + * + * A delegated attestation key must be derived before requesting for the + * platform attestation token as they are cryptographically linked together. + * Otherwise, the token request will fail and the PSA_ERROR_INVALID_ARGUMENT + * code will be returned. + */ +psa_status_t +rss_delegated_attest_get_token(const uint8_t *dak_pub_hash, + size_t dak_pub_hash_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size); + +#endif /* DELEGATED_ATTESTATION_H */ diff --git a/include/lib/psa/dice_protection_environment.h b/include/lib/psa/dice_protection_environment.h new file mode 100644 index 0000000000..61b648266f --- /dev/null +++ b/include/lib/psa/dice_protection_environment.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DICE_PROTECTION_ENVIRONMENT_H +#define DICE_PROTECTION_ENVIRONMENT_H + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#include <dice.h> + +/* Additional defines for max size limit. These limits are set by DPE in RSS. */ +#define DICE_AUTHORITY_DESCRIPTOR_MAX_SIZE 64 +#define DICE_CONFIG_DESCRIPTOR_MAX_SIZE 64 +#define DICE_CODE_DESCRIPTOR_MAX_SIZE 32 + +typedef int32_t dpe_error_t; + +#define DPE_NO_ERROR ((dpe_error_t)0) +#define DPE_INTERNAL_ERROR ((dpe_error_t)1) +#define DPE_INVALID_COMMAND ((dpe_error_t)2) +#define DPE_INVALID_ARGUMENT ((dpe_error_t)3) +#define DPE_ARGUMENT_NOT_SUPPORTED ((dpe_error_t)4) +#define DPE_SESSION_EXHAUSTED ((dpe_error_t)5) + +/* Custom values in RSS based DPE implementation */ +#define DPE_INSUFFICIENT_MEMORY ((dpe_error_t)128) +#define DPE_ERR_CBOR_FORMATTING ((dpe_error_t)129) + +/** + * Client facing API. Parameters are according to the DPE spec version r0.9 + * + * \brief Performs the DICE computation to derive a new context and optionally + * creates an intermediate certificate. Software component measurement + * must be provided in dice_inputs. + * + * \param[in] context_handle Input context handle for the DPE + * context. + * \param[in] cert_id Logical certificate id to which derived + * context belongs to. + * \param[in] retain_parent_context Flag to indicate whether to retain the + * parent context. True only if a client + * will call further DPE commands on the + * same context. + * \param[in] allow_new_context_to_derive Flag to indicate whether derived context + * can derive further. True only if the + * new context will load further components. + * \param[in] create_certificate Flag to indicate whether to create an + * intermediate certificate. True only if + * it is the last component in the layer. + * \param[in] dice_inputs DICE input values. + * \param[in] target_locality Identifies the locality to which the + * derived context will be bound. Could be + * MHU id. + * \param[in] return_certificate Indicates whether to return the generated + * certificate when create_certificate is true. + * \param[in] allow_new_context_to_export Indicates whether the DPE permits export of + * the CDI from the newly derived context. + * \param[in] export_cdi Indicates whether to export derived CDI. + * \param[out] new_context_handle New handle for the derived context. + * \param[out] new_parent_context_handle New handle for the parent context. + * \param[out] new_certificate_buf If create_certificate and return_certificate + * are both true, this argument holds the new + * certificate generated for the new context + * \param[in] new_certificate_buf_size Size of the allocated buffer for + * new certificate. + * \param[out] new_certificate_actual_size Actual size of the new certificate. + * \param[out] exported_cdi_buf If export_cdi is true, this is the + * exported CDI value. + * \param[in] exported_cdi_buf_size Size of the allocated buffer for + * exported cdi. + * \param[out] exported_cdi_actual_size Actual size of the exported cdi. + * + * \return Returns error code of type dpe_error_t + */ +dpe_error_t dpe_derive_context(int context_handle, + uint32_t cert_id, + bool retain_parent_context, + bool allow_new_context_to_derive, + bool create_certificate, + const DiceInputValues *dice_inputs, + int32_t target_locality, + bool return_certificate, + bool allow_new_context_to_export, + bool export_cdi, + int *new_context_handle, + int *new_parent_context_handle, + uint8_t *new_certificate_buf, + size_t new_certificate_buf_size, + size_t *new_certificate_actual_size, + uint8_t *exported_cdi_buf, + size_t exported_cdi_buf_size, + size_t *exported_cdi_actual_size); + +#endif /* DICE_PROTECTION_ENVIRONMENT_H */ diff --git a/include/lib/psa/measured_boot.h b/include/lib/psa/measured_boot.h new file mode 100644 index 0000000000..79cdfa0040 --- /dev/null +++ b/include/lib/psa/measured_boot.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PSA_MEASURED_BOOT_H +#define PSA_MEASURED_BOOT_H + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#include "psa/error.h" + +/** + * Extends and stores a measurement to the requested slot. + * + * index Slot number in which measurement is to be stored + * signer_id Pointer to signer_id buffer. + * signer_id_size Size of the signer_id in bytes. + * version Pointer to version buffer. + * version_size Size of the version string in bytes. + * measurement_algo Algorithm identifier used for measurement. + * sw_type Pointer to sw_type buffer. + * sw_type_size Size of the sw_type string in bytes. + * measurement_value Pointer to measurement_value buffer. + * measurement_value_size Size of the measurement_value in bytes. + * lock_measurement Boolean flag requesting whether the measurement + * is to be locked. + * + * PSA_SUCCESS: + * - Success. + * PSA_ERROR_INVALID_ARGUMENT: + * - The size of any argument is invalid OR + * - Input Measurement value is NULL OR + * - Input Signer ID is NULL OR + * - Requested slot index is invalid. + * PSA_ERROR_BAD_STATE: + * - Request to lock, when slot is already locked. + * PSA_ERROR_NOT_PERMITTED: + * - When the requested slot is not accessible to the caller. + */ + +/* Not a standard PSA API, just an extension therefore use the 'rss_' prefix + * rather than the usual 'psa_'. + */ +psa_status_t +rss_measured_boot_extend_measurement(uint8_t index, + const uint8_t *signer_id, + size_t signer_id_size, + const uint8_t *version, + size_t version_size, + uint32_t measurement_algo, + const uint8_t *sw_type, + size_t sw_type_size, + const uint8_t *measurement_value, + size_t measurement_value_size, + bool lock_measurement); + +/** + * Retrieves a measurement from the requested slot. + * + * index Slot number from which measurement is to be + * retrieved. + * signer_id Pointer to signer_id buffer. + * signer_id_size Size of the signer_id buffer in bytes. + * signer_id_len On success, number of bytes that make up + * signer_id. + * version Pointer to version buffer. + * version_size Size of the version buffer in bytes. + * version_len On success, number of bytes that makeup the + * version. + * measurement_algo Pointer to measurement_algo. + * sw_type Pointer to sw_type buffer. + * sw_type_size Size of the sw_type buffer in bytes. + * sw_type_len On success, number of bytes that makeup the + * sw_type. + * measurement_value Pointer to measurement_value buffer. + * measurement_value_size Size of the measurement_value buffer in bytes. + * measurement_value_len On success, number of bytes that make up the + * measurement_value. + * is_locked Pointer to lock status of requested measurement + * slot. + * + * PSA_SUCCESS + * - Success. + * PSA_ERROR_INVALID_ARGUMENT + * - The size of at least one of the output buffers is incorrect or the + * requested slot index is invalid. + * PSA_ERROR_DOES_NOT_EXIST + * - The requested slot is empty, does not contain a measurement. + */ +psa_status_t rss_measured_boot_read_measurement(uint8_t index, + uint8_t *signer_id, + size_t signer_id_size, + size_t *signer_id_len, + uint8_t *version, + size_t version_size, + size_t *version_len, + uint32_t *measurement_algo, + uint8_t *sw_type, + size_t sw_type_size, + size_t *sw_type_len, + uint8_t *measurement_value, + size_t measurement_value_size, + size_t *measurement_value_len, + bool *is_locked); + +#endif /* PSA_MEASURED_BOOT_H */ diff --git a/include/lib/psa/psa/client.h b/include/lib/psa/psa/client.h new file mode 100644 index 0000000000..46fac4a8d4 --- /dev/null +++ b/include/lib/psa/psa/client.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2018-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PSA_CLIENT_H +#define PSA_CLIENT_H + +#include <stddef.h> +#include <stdint.h> + +#include <psa/error.h> + +#ifndef IOVEC_LEN +#define IOVEC_LEN(arr) ((uint32_t)(sizeof(arr)/sizeof(arr[0]))) +#endif + +/*********************** PSA Client Macros and Types *************************/ + +/** + * The version of the PSA Framework API that is being used to build the calling + * firmware. Only part of features of FF-M v1.1 have been implemented. FF-M v1.1 + * is compatible with v1.0. + */ +#define PSA_FRAMEWORK_VERSION (0x0101u) + +/** + * Return value from psa_version() if the requested RoT Service is not present + * in the system. + */ +#define PSA_VERSION_NONE (0u) + +/** + * The zero-value null handle can be assigned to variables used in clients and + * RoT Services, indicating that there is no current connection or message. + */ +#define PSA_NULL_HANDLE ((psa_handle_t)0) + +/** + * Tests whether a handle value returned by psa_connect() is valid. + */ +#define PSA_HANDLE_IS_VALID(handle) ((psa_handle_t)(handle) > 0) + +/** + * Converts the handle value returned from a failed call psa_connect() into + * an error code. + */ +#define PSA_HANDLE_TO_ERROR(handle) ((psa_status_t)(handle)) + +/** + * Maximum number of input and output vectors for a request to psa_call(). + */ +#define PSA_MAX_IOVEC (4u) + +/** + * The minimum and maximum value that can be passed + * as the type parameter in a call to psa_call(). + */ +#define PSA_CALL_TYPE_MIN (0) +#define PSA_CALL_TYPE_MAX (INT16_MAX) + +/** + * An IPC message type that indicates a generic client request. + */ +#define PSA_IPC_CALL (0) +typedef int32_t psa_handle_t; + +/** + * A read-only input memory region provided to an RoT Service. + */ +typedef struct psa_invec { + const void *base; /*!< the start address of the memory buffer */ + size_t len; /*!< the size in bytes */ +} psa_invec; + +/** + * A writable output memory region provided to an RoT Service. + */ +typedef struct psa_outvec { + void *base; /*!< the start address of the memory buffer */ + size_t len; /*!< the size in bytes */ +} psa_outvec; + +/** + * Call an RoT Service on an established connection. + * + * handle A handle to an established connection. + * type The request type. Must be zero(PSA_IPC_CALL) or positive. + * in_vec Array of input psa_invec structures. + * in_len Number of input psa_invec structures. + * out_vec Array of output psa_outvec structures. + * out_len Number of output psa_outvec structures. + * + * Return value >=0 RoT Service-specific status value. + * Return value <0 RoT Service-specific error code. + * + * PSA_ERROR_PROGRAMMER_ERROR: + * - The connection has been terminated by the RoT Service. + * + * The call is a PROGRAMMER ERROR if one or more of the following are true: + * - An invalid handle was passed. + * - The connection is already handling a request. + * - type < 0. + * - An invalid memory reference was provided. + * - in_len + out_len > PSA_MAX_IOVEC. + * - The message is unrecognized by the RoT. + * - Service or incorrectly formatted. + */ +psa_status_t psa_call(psa_handle_t handle, + int32_t type, + const psa_invec *in_vec, + size_t in_len, + psa_outvec *out_vec, + size_t out_len); + +#endif /* PSA_CLIENT_H */ diff --git a/include/lib/psa/psa/error.h b/include/lib/psa/psa/error.h new file mode 100644 index 0000000000..8a6eb7be7c --- /dev/null +++ b/include/lib/psa/psa/error.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2019-2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PSA_ERROR_H +#define PSA_ERROR_H + +#include <stdint.h> + +typedef int32_t psa_status_t; + +#define PSA_SUCCESS ((psa_status_t)0) +#define PSA_SUCCESS_REBOOT ((psa_status_t)1) +#define PSA_SUCCESS_RESTART ((psa_status_t)2) +#define PSA_ERROR_PROGRAMMER_ERROR ((psa_status_t)-129) +#define PSA_ERROR_CONNECTION_REFUSED ((psa_status_t)-130) +#define PSA_ERROR_CONNECTION_BUSY ((psa_status_t)-131) +#define PSA_ERROR_GENERIC_ERROR ((psa_status_t)-132) +#define PSA_ERROR_NOT_PERMITTED ((psa_status_t)-133) +#define PSA_ERROR_NOT_SUPPORTED ((psa_status_t)-134) +#define PSA_ERROR_INVALID_ARGUMENT ((psa_status_t)-135) +#define PSA_ERROR_INVALID_HANDLE ((psa_status_t)-136) +#define PSA_ERROR_BAD_STATE ((psa_status_t)-137) +#define PSA_ERROR_BUFFER_TOO_SMALL ((psa_status_t)-138) +#define PSA_ERROR_ALREADY_EXISTS ((psa_status_t)-139) +#define PSA_ERROR_DOES_NOT_EXIST ((psa_status_t)-140) +#define PSA_ERROR_INSUFFICIENT_MEMORY ((psa_status_t)-141) +#define PSA_ERROR_INSUFFICIENT_STORAGE ((psa_status_t)-142) +#define PSA_ERROR_INSUFFICIENT_DATA ((psa_status_t)-143) +#define PSA_ERROR_SERVICE_FAILURE ((psa_status_t)-144) +#define PSA_ERROR_COMMUNICATION_FAILURE ((psa_status_t)-145) +#define PSA_ERROR_STORAGE_FAILURE ((psa_status_t)-146) +#define PSA_ERROR_HARDWARE_FAILURE ((psa_status_t)-147) +#define PSA_ERROR_INVALID_SIGNATURE ((psa_status_t)-149) +#define PSA_ERROR_DEPENDENCY_NEEDED ((psa_status_t)-156) +#define PSA_ERROR_CURRENTLY_INSTALLING ((psa_status_t)-157) + +#endif /* PSA_ERROR_H */ diff --git a/include/lib/psa/psa_manifest/sid.h b/include/lib/psa/psa_manifest/sid.h new file mode 100644 index 0000000000..6c1565641a --- /dev/null +++ b/include/lib/psa/psa_manifest/sid.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef PSA_MANIFEST_SID_H +#define PSA_MANIFEST_SID_H + +/******** RSS_SP_CRYPTO ********/ +#define RSS_CRYPTO_HANDLE (0x40000100U) + +/******** RSS_SP_PLATFORM ********/ +#define RSS_PLATFORM_SERVICE_HANDLE (0x40000105U) + +/******** PSA_SP_MEASURED_BOOT ********/ +#define RSS_MEASURED_BOOT_HANDLE (0x40000110U) + +/******** PSA_SP_DELEGATED_ATTESTATION ********/ +#define RSS_DELEGATED_SERVICE_HANDLE (0x40000111U) + +/******** PSA_SP_DICE_PROTECTION_ENVIRONMENT ********/ +#define RSS_DPE_SERVICE_HANDLE (0x40000112U) + +#endif /* PSA_MANIFEST_SID_H */ diff --git a/include/lib/psa/rss_crypto_defs.h b/include/lib/psa/rss_crypto_defs.h new file mode 100644 index 0000000000..301dc05f99 --- /dev/null +++ b/include/lib/psa/rss_crypto_defs.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef RSS_CRYPTO_DEFS_H +#define RSS_CRYPTO_DEFS_H + +/* Declares types that encode errors, algorithms, key types, policies, etc. */ +#include "psa/crypto_types.h" + +/* + * Value identifying export public key function API, used to dispatch the request + * to the corresponding API implementation in the Crypto service backend. + * + */ +#define RSS_CRYPTO_EXPORT_PUBLIC_KEY_SID (uint16_t)(0x701) + +/* + * The persistent key identifiers for RSS builtin keys. + */ +enum rss_key_id_builtin_t { + RSS_BUILTIN_KEY_ID_HOST_S_ROTPK = 0x7FFF816Cu, + RSS_BUILTIN_KEY_ID_HOST_NS_ROTPK, + RSS_BUILTIN_KEY_ID_HOST_CCA_ROTPK, +}; + +/* + * This type is used to overcome a limitation within RSS firmware in the number of maximum + * IOVECs it can use especially in psa_aead_encrypt and psa_aead_decrypt. + */ +#define RSS_CRYPTO_MAX_NONCE_LENGTH (16u) +struct rss_crypto_aead_pack_input { + uint8_t nonce[RSS_CRYPTO_MAX_NONCE_LENGTH]; + uint32_t nonce_length; +}; + +/* + * Structure used to pack non-pointer types in a call to PSA Crypto APIs + */ +struct rss_crypto_pack_iovec { + psa_key_id_t key_id; /* !< Key id */ + psa_algorithm_t alg; /* !< Algorithm */ + uint32_t op_handle; /* + * !< Frontend context handle + * associated to a multipart operation + */ + uint32_t ad_length; /* + * !< Additional Data length for + * multipart AEAD + */ + uint32_t plaintext_length; /* + * !< Plaintext length for multipart + * AEAD + */ + + struct rss_crypto_aead_pack_input aead_in; /* + * !< Packs AEAD-related + * inputs + */ + + uint16_t function_id; /* + * !< Used to identify the function in the + * API dispatcher to the service backend + * See rss_crypto_func_sid for detail + */ + uint16_t step; /* !< Key derivation step */ + union { + size_t capacity; /* !< Key derivation capacity */ + uint64_t value; /* + * !< Key derivation integer for + * update + */ + }; +}; + +#endif /* RSS_CRYPTO_DEFS_H */ diff --git a/include/lib/psa/rss_platform_api.h b/include/lib/psa/rss_platform_api.h new file mode 100644 index 0000000000..8f74a51fd4 --- /dev/null +++ b/include/lib/psa/rss_platform_api.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef RSS_PLATFORM_API_H +#define RSS_PLATFORM_API_H + +#include <stdint.h> + +#include "psa/error.h" +#include <rss_crypto_defs.h> + +#define RSS_PLATFORM_API_ID_NV_READ (1010) +#define RSS_PLATFORM_API_ID_NV_INCREMENT (1011) + +/* + * Increments the given non-volatile (NV) counter by one + * + * counter_id NV counter ID. + * + * PSA_SUCCESS if the value is read correctly. Otherwise, + * it returns a PSA_ERROR. + */ +psa_status_t +rss_platform_nv_counter_increment(uint32_t counter_id); + +/* + * Reads the given non-volatile (NV) counter + * + * counter_id NV counter ID. + * size Size of the buffer to store NV counter value + * in bytes. + * val Pointer to store the current NV counter value. + * + * PSA_SUCCESS if the value is read correctly. Otherwise, + * it returns a PSA_ERROR. + */ +psa_status_t +rss_platform_nv_counter_read(uint32_t counter_id, + uint32_t size, uint8_t *val); + +/* + * Reads the public key or the public part of a key pair in binary format. + * + * key Identifier of the key to export. + * data Buffer where the key data is to be written. + * data_size Size of the data buffer in bytes. + * data_length On success, the number of bytes that make up the key data. + * + * PSA_SUCCESS if the value is read correctly. Otherwise, + * it returns a PSA_ERROR. + */ +psa_status_t +rss_platform_key_read(enum rss_key_id_builtin_t key, uint8_t *data, + size_t data_size, size_t *data_length); + +#endif /* RSS_PLATFORM_API_H */ diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index b56e98b5f3..c40f955f0a 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -59,6 +60,7 @@ #define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) #define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) #define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) +#define PSCI_SET_SUSPEND_MODE U(0x8400000F) #define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) #define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) #define PSCI_STAT_COUNT_AARCH32 U(0x84000011) @@ -73,9 +75,17 @@ * Number of PSCI calls (above) implemented */ #if ENABLE_PSCI_STAT -#define PSCI_NUM_CALLS U(22) +#if PSCI_OS_INIT_MODE +#define PSCI_NUM_CALLS U(30) #else -#define PSCI_NUM_CALLS U(18) +#define PSCI_NUM_CALLS U(29) +#endif +#else +#if PSCI_OS_INIT_MODE +#define PSCI_NUM_CALLS U(26) +#else +#define PSCI_NUM_CALLS U(25) +#endif #endif /* The macros below are used to identify PSCI calls from the SMC function ID */ @@ -134,7 +144,11 @@ /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ #define FF_MODE_SUPPORT_SHIFT U(0) +#if PSCI_OS_INIT_MODE #define FF_SUPPORTS_OS_INIT_MODE U(1) +#else +#define FF_SUPPORTS_OS_INIT_MODE U(0) +#endif /******************************************************************************* * PSCI version @@ -268,6 +282,13 @@ typedef struct psci_power_state { * for the CPU. */ plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; +#if PSCI_OS_INIT_MODE + /* + * The highest power level at which the current CPU is the last running + * CPU. + */ + unsigned int last_at_pwrlvl; +#endif } psci_power_state_t; /******************************************************************************* @@ -297,6 +318,11 @@ typedef struct plat_psci_ops { void (*cpu_standby)(plat_local_state_t cpu_state); int (*pwr_domain_on)(u_register_t mpidr); void (*pwr_domain_off)(const psci_power_state_t *target_state); + int (*pwr_domain_off_early)(const psci_power_state_t *target_state); +#if PSCI_OS_INIT_MODE + int (*pwr_domain_validate_suspend)( + const psci_power_state_t *target_state); +#endif void (*pwr_domain_suspend_pwrdown_early)( const psci_power_state_t *target_state); void (*pwr_domain_suspend)(const psci_power_state_t *target_state); @@ -347,6 +373,9 @@ u_register_t psci_migrate_info_up_cpu(void); int psci_node_hw_state(u_register_t target_cpu, unsigned int power_level); int psci_features(unsigned int psci_fid); +#if PSCI_OS_INIT_MODE +int psci_set_suspend_mode(unsigned int mode); +#endif void __dead2 psci_power_down_wfi(void); void psci_arch_setup(void); diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h index 1ac45adf79..c50f8cbb1d 100644 --- a/include/lib/psci/psci_lib.h +++ b/include/lib/psci/psci_lib.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -91,6 +91,11 @@ void psci_prepare_next_non_secure_ctx( entry_point_info_t *next_image_info); int psci_stop_other_cores(unsigned int wait_ms, void (*stop_func)(u_register_t mpidr)); +bool psci_is_last_on_cpu_safe(void); +bool psci_are_all_cpus_on_safe(void); +void psci_pwrdown_cpu(unsigned int power_level); +void psci_do_manage_extensions(void); + #endif /* __ASSEMBLER__ */ #endif /* PSCI_LIB_H */ diff --git a/include/lib/runtime_instr.h b/include/lib/runtime_instr.h index 303f27e5bf..65fafa795f 100644 --- a/include/lib/runtime_instr.h +++ b/include/lib/runtime_instr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h index 24b030cfdd..5c72e8bf33 100644 --- a/include/lib/semihosting.h +++ b/include/lib/semihosting.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 470317dd00..c4931058df 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,7 @@ SMCCC_VERSION_MINOR_SHIFT)) #define SMCCC_MAJOR_VERSION U(1) -#define SMCCC_MINOR_VERSION U(2) +#define SMCCC_MINOR_VERSION U(4) /******************************************************************************* * Bit definitions inside the function id as per the SMC calling convention @@ -37,10 +37,20 @@ #define FUNCID_OEN_MASK U(0x3f) #define FUNCID_OEN_WIDTH U(6) +#define FUNCID_FC_RESERVED_SHIFT U(17) +#define FUNCID_FC_RESERVED_MASK U(0x7f) +#define FUNCID_FC_RESERVED_WIDTH U(7) + +#define FUNCID_SVE_HINT_SHIFT U(16) +#define FUNCID_SVE_HINT_MASK U(1) +#define FUNCID_SVE_HINT_WIDTH U(1) + #define FUNCID_NUM_SHIFT U(0) #define FUNCID_NUM_MASK U(0xffff) #define FUNCID_NUM_WIDTH U(16) +#define FUNCID_MASK U(0xffffffff) + #define GET_SMC_NUM(id) (((id) >> FUNCID_NUM_SHIFT) & \ FUNCID_NUM_MASK) #define GET_SMC_TYPE(id) (((id) >> FUNCID_TYPE_SHIFT) & \ @@ -51,6 +61,23 @@ FUNCID_OEN_MASK) /******************************************************************************* + * SMCCC_ARCH_SOC_ID SoC version & revision bit definition + ******************************************************************************/ +#define SOC_ID_JEP_106_BANK_IDX_MASK GENMASK_32(30, 24) +#define SOC_ID_JEP_106_BANK_IDX_SHIFT U(24) +#define SOC_ID_JEP_106_ID_CODE_MASK GENMASK_32(23, 16) +#define SOC_ID_JEP_106_ID_CODE_SHIFT U(16) +#define SOC_ID_IMPL_DEF_MASK GENMASK_32(15, 0) +#define SOC_ID_IMPL_DEF_SHIFT U(0) +#define SOC_ID_SET_JEP_106(bkid, mfid) ((((bkid) << SOC_ID_JEP_106_BANK_IDX_SHIFT) & \ + SOC_ID_JEP_106_BANK_IDX_MASK) | \ + (((mfid) << SOC_ID_JEP_106_ID_CODE_SHIFT) & \ + SOC_ID_JEP_106_ID_CODE_MASK)) + +#define SOC_ID_REV_MASK GENMASK_32(30, 0) +#define SOC_ID_REV_SHIFT U(0) + +/******************************************************************************* * Owning entity number definitions inside the function id as per the SMC * calling convention ******************************************************************************/ @@ -84,6 +111,8 @@ #define SMC_OK ULL(0) #define SMC_UNK -1 #define SMC_PREEMPTED -2 /* Not defined by the SMCCC */ +#define SMC_DENIED -3 /* Not defined by the SMCCC */ +#define SMC_INVALID_PARAM -4 /* Not defined by the SMCCC */ /* Return codes for Arm Architecture Service SMC calls */ #define SMC_ARCH_CALL_SUCCESS 0 @@ -91,9 +120,30 @@ #define SMC_ARCH_CALL_NOT_REQUIRED -2 #define SMC_ARCH_CALL_INVAL_PARAM -3 -/* Various flags passed to SMC handlers */ +/* + * Various flags passed to SMC handlers + * + * Bit 5 and bit 0 of the flag are used to + * determine the source security state as + * follows: + * --------------------------------- + * Bit 5 | Bit 0 | Security state + * --------------------------------- + * 0 0 SMC_FROM_SECURE + * 0 1 SMC_FROM_NON_SECURE + * 1 1 SMC_FROM_REALM + * + * Bit 16 of flags records the caller's SMC + * SVE hint bit according to SMCCCv1.3. + * It can be consumed by dispatchers using + * is_sve_hint_set macro. + * + */ + #define SMC_FROM_SECURE (U(0) << 0) #define SMC_FROM_NON_SECURE (U(1) << 0) +#define SMC_FROM_REALM U(0x21) +#define SMC_FROM_MASK U(0x21) #ifndef __ASSEMBLER__ @@ -101,8 +151,21 @@ #include <lib/cassert.h> +#if ENABLE_RME +#define is_caller_non_secure(_f) (((_f) & SMC_FROM_MASK) \ + == SMC_FROM_NON_SECURE) +#define is_caller_secure(_f) (((_f) & SMC_FROM_MASK) \ + == SMC_FROM_SECURE) +#define is_caller_realm(_f) (((_f) & SMC_FROM_MASK) \ + == SMC_FROM_REALM) +#define caller_sec_state(_f) ((_f) & SMC_FROM_MASK) +#else /* ENABLE_RME */ #define is_caller_non_secure(_f) (((_f) & SMC_FROM_NON_SECURE) != U(0)) #define is_caller_secure(_f) (!is_caller_non_secure(_f)) +#endif /* ENABLE_RME */ + +#define is_sve_hint_set(_f) (((_f) & (FUNCID_SVE_HINT_MASK \ + << FUNCID_SVE_HINT_SHIFT)) != U(0)) /* The macro below is used to identify a Standard Service SMC call */ #define is_std_svc_call(_fid) (GET_SMC_OEN(_fid) == OEN_STD_START) diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h index 0bf3ee066f..9fd3fc65fe 100644 --- a/include/lib/spinlock.h +++ b/include/lib/spinlock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h new file mode 100644 index 0000000000..5ea5a41a95 --- /dev/null +++ b/include/lib/transfer_list.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __TRANSFER_LIST_H +#define __TRANSFER_LIST_H + +#include <stdbool.h> +#include <stdint.h> + +#include <common/ep_info.h> +#include <lib/utils_def.h> + +#define TRANSFER_LIST_SIGNATURE U(0x4a0fb10b) +#define TRANSFER_LIST_VERSION U(0x0001) + +/* + * Init value of maximum alignment required by any TE data in the TL + * specified as a power of two + */ +#define TRANSFER_LIST_INIT_MAX_ALIGN U(3) + +/* Alignment required by TE header start address, in bytes */ +#define TRANSFER_LIST_GRANULE U(8) + +/* + * Version of the register convention used. + * Set to 1 for both AArch64 and AArch32 according to fw handoff spec v0.9 + */ +#define REGISTER_CONVENTION_VERSION_MASK (1 << 24) + +#ifndef __ASSEMBLER__ + +#define TL_FLAGS_HAS_CHECKSUM BIT(0) + +enum transfer_list_tag_id { + TL_TAG_EMPTY = 0, + TL_TAG_FDT = 1, + TL_TAG_HOB_BLOCK = 2, + TL_TAG_HOB_LIST = 3, + TL_TAG_ACPI_TABLE_AGGREGATE = 4, + TL_TAG_OPTEE_PAGABLE_PART = 0x100, +}; + +enum transfer_list_ops { + TL_OPS_NON, /* invalid for any operation */ + TL_OPS_ALL, /* valid for all operations */ + TL_OPS_RO, /* valid for read only */ + TL_OPS_CUS, /* abort or switch to special code to interpret */ +}; + +struct transfer_list_header { + uint32_t signature; + uint8_t checksum; + uint8_t version; + uint8_t hdr_size; + uint8_t alignment; /* max alignment of TE data */ + uint32_t size; /* TL header + all TEs */ + uint32_t max_size; + uint32_t flags; + uint32_t reserved; /* spare bytes */ + /* + * Commented out element used to visualize dynamic part of the + * data structure. + * + * Note that struct transfer_list_entry also is dynamic in size + * so the elements can't be indexed directly but instead must be + * traversed in order + * + * struct transfer_list_entry entries[]; + */ +}; + +struct transfer_list_entry { + uint16_t tag_id; + uint8_t reserved0; /* place holder */ + uint8_t hdr_size; + uint32_t data_size; + /* + * Commented out element used to visualize dynamic part of the + * data structure. + * + * Note that padding is added at the end of @data to make to reach + * a 8-byte boundary. + * + * uint8_t data[ROUNDUP(data_size, 8)]; + */ +}; + +void transfer_list_dump(struct transfer_list_header *tl); +entry_point_info_t * +transfer_list_set_handoff_args(struct transfer_list_header *tl, + entry_point_info_t *ep_info); +struct transfer_list_header *transfer_list_init(void *addr, size_t max_size); + +struct transfer_list_header * +transfer_list_relocate(struct transfer_list_header *tl, void *addr, + size_t max_size); +enum transfer_list_ops +transfer_list_check_header(const struct transfer_list_header *tl); + +void transfer_list_update_checksum(struct transfer_list_header *tl); +bool transfer_list_verify_checksum(const struct transfer_list_header *tl); + +bool transfer_list_set_data_size(struct transfer_list_header *tl, + struct transfer_list_entry *entry, + uint32_t new_data_size); + +void *transfer_list_entry_data(struct transfer_list_entry *entry); +bool transfer_list_rem(struct transfer_list_header *tl, + struct transfer_list_entry *entry); + +struct transfer_list_entry *transfer_list_add(struct transfer_list_header *tl, + uint16_t tag_id, + uint32_t data_size, + const void *data); + +struct transfer_list_entry * +transfer_list_add_with_align(struct transfer_list_header *tl, uint16_t tag_id, + uint32_t data_size, const void *data, + uint8_t alignment); + +struct transfer_list_entry * +transfer_list_next(struct transfer_list_header *tl, + struct transfer_list_entry *last); + +struct transfer_list_entry *transfer_list_find(struct transfer_list_header *tl, + uint16_t tag_id); + +#endif /*__ASSEMBLER__*/ +#endif /*__TRANSFER_LIST_H*/ diff --git a/include/lib/utils.h b/include/lib/utils.h index 17ee93694e..ce76de24f3 100644 --- a/include/lib/utils.h +++ b/include/lib/utils.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 7a7012d3d1..8a03c7db99 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -53,6 +53,9 @@ #define GENMASK GENMASK_32 #endif +#define HI(addr) (addr >> 32) +#define LO(addr) (addr & 0xffffffff) + /* * This variant of div_round_up can be used in macro definition but should not * be used in C code as the `div` parameter is evaluated twice. @@ -68,14 +71,14 @@ __typeof__(x) _x = (x); \ __typeof__(y) _y = (y); \ (void)(&_x == &_y); \ - _x < _y ? _x : _y; \ + (_x < _y) ? _x : _y; \ }) #define MAX(x, y) __extension__ ({ \ __typeof__(x) _x = (x); \ __typeof__(y) _y = (y); \ (void)(&_x == &_y); \ - _x > _y ? _x : _y; \ + (_x > _y) ? _x : _y; \ }) #define CLAMP(x, min, max) __extension__ ({ \ @@ -84,7 +87,7 @@ __typeof__(max) _max = (max); \ (void)(&_x == &_min); \ (void)(&_x == &_max); \ - (_x > _max ? _max : (_x < _min ? _min : _x)); \ + ((_x > _max) ? _max : ((_x < _min) ? _min : _x)); \ }) /* @@ -104,6 +107,48 @@ #define round_down(value, boundary) \ ((value) & ~round_boundary(value, boundary)) +/* add operation together with checking whether the operation overflowed + * The result is '*res', + * return 0 on success and 1 on overflow + */ +#define add_overflow(a, b, res) __builtin_add_overflow((a), (b), (res)) + +/* + * Round up a value to align with a given size and + * check whether overflow happens. + * The rounduped value is '*res', + * return 0 on success and 1 on overflow + */ +#define round_up_overflow(v, size, res) (__extension__({ \ + typeof(res) __res = res; \ + typeof(*(__res)) __roundup_tmp = 0; \ + typeof(v) __roundup_mask = (typeof(v))(size) - 1; \ + \ + add_overflow((v), __roundup_mask, &__roundup_tmp) ? 1 : \ + (void)(*(__res) = __roundup_tmp & ~__roundup_mask), 0; \ +})) + +/* + * Add a with b, then round up the result to align with a given size and + * check whether overflow happens. + * The rounduped value is '*res', + * return 0 on success and 1 on overflow + */ +#define add_with_round_up_overflow(a, b, size, res) (__extension__({ \ + typeof(a) __a = (a); \ + typeof(__a) __add_res = 0; \ + \ + add_overflow((__a), (b), &__add_res) ? 1 : \ + round_up_overflow(__add_res, (size), (res)) ? 1 : 0; \ +})) + +/** + * Helper macro to ensure a value lies on a given boundary. + */ +#define is_aligned(value, boundary) \ + (round_up((uintptr_t) value, boundary) == \ + round_down((uintptr_t) value, boundary)) + /* * Evaluates to 1 if (ptr + inc) overflows, 0 otherwise. * Both arguments must be unsigned pointer values (i.e. uintptr_t). diff --git a/include/lib/xlat_mpu/xlat_mpu.h b/include/lib/xlat_mpu/xlat_mpu.h new file mode 100644 index 0000000000..3a470ad718 --- /dev/null +++ b/include/lib/xlat_mpu/xlat_mpu.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef XLAT_MPU_H +#define XLAT_MPU_H + +#ifndef __ASSEMBLER__ + +#include <lib/cassert.h> + +#define XLAT_TABLES_LIB_V2 1 + +void enable_mpu_el2(unsigned int flags); +void enable_mpu_direct_el2(unsigned int flags); + +/* + * Function to wipe clean and disable all MPU regions. This function expects + * that the MPU has already been turned off, and caching concerns addressed, + * but it nevertheless also explicitly turns off the MPU. + */ +void clear_all_mpu_regions(void); + +#endif /* __ASSEMBLER__ */ +#endif /* XLAT_MPU_H */ diff --git a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h index 30eb5e9ec4..42a48f437b 100644 --- a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h +++ b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h index 3014c8fea4..6c0d73bf59 100644 --- a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h +++ b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h index 269afd2878..fabc494604 100644 --- a/include/lib/xlat_tables/xlat_mmu_helpers.h +++ b/include/lib/xlat_tables/xlat_mmu_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h index 082bb5e454..24f833cd17 100644 --- a/include/lib/xlat_tables/xlat_tables.h +++ b/include/lib/xlat_tables/xlat_tables.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -72,6 +72,13 @@ #define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) #define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER) +/* Memory type for EL3 regions */ +#if ENABLE_RME +#error FEAT_RME requires version 2 of the Translation Tables Library +#else +#define EL3_PAS MT_SECURE +#endif + /* * Structure for specifying a single region of memory. */ diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h index 0ce0cacb45..46e058cfb3 100644 --- a/include/lib/xlat_tables/xlat_tables_arch.h +++ b/include/lib/xlat_tables/xlat_tables_arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/xlat_tables/xlat_tables_compat.h b/include/lib/xlat_tables/xlat_tables_compat.h index 90768db5db..3877c91d19 100644 --- a/include/lib/xlat_tables/xlat_tables_compat.h +++ b/include/lib/xlat_tables/xlat_tables_compat.h @@ -1,11 +1,16 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#ifndef XLAT_TABLES_COMPAT_H +#define XLAT_TABLES_COMPAT_H + #if XLAT_TABLES_LIB_V2 #include <lib/xlat_tables/xlat_tables_v2.h> #else #include <lib/xlat_tables/xlat_tables.h> #endif + +#endif /* XLAT_TABLES_COMPAT_H */ diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 579d8d89cf..2d0949b517 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -142,6 +142,7 @@ #define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4) #define AP_ONE_VA_RANGE_RES1 (AP1_RES1 << 4) #define NS (U(0x1) << 3) +#define EL3_S1_NSE (U(0x1) << 9) #define ATTR_NON_CACHEABLE_INDEX ULL(0x2) #define ATTR_DEVICE_INDEX ULL(0x1) #define ATTR_IWBWA_OWBWA_NTR_INDEX ULL(0x0) diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 359b9839a9..64fe5ef8e4 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -60,17 +60,22 @@ #define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) /* Access permissions (RO/RW) */ #define MT_PERM_SHIFT U(3) -/* Security state (SECURE/NS) */ -#define MT_SEC_SHIFT U(4) + +/* Physical address space (SECURE/NS/Root/Realm) */ +#define MT_PAS_SHIFT U(4) +#define MT_PAS_MASK (U(3) << MT_PAS_SHIFT) +#define MT_PAS(_attr) ((_attr) & MT_PAS_MASK) + /* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ -#define MT_EXECUTE_SHIFT U(5) +#define MT_EXECUTE_SHIFT U(6) /* In the EL1&0 translation regime, User (EL0) or Privileged (EL1). */ -#define MT_USER_SHIFT U(6) +#define MT_USER_SHIFT U(7) /* Shareability attribute for the memory region */ -#define MT_SHAREABILITY_SHIFT U(7) +#define MT_SHAREABILITY_SHIFT U(8) #define MT_SHAREABILITY_MASK (U(3) << MT_SHAREABILITY_SHIFT) #define MT_SHAREABILITY(_attr) ((_attr) & MT_SHAREABILITY_MASK) + /* All other bits are reserved */ /* @@ -91,8 +96,10 @@ #define MT_RO (U(0) << MT_PERM_SHIFT) #define MT_RW (U(1) << MT_PERM_SHIFT) -#define MT_SECURE (U(0) << MT_SEC_SHIFT) -#define MT_NS (U(1) << MT_SEC_SHIFT) +#define MT_SECURE (U(0) << MT_PAS_SHIFT) +#define MT_NS (U(1) << MT_PAS_SHIFT) +#define MT_ROOT (U(2) << MT_PAS_SHIFT) +#define MT_REALM (U(3) << MT_PAS_SHIFT) /* * Access permissions for instruction execution are only relevant for normal @@ -149,6 +156,13 @@ typedef struct mmap_region { #define EL3_REGIME 3 #define EL_REGIME_INVALID -1 +/* Memory type for EL3 regions. With RME, EL3 is in ROOT PAS */ +#if ENABLE_RME +#define EL3_PAS MT_ROOT +#else +#define EL3_PAS MT_SECURE +#endif /* ENABLE_RME */ + /* * Declare the translation context type. * Its definition is private. @@ -189,7 +203,7 @@ typedef struct xlat_ctx xlat_ctx_t; (_virt_addr_space_size), \ (_phy_addr_space_size), \ EL_REGIME_INVALID, \ - "xlat_table", "base_xlat_table") + ".xlat_table", ".base_xlat_table") /* * Same as REGISTER_XLAT_CONTEXT plus the additional parameters: diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h index 62f853d18c..992c94e589 100644 --- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h +++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/lib/zlib/tf_gunzip.h b/include/lib/zlib/tf_gunzip.h index 741ba50142..94358608e1 100644 --- a/include/lib/zlib/tf_gunzip.h +++ b/include/lib/zlib/tf_gunzip.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/plat/arm/board/common/rotpk/rotpk_def.h b/include/plat/arm/board/common/rotpk/rotpk_def.h new file mode 100644 index 0000000000..685c21a607 --- /dev/null +++ b/include/plat/arm/board/common/rotpk/rotpk_def.h @@ -0,0 +1,24 @@ + +/* + * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ROTPK_DEF_H +#define ROTPK_DEF_H + +/* + * Definitions related to ROTPK + */ + +/* + * Root of trust key lengths + */ +#ifndef ARM_ROTPK_HEADER_LEN +#define ARM_ROTPK_HEADER_LEN 19 +#endif +#ifndef ARM_ROTPK_HASH_LEN +#define ARM_ROTPK_HASH_LEN 32 +#endif +#endif /* ROTPK_DEF_H */ diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h index 6a6979c9c3..cb11dac476 100644 --- a/include/plat/arm/board/common/v2m_def.h +++ b/include/plat/arm/board/common/v2m_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,13 @@ #include <lib/utils_def.h> +/* Base address of all V2M */ +#ifdef PLAT_V2M_OFFSET +#define V2M_OFFSET PLAT_V2M_OFFSET +#else +#define V2M_OFFSET UL(0) +#endif + /* V2M motherboard system registers & offsets */ #define V2M_SYSREGS_BASE UL(0x1c010000) #define V2M_SYS_ID UL(0x0) @@ -69,18 +76,18 @@ /* NOR Flash */ -#define V2M_FLASH0_BASE UL(0x08000000) +#define V2M_FLASH0_BASE (V2M_OFFSET + UL(0x08000000)) #define V2M_FLASH0_SIZE UL(0x04000000) -#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ +#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ -#define V2M_IOFPGA_BASE UL(0x1c000000) +#define V2M_IOFPGA_BASE (V2M_OFFSET + UL(0x1c000000)) #define V2M_IOFPGA_SIZE UL(0x03000000) /* PL011 UART related constants */ -#define V2M_IOFPGA_UART0_BASE UL(0x1c090000) -#define V2M_IOFPGA_UART1_BASE UL(0x1c0a0000) -#define V2M_IOFPGA_UART2_BASE UL(0x1c0b0000) -#define V2M_IOFPGA_UART3_BASE UL(0x1c0c0000) +#define V2M_IOFPGA_UART0_BASE (V2M_OFFSET + UL(0x1c090000)) +#define V2M_IOFPGA_UART1_BASE (V2M_OFFSET + UL(0x1c0a0000)) +#define V2M_IOFPGA_UART2_BASE (V2M_OFFSET + UL(0x1c0b0000)) +#define V2M_IOFPGA_UART3_BASE (V2M_OFFSET + UL(0x1c0c0000)) #define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 #define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 @@ -88,11 +95,11 @@ #define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 /* SP804 timer related constants */ -#define V2M_SP804_TIMER0_BASE UL(0x1C110000) -#define V2M_SP804_TIMER1_BASE UL(0x1C120000) +#define V2M_SP804_TIMER0_BASE (V2M_OFFSET + UL(0x1C110000)) +#define V2M_SP804_TIMER1_BASE (V2M_OFFSET + UL(0x1C120000)) /* SP810 controller */ -#define V2M_SP810_BASE UL(0x1c020000) +#define V2M_SP810_BASE (V2M_OFFSET + UL(0x1c020000)) #define V2M_SP810_CTRL_TIM0_SEL BIT_32(15) #define V2M_SP810_CTRL_TIM1_SEL BIT_32(17) #define V2M_SP810_CTRL_TIM2_SEL BIT_32(19) diff --git a/include/plat/arm/board/fvp_r/fvp_r_bl1.h b/include/plat/arm/board/fvp_r/fvp_r_bl1.h new file mode 100644 index 0000000000..0b41e672f0 --- /dev/null +++ b/include/plat/arm/board/fvp_r/fvp_r_bl1.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_R_BL1_H +#define FVP_R_BL1_H + +void bl1_load_bl33(void); +void bl1_transfer_bl33(void); + +#endif /* FVP_R_BL1_H */ diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S index d47e4e0969..8aacfb0a93 100644 --- a/include/plat/arm/common/aarch64/arm_macros.S +++ b/include/plat/arm/common/aarch64/arm_macros.S @@ -39,11 +39,17 @@ prefix: * --------------------------------------------- */ .macro arm_print_gic_regs - /* Check for GICv3 system register access */ + /* Check for GICv3/v4 system register access. + * ID_AA64PFR0_GIC indicates presence of the CPU + * system registers by either 0b0011 or 0xb0001. + * A value of 0b000 means CPU system registers aren't + * available and the code needs to use the memory + * mapped registers like in GICv2. + */ mrs x7, id_aa64pfr0_el1 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH - cmp x7, #1 - b.ne print_gicv2 + cmp x7, #0 + b.eq print_gicv2 /* Check for SRE enable */ mrs x8, ICC_SRE_EL3 diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 00746c6da0..c3a88e7cb7 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,7 @@ #include <drivers/arm/gic_common.h> #include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_defs.h> +#include <plat/arm/board/common/rotpk/rotpk_def.h> #include <plat/arm/common/smccc_def.h> #include <plat/common/common_def.h> @@ -19,11 +20,6 @@ * Definitions common to all ARM standard platforms *****************************************************************************/ -/* - * Root of trust key hash lengths - */ -#define ARM_ROTPK_HEADER_LEN 19 -#define ARM_ROTPK_HASH_LEN 32 /* Special value used to verify platform parameters from BL2 to BL31 */ #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) @@ -58,8 +54,12 @@ #define ARM_TRUSTED_DRAM_ID 1 #define ARM_DRAM_ID 2 -/* The first 4KB of Trusted SRAM are used as shared memory */ +#ifdef PLAT_ARM_TRUSTED_SRAM_BASE +#define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE +#else #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) +#endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ + #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ @@ -70,50 +70,129 @@ ARM_SHARED_RAM_SIZE) /* - * The top 16MB of DRAM1 is configured as secure access only using the TZC + * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as + * follows: * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled + * - REALM DRAM: Reserved for Realm world if RME is enabled + * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM + * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use - */ -#define ARM_TZC_DRAM1_SIZE UL(0x01000000) + * + * RME enabled(64MB) RME not enabled(16MB) + * -------------------- ------------------- + * | | | | + * | AP TZC (~28MB) | | AP TZC (~14MB) | + * -------------------- ------------------- + * | Event Log | | Event Log | + * | (4KB) | | (4KB) | + * -------------------- ------------------- + * | REALM (RMM) | | | + * | (32MB - 4KB) | | EL3 TZC (2MB) | + * -------------------- ------------------- + * | | | | + * | TF-A <-> RMM | | SCP TZC | + * | SHARED (4KB) | 0xFFFF_FFFF------------------- + * -------------------- + * | | + * | EL3 TZC (3MB) | + * -------------------- + * | L1 GPT + SCP TZC | + * | (~1MB) | + * 0xFFFF_FFFF -------------------- + */ +#if ENABLE_RME +#define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ +/* + * Define a region within the TZC secured DRAM for use by EL3 runtime + * firmware. This region is meant to be NOLOAD and will not be zero + * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be + * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. + */ +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ +#define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ +/* 32MB - ARM_EL3_RMM_SHARED_SIZE */ +#define ARM_REALM_SIZE (UL(0x02000000) - \ + ARM_EL3_RMM_SHARED_SIZE) +#define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ +#else +#define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ +#define ARM_L1_GPT_SIZE UL(0) +#define ARM_REALM_SIZE UL(0) +#define ARM_EL3_RMM_SHARED_SIZE UL(0) +#endif /* ENABLE_RME */ #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ - ARM_DRAM1_SIZE - \ - ARM_SCP_TZC_DRAM1_SIZE) + ARM_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_L1_GPT_SIZE)) #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ - ARM_SCP_TZC_DRAM1_SIZE - 1U) + ARM_SCP_TZC_DRAM1_SIZE - 1U) -/* - * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime - * firmware. This region is meant to be NOLOAD and will not be zero - * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be - * placed here. - */ -#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) -#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ +# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ +MEASURED_BOOT +#define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ + +#if ENABLE_RME +#define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ + ARM_EVENT_LOG_DRAM1_SIZE) +#else +#define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ + ARM_EVENT_LOG_DRAM1_SIZE) +#endif /* ENABLE_RME */ +#define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ + ARM_EVENT_LOG_DRAM1_SIZE - \ + 1U) +#else +#define ARM_EVENT_LOG_DRAM1_SIZE UL(0) +#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ + +#if ENABLE_RME +#define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + ARM_L1_GPT_SIZE) +#define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \ + ARM_L1_GPT_SIZE - 1U) + +#define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ + ARM_REALM_SIZE) + +#define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) + +#define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_L1_GPT_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE)) + +#define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ + ARM_EL3_RMM_SHARED_SIZE - 1U) +#endif /* ENABLE_RME */ + +#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ + ARM_EL3_TZC_DRAM1_SIZE) #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ ARM_EL3_TZC_DRAM1_SIZE - 1U) #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ - ARM_DRAM1_SIZE - \ - ARM_TZC_DRAM1_SIZE) + ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ - (ARM_SCP_TZC_DRAM1_SIZE + \ - ARM_EL3_TZC_DRAM1_SIZE)) + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE + \ + ARM_REALM_SIZE + \ + ARM_L1_GPT_SIZE + \ + ARM_EVENT_LOG_DRAM1_SIZE)) + #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ - ARM_AP_TZC_DRAM1_SIZE - 1U) + ARM_AP_TZC_DRAM1_SIZE - 1U) /* Define the Access permissions for Secure peripherals to NS_DRAM */ -#if ARM_CRYPTOCELL_INTEG -/* - * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. - * This is required by CryptoCell to authenticate BL33 which is loaded - * into the Non Secure DDR. - */ -#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD -#else #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE -#endif #ifdef SPD_opteed /* @@ -147,10 +226,15 @@ #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ ARM_TZC_DRAM1_SIZE) + #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ ARM_NS_DRAM1_SIZE - 1U) - +#ifdef PLAT_ARM_DRAM1_BASE +#define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE +#else #define ARM_DRAM1_BASE ULL(0x80000000) +#endif /* PLAT_ARM_DRAM1_BASE */ + #define ARM_DRAM1_SIZE ULL(0x80000000) #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1U) @@ -159,6 +243,8 @@ #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ ARM_DRAM2_SIZE - 1U) +/* Number of DRAM banks */ +#define ARM_DRAM_NUM_BANKS 2UL #define ARM_IRQ_SEC_PHY_TIMER 29 @@ -198,45 +284,76 @@ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ GIC_INTR_CFG_EDGE) -#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ - ARM_SHARED_RAM_BASE, \ - ARM_SHARED_RAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | EL3_PAS) -#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ - ARM_NS_DRAM1_BASE, \ - ARM_NS_DRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) -#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ - ARM_DRAM2_BASE, \ - ARM_DRAM2_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) +#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ + ARM_DRAM2_BASE, \ + ARM_DRAM2_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) -#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ - TSP_SEC_MEM_BASE, \ - TSP_SEC_MEM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) +#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ + TSP_SEC_MEM_BASE, \ + TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) #if ARM_BL31_IN_DRAM -#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ - BL31_BASE, \ - PLAT_ARM_MAX_BL31_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) +#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, \ + PLAT_ARM_MAX_BL31_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) #endif -#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ - ARM_EL3_TZC_DRAM1_BASE, \ - ARM_EL3_TZC_DRAM1_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) +#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ + ARM_EL3_TZC_DRAM1_BASE, \ + ARM_EL3_TZC_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_TRUSTED_DRAM_BASE, \ + PLAT_ARM_TRUSTED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ +MEASURED_BOOT +#define ARM_MAP_EVENT_LOG_DRAM1 \ + MAP_REGION_FLAT( \ + ARM_EVENT_LOG_DRAM1_BASE, \ + ARM_EVENT_LOG_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ + +#if ENABLE_RME +/* + * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. + * Else we end up requiring more pagetables in BL2 for ROMLIB build. + */ +#define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_RMM_BASE, \ + (PLAT_ARM_RMM_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE), \ + MT_MEMORY | MT_RW | MT_REALM) -#if defined(SPD_spmd) -#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ - PLAT_ARM_TRUSTED_DRAM_BASE, \ - PLAT_ARM_TRUSTED_DRAM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) -#endif +#define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ + ARM_L1_GPT_BASE, \ + ARM_L1_GPT_SIZE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +#define ARM_MAP_EL3_RMM_SHARED_MEM \ + MAP_REGION_FLAT( \ + ARM_EL3_RMM_SHARED_BASE, \ + ARM_EL3_RMM_SHARED_SIZE, \ + MT_MEMORY | MT_RW | MT_REALM) + +#endif /* ENABLE_RME */ /* * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to @@ -247,7 +364,7 @@ #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ BL1_RW_BASE, \ BL1_RW_LIMIT - BL1_RW_BASE, \ - MT_MEMORY | MT_RW | MT_SECURE) + MT_MEMORY | MT_RW | EL3_PAS) /* * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section @@ -257,35 +374,35 @@ #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ BL_CODE_BASE, \ BL_CODE_END - BL_CODE_BASE, \ - MT_CODE | MT_SECURE), \ + MT_CODE | EL3_PAS), \ MAP_REGION_FLAT( \ BL_RO_DATA_BASE, \ BL_RO_DATA_END \ - BL_RO_DATA_BASE, \ - MT_RO_DATA | MT_SECURE) + MT_RO_DATA | EL3_PAS) #else #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ BL_CODE_BASE, \ BL_CODE_END - BL_CODE_BASE, \ - MT_CODE | MT_SECURE) + MT_CODE | EL3_PAS) #endif #if USE_COHERENT_MEM #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ BL_COHERENT_RAM_BASE, \ BL_COHERENT_RAM_END \ - BL_COHERENT_RAM_BASE, \ - MT_DEVICE | MT_RW | MT_SECURE) + MT_DEVICE | MT_RW | EL3_PAS) #endif #if USE_ROMLIB #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ ROMLIB_RO_BASE, \ ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ - MT_CODE | MT_SECURE) + MT_CODE | EL3_PAS) #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ ROMLIB_RW_BASE, \ ROMLIB_RW_END - ROMLIB_RW_BASE,\ - MT_MEMORY | MT_RW | MT_SECURE) + MT_MEMORY | MT_RW | EL3_PAS) #endif /* @@ -300,28 +417,64 @@ #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ (ARM_FW_CONFIGS_LIMIT \ - ARM_BL_RAM_BASE), \ - MT_MEMORY | MT_RW | MT_SECURE) + MT_MEMORY | MT_RW | EL3_PAS) +/* + * Map L0_GPT with read and write permissions + */ +#if ENABLE_RME +#define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_BASE, \ + ARM_L0_GPT_SIZE, \ + MT_MEMORY | MT_RW | MT_ROOT) +#endif /* * The max number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. */ -#define ARM_BL_REGIONS 6 +#define ARM_BL_REGIONS 7 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ ARM_BL_REGIONS) /* Memory mapped Generic timer interfaces */ +#ifdef PLAT_ARM_SYS_CNTCTL_BASE +#define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE +#else #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) +#endif + +#ifdef PLAT_ARM_SYS_CNTREAD_BASE +#define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE +#else #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) +#endif + +#ifdef PLAT_ARM_SYS_TIMCTL_BASE +#define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE +#else #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) +#endif + +#ifdef PLAT_ARM_SYS_CNT_BASE_S +#define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S +#else #define ARM_SYS_CNT_BASE_S UL(0x2a820000) +#endif + +#ifdef PLAT_ARM_SYS_CNT_BASE_NS +#define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS +#else #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) +#endif #define ARM_CONSOLE_BAUDRATE 115200 /* Trusted Watchdog constants */ +#ifdef PLAT_ARM_SP805_TWDG_BASE +#define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE +#else #define ARM_SP805_TWDG_BASE UL(0x2a490000) +#endif #define ARM_SP805_TWDG_CLK_HZ 32768 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ @@ -371,7 +524,20 @@ * Define limit of firmware configuration memory: * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory */ -#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) +#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) +#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) + +#if ENABLE_RME +/* + * Store the L0 GPT on Trusted SRAM next to firmware + * configuration memory, 4KB aligned. + */ +#define ARM_L0_GPT_SIZE (PAGE_SIZE) +#define ARM_L0_GPT_BASE (ARM_FW_CONFIGS_LIMIT) +#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE) +#else +#define ARM_L0_GPT_SIZE U(0) +#endif /******************************************************************************* * BL1 specific defines. @@ -379,9 +545,14 @@ * addresses. ******************************************************************************/ #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE +#ifdef PLAT_BL1_RO_LIMIT +#define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT +#else #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ + (PLAT_ARM_TRUSTED_ROM_SIZE - \ PLAT_ARM_MAX_ROMLIB_RO_SIZE)) +#endif + /* * Put BL1 RW at the top of the Trusted SRAM. */ @@ -401,10 +572,21 @@ /******************************************************************************* * BL2 specific defines. ******************************************************************************/ -#if BL2_AT_EL3 +#if RESET_TO_BL2 +#if ENABLE_PIE +/* + * As the BL31 image size appears to be increased when built with the ENABLE_PIE + * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. + */ +#define BL2_OFFSET (0x5000) +#else /* Put BL2 towards the middle of the Trusted SRAM */ +#define BL2_OFFSET (0x2000) +#endif /* ENABLE_PIE */ + #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ - (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) + (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ + BL2_OFFSET) #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) #else @@ -450,27 +632,42 @@ - PLAT_ARM_MAX_BL31_SIZE) #define BL31_PROGBITS_LIMIT BL2_BASE /* - * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is - * because in the BL2_AT_EL3 configuration, BL2 is always resident. + * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. + * This is because in the RESET_TO_BL2 configuration, + * BL2 is always resident. */ -#if BL2_AT_EL3 +#if RESET_TO_BL2 #define BL31_LIMIT BL2_BASE #else #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) #endif #endif +/****************************************************************************** + * RMM specific defines + *****************************************************************************/ +#if ENABLE_RME +#define RMM_BASE (ARM_REALM_BASE) +#define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) +#define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) +#define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) +#endif + #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME /******************************************************************************* * BL32 specific defines for EL3 runtime in AArch32 mode ******************************************************************************/ # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +# if !ENABLE_PIE +# error "BL32 must be a PIE if RESET_TO_SP_MIN=1." +#endif /* - * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding - * the page reserved for fw_configs) to BL32 + * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely + * used for building BL32 and not used for loading BL32. */ -# define BL32_BASE ARM_FW_CONFIGS_LIMIT -# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +# define BL32_BASE 0x0 +# define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE # else /* Put BL32 below BL2 in the Trusted SRAM.*/ # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ @@ -488,7 +685,7 @@ * Trusted DRAM (if available) or the DRAM region secured by the TrustZone * controller. */ -# if SPM_MM +# if SPM_MM || SPMC_AT_EL3 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) @@ -520,7 +717,7 @@ # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ - + (UL(1) << 21)) + + SZ_4M) # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE @@ -534,12 +731,13 @@ /* * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no - * SPD and no SPM-MM, as they are the only ones that can be used as BL32. + * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be + * used as BL32. */ #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME -# if defined(SPD_none) && !SPM_MM +# if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 # undef BL32_BASE -# endif /* defined(SPD_none) && !SPM_MM */ +# endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ /******************************************************************************* @@ -563,10 +761,15 @@ #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) /* Priority levels for ARM platforms */ +#if ENABLE_FEAT_RAS && FFH_SUPPORT #define PLAT_RAS_PRI 0x10 +#endif #define PLAT_SDEI_CRITICAL_PRI 0x60 #define PLAT_SDEI_NORMAL_PRI 0x70 +/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ +#define PLAT_CORE_FAULT_IRQ 17 + /* ARM platforms use 3 upper bits of secure interrupt priority */ #define PLAT_PRI_BITS 3 diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h index 34bf07c0df..ff00fe7bed 100644 --- a/include/plat/arm/common/arm_dyn_cfg_helpers.h +++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,8 +14,4 @@ int arm_dyn_tb_fw_cfg_init(void *dtb, int *node); int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size); -#if MEASURED_BOOT -int arm_set_bl2_hash_info(void *dtb, void *data); -#endif - #endif /* ARM_DYN_CFG_HELPERS_H */ diff --git a/include/plat/arm/common/arm_reclaim_init.ld.S b/include/plat/arm/common/arm_reclaim_init.ld.S index 717f65e2be..a77c964535 100644 --- a/include/plat/arm/common/arm_reclaim_init.ld.S +++ b/include/plat/arm/common/arm_reclaim_init.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ SECTIONS . = . + PLATFORM_STACK_SIZE; . = ALIGN(PAGE_SIZE); __INIT_CODE_START__ = .; - *(*text.init*); + *(*text.init.*); __INIT_CODE_END__ = .; INIT_CODE_END_ALIGNED = ALIGN(PAGE_SIZE); } >RAM @@ -26,9 +26,9 @@ SECTIONS #define ABS ABSOLUTE #define STACK_SECTION \ - stacks (NOLOAD) : { \ + .stacks (NOLOAD) : { \ __STACKS_START__ = .; \ - *(tzfw_normal_stacks) \ + *(.tzfw_normal_stacks) \ __STACKS_END__ = .; \ /* Allow room for the init section where necessary. */ \ OFFSET = ABS(SIZEOF(.init) - (. - __STACKS_START__)); \ diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h index 2eeed95f02..a6fd42bac5 100644 --- a/include/plat/arm/common/arm_sip_svc.h +++ b/include/plat/arm/common/arm_sip_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019,2021-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,7 +26,7 @@ /* DEBUGFS_SMC_64 0xC2000030U */ /* - * Arm Ethos-N NPU SiP SMC function IDs + * Arm(R) Ethos(TM)-N NPU SiP SMC function IDs * 0xC2000050-0xC200005F * 0x82000050-0x8200005F */ @@ -35,4 +35,31 @@ #define ARM_SIP_SVC_VERSION_MAJOR U(0x0) #define ARM_SIP_SVC_VERSION_MINOR U(0x2) +/* + * Arm SiP SMC calls that are primarily used for testing purposes. + */ +#if PLAT_TEST_SPM +#define ARM_SIP_SET_INTERRUPT_PENDING U(0x82000100) +#endif + +/** + * Arm SiP Service Call for the SPM to leverage RME to protect a give memory range. + * Protected memory range is one whose PAS was made secure. + * Unprotect relates to reverting a protect operation. + */ +#if SPMD_SPM_AT_SEL2 && ENABLE_RME +#define PLAT_PROTECT_MEM_SMC64 0xC2000101 +#define PLAT_UNPROTECT_MEM_SMC64 0xC2000102 +#endif + +/* SiP handler specific to each Arm platform. */ +uintptr_t plat_arm_sip_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); + #endif /* ARM_SIP_SVC_H */ diff --git a/include/plat/arm/common/arm_tzc_dram.ld.S b/include/plat/arm/common/arm_tzc_dram.ld.S index 6dcea0b6e3..08990f61c1 100644 --- a/include/plat/arm/common/arm_tzc_dram.ld.S +++ b/include/plat/arm/common/arm_tzc_dram.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,9 +17,12 @@ SECTIONS . = ARM_EL3_TZC_DRAM1_BASE; ASSERT(. == ALIGN(PAGE_SIZE), "ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.") - el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) { + .el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) { + __PLAT_SPMC_SHMEM_DATASTORE_START__ = .; + *(.arm_spmc_shmem_datastore) + __PLAT_SPMC_SHMEM_DATASTORE_END__ = .; __EL3_SEC_DRAM_START__ = .; - *(arm_el3_tzc_dram) + *(.arm_el3_tzc_dram) __EL3_SEC_DRAM_UNALIGNED_END__ = .; . = ALIGN(PAGE_SIZE); diff --git a/include/plat/arm/common/fconf_arm_sp_getter.h b/include/plat/arm/common/fconf_arm_sp_getter.h index aa628dfd39..d8a332ec69 100644 --- a/include/plat/arm/common/fconf_arm_sp_getter.h +++ b/include/plat/arm/common/fconf_arm_sp_getter.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,13 +7,19 @@ #ifndef FCONF_ARM_SP_GETTER_H #define FCONF_ARM_SP_GETTER_H +#include <common/tbbr/tbbr_img_def.h> #include <lib/fconf/fconf.h> +#include <platform_def.h> #include <tools_share/uuid.h> /* arm_sp getter */ #define arm__sp_getter(prop) arm_sp.prop +#ifdef PLAT_ARM_SP_MAX_SIZE +#define ARM_SP_MAX_SIZE PLAT_ARM_SP_MAX_SIZE +#else #define ARM_SP_MAX_SIZE U(0xb0000) +#endif /* PLAT_ARM_SP_MAX_SIZE */ #define ARM_SP_OWNER_NAME_LEN U(8) struct arm_sp_t { diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h index 0fd1f025a8..d45c269c7a 100644 --- a/include/plat/arm/common/fconf_ethosn_getter.h +++ b/include/plat/arm/common/fconf_ethosn_getter.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,27 +8,54 @@ #define FCONF_ETHOSN_GETTER_H #include <assert.h> +#include <stdbool.h> #include <lib/fconf/fconf.h> #define hw_config__ethosn_config_getter(prop) ethosn_config.prop -#define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \ - assert(idx < ethosn_config.num_cores); \ - ethosn_config.core_addr[idx]; \ +#define hw_config__ethosn_device_getter(dev_idx) __extension__ ({ \ + assert(dev_idx < ethosn_config.num_devices); \ + ðosn_config.devices[dev_idx]; \ }) -#define ETHOSN_STATUS_DISABLED U(0) -#define ETHOSN_STATUS_ENABLED U(1) +#define ETHOSN_DEV_NUM_MAX U(2) +#define ETHOSN_DEV_CORE_NUM_MAX U(8) +#define ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX U(16) -#define ETHOSN_CORE_NUM_MAX U(64) +struct ethosn_allocator_t { + uint32_t stream_id; +}; -struct ethosn_config_t { - uint8_t status; +struct ethosn_main_allocator_t { + struct ethosn_allocator_t firmware; + struct ethosn_allocator_t working_data; +}; + +struct ethosn_asset_allocator_t { + struct ethosn_allocator_t command_stream; + struct ethosn_allocator_t weight_data; + struct ethosn_allocator_t buffer_data; + struct ethosn_allocator_t intermediate_data; +}; + +struct ethosn_core_t { + uint64_t addr; + struct ethosn_main_allocator_t main_allocator; +}; + +struct ethosn_device_t { + bool has_reserved_memory; + uint64_t reserved_memory_addr; uint32_t num_cores; - uint64_t core_addr[ETHOSN_CORE_NUM_MAX]; + struct ethosn_core_t cores[ETHOSN_DEV_CORE_NUM_MAX]; + uint32_t num_allocators; + struct ethosn_asset_allocator_t asset_allocators[ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX]; }; -int fconf_populate_arm_ethosn(uintptr_t config); +struct ethosn_config_t { + uint32_t num_devices; + struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX]; +}; extern struct ethosn_config_t ethosn_config; diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 846c9a4493..828d43a1df 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,7 @@ #include <lib/bakery_lock.h> #include <lib/cassert.h> #include <lib/el3_runtime/cpu_data.h> +#include <lib/gpt_rme/gpt_rme.h> #include <lib/spinlock.h> #include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_compat.h> @@ -31,6 +32,17 @@ typedef struct arm_tzc_regions_info { unsigned int nsaid_permissions; } arm_tzc_regions_info_t; +typedef struct arm_gpt_info { + pas_region_t *pas_region_base; + unsigned int pas_region_count; + uintptr_t l0_base; + uintptr_t l1_base; + size_t l0_size; + size_t l1_size; + gpccr_pps_e pps; + gpccr_pgs_e pgs; +} arm_gpt_info_t; + /******************************************************************************* * Default mapping definition of the TrustZone Controller for ARM standard * platforms. @@ -39,9 +51,23 @@ typedef struct arm_tzc_regions_info { * - Region 1 with secure access only; * - the remaining DRAM regions access from the given Non-Secure masters. ******************************************************************************/ -#if SPM_MM + +#if ENABLE_RME +#define ARM_TZC_RME_REGIONS_DEF \ + {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ + {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ + {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + /* Realm and Shared area share the same PAS */ \ + {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS} +#endif + +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) #define ARM_TZC_REGIONS_DEF \ - {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ + {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ TZC_REGION_S_RDWR, 0}, \ {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ PLAT_ARM_TZC_NS_DEV_ACCESS}, \ @@ -51,9 +77,21 @@ typedef struct arm_tzc_regions_info { PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ PLAT_ARM_TZC_NS_DEV_ACCESS} +#elif ENABLE_RME +#if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ +MEASURED_BOOT +#define ARM_TZC_REGIONS_DEF \ + ARM_TZC_RME_REGIONS_DEF, \ + {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ + TZC_REGION_S_RDWR, 0} +#else +#define ARM_TZC_REGIONS_DEF \ + ARM_TZC_RME_REGIONS_DEF +#endif + #else #define ARM_TZC_REGIONS_DEF \ - {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ + {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ TZC_REGION_S_RDWR, 0}, \ {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ PLAT_ARM_TZC_NS_DEV_ACCESS}, \ @@ -113,6 +151,12 @@ void arm_setup_romlib(void); #define ARM_LOCAL_PSTATE_WIDTH 4 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) +#if PSCI_OS_INIT_MODE +#define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ + (ARM_LOCAL_PSTATE_WIDTH * \ + (PLAT_MAX_PWR_LVL + 1))) +#endif /* __PSCI_OS_INIT_MODE__ */ + /* Macros to construct the composite power state */ /* Make composite power state parameter till power level 0 */ @@ -144,16 +188,25 @@ void arm_setup_romlib(void); #define STATE_SW_E_DENIED (-3) /* plat_get_rotpk_info() flags */ -#define ARM_ROTPK_REGS_ID 1 -#define ARM_ROTPK_DEVEL_RSA_ID 2 -#define ARM_ROTPK_DEVEL_ECDSA_ID 3 - +#define ARM_ROTPK_REGS_ID 1 +#define ARM_ROTPK_DEVEL_RSA_ID 2 +#define ARM_ROTPK_DEVEL_ECDSA_ID 3 +#define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 +#define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 + +#define ARM_USE_DEVEL_ROTPK \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) /* IO storage utility functions */ int arm_io_setup(void); /* Set image specification in IO block policy */ -int arm_set_image_source(unsigned int image_id, const char *part_name); +int arm_set_image_source(unsigned int image_id, const char *part_name, + uintptr_t *dev_handle, uintptr_t *image_spec); +void arm_set_fip_addr(uint32_t active_fw_bank_idx); /* Security utility functions */ void arm_tzc400_setup(uintptr_t tzc_base, @@ -237,12 +290,14 @@ void arm_bl1_set_mbedtls_heap(void); int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); #if MEASURED_BOOT -/* Measured boot related functions */ -void arm_bl1_set_bl2_hash(const image_desc_t *image_desc); -void arm_bl2_get_hash(void *data); -int arm_set_tos_fw_info(uintptr_t config_base, uintptr_t log_addr, - size_t log_size); -int arm_set_nt_fw_info(uintptr_t config_base, +#if DICE_PROTECTION_ENVIRONMENT +int arm_set_nt_fw_info(int *ctx_handle); +int arm_set_tb_fw_info(int *ctx_handle); +int arm_get_tb_fw_info(int *ctx_handle); +#else +/* Specific to event log backend */ +int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); +int arm_set_nt_fw_info( /* * Currently OP-TEE does not support reading DTBs from Secure memory * and this option should be removed when feature is supported. @@ -251,6 +306,11 @@ int arm_set_nt_fw_info(uintptr_t config_base, uintptr_t log_addr, #endif size_t log_size, uintptr_t *ns_log_addr); +int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, + size_t log_max_size); +int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, + size_t *log_max_size); +#endif /* DICE_PROTECTION_ENVIRONMENT */ #endif /* MEASURED_BOOT */ /* @@ -285,6 +345,7 @@ void plat_arm_interconnect_exit_coherency(void); void plat_arm_program_trusted_mailbox(uintptr_t address); bool plat_arm_bl1_fwu_needed(void); __dead2 void plat_arm_error_handler(int err); +__dead2 void plat_arm_system_reset(void); /* * Optional functions in ARM standard platforms @@ -320,6 +381,9 @@ int plat_arm_get_alt_image_source( unsigned int plat_arm_calc_core_pos(u_register_t mpidr); const mmap_region_t *plat_arm_get_mmap(void); +const arm_gpt_info_t *plat_arm_get_gpt_info(void); +void arm_gpt_setup(void); + /* Allow platform to override psci_pm_ops during runtime */ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); @@ -343,6 +407,7 @@ extern const unsigned int arm_pm_idle_states[]; /* secure watchdog */ void plat_arm_secure_wdt_start(void); void plat_arm_secure_wdt_stop(void); +void plat_arm_secure_wdt_refresh(void); /* Get SOC-ID of ARM platform */ uint32_t plat_arm_get_soc_id(void); diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h index 6e698e5d2c..0f4e57386f 100644 --- a/include/plat/arm/common/smccc_def.h +++ b/include/plat/arm/common/smccc_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,5 @@ /* Defines used to retrieve ARM SOC revision */ #define ARM_SOC_CONTINUATION_CODE U(0x4) #define ARM_SOC_IDENTIFICATION_CODE U(0x3B) -#define ARM_SOC_CONTINUATION_SHIFT U(24) -#define ARM_SOC_IDENTIFICATION_SHIFT U(16) #endif /* SMCCC_DEF_H */ diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index dde174c37f..0aea54803e 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -52,18 +52,21 @@ * terminology. On a GICv2 system or mode, the interrupts will be treated as * Group 0 interrupts. */ -#define CSS_G1S_IRQ_PROPS(grp) \ +#define CSS_G1S_INT_PROPS(grp) \ INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL) +#define CSS_G1S_IRQ_PROPS(grp) \ + CSS_G1S_INT_PROPS(grp), \ + INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + #if CSS_USE_SCMI_SDS_DRIVER /* Memory region for shared data storage */ #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE @@ -72,6 +75,7 @@ * The SCMI Channel is placed right after the SDS region */ #define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) +#define CSS_SCMI_PAYLOAD_SIZE_MAX 0x100 /* 2x128 bytes for bidirectional communication */ #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET /* Trusted mailbox base address common to all CSS */ diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h index e5357f50be..84e6b38de5 100644 --- a/include/plat/arm/css/common/css_pm.h +++ b/include/plat/arm/css/common/css_pm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,9 @@ #include <lib/psci/psci.h> +/* SGI used to trigger per-core power down request */ +#define CSS_CPU_PWR_DOWN_REQ_INTR ARM_IRQ_SEC_SGI_7 + /* Macros to read the CSS power domain state */ #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] @@ -37,6 +40,9 @@ void __dead2 css_system_reset(void); void css_cpu_standby(plat_local_state_t cpu_state); void css_get_sys_suspend_power_state(psci_power_state_t *req_state); int css_node_hw_state(u_register_t mpidr, unsigned int power_level); +void css_setup_cpu_pwr_down_intr(void); +int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags, + void *handle, void *cookie); /* * This mapping array has to be exported by the platform. Each element at diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h index 14ae603b9b..ecec5bc9dd 100644 --- a/include/plat/common/common_def.h +++ b/include/plat/common/common_def.h @@ -1,17 +1,81 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef COMMON_DEF_H #define COMMON_DEF_H -#include <platform_def.h> - #include <common/bl_common.h> #include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_defs.h> +#include <platform_def.h> + +#ifdef __aarch64__ +#define SZ_32 UL(0x00000020) +#define SZ_64 UL(0x00000040) +#define SZ_128 UL(0x00000080) +#define SZ_256 UL(0x00000100) +#define SZ_512 UL(0x00000200) + +#define SZ_1K UL(0x00000400) +#define SZ_2K UL(0x00000800) +#define SZ_4K UL(0x00001000) +#define SZ_8K UL(0x00002000) +#define SZ_16K UL(0x00004000) +#define SZ_32K UL(0x00008000) +#define SZ_64K UL(0x00010000) +#define SZ_128K UL(0x00020000) +#define SZ_256K UL(0x00040000) +#define SZ_512K UL(0x00080000) + +#define SZ_1M UL(0x00100000) +#define SZ_2M UL(0x00200000) +#define SZ_4M UL(0x00400000) +#define SZ_8M UL(0x00800000) +#define SZ_16M UL(0x01000000) +#define SZ_32M UL(0x02000000) +#define SZ_64M UL(0x04000000) +#define SZ_128M UL(0x08000000) +#define SZ_256M UL(0x10000000) +#define SZ_512M UL(0x20000000) + +#define SZ_1G UL(0x40000000) +#define SZ_2G UL(0x80000000) +#else /* !__aarch64__ */ +#define SZ_32 U(0x00000020) +#define SZ_64 U(0x00000040) +#define SZ_128 U(0x00000080) +#define SZ_256 U(0x00000100) +#define SZ_512 U(0x00000200) + +#define SZ_1K U(0x00000400) +#define SZ_2K U(0x00000800) +#define SZ_4K U(0x00001000) +#define SZ_8K U(0x00002000) +#define SZ_16K U(0x00004000) +#define SZ_32K U(0x00008000) +#define SZ_64K U(0x00010000) +#define SZ_128K U(0x00020000) +#define SZ_256K U(0x00040000) +#define SZ_512K U(0x00080000) + +#define SZ_1M U(0x00100000) +#define SZ_2M U(0x00200000) +#define SZ_4M U(0x00400000) +#define SZ_8M U(0x00800000) +#define SZ_16M U(0x01000000) +#define SZ_32M U(0x02000000) +#define SZ_64M U(0x04000000) +#define SZ_128M U(0x08000000) +#define SZ_256M U(0x10000000) +#define SZ_512M U(0x20000000) + +#define SZ_1G U(0x40000000) +#define SZ_2G U(0x80000000) +#endif /* __aarch64__ */ + /****************************************************************************** * Required platform porting definitions that are expected to be common to * all platforms @@ -85,4 +149,12 @@ #endif /* BL2_IN_XIP_MEM */ #endif /* SEPARATE_CODE_AND_RODATA */ +#if MEASURED_BOOT +/* + * Start critical data Ids from 2^32/2 reserving Ids from 0 to (2^32/2 - 1) + * for Images, It is a critical data Id base for all platforms. + */ +#define CRITICAL_DATA_ID_BASE U(0x80000000) +#endif /* MEASURED_BOOT */ + #endif /* COMMON_DEF_H */ diff --git a/include/plat/common/plat_drtm.h b/include/plat/common/plat_drtm.h new file mode 100644 index 0000000000..07545a68f3 --- /dev/null +++ b/include/plat/common/plat_drtm.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DRTM_H +#define PLAT_DRTM_H + +#include <stdint.h> +#include <lib/xlat_tables/xlat_tables_compat.h> + +typedef struct { + uint8_t max_num_mem_prot_regions; + uint8_t dma_protection_support; +} plat_drtm_dma_prot_features_t; + +typedef struct { + bool tpm_based_hash_support; + uint16_t firmware_hash_algorithm; +} plat_drtm_tpm_features_t; + +typedef struct { + uint64_t region_address; + uint64_t region_size_type; +} __attribute__((packed)) drtm_mem_region_t; + +/* + * Memory region descriptor table structure as per DRTM 1.0 section 3.13 + * Table 11 MEMORY_REGION_DESCRIPTOR_TABLE + */ +typedef struct { + uint16_t revision; + uint16_t reserved; + uint32_t num_regions; + drtm_mem_region_t region[]; +} __attribute__((packed)) drtm_memory_region_descriptor_table_t; + +/* platform specific address map functions */ +const mmap_region_t *plat_get_addr_mmap(void); + +/* platform-specific DMA protection functions */ +bool plat_has_non_host_platforms(void); +bool plat_has_unmanaged_dma_peripherals(void); +unsigned int plat_get_total_smmus(void); +void plat_enumerate_smmus(const uintptr_t **smmus_out, + size_t *smmu_count_out); +const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void); +uint64_t plat_drtm_dma_prot_get_max_table_bytes(void); + +/* platform-specific TPM functions */ +const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void); + +/* + * TODO: Implement these functions as per the platform use case, + * as of now none of the platform uses these functions + */ +uint64_t plat_drtm_get_min_size_normal_world_dce(void); +uint64_t plat_drtm_get_tcb_hash_table_size(void); +uint64_t plat_drtm_get_imp_def_dlme_region_size(void); +uint64_t plat_drtm_get_tcb_hash_features(void); + +/* DRTM error handling functions */ +int plat_set_drtm_error(uint64_t error_code); +int plat_get_drtm_error(uint64_t *error_code); + +/* + * Platform-specific function to ensure passed region lies within + * Non-Secure region of DRAM + */ +int plat_drtm_validate_ns_region(uintptr_t region_start, + size_t region_size); + +#endif /* PLAT_DRTM_H */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 1def86ea7d..4fe362005b 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,11 +11,18 @@ #include <lib/psci/psci.h> #if defined(SPD_spmd) - #include <services/spm_core_manifest.h> +#include <services/spm_core_manifest.h> #endif +#if ENABLE_RME +#include <services/rmm_core_manifest.h> +#endif +#include <drivers/fwu/fwu_metadata.h> #if TRNG_SUPPORT #include "plat_trng.h" -#endif +#endif /* TRNG_SUPPORT */ +#if DRTM_SUPPORT +#include "plat_drtm.h" +#endif /* DRTM_SUPPORT */ /******************************************************************************* * Forward declarations @@ -30,16 +37,24 @@ struct bl_params; struct mmap_region; struct spm_mm_boot_info; struct sp_res_desc; +struct rmm_manifest; enum fw_enc_status_t; /******************************************************************************* * plat_get_rotpk_info() flags ******************************************************************************/ #define ROTPK_IS_HASH (1 << 0) + /* Flag used to skip verification of the certificate ROTPK while the platform ROTPK is not deployed */ #define ROTPK_NOT_DEPLOYED (1 << 1) +static inline bool is_rotpk_flags_valid(unsigned int flags) +{ + unsigned int valid_flags = ROTPK_IS_HASH; + return (flags == ROTPK_NOT_DEPLOYED) || ((flags & ~valid_flags) == 0); +} + /******************************************************************************* * plat_get_enc_key_info() flags ******************************************************************************/ @@ -65,6 +80,20 @@ unsigned int plat_my_core_pos(void); int plat_core_pos_by_mpidr(u_register_t mpidr); int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size); +/******************************************************************************* + * Simple routine to determine whether a mpidr is valid or not. + ******************************************************************************/ +static inline bool is_valid_mpidr(u_register_t mpidr) +{ + int pos = plat_core_pos_by_mpidr(mpidr); + + if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) { + return false; + } + + return true; +} + #if STACK_PROTECTOR_ENABLED /* * Return a new value to be used for the stack protection's canary. @@ -96,15 +125,18 @@ int plat_ic_is_sgi(unsigned int id); unsigned int plat_ic_get_interrupt_active(unsigned int id); void plat_ic_disable_interrupt(unsigned int id); void plat_ic_enable_interrupt(unsigned int id); -int plat_ic_has_interrupt_type(unsigned int type); +bool plat_ic_has_interrupt_type(unsigned int type); void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target); +void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target); +void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target); void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, u_register_t mpidr); void plat_ic_set_interrupt_pending(unsigned int id); void plat_ic_clear_interrupt_pending(unsigned int id); unsigned int plat_ic_set_priority_mask(unsigned int mask); +unsigned int plat_ic_deactivate_priority(unsigned int mask); unsigned int plat_ic_get_interrupt_id(unsigned int raw); /******************************************************************************* @@ -112,15 +144,46 @@ unsigned int plat_ic_get_interrupt_id(unsigned int raw); ******************************************************************************/ uintptr_t plat_get_my_stack(void); void plat_report_exception(unsigned int exception_type); +void plat_report_prefetch_abort(unsigned int fault_address); +void plat_report_data_abort(unsigned int fault_address); int plat_crash_console_init(void); int plat_crash_console_putc(int c); void plat_crash_console_flush(void); void plat_error_handler(int err) __dead2; void plat_panic_handler(void) __dead2; +void plat_system_reset(void) __dead2; const char *plat_log_get_prefix(unsigned int log_level); void bl2_plat_preload_setup(void); int plat_try_next_boot_source(void); +#if MEASURED_BOOT +int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data); +int plat_mboot_measure_critical_data(unsigned int critical_data_id, + const void *base, + size_t size); +int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, + size_t pk_len); +#else +static inline int plat_mboot_measure_image(unsigned int image_id __unused, + image_info_t *image_data __unused) +{ + return 0; +} +static inline int plat_mboot_measure_critical_data( + unsigned int critical_data_id __unused, + const void *base __unused, + size_t size __unused) +{ + return 0; +} +static inline int plat_mboot_measure_key(const void *pk_oid __unused, + const void *pk_ptr __unused, + size_t pk_len __unused) +{ + return 0; +} +#endif /* MEASURED_BOOT */ + /******************************************************************************* * Mandatory BL1 functions ******************************************************************************/ @@ -140,6 +203,8 @@ int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode); void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr); #endif +void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, + void *handle, uint64_t flags); void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, void *handle, uint64_t flags); @@ -178,13 +243,17 @@ __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved); int bl1_plat_handle_pre_image_load(unsigned int image_id); int bl1_plat_handle_post_image_load(unsigned int image_id); -#if MEASURED_BOOT -/* - * Calculates and writes BL2 hash data to the platform's defined location. - * For ARM platforms the data are written to TB_FW_CONFIG DTB. - */ -void bl1_plat_set_bl2_hash(const image_desc_t *image_desc); -#endif +#if (MEASURED_BOOT || DICE_PROTECTION_ENVIRONMENT) +void bl1_plat_mboot_init(void); +void bl1_plat_mboot_finish(void); +#else +static inline void bl1_plat_mboot_init(void) +{ +} +static inline void bl1_plat_mboot_finish(void) +{ +} +#endif /* MEASURED_BOOT || DICE_PROTECTION_ENVIRONMENT */ /******************************************************************************* * Mandatory BL2 functions @@ -204,14 +273,21 @@ int bl2_plat_handle_post_image_load(unsigned int image_id); /******************************************************************************* * Optional BL2 functions (may be overridden) ******************************************************************************/ -#if MEASURED_BOOT -/* Read TCG_DIGEST_SIZE bytes of BL2 hash data */ -void bl2_plat_get_hash(void *data); -#endif +#if (MEASURED_BOOT || DICE_PROTECTION_ENVIRONMENT) +void bl2_plat_mboot_init(void); +void bl2_plat_mboot_finish(void); +#else +static inline void bl2_plat_mboot_init(void) +{ +} +static inline void bl2_plat_mboot_finish(void) +{ +} +#endif /* MEASURED_BOOT || DICE_PROTECTION_ENVIRONMENTs */ /******************************************************************************* - * Mandatory BL2 at EL3 functions: Must be implemented if BL2_AT_EL3 image is - * supported + * Mandatory BL2 at EL3 functions: Must be implemented + * if RESET_TO_BL2 image is supported ******************************************************************************/ void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3); @@ -269,6 +345,18 @@ plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, unsigned int ncpu); /******************************************************************************* + * Mandatory BL31 functions when ENABLE_RME=1 + ******************************************************************************/ +#if ENABLE_RME +int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len, + uintptr_t hash, size_t hash_size); +int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len, + unsigned int type); +size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared); +int plat_rmmd_load_manifest(struct rmm_manifest *manifest); +#endif + +/******************************************************************************* * Optional BL31 functions (may be overridden) ******************************************************************************/ void bl31_plat_enable_mmu(uint32_t flags); @@ -305,6 +393,10 @@ int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size, int plat_spm_core_manifest_load(spmc_manifest_attribute_t *manifest, const void *pm_addr); #endif +#if defined(SPMC_AT_EL3) +int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size); +#endif + /******************************************************************************* * Mandatory BL image load functions(may be overridden). ******************************************************************************/ @@ -349,4 +441,26 @@ int32_t plat_get_soc_revision(void); */ int32_t plat_is_smccc_feature_available(u_register_t fid); +/******************************************************************************* + * FWU platform specific functions + ******************************************************************************/ +int plat_fwu_set_metadata_image_source(unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +void plat_fwu_set_images_source(const struct fwu_metadata *metadata); +uint32_t plat_fwu_get_boot_idx(void); + +/* + * Optional function to indicate if cache management operations can be + * performed. + */ +#if CONDITIONAL_CMO +uint64_t plat_can_cmo(void); +#else +static inline uint64_t plat_can_cmo(void) +{ + return 1; +} +#endif /* CONDITIONAL_CMO */ + #endif /* PLATFORM_H */ diff --git a/include/plat/marvell/armada/a8k/common/plat_marvell.h b/include/plat/marvell/armada/a8k/common/plat_marvell.h index 5d805a7f19..bec21a0dcf 100644 --- a/include/plat/marvell/armada/a8k/common/plat_marvell.h +++ b/include/plat/marvell/armada/a8k/common/plat_marvell.h @@ -10,6 +10,7 @@ #include <stdint.h> +#include <common/bl_common.h> #include <lib/cassert.h> #include <lib/el3_runtime/cpu_data.h> #include <lib/utils.h> diff --git a/include/plat/nuvoton/common/npcm845x_arm_def.h b/include/plat/nuvoton/common/npcm845x_arm_def.h new file mode 100644 index 0000000000..df3ad243c3 --- /dev/null +++ b/include/plat/nuvoton/common/npcm845x_arm_def.h @@ -0,0 +1,577 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (C) 2017-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NPCM845x_ARM_DEF_H +#define NPCM845x_ARM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +/* This flag will add zones to the MMU so that it will be possible to debug */ +#ifdef NPCM845X_DEBUG +#define ALLOW_DEBUG_MMU +#undef ALLOW_DEBUG_MMU +#endif /* NPCM845X_DEBUG */ + +#undef CONFIG_TARGET_ARBEL_PALLADIUM +/****************************************************************************** + * Definitions common to all ARM standard platforms + *****************************************************************************/ + +/* + * Root of trust key hash lengths + */ +#define ARM_ROTPK_HEADER_LEN 19 +#define ARM_ROTPK_HASH_LEN 32 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) + +/* No need for system because we have only one cluster */ +#define ARM_SYSTEM_COUNT U(0) + +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. + * The power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +/* In NPCM845x - refers to cores */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 + +/* In NPCM845x - refers to cluster */ +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 + +/* No need for additional settings because the platform doesn't have system */ + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +#define NPCM845x_PLAT_PRIMARY_CPU U(0x0) +#define NPCM845x_CLUSTER_COUNT U(1) + +#ifdef SECONDARY_BRINGUP +#define NPCM845x_MAX_CPU_PER_CLUSTER U(2) +#define NPCM845x_PLATFORM_CORE_COUNT U(2) +#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(2) +#else +#define NPCM845x_MAX_CPU_PER_CLUSTER U(4) +#define NPCM845x_PLATFORM_CORE_COUNT U(4) +#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(4) +#endif /* SECONDARY_BRINGUP */ + +#define NPCM845x_SYSTEM_COUNT U(0) + +/* Memory mapping for NPCM845x */ +#define NPCM845x_REG_BASE 0xf0000000 +#define NPCM845x_REG_SIZE 0x0ff16000 + +/* + * DRAM + * 0x3fffffff +-------------+ + * | BL33 | (non-secure) + * 0x06200000 +-------------+ + * | BL32 SHARED | (non-secure) + * 0x06000000 +-------------+ + * | BL32 | (secure) + * 0x02100000 +-------------+ + * | BL31 | (secure) + * 0x02000000 +-------------+ + * | | (non-secure) + * 0x00000000 +-------------+ + * + * Trusted ROM + * 0xfff50000 +-------------+ + * | BL1 (ro) | + * 0xfff40000 +-------------+ + */ + +#define ARM_DRAM1_BASE ULL(0x00000000) +#ifndef CONFIG_TARGET_ARBEL_PALLADIUM +/* + * Although npcm845x is 4G, + * consider only 2G Trusted Firmware memory allocation + */ +#define ARM_DRAM1_SIZE ULL(0x37000000) +#else +#define ARM_DRAM1_SIZE ULL(0x10000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1U) +#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ + +/* + * The top 16MB of DRAM1 is configured as secure access only using the TZC + * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + */ + +/* Check for redundancy */ +#ifdef NPCM845X_DEBUG +#define PLAT_ARM_NS_IMAGE_BASE 0x0 +#endif /* NPCM845X_DEBUG */ + +#define ARM_TZC_DRAM1_SIZE UL(0x01000000) +#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE +#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ + ARM_SCP_TZC_DRAM1_SIZE - 1U) + +/* + * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime + * firmware. This region is meant to be NOLOAD and will not be zero + * initialized. Data sections with the attribute `arm_el3_tzc_dram` + * will be placed here. + * + * NPCM845x - Currently the platform doesn't have EL3 implementation + * on secured DRAM. + */ +#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ + ARM_EL3_TZC_DRAM1_SIZE) +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ +#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ + ARM_EL3_TZC_DRAM1_SIZE - 1U) + +#define ARM_AP_TZC_DRAM1_BASE 0x02100000 +#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE)) +#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE - 1U) + +/* Define the Access permissions for Secure peripherals to NS_DRAM */ +#if ARM_CRYPTOCELL_INTEG +/* + * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. + * This is required by CryptoCell to authenticate BL33 which is loaded + * into the Non Secure DDR. + */ +#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD +#else +#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE +#endif /* ARM_CRYPTOCELL_INTEG */ + +#ifdef SPD_opteed +/* + * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to + * load/authenticate the trusted os extra image. The first 512KB of + * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading + * for OPTEE is paged image which only include the paging part using + * virtual memory but without "init" data. OPTEE will copy the "init" data + * (from pager image) to the first 512KB of TZC_DRAM, and then copy the + * extra image behind the "init" data. + */ +#define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE +#define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE +#define BL32_BASE ARM_AP_TZC_DRAM1_BASE +#define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) + +#define ARM_OPTEE_PAGEABLE_LOAD_BASE ( \ + ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \ + ARM_OPTEE_PAGEABLE_LOAD_SIZE) +#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) +#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ + ARM_OPTEE_PAGEABLE_LOAD_BASE, \ + ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * Map the memory for the OP-TEE core (also known as OP-TEE pager + * when paging support is enabled). + */ +#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_opteed */ + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1U) + +/* The platform doesn't use DRAM2 but it has to have a value for calculation */ +#define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */ +#define ARM_DRAM2_SIZE 1 /* PLAT_ARM_DRAM_SIZE */ +#define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U) + +#define FIRST_EXT_INTERRUPT_NUM U(32) +#define ARM_IRQ_SEC_PHY_TIMER (U(29) + FIRST_EXT_INTERRUPT_NUM) + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties + * as per GICv3 terminology. On a GICv2 system or mode, + * the lists will be merged and treated as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ + PLAT_SDEI_NORMAL_PRI, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef ALLOW_DEBUG_MMU +/* In order to be able to debug, + * the platform needs to add BL33 and BL32 to MMU as well. + */ +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#ifdef BL32_BASE +#define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* BL32_BASE */ + +#ifdef NPCM845X_DEBUG +#define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \ + 0xFFFB0000, 0x20000, \ + MT_MEMORY | MT_RW | MT_NS) +#endif /* NPCM845X_DEBUG */ +#endif /* BL32_BASE */ + +#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ + ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ + TSP_SEC_MEM_BASE, TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if ARM_BL31_IN_DRAM +#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, PLAT_ARM_MAX_BL31_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* ARM_BL31_IN_DRAM */ + +/* Currently the platform doesn't have EL3 implementation on secured DRAM. */ +#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ + ARM_EL3_TZC_DRAM1_BASE, \ + ARM_EL3_TZC_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if defined(SPD_spmd) +#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_TRUSTED_DRAM_BASE, \ + PLAT_ARM_TRUSTED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_spmd */ + +/* + * Mapping for the BL1 RW region. This mapping is needed by BL2 + * in order to share the Mbed TLS heap. Since the heap is allocated + * inside BL1, it resides in the BL1 RW region. Hence, BL2 needs access + * to the BL1 RW region in order to be able to access the heap. + */ +#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ + BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +/* + * If SEPARATE_CODE_AND_RODATA=1 the platform will define a region + * for each section, otherwise one region containing both sections + * is defined. + */ +#if SEPARATE_CODE_AND_RODATA +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS), \ + MAP_REGION_FLAT(BL_RO_DATA_BASE, \ + BL_RO_DATA_END - BL_RO_DATA_BASE, \ + MT_RO_DATA | EL3_PAS) +#else +#define ARM_MAP_BL_RO_NOT_USED MAP_REGION_FLAT( \ + BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS) +#endif /* SEPARATE_CODE_AND_RODATA */ + +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | EL3_PAS) +#endif /* USE_COHERENT_MEM */ + +#if USE_ROMLIB +#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ + ROMLIB_RO_BASE, \ + ROMLIB_RO_LIMIT - ROMLIB_RO_BASE, \ + MT_CODE | MT_SECURE) + +#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ + ROMLIB_RW_BASE, \ + ROMLIB_RW_END - ROMLIB_RW_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* USE_ROMLIB */ + +/* + * Map mem_protect flash region with read and write permissions + */ +#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT( \ + PLAT_ARM_MEM_PROT_ADDR, \ + V2M_FLASH_BLOCK_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +/* + * Map the region for device tree configuration with read and write permissions + */ +#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ + ARM_BL_RAM_BASE, \ + (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 10 + +#define MAX_MMAP_REGIONS ( \ + PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) + +/* Memory mapped Generic timer interfaces */ +#define ARM_SYS_CNTCTL_BASE UL(0XF07FC000) + +#define ARM_CONSOLE_BAUDRATE 115200 + +/* + * The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) + */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + +/****************************************************************************** + * Required platform porting definitions common to all ARM standard platforms + *****************************************************************************/ + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches (64 on Arbel). + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) + +/* + * To enable FW_CONFIG to be loaded by BL1, define the corresponding base + * and limit. Leave enough space of BL2 meminfo. + */ +#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT ( \ + (ARM_BL_RAM_BASE + PAGE_SIZE) + (PAGE_SIZE / 2U)) + +/* + * Boot parameters passed from BL2 to BL31/BL32 are stored here + */ +#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) +#define ARM_BL2_MEM_DESC_LIMIT ( \ + ARM_BL2_MEM_DESC_BASE + (PAGE_SIZE / 2U)) + +/* + * Define limit of firmware configuration memory: + * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory + */ +#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need + * two sets of addresses. + ******************************************************************************/ +#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + \ + (PLAT_ARM_TRUSTED_ROM_SIZE - PLAT_ARM_MAX_ROMLIB_RO_SIZE)) +/* + * Put BL1 RW at the top of the Trusted SRAM. + */ +#define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \ + (PLAT_ARM_MAX_BL1_RW_SIZE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)) +#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ + (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) + +#define ROMLIB_RO_BASE BL1_RO_LIMIT +#define ROMLIB_RO_LIMIT ( \ + PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) + +#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) +#define ROMLIB_RW_END ( \ + ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) + +/****************************************************************************** + * BL2 specific defines. + *****************************************************************************/ +#if BL2_AT_EL3 +/* Put BL2 towards the middle of the Trusted SRAM */ +#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ + PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) +#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +#else +/* + * Put BL2 just below BL1. + */ +#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) +#define BL2_LIMIT BL1_RW_BASE +#endif /* BL2_AT_EL3 */ + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION +/* + * Put BL31 at the bottom of TZC secured DRAM + */ +#define BL31_BASE ARM_AP_TZC_DRAM1_BASE +#define BL31_LIMIT ( \ + ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE) + +/* + * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. + * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. + */ +#if SEPARATE_NOBITS_REGION +#define BL31_NOBITS_BASE BL2_BASE +#define BL31_NOBITS_LIMIT BL2_LIMIT +#endif /* SEPARATE_NOBITS_REGION */ +#elif (RESET_TO_BL31) +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +#if !ENABLE_PIE +#error "BL31 must be a PIE if RESET_TO_BL31=1." +#endif /* !ENABLE_PIE */ +/* + * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely + * used for building BL31 and not used for loading BL31. + */ +#define NEW_SRAM_ALLOCATION + +#ifdef NEW_SRAM_ALLOCATION + #define BL31_BASE 0x02000000 +#else + #define BL31_BASE 0x02001000 +#endif /* NEW_SRAM_ALLOCATION */ + +#define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */ +#else +/* Put BL31 below BL2 in the Trusted SRAM.*/ +#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - \ + PLAT_ARM_MAX_BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL2_BASE + +/* + * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. + * This is because in the BL2_AT_EL3 configuration, BL2 is always resident. + */ +#if BL2_AT_EL3 +#define BL31_LIMIT BL2_BASE +#else +#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +#endif /* BL2_AT_EL3 */ +#endif /* ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION */ + +/* + * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is + * no SPD and no SPM-MM, as they are the only ones that can be used as BL32. + */ +#if defined(SPD_none) && !SPM_MM +#error BL32_BASE is not defined +#undef BL32_BASE +#endif /* SPD_none && !SPM_MM */ + +/****************************************************************************** + * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. + *****************************************************************************/ +#define BL2U_BASE BL2_BASE +#define BL2U_LIMIT BL2_LIMIT + +#define NS_BL2U_BASE ARM_NS_DRAM1_BASE +#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) + +/* + * ID of the secure physical generic timer interrupt used by the TSP. + */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + +/* + * One cache line needed for bakery locks on ARM platforms + */ +#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) + +/* Priority levels for ARM platforms */ +#define PLAT_RAS_PRI 0x10 +#define PLAT_SDEI_CRITICAL_PRI 0x60 +#define PLAT_SDEI_NORMAL_PRI 0x70 + +/* ARM platforms use 3 upper bits of secure interrupt priority */ +#define ARM_PRI_BITS 3 + +/* SGI used for SDEI signalling */ +#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 + +#if SDEI_IN_FCONF +/* ARM SDEI dynamic private event max count */ +#define ARM_SDEI_DP_EVENT_MAX_CNT 3 + +/* ARM SDEI dynamic shared event max count */ +#define ARM_SDEI_DS_EVENT_MAX_CNT 3 +#else +/* ARM SDEI dynamic private event numbers */ +#define ARM_SDEI_DP_EVENT_0 1000 +#define ARM_SDEI_DP_EVENT_1 1001 +#define ARM_SDEI_DP_EVENT_2 1002 + +/* ARM SDEI dynamic shared event numbers */ +#define ARM_SDEI_DS_EVENT_0 2000 +#define ARM_SDEI_DS_EVENT_1 2001 +#define ARM_SDEI_DS_EVENT_2 2002 + +#define ARM_SDEI_PRIVATE_EVENTS \ + SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) + +#define ARM_SDEI_SHARED_EVENTS \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) +#endif /* SDEI_IN_FCONF */ + +#endif /* ARM_DEF_H */ diff --git a/include/plat/nuvoton/common/plat_macros.S b/include/plat/nuvoton/common/plat_macros.S new file mode 100644 index 0000000000..549db395c4 --- /dev/null +++ b/include/plat/nuvoton/common/plat_macros.S @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <arm_macros.S> +#include <cci_macros.S> +#include <platform_def.h> + +/* + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + */ +.macro plat_print_gic_regs +mov_imm x17, BASE_GICC_BASE +mov_imm x16, BASE_GICD_BASE +arm_print_gic_regs +.endm + +/* + * the below macros print out relevant interconnect + * registers whenever an unhandled exception is + * taken in BL3-1 + */ +.macro plat_print_interconnect_regs + /* TODO */ +.endm + +/* + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + */ +.macro plat_crash_print_regs +plat_print_gic_regs +/*print_cci_regs*/ +.endm + +#endif /* PLAT_MACROS_S */ diff --git a/include/plat/nuvoton/common/plat_npcm845x.h b/include/plat/nuvoton/common/plat_npcm845x.h new file mode 100644 index 0000000000..d90952a833 --- /dev/null +++ b/include/plat/nuvoton/common/plat_npcm845x.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_NPCM845X_H +#define PLAT_NPCM845X_H + +#include <drivers/arm/gicv2.h> +#include <lib/psci/psci.h> + +unsigned int plat_calc_core_pos(uint64_t mpidr); +void npcm845x_mailbox_init(uintptr_t base_addr); +void plat_gic_driver_init(void); +void plat_gic_init(void); +void plat_gic_cpuif_enable(void); +void plat_gic_cpuif_disable(void); +void plat_gic_pcpu_init(void); + +void __dead2 npcm845x_system_off(void); +void __dead2 npcm845x_system_reset(void); +void npcm845x_pwr_domain_on_finish(const psci_power_state_t *target_state); +bool npcm845x_is_wakeup_src_irqsteer(void); +void __dead2 npcm845x_pwr_down_wfi(const psci_power_state_t *target_state); +void npcm845x_cpu_standby(plat_local_state_t cpu_state); +int npcm845x_validate_ns_entrypoint(uintptr_t entrypoint); +int npcm845x_pwr_domain_on(u_register_t mpidr); +int npcm845x_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state); + +#if !ARM_BL31_IN_DRAM +void npcm845x_get_sys_suspend_power_state(psci_power_state_t *req_state); +#endif + +void __dead2 npcm845x_pwr_domain_pwr_down_wfi( + const psci_power_state_t *target_state); +void npcm845x_pwr_domain_suspend_finish(const psci_power_state_t *target_state); +void npcm845x_pwr_domain_suspend(const psci_power_state_t *target_state); +void npcm845x_pwr_domain_off(const psci_power_state_t *target_state); +void __init npcm845x_bl31_plat_arch_setup(void); + +#endif /* PLAT_NPCM845X_H */ diff --git a/include/plat/nuvoton/npcm845x/platform_def.h b/include/plat/nuvoton/npcm845x/platform_def.h new file mode 100644 index 0000000000..09da36ba18 --- /dev/null +++ b/include/plat/nuvoton/npcm845x/platform_def.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <npcm845x_arm_def.h> +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +#define VALUE_TO_STRING(x) #x +#define VALUE(x) VALUE_TO_STRING(x) +#define VAR_NAME_VALUE(var) #var "=" VALUE(var) + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE 0x400 + +#define PLATFORM_CORE_COUNT NPCM845x_PLATFORM_CORE_COUNT +#define PLATFORM_CLUSTER_COUNT NPCM845x_CLUSTER_COUNT +#define PLATFORM_MAX_CPU_PER_CLUSTER NPCM845x_MAX_CPU_PER_CLUSTER +#define PLAT_PRIMARY_CPU NPCM845x_PLAT_PRIMARY_CPU +#define PLATFORM_SYSTEM_COUNT NPCM845x_SYSTEM_COUNT + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF +#define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) +#define NPCM845x_MAX_PWR_LVL ARM_PWR_LVL1 + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER_COUNT PLATFORM_CLUSTER_COUNT + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL NPCM845x_MAX_PWR_LVL + +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +#ifdef BL32_BASE + +#ifndef CONFIG_TARGET_ARBEL_PALLADIUM +#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE +#else +#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE +#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ + +#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ +#endif /* BL32_BASE */ + +#define PWR_DOMAIN_AT_MAX_LVL U(1) + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 16 +#define PLAT_ARM_MMAP_ENTRIES 17 + +#ifdef NPCM845X_DEBUG +#define MAX_MMAP_REGIONS 8 +#define NPCM845X_TZ1_BASE 0xFFFB0000 +#endif /* NPCM845X_DEBUG */ + +#define FIQ_SMP_CALL_SGI 10 + +/* (0x00040000) 128 KB, the rest 128K if it is non secured */ +#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00020000) + +#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ + +/* UL(0xfffCE000) add calc ARM_TRUSTED_SRAM_BASE */ +#define ARM_SHARED_RAM_BASE (BL31_BASE + 0x00020000 - ARM_SHARED_RAM_SIZE) + +/* The remaining Trusted SRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE) + +/* + * PLAT_ARM_TRUSTED_SRAM_SIZE is taken from platform_def.h 0x20000 + * because only half is secured in this specific implementation + */ +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) + +#if RESET_TO_BL31 +/* Size of Trusted SRAM - the first 4KB of shared memory */ +#define PLAT_ARM_MAX_BL31_SIZE \ + (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) +#else +/* + * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE + * is calculated using the current BL31 PROGBITS debug size plus the sizes + * of BL2 and BL1-RW + */ +#define PLAT_ARM_MAX_BL31_SIZE \ + (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) +#endif /* RESET_TO_BL31 */ +/* + * Load address of BL33 for this platform port + */ +#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x6208000)) + +#ifdef NPCM845X_DEBUG +#define COUNTER_FREQUENCY 0x07735940 /* f/4 = 125MHz */ +#endif /* NPCM845X_DEBUG */ + +#define COUNTER_FREQUENCY 0x0EE6B280 /* f/2 = 250MHz */ +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) + +/* GIC parameters */ + +/* Base compatible GIC memory map */ +#define NT_GIC_BASE (0xDFFF8000) +#define BASE_GICD_BASE (NT_GIC_BASE + 0x1000) +#define BASE_GICC_BASE (NT_GIC_BASE + 0x2000) +#define BASE_GICR_BASE (NT_GIC_BASE + 0x200000) +#define BASE_GICH_BASE (NT_GIC_BASE + 0x4000) +#define BASE_GICV_BASE (NT_GIC_BASE + 0x6000) + +#define DEVICE1_BASE BASE_GICD_BASE +#define DEVICE1_SIZE 0x7000 + +#ifdef NPCM845X_DEBUG +/* ((BASE_GICR_BASE - BASE_GICD_BASE) + (PLATFORM_CORE_COUNT * 0x20000)) */ +#define ARM_CPU_START_ADDRESS(m) UL(0xf0800e00 + 0x10 + m * 4) +#endif /* NPCM845X_DEBUG */ + +#define PLAT_REG_BASE NPCM845x_REG_BASE +#define PLAT_REG_SIZE NPCM845x_REG_SIZE + +/* MMU entry for internal (register) space access */ +#define MAP_DEVICE0 \ + MAP_REGION_FLAT(PLAT_REG_BASE, PLAT_REG_SIZE, MT_DEVICE | MT_RW | MT_NS) + +#define MAP_DEVICE1 \ + MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties + * as per GICv3 terminology. On a GICv2 system or mode, + * the lists will be merged and treated as Group 0 interrupts. + */ +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE + +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) + +/* Required for compilation: */ + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE 0 /* UL(0xB000) */ +#if USE_ROMLIB +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) +#else +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) +#endif /* USE_ROMLIB */ + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size + * plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +#define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) * FVP_BL2_ROMLIB_OPTIMIZATION) +#else +/* (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) */ +#define PLAT_ARM_MAX_BL2_SIZE 0 +#endif /* TRUSTED_BOARD_BOOT */ + +#undef NPCM_PRINT_ONCE +#ifdef NPCM_PRINT_ONCE +#define PRINT_ONLY_ONCE +#pragma message(VAR_NAME_VALUE(ARM_AP_TZC_DRAM1_BASE)) +#pragma message(VAR_NAME_VALUE(BL31_BASE)) +#pragma message(VAR_NAME_VALUE(BL31_LIMIT)) +#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL31_SIZE)) +#pragma message(VAR_NAME_VALUE(BL32_BASE)) +#pragma message(VAR_NAME_VALUE(BL32_LIMIT)) +#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL32_SIZE) +#pragma message(VAR_NAME_VALUE(SPMD_SPM_AT_SEL2_KKO)) +#endif /* NPCM_PRINT_ONCE */ + +#define MAX_IO_DEVICES 4 +#define MAX_IO_HANDLES 4 + +#define PLAT_ARM_FIP_BASE 0x0 +#define PLAT_ARM_FIP_MAX_SIZE PLAT_ARM_MAX_BL31_SIZE + +#define PLAT_ARM_BOOT_UART_BASE 0xF0000000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 115200 +#define PLAT_ARM_RUN_UART_BASE 0xF0000000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ 115200 +#define PLAT_ARM_CRASH_UART_BASE 0xF0000000 +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 115200 + +/* + * Mailbox to control the secondary cores.All secondary cores are held in a wait + * loop in cold boot. To release them perform the following steps (plus any + * additional barriers that may be needed): + * + * uint64_t *entrypoint = (uint64_t *)PLAT_NPCM_TM_ENTRYPOINT; + * *entrypoint = ADDRESS_TO_JUMP_TO; + * + * uint64_t *mbox_entry = (uint64_t *)PLAT_NPCM_TM_HOLD_BASE; + * mbox_entry[cpu_id] = PLAT_NPCM_TM_HOLD_BASE; + * + * sev(); + */ +#define PLAT_NPCM_TRUSTED_MAILBOX_BASE ARM_SHARED_RAM_BASE + +/* The secure entry point to be used on warm reset by all CPUs. */ +#define PLAT_NPCM_TM_ENTRYPOINT PLAT_NPCM_TRUSTED_MAILBOX_BASE +#define PLAT_NPCM_TM_ENTRYPOINT_SIZE ULL(8) + +/* Hold entries for each CPU. */ +#define PLAT_NPCM_TM_HOLD_BASE \ + (PLAT_NPCM_TM_ENTRYPOINT + PLAT_NPCM_TM_ENTRYPOINT_SIZE) +#define PLAT_NPCM_TM_HOLD_ENTRY_SIZE ULL(8) +#define PLAT_NPCM_TM_HOLD_SIZE \ + (PLAT_NPCM_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT) +#define PLAT_NPCM_TRUSTED_NOTIFICATION_BASE \ + (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE) + +#define PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE ULL(8) + +#define PLAT_NPCM_TRUSTED_NOTIFICATION_SIZE \ + (PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE * PLATFORM_CORE_COUNT) + +#define PLAT_NPCM_TRUSTED_MAILBOX_SIZE \ + (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE + \ + PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE) + +#define PLAT_NPCM_TM_HOLD_STATE_WAIT ULL(0) +#define PLAT_NPCM_TM_HOLD_STATE_GO ULL(1) +#define PLAT_NPCM_TM_HOLD_STATE_BSP_OFF ULL(2) + +#define PLAT_NPCM_TM_NOTIFICATION_START ULL(0xAA) +#define PLAT_NPCM_TM_NOTIFICATION_BR ULL(0xCC) + +#ifdef NPCM845X_DEBUG +#define PLAT_ARM_TRUSTED_MAILBOX_BASE 0xfffB0000 +#endif /* NPCM845X_DEBUG */ + +#endif /* PLATFORM_DEF_H */ diff --git a/include/services/arm_arch_svc.h b/include/services/arm_arch_svc.h index 5bbd8bb6c5..645b388fee 100644 --- a/include/services/arm_arch_svc.h +++ b/include/services/arm_arch_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,7 @@ #define SMCCC_ARCH_SOC_ID U(0x80000002) #define SMCCC_ARCH_WORKAROUND_1 U(0x80008000) #define SMCCC_ARCH_WORKAROUND_2 U(0x80007FFF) +#define SMCCC_ARCH_WORKAROUND_3 U(0x80003FFF) #define SMCCC_GET_SOC_VERSION U(0) #define SMCCC_GET_SOC_REVISION U(1) diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h new file mode 100644 index 0000000000..f0d3c63bc1 --- /dev/null +++ b/include/services/drtm_svc.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2022-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * DRTM service + * + * Authors: + * Lucian Paul-Trifu <lucian.paultrifu@gmail.com> + * Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01 + * + */ + +#ifndef ARM_DRTM_SVC_H +#define ARM_DRTM_SVC_H + +/* + * SMC function IDs for DRTM Service + * Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4) + */ +#define DRTM_FID(func_num) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + (SMC_64 << FUNCID_CC_SHIFT) | \ + (OEN_STD_START << FUNCID_OEN_SHIFT) | \ + ((func_num) << FUNCID_NUM_SHIFT)) + +#define DRTM_FNUM_SVC_VERSION U(0x110) +#define DRTM_FNUM_SVC_FEATURES U(0x111) +#define DRTM_FNUM_SVC_UNPROTECT_MEM U(0x113) +#define DRTM_FNUM_SVC_DYNAMIC_LAUNCH U(0x114) +#define DRTM_FNUM_SVC_CLOSE_LOCALITY U(0x115) +#define DRTM_FNUM_SVC_GET_ERROR U(0x116) +#define DRTM_FNUM_SVC_SET_ERROR U(0x117) +#define DRTM_FNUM_SVC_SET_TCB_HASH U(0x118) +#define DRTM_FNUM_SVC_LOCK_TCB_HASH U(0x119) + +#define ARM_DRTM_SVC_VERSION DRTM_FID(DRTM_FNUM_SVC_VERSION) +#define ARM_DRTM_SVC_FEATURES DRTM_FID(DRTM_FNUM_SVC_FEATURES) +#define ARM_DRTM_SVC_UNPROTECT_MEM DRTM_FID(DRTM_FNUM_SVC_UNPROTECT_MEM) +#define ARM_DRTM_SVC_DYNAMIC_LAUNCH DRTM_FID(DRTM_FNUM_SVC_DYNAMIC_LAUNCH) +#define ARM_DRTM_SVC_CLOSE_LOCALITY DRTM_FID(DRTM_FNUM_SVC_CLOSE_LOCALITY) +#define ARM_DRTM_SVC_GET_ERROR DRTM_FID(DRTM_FNUM_SVC_GET_ERROR) +#define ARM_DRTM_SVC_SET_ERROR DRTM_FID(DRTM_FNUM_SVC_SET_ERROR) +#define ARM_DRTM_SVC_SET_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_SET_TCB_HASH) +#define ARM_DRTM_SVC_LOCK_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_LOCK_TCB_HASH) + +#define ARM_DRTM_FEATURES_TPM U(0x1) +#define ARM_DRTM_FEATURES_MEM_REQ U(0x2) +#define ARM_DRTM_FEATURES_DMA_PROT U(0x3) +#define ARM_DRTM_FEATURES_BOOT_PE_ID U(0x4) +#define ARM_DRTM_FEATURES_TCB_HASHES U(0x5) + +#define is_drtm_fid(_fid) \ + (((_fid) >= ARM_DRTM_SVC_VERSION) && ((_fid) <= ARM_DRTM_SVC_LOCK_TCB_HASH)) + +/* ARM DRTM Service Calls version numbers */ +#define ARM_DRTM_VERSION_MAJOR U(1) +#define ARM_DRTM_VERSION_MAJOR_SHIFT 16 +#define ARM_DRTM_VERSION_MAJOR_MASK U(0x7FFF) +#define ARM_DRTM_VERSION_MINOR U(0) +#define ARM_DRTM_VERSION_MINOR_SHIFT 0 +#define ARM_DRTM_VERSION_MINOR_MASK U(0xFFFF) + +#define ARM_DRTM_VERSION \ + ((((ARM_DRTM_VERSION_MAJOR) & ARM_DRTM_VERSION_MAJOR_MASK) << \ + ARM_DRTM_VERSION_MAJOR_SHIFT) \ + | (((ARM_DRTM_VERSION_MINOR) & ARM_DRTM_VERSION_MINOR_MASK) << \ + ARM_DRTM_VERSION_MINOR_SHIFT)) + +#define ARM_DRTM_FUNC_SHIFT U(63) +#define ARM_DRTM_FUNC_MASK ULL(0x1) +#define ARM_DRTM_FUNC_ID U(0x0) +#define ARM_DRTM_FEAT_ID U(0x1) +#define ARM_DRTM_FEAT_ID_MASK ULL(0xff) + +/* + * Definitions for DRTM features as per DRTM 1.0 section 3.3, + * Table 6 DRTM_FEATURES + */ +#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT U(33) +#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF) +#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1) + +#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT U(32) +#define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1) +#define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED ULL(0x0) +#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1) + +#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT U(0) +#define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK ULL(0xFFFF) +#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB) +#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC) +#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512 ULL(0xD) + +#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT U(32) +#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK ULL(0xFFFFFFFF) + +#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT U(0) +#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF) + +#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8) +#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF) + +#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0) +#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF) +#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE ULL(0x1) +#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION ULL(0x2) + +#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT U(0) +#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK ULL(0xFF) + +#define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \ + do { \ + reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \ + << ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \ + ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) << \ + ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)); \ + } while (false) + +#define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \ + do { \ + reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK \ + << ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) & \ + ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) << \ + ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)); \ + } while (false) + +#define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \ + do { \ + reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK \ + << ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) & \ + ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) << \ + ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)); \ + } while (false) + +#define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \ + do { \ + reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK \ + << ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) & \ + ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) << \ + ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)); \ + } while (false) + +#define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK << \ + ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) | \ + (((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \ + << ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)); \ + } while (false) + +#define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK << \ + ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) | \ + (((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK) \ + << ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)); \ + } while (false) + +#define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK << \ + ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) | \ + (((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK) \ + << ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)); \ + } while (false) + +#define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK << \ + ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) | \ + (((val) & \ + ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) << \ + ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)); \ + } while (false) + +/* Definitions for DRTM address map */ +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT U(55) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK ULL(0x3) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC ULL(0) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC ULL(1) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT ULL(2) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB ULL(3) + +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT U(52) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK ULL(0x7) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL ULL(0) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR ULL(1) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE ULL(2) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV ULL(3) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD ULL(4) + +#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT U(0) +#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK ULL(0xFFFFFFFFFFFFF) + +#define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << \ + ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) | \ + (((val) & \ + ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) << \ + ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)); \ + } while (false) + +#define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK << \ + ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) | \ + (((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK) \ + << ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)); \ + } while (false) + +#define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK << \ + ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) | \ + (((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK) \ + << ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)); \ + } while (false) + +/* Initialization routine for the DRTM service */ +int drtm_setup(void); + +/* Handler to be called to handle DRTM SMC calls */ +uint64_t drtm_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); + +#endif /* ARM_DRTM_SVC_H */ diff --git a/include/services/el3_spmc_ffa_memory.h b/include/services/el3_spmc_ffa_memory.h new file mode 100644 index 0000000000..5d3af5de78 --- /dev/null +++ b/include/services/el3_spmc_ffa_memory.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EL3_SPMC_FFA_MEM_H +#define EL3_SPMC_FFA_MEM_H + +#include <assert.h> + +/* + * Subset of Arm Firmware Framework for Armv8-A + * (https://developer.arm.com/docs/den0077/a) needed for shared memory. + */ + +/** + * typedef ffa_endpoint_id16_t - Endpoint ID + * + * Current implementation only supports VM IDs. FF-A spec also support stream + * endpoint ids. + */ +typedef uint16_t ffa_endpoint_id16_t; + +/** + * struct ffa_cons_mrd - Constituent memory region descriptor + * @address: + * Start address of contiguous memory region. Must be 4K page aligned. + * @page_count: + * Number of 4K pages in region. + * @reserved_12_15: + * Reserve bytes 12-15 to pad struct size to 16 bytes. + */ +struct ffa_cons_mrd { + uint64_t address; + uint32_t page_count; + uint32_t reserved_12_15; +}; +CASSERT(sizeof(struct ffa_cons_mrd) == 16, assert_ffa_cons_mrd_size_mismatch); + +/** + * struct ffa_comp_mrd - Composite memory region descriptor + * @total_page_count: + * Number of 4k pages in memory region. Must match sum of + * @address_range_array[].page_count. + * @address_range_count: + * Number of entries in @address_range_array. + * @reserved_8_15: + * Reserve bytes 8-15 to pad struct size to 16 byte alignment and + * make @address_range_array 16 byte aligned. + * @address_range_array: + * Array of &struct ffa_cons_mrd entries. + */ +struct ffa_comp_mrd { + uint32_t total_page_count; + uint32_t address_range_count; + uint64_t reserved_8_15; + struct ffa_cons_mrd address_range_array[]; +}; +CASSERT(sizeof(struct ffa_comp_mrd) == 16, assert_ffa_comp_mrd_size_mismatch); + +/** + * typedef ffa_mem_attr8_t - Memory region attributes v1.0. + * typedef ffa_mem_attr16_t - Memory region attributes v1.1. + * + * * @FFA_MEM_ATTR_NS_BIT: + * Memory security state. + * * @FFA_MEM_ATTR_DEVICE_NGNRNE: + * Device-nGnRnE. + * * @FFA_MEM_ATTR_DEVICE_NGNRE: + * Device-nGnRE. + * * @FFA_MEM_ATTR_DEVICE_NGRE: + * Device-nGRE. + * * @FFA_MEM_ATTR_DEVICE_GRE: + * Device-GRE. + * * @FFA_MEM_ATTR_NORMAL_MEMORY_UNCACHED + * Normal memory. Non-cacheable. + * * @FFA_MEM_ATTR_NORMAL_MEMORY_CACHED_WB + * Normal memory. Write-back cached. + * * @FFA_MEM_ATTR_NON_SHAREABLE + * Non-shareable. Combine with FFA_MEM_ATTR_NORMAL_MEMORY_*. + * * @FFA_MEM_ATTR_OUTER_SHAREABLE + * Outer Shareable. Combine with FFA_MEM_ATTR_NORMAL_MEMORY_*. + * * @FFA_MEM_ATTR_INNER_SHAREABLE + * Inner Shareable. Combine with FFA_MEM_ATTR_NORMAL_MEMORY_*. + */ +typedef uint8_t ffa_mem_attr8_t; +typedef uint16_t ffa_mem_attr16_t; +#define FFA_MEM_ATTR_NS_BIT (0x1U << 6) +#define FFA_MEM_ATTR_DEVICE_NGNRNE ((1U << 4) | (0x0U << 2)) +#define FFA_MEM_ATTR_DEVICE_NGNRE ((1U << 4) | (0x1U << 2)) +#define FFA_MEM_ATTR_DEVICE_NGRE ((1U << 4) | (0x2U << 2)) +#define FFA_MEM_ATTR_DEVICE_GRE ((1U << 4) | (0x3U << 2)) +#define FFA_MEM_ATTR_NORMAL_MEMORY_UNCACHED ((2U << 4) | (0x1U << 2)) +#define FFA_MEM_ATTR_NORMAL_MEMORY_CACHED_WB ((2U << 4) | (0x3U << 2)) +#define FFA_MEM_ATTR_NON_SHAREABLE (0x0U << 0) +#define FFA_MEM_ATTR_OUTER_SHAREABLE (0x2U << 0) +#define FFA_MEM_ATTR_INNER_SHAREABLE (0x3U << 0) + +/** + * typedef ffa_mem_perm8_t - Memory access permissions + * + * * @FFA_MEM_ATTR_RO + * Request or specify read-only mapping. + * * @FFA_MEM_ATTR_RW + * Request or allow read-write mapping. + * * @FFA_MEM_PERM_NX + * Deny executable mapping. + * * @FFA_MEM_PERM_X + * Request executable mapping. + */ +typedef uint8_t ffa_mem_perm8_t; +#define FFA_MEM_PERM_RO (1U << 0) +#define FFA_MEM_PERM_RW (1U << 1) +#define FFA_MEM_PERM_NX (1U << 2) +#define FFA_MEM_PERM_X (1U << 3) + +/** + * typedef ffa_mem_flag8_t - Endpoint memory flags + * + * * @FFA_MEM_FLAG_NON_RETRIEVAL_BORROWER + * Non-retrieval Borrower. Memory region must not be or was not retrieved on + * behalf of this endpoint. + */ +typedef uint8_t ffa_mem_flag8_t; +#define FFA_MEM_FLAG_NON_RETRIEVAL_BORROWER (1U << 0) + +/** + * typedef ffa_mtd_flag32_t - Memory transaction descriptor flags + * + * * @FFA_MTD_FLAG_ZERO_MEMORY + * Zero memory after unmapping from sender (must be 0 for share). + * * @FFA_MTD_FLAG_TIME_SLICING + * Not supported by this implementation. + * * @FFA_MTD_FLAG_ZERO_MEMORY_AFTER_RELINQUISH + * Zero memory after unmapping from borrowers (must be 0 for share). + * * @FFA_MTD_FLAG_TYPE_MASK + * Bit-mask to extract memory management transaction type from flags. + * * @FFA_MTD_FLAG_TYPE_SHARE_MEMORY + * Share memory transaction flag. + * Used by @SMC_FC_FFA_MEM_RETRIEVE_RESP to indicate that memory came from + * @SMC_FC_FFA_MEM_SHARE and by @SMC_FC_FFA_MEM_RETRIEVE_REQ to specify that + * it must have. + * * @FFA_MTD_FLAG_ADDRESS_RANGE_ALIGNMENT_HINT_MASK + * Not supported by this implementation. + */ +typedef uint32_t ffa_mtd_flag32_t; +#define FFA_MTD_FLAG_ZERO_MEMORY (1U << 0) +#define FFA_MTD_FLAG_TIME_SLICING (1U << 1) +#define FFA_MTD_FLAG_ZERO_MEMORY_AFTER_RELINQUISH (1U << 2) +#define FFA_MTD_FLAG_TYPE_MASK (3U << 3) +#define FFA_MTD_FLAG_TYPE_SHARE_MEMORY (1U << 3) +#define FFA_MTD_FLAG_TYPE_LEND_MEMORY (1U << 4) +#define FFA_MTD_FLAG_ADDRESS_RANGE_ALIGNMENT_HINT_MASK (0x1FU << 5) + +/** + * struct ffa_mapd - Memory access permissions descriptor + * @endpoint_id: + * Endpoint id that @memory_access_permissions and @flags apply to. + * (&typedef ffa_endpoint_id16_t). + * @memory_access_permissions: + * FFA_MEM_PERM_* values or'ed together (&typedef ffa_mem_perm8_t). + * @flags: + * FFA_MEM_FLAG_* values or'ed together (&typedef ffa_mem_flag8_t). + */ +struct ffa_mapd { + ffa_endpoint_id16_t endpoint_id; + ffa_mem_perm8_t memory_access_permissions; + ffa_mem_flag8_t flags; +}; +CASSERT(sizeof(struct ffa_mapd) == 4, assert_ffa_mapd_size_mismatch); + +/** + * struct ffa_emad_v1_0 - Endpoint memory access descriptor. + * @mapd: &struct ffa_mapd. + * @comp_mrd_offset: + * Offset of &struct ffa_comp_mrd from start of &struct ffa_mtd_v1_0. + * @reserved_8_15: + * Reserved bytes 8-15. Must be 0. + */ +struct ffa_emad_v1_0 { + struct ffa_mapd mapd; + uint32_t comp_mrd_offset; + uint64_t reserved_8_15; +}; +CASSERT(sizeof(struct ffa_emad_v1_0) == 16, assert_ffa_emad_v1_0_size_mismatch); + +/** + * struct ffa_mtd_v1_0 - Memory transaction descriptor. + * @sender_id: + * Sender endpoint id. + * @memory_region_attributes: + * FFA_MEM_ATTR_* values or'ed together (&typedef ffa_mem_attr8_t). + * @reserved_3: + * Reserved bytes 3. Must be 0. + * @flags: + * FFA_MTD_FLAG_* values or'ed together (&typedef ffa_mtd_flag32_t). + * @handle: + * Id of shared memory object. Must be 0 for MEM_SHARE or MEM_LEND. + * @tag: Client allocated tag. Must match original value. + * @reserved_24_27: + * Reserved bytes 24-27. Must be 0. + * @emad_count: + * Number of entries in @emad. + * @emad: + * Endpoint memory access descriptor array (see @struct ffa_emad_v1_0). + */ +struct ffa_mtd_v1_0 { + ffa_endpoint_id16_t sender_id; + ffa_mem_attr8_t memory_region_attributes; + uint8_t reserved_3; + ffa_mtd_flag32_t flags; + uint64_t handle; + uint64_t tag; + uint32_t reserved_24_27; + uint32_t emad_count; + struct ffa_emad_v1_0 emad[]; +}; +CASSERT(sizeof(struct ffa_mtd_v1_0) == 32, assert_ffa_mtd_size_v1_0_mismatch); +CASSERT(offsetof(struct ffa_mtd_v1_0, emad) == 32, + assert_ffa_mtd_size_v1_0_mismatch_2); + +/** + * struct ffa_mtd - Memory transaction descriptor for FF-A v1.1. + * @sender_id: + * Sender endpoint id. + * @memory_region_attributes: + * FFA_MEM_ATTR_* values or'ed together (&typedef ffa_mem_attr16_t). + * @flags: + * FFA_MTD_FLAG_* values or'ed together (&typedef ffa_mtd_flag32_t). + * @handle: + * Id of shared memory object. Must be 0 for MEM_SHARE or MEM_LEND. + * @tag: Client allocated tag. Must match original value. + * @emad_size: + * Size of the emad descriptor. + * @emad_count: + * Number of entries in the emad array. + * @emad_offset: + * Offset from the beginning of the descriptor to the location of the + * memory access descriptor array (see @struct ffa_emad_v1_0). + * @reserved_36_39: + * Reserved bytes 36-39. Must be 0. + * @reserved_40_47: + * Reserved bytes 44-47. Must be 0. + */ +struct ffa_mtd { + ffa_endpoint_id16_t sender_id; + ffa_mem_attr16_t memory_region_attributes; + ffa_mtd_flag32_t flags; + uint64_t handle; + uint64_t tag; + uint32_t emad_size; + uint32_t emad_count; + uint32_t emad_offset; + uint32_t reserved_36_39; + uint64_t reserved_40_47; +}; +CASSERT(sizeof(struct ffa_mtd) == 48, assert_ffa_mtd_size_mismatch); +CASSERT(offsetof(struct ffa_mtd, emad_count) == + offsetof(struct ffa_mtd_v1_0, emad_count), + assert_ffa_mtd_emad_count_offset_mismatch); + +#endif /* EL3_SPMC_FFA_MEM_H */ diff --git a/include/services/el3_spmc_logical_sp.h b/include/services/el3_spmc_logical_sp.h new file mode 100644 index 0000000000..dccd362da1 --- /dev/null +++ b/include/services/el3_spmc_logical_sp.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef EL3_SP_H +#define EL3_SP_H + +#include <common/bl_common.h> +#include <lib/cassert.h> + +/******************************************************************************* + * Structure definition, typedefs & constants for the Logical SPs. + ******************************************************************************/ + +typedef uint64_t (*direct_msg_handler)(uint32_t smc_fid, bool secure_origin, + uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, + uint64_t flags); + +/* Prototype for logical partition initializing function. */ +typedef int32_t (*ffa_partition_init_t)(void); + +/* Logical Partition Descriptor. */ +struct el3_lp_desc { + ffa_partition_init_t init; + uint16_t sp_id; + uint32_t properties; + uint32_t uuid[4]; /* Little Endian. */ + direct_msg_handler direct_req; + const char *debug_name; +}; + +/* Convenience macro to declare a logical partition descriptor. */ +#define DECLARE_LOGICAL_PARTITION(_name, _init, _sp_id, _uuid, _properties, \ + _direct_req) \ + static const struct el3_lp_desc __partition_desc_ ## _name \ + __section(".el3_lp_descs") __used = { \ + .debug_name = #_name, \ + .init = (_init), \ + .sp_id = (_sp_id), \ + .uuid = _uuid, \ + .properties = (_properties), \ + .direct_req = (_direct_req), \ + } + + +/******************************************************************************* + * Function & variable prototypes. + ******************************************************************************/ +int el3_sp_desc_validate(void); + +IMPORT_SYM(uintptr_t, __EL3_LP_DESCS_START__, EL3_LP_DESCS_START); +IMPORT_SYM(uintptr_t, __EL3_LP_DESCS_END__, EL3_LP_DESCS_END); + +#define EL3_LP_DESCS_COUNT ((EL3_LP_DESCS_END - EL3_LP_DESCS_START) \ + / sizeof(struct el3_lp_desc)) + +#endif /* EL3_SP_H */ diff --git a/include/services/el3_spmd_logical_sp.h b/include/services/el3_spmd_logical_sp.h new file mode 100644 index 0000000000..15bea9f5f0 --- /dev/null +++ b/include/services/el3_spmd_logical_sp.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef EL3_SPMD_LOGICAL_SP_H +#define EL3_SPMD_LOGICAL_SP_H + +#include <common/bl_common.h> +#include <lib/cassert.h> +#include <services/ffa_svc.h> + +/******************************************************************************* + * Structure definition, typedefs & constants for the SPMD Logical Partitions. + ******************************************************************************/ +typedef struct spmd_spm_core_context spmd_spm_core_context_t; + +/* Prototype for SPMD logical partition initializing function. */ +typedef int32_t (*ffa_spmd_lp_init_t)(void); + +/* SPMD Logical Partition Descriptor. */ +struct spmd_lp_desc { + ffa_spmd_lp_init_t init; + uint16_t sp_id; + uint32_t properties; + uint32_t uuid[4]; /* Little Endian. */ + const char *debug_name; +}; + +struct ffa_value { + uint64_t func; + uint64_t arg1; + uint64_t arg2; + uint64_t arg3; + uint64_t arg4; + uint64_t arg5; + uint64_t arg6; + uint64_t arg7; + uint64_t arg8; + uint64_t arg9; + uint64_t arg10; + uint64_t arg11; + uint64_t arg12; + uint64_t arg13; + uint64_t arg14; + uint64_t arg15; + uint64_t arg16; + uint64_t arg17; +}; + +/* Convenience macro to declare a SPMD logical partition descriptor. */ +#define DECLARE_SPMD_LOGICAL_PARTITION(_name, _init, _sp_id, _uuid, _properties) \ + static const struct spmd_lp_desc __partition_desc_ ## _name \ + __section(".spmd_lp_descs") __used = { \ + .debug_name = #_name, \ + .init = (_init), \ + .sp_id = (_sp_id), \ + .uuid = _uuid, \ + .properties = (_properties), \ + } + +IMPORT_SYM(uintptr_t, __SPMD_LP_DESCS_START__, SPMD_LP_DESCS_START); +IMPORT_SYM(uintptr_t, __SPMD_LP_DESCS_END__, SPMD_LP_DESCS_END); + +#define SPMD_LP_DESCS_COUNT ((SPMD_LP_DESCS_END - SPMD_LP_DESCS_START) \ + / sizeof(struct spmd_lp_desc)) +CASSERT(sizeof(struct spmd_lp_desc) == 40, assert_spmd_lp_desc_size_mismatch); + +/* + * Reserve 63 IDs for SPMD Logical Partitions. Currently, 0xFFC0 to 0xFFFE + * is reserved. + */ +#define SPMD_LP_ID_END (SPMD_DIRECT_MSG_ENDPOINT_ID - 1) +#define SPMD_LP_ID_START (SPMD_LP_ID_END - 62) + +/* + * TODO: Arbitrary number. Can make this platform specific in the future, + * no known use cases for more LPs at this point. + */ +#define EL3_SPMD_MAX_NUM_LP U(5) + +static inline bool is_spmd_lp_id(unsigned int id) +{ +#if ENABLE_SPMD_LP + return (id >= SPMD_LP_ID_START && id <= SPMD_LP_ID_END); +#else + return false; +#endif +} + +static inline bool is_ffa_error(struct ffa_value *retval) +{ + return retval->func == FFA_ERROR; +} + +static inline bool is_ffa_success(struct ffa_value *retval) +{ + return (retval->func == FFA_SUCCESS_SMC32) || + (retval->func == FFA_SUCCESS_SMC64); +} + +static inline bool is_ffa_direct_msg_resp(struct ffa_value *retval) +{ + return (retval->func == FFA_MSG_SEND_DIRECT_RESP_SMC32) || + (retval->func == FFA_MSG_SEND_DIRECT_RESP_SMC64); +} + +static inline uint16_t ffa_partition_info_regs_get_last_idx( + struct ffa_value *args) +{ + return (uint16_t)(args->arg2 & 0xFFFFU); +} + +static inline uint16_t ffa_partition_info_regs_get_curr_idx( + struct ffa_value *args) +{ + return (uint16_t)((args->arg2 >> 16) & 0xFFFFU); +} + +static inline uint16_t ffa_partition_info_regs_get_tag(struct ffa_value *args) +{ + return (uint16_t)((args->arg2 >> 32) & 0xFFFFU); +} + +static inline uint16_t ffa_partition_info_regs_get_desc_size( + struct ffa_value *args) +{ + return (uint16_t)(args->arg2 >> 48); +} + +uint64_t spmd_el3_populate_logical_partition_info(void *handle, uint64_t x1, + uint64_t x2, uint64_t x3); + +bool ffa_partition_info_regs_get_part_info( + struct ffa_value *args, uint8_t idx, + struct ffa_partition_info_v1_1 *partition_info); + +bool spmd_el3_invoke_partition_info_get( + const uint32_t target_uuid[4], + const uint16_t start_index, + const uint16_t tag, + struct ffa_value *retval); +void spmd_logical_sp_set_spmc_initialized(void); +void spmc_logical_sp_set_spmc_failure(void); + +int32_t spmd_logical_sp_init(void); +bool is_spmd_logical_sp_dir_req_in_progress( + spmd_spm_core_context_t *ctx); + +bool is_spmd_logical_sp_info_regs_req_in_progress( + spmd_spm_core_context_t *ctx); + +bool spmd_el3_ffa_msg_direct_req(uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *handle, + struct ffa_value *retval); + +uintptr_t plat_spmd_logical_sp_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); + +#endif /* EL3_SPMD_LOGICAL_SP_H */ diff --git a/include/services/errata_abi_svc.h b/include/services/errata_abi_svc.h new file mode 100644 index 0000000000..12500661b5 --- /dev/null +++ b/include/services/errata_abi_svc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ERRATA_ABI_SVC_H +#define ERRATA_ABI_SVC_H + +#include <lib/smccc.h> + +#define ARM_EM_VERSION U(0x840000F0) +#define ARM_EM_FEATURES U(0x840000F1) +#define ARM_EM_CPU_ERRATUM_FEATURES U(0x840000F2) + +/* EM version numbers */ +#define EM_VERSION_MAJOR (0x1) +#define EM_VERSION_MINOR (0x0) + +/* EM CPU_ERRATUM_FEATURES return codes */ +#define EM_HIGHER_EL_MITIGATION (3) +#define EM_NOT_AFFECTED (2) +#define EM_AFFECTED (1) +#define EM_SUCCESS (0) +#define EM_NOT_SUPPORTED (-1) +#define EM_INVALID_PARAMETERS (-2) +#define EM_UNKNOWN_ERRATUM (-3) + +#if ERRATA_ABI_SUPPORT +bool is_errata_fid(uint32_t smc_fid); +#else +static inline bool is_errata_fid(uint32_t smc_fid) +{ + return false; +} +#endif /* ERRATA_ABI_SUPPORT */ +uintptr_t errata_abi_smc_handler( + uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags +); +#endif /* ERRATA_ABI_SVC_H */ + diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h index ec75bc935b..01dbea9797 100644 --- a/include/services/ffa_svc.h +++ b/include/services/ffa_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef FFA_SVC_H #define FFA_SVC_H +#include <stdbool.h> + #include <lib/smccc.h> #include <lib/utils_def.h> #include <tools_share/uuid.h> @@ -22,7 +24,7 @@ /* The macros below are used to identify FFA calls from the SMC function ID */ #define FFA_FNUM_MIN_VALUE U(0x60) -#define FFA_FNUM_MAX_VALUE U(0x84) +#define FFA_FNUM_MAX_VALUE U(0x8E) #define is_ffa_fid(fid) __extension__ ({ \ __typeof__(fid) _fid = (fid); \ ((GET_SMC_NUM(_fid) >= FFA_FNUM_MIN_VALUE) && \ @@ -32,10 +34,11 @@ #define FFA_VERSION_MAJOR U(1) #define FFA_VERSION_MAJOR_SHIFT 16 #define FFA_VERSION_MAJOR_MASK U(0x7FFF) -#define FFA_VERSION_MINOR U(0) +#define FFA_VERSION_MINOR U(2) #define FFA_VERSION_MINOR_SHIFT 0 #define FFA_VERSION_MINOR_MASK U(0xFFFF) #define FFA_VERSION_BIT31_MASK U(0x1u << 31) +#define FFA_VERSION_MASK U(0xFFFFFFFF) #define MAKE_FFA_VERSION(major, minor) \ @@ -53,6 +56,19 @@ (((blk) & FFA_MSG_SEND_ATTRS_BLK_MASK) \ << FFA_MSG_SEND_ATTRS_BLK_SHIFT) +/* Defines for FF-A framework messages exchanged using direct messages. */ +#define FFA_FWK_MSG_BIT BIT(31) +#define FFA_FWK_MSG_MASK 0xFF +#define FFA_FWK_MSG_PSCI U(0x0) + +/* Defines for FF-A power management messages framework messages. */ +#define FFA_PM_MSG_WB_REQ U(0x1) /* Warm boot request. */ +#define FFA_PM_MSG_PM_RESP U(0x2) /* Response to PSCI or warmboot req. */ + +/* FF-A warm boot types. */ +#define FFA_WB_TYPE_S2RAM 0x0 +#define FFA_WB_TYPE_NOTS2RAM 0x1 + /* Get FFA fastcall std FID from function number */ #define FFA_FID(smc_cc, func_num) \ ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ @@ -61,31 +77,56 @@ ((func_num) << FUNCID_NUM_SHIFT)) /* FFA function numbers */ -#define FFA_FNUM_ERROR U(0x60) -#define FFA_FNUM_SUCCESS U(0x61) -#define FFA_FNUM_INTERRUPT U(0x62) -#define FFA_FNUM_VERSION U(0x63) -#define FFA_FNUM_FEATURES U(0x64) -#define FFA_FNUM_RX_RELEASE U(0x65) -#define FFA_FNUM_RXTX_MAP U(0x66) -#define FFA_FNUM_RXTX_UNMAP U(0x67) -#define FFA_FNUM_PARTITION_INFO_GET U(0x68) -#define FFA_FNUM_ID_GET U(0x69) -#define FFA_FNUM_MSG_POLL U(0x6A) -#define FFA_FNUM_MSG_WAIT U(0x6B) -#define FFA_FNUM_MSG_YIELD U(0x6C) -#define FFA_FNUM_MSG_RUN U(0x6D) -#define FFA_FNUM_MSG_SEND U(0x6E) -#define FFA_FNUM_MSG_SEND_DIRECT_REQ U(0x6F) -#define FFA_FNUM_MSG_SEND_DIRECT_RESP U(0x70) -#define FFA_FNUM_MEM_DONATE U(0x71) -#define FFA_FNUM_MEM_LEND U(0x72) -#define FFA_FNUM_MEM_SHARE U(0x73) -#define FFA_FNUM_MEM_RETRIEVE_REQ U(0x74) -#define FFA_FNUM_MEM_RETRIEVE_RESP U(0x75) -#define FFA_FNUM_MEM_RELINQUISH U(0x76) -#define FFA_FNUM_MEM_RECLAIM U(0x77) -#define FFA_FNUM_SECONDARY_EP_REGISTER U(0x84) +#define FFA_FNUM_ERROR U(0x60) +#define FFA_FNUM_SUCCESS U(0x61) +#define FFA_FNUM_INTERRUPT U(0x62) +#define FFA_FNUM_VERSION U(0x63) +#define FFA_FNUM_FEATURES U(0x64) +#define FFA_FNUM_RX_RELEASE U(0x65) +#define FFA_FNUM_RXTX_MAP U(0x66) +#define FFA_FNUM_RXTX_UNMAP U(0x67) +#define FFA_FNUM_PARTITION_INFO_GET U(0x68) +#define FFA_FNUM_ID_GET U(0x69) +#define FFA_FNUM_MSG_POLL U(0x6A) /* Legacy FF-A v1.0 */ +#define FFA_FNUM_MSG_WAIT U(0x6B) +#define FFA_FNUM_MSG_YIELD U(0x6C) +#define FFA_FNUM_MSG_RUN U(0x6D) +#define FFA_FNUM_MSG_SEND U(0x6E) /* Legacy FF-A v1.0 */ +#define FFA_FNUM_MSG_SEND_DIRECT_REQ U(0x6F) +#define FFA_FNUM_MSG_SEND_DIRECT_RESP U(0x70) +#define FFA_FNUM_MEM_DONATE U(0x71) +#define FFA_FNUM_MEM_LEND U(0x72) +#define FFA_FNUM_MEM_SHARE U(0x73) +#define FFA_FNUM_MEM_RETRIEVE_REQ U(0x74) +#define FFA_FNUM_MEM_RETRIEVE_RESP U(0x75) +#define FFA_FNUM_MEM_RELINQUISH U(0x76) +#define FFA_FNUM_MEM_RECLAIM U(0x77) +#define FFA_FNUM_MEM_FRAG_RX U(0x7A) +#define FFA_FNUM_MEM_FRAG_TX U(0x7B) +#define FFA_FNUM_NORMAL_WORLD_RESUME U(0x7C) + +/* FF-A v1.1 */ +#define FFA_FNUM_NOTIFICATION_BITMAP_CREATE U(0x7D) +#define FFA_FNUM_NOTIFICATION_BITMAP_DESTROY U(0x7E) +#define FFA_FNUM_NOTIFICATION_BIND U(0x7F) +#define FFA_FNUM_NOTIFICATION_UNBIND U(0x80) +#define FFA_FNUM_NOTIFICATION_SET U(0x81) +#define FFA_FNUM_NOTIFICATION_GET U(0x82) +#define FFA_FNUM_NOTIFICATION_INFO_GET U(0x83) +#define FFA_FNUM_RX_ACQUIRE U(0x84) +#define FFA_FNUM_SPM_ID_GET U(0x85) +#define FFA_FNUM_MSG_SEND2 U(0x86) +#define FFA_FNUM_SECONDARY_EP_REGISTER U(0x87) +#define FFA_FNUM_MEM_PERM_GET U(0x88) +#define FFA_FNUM_MEM_PERM_SET U(0x89) + +/* FF-A v1.2 */ +#define FFA_FNUM_PARTITION_INFO_GET_REGS U(0x8B) +#define FFA_FNUM_EL3_INTR_HANDLE U(0x8C) +#define FFA_FNUM_MSG_SEND_DIRECT_REQ2 U(0x8D) +#define FFA_FNUM_MSG_SEND_DIRECT_RESP2 U(0x8E) + +#define FFA_FNUM_CONSOLE_LOG U(0x8A) /* FFA SMC32 FIDs */ #define FFA_ERROR FFA_FID(SMC_32, FFA_FNUM_ERROR) @@ -94,6 +135,7 @@ #define FFA_VERSION FFA_FID(SMC_32, FFA_FNUM_VERSION) #define FFA_FEATURES FFA_FID(SMC_32, FFA_FNUM_FEATURES) #define FFA_RX_RELEASE FFA_FID(SMC_32, FFA_FNUM_RX_RELEASE) +#define FFA_RX_ACQUIRE FFA_FID(SMC_32, FFA_FNUM_RX_ACQUIRE) #define FFA_RXTX_MAP_SMC32 FFA_FID(SMC_32, FFA_FNUM_RXTX_MAP) #define FFA_RXTX_UNMAP FFA_FID(SMC_32, FFA_FNUM_RXTX_UNMAP) #define FFA_PARTITION_INFO_GET FFA_FID(SMC_32, FFA_FNUM_PARTITION_INFO_GET) @@ -103,6 +145,7 @@ #define FFA_MSG_YIELD FFA_FID(SMC_32, FFA_FNUM_MSG_YIELD) #define FFA_MSG_RUN FFA_FID(SMC_32, FFA_FNUM_MSG_RUN) #define FFA_MSG_SEND FFA_FID(SMC_32, FFA_FNUM_MSG_SEND) +#define FFA_MSG_SEND2 FFA_FID(SMC_32, FFA_FNUM_MSG_SEND2) #define FFA_MSG_SEND_DIRECT_REQ_SMC32 \ FFA_FID(SMC_32, FFA_FNUM_MSG_SEND_DIRECT_REQ) #define FFA_MSG_SEND_DIRECT_RESP_SMC32 \ @@ -115,6 +158,24 @@ #define FFA_MEM_RETRIEVE_RESP FFA_FID(SMC_32, FFA_FNUM_MEM_RETRIEVE_RESP) #define FFA_MEM_RELINQUISH FFA_FID(SMC_32, FFA_FNUM_MEM_RELINQUISH) #define FFA_MEM_RECLAIM FFA_FID(SMC_32, FFA_FNUM_MEM_RECLAIM) +#define FFA_NOTIFICATION_BITMAP_CREATE \ + FFA_FID(SMC_32, FFA_FNUM_NOTIFICATION_BITMAP_CREATE) +#define FFA_NOTIFICATION_BITMAP_DESTROY \ + FFA_FID(SMC_32, FFA_FNUM_NOTIFICATION_BITMAP_DESTROY) +#define FFA_NOTIFICATION_BIND FFA_FID(SMC_32, FFA_FNUM_NOTIFICATION_BIND) +#define FFA_NOTIFICATION_UNBIND FFA_FID(SMC_32, FFA_FNUM_NOTIFICATION_UNBIND) +#define FFA_NOTIFICATION_SET FFA_FID(SMC_32, FFA_FNUM_NOTIFICATION_SET) +#define FFA_NOTIFICATION_GET FFA_FID(SMC_32, FFA_FNUM_NOTIFICATION_GET) +#define FFA_NOTIFICATION_INFO_GET \ + FFA_FID(SMC_32, FFA_FNUM_NOTIFICATION_INFO_GET) +#define FFA_MEM_FRAG_RX FFA_FID(SMC_32, FFA_FNUM_MEM_FRAG_RX) +#define FFA_MEM_FRAG_TX FFA_FID(SMC_32, FFA_FNUM_MEM_FRAG_TX) +#define FFA_SPM_ID_GET FFA_FID(SMC_32, FFA_FNUM_SPM_ID_GET) +#define FFA_NORMAL_WORLD_RESUME FFA_FID(SMC_32, FFA_FNUM_NORMAL_WORLD_RESUME) +#define FFA_EL3_INTR_HANDLE FFA_FID(SMC_32, FFA_FNUM_EL3_INTR_HANDLE) +#define FFA_MEM_PERM_GET FFA_FID(SMC_32, FFA_FNUM_MEM_PERM_GET) +#define FFA_MEM_PERM_SET FFA_FID(SMC_32, FFA_FNUM_MEM_PERM_SET) +#define FFA_CONSOLE_LOG_SMC32 FFA_FID(SMC_32, FFA_FNUM_CONSOLE_LOG) /* FFA SMC64 FIDs */ #define FFA_ERROR_SMC64 FFA_FID(SMC_64, FFA_FNUM_ERROR) @@ -131,6 +192,22 @@ FFA_FID(SMC_64, FFA_FNUM_MEM_RETRIEVE_REQ) #define FFA_SECONDARY_EP_REGISTER_SMC64 \ FFA_FID(SMC_64, FFA_FNUM_SECONDARY_EP_REGISTER) +#define FFA_NOTIFICATION_INFO_GET_SMC64 \ + FFA_FID(SMC_64, FFA_FNUM_NOTIFICATION_INFO_GET) +#define FFA_PARTITION_INFO_GET_REGS_SMC64 \ + FFA_FID(SMC_64, FFA_FNUM_PARTITION_INFO_GET_REGS) +#define FFA_CONSOLE_LOG_SMC64 FFA_FID(SMC_64, FFA_FNUM_CONSOLE_LOG) +#define FFA_MSG_SEND_DIRECT_REQ2_SMC64 \ + FFA_FID(SMC_64, FFA_FNUM_MSG_SEND_DIRECT_REQ2) +#define FFA_MSG_SEND_DIRECT_RESP2_SMC64 \ + FFA_FID(SMC_64, FFA_FNUM_MSG_SEND_DIRECT_RESP2) + +/* + * FF-A partition properties values. + */ +#define FFA_PARTITION_DIRECT_REQ_RECV U(1 << 0) +#define FFA_PARTITION_DIRECT_REQ_SEND U(1 << 1) +#define FFA_PARTITION_INDIRECT_MSG U(1 << 2) /* * Reserve a special value for traffic targeted to the Hypervisor or SPM. @@ -148,6 +225,20 @@ #define FFA_ENDPOINT_ID_MAX U(1 << 16) /* + * Reserve endpoint id for the SPMD. + */ +#define SPMD_DIRECT_MSG_ENDPOINT_ID U(FFA_ENDPOINT_ID_MAX - 1) + +/* Mask and shift to check valid secure FF-A Endpoint ID. */ +#define SPMC_SECURE_ID_MASK U(1) +#define SPMC_SECURE_ID_SHIFT U(15) + +/* + * Partition Count Flag in FFA_PARTITION_INFO_GET. + */ +#define FFA_PARTITION_INFO_GET_COUNT_FLAG_MASK U(1 << 0) + +/* * Mask for source and destination endpoint id in * a direct message request/response. */ @@ -181,4 +272,115 @@ static inline uint16_t ffa_endpoint_source(unsigned int ep) FFA_DIRECT_MSG_ENDPOINT_ID_MASK; } +/****************************************************************************** + * FF-A helper functions to determine partition ID world. + *****************************************************************************/ + +/* + * Determine if provided ID is in the secure world. + */ +static inline bool ffa_is_secure_world_id(uint16_t id) +{ + return ((id >> SPMC_SECURE_ID_SHIFT) & SPMC_SECURE_ID_MASK) == 1; +} + +/* + * Determine if provided ID is in the normal world. + */ +static inline bool ffa_is_normal_world_id(uint16_t id) +{ + return !ffa_is_secure_world_id(id); +} + + +/****************************************************************************** + * Boot information protocol as per the FF-A v1.1 spec. + *****************************************************************************/ +#define FFA_INIT_DESC_SIGNATURE 0x00000FFA + +/* Boot information type. */ +#define FFA_BOOT_INFO_TYPE_STD U(0x0) +#define FFA_BOOT_INFO_TYPE_IMPL U(0x1) + +#define FFA_BOOT_INFO_TYPE_MASK U(0x1) +#define FFA_BOOT_INFO_TYPE_SHIFT U(0x7) +#define FFA_BOOT_INFO_TYPE(type) \ + (((type) & FFA_BOOT_INFO_TYPE_MASK) \ + << FFA_BOOT_INFO_TYPE_SHIFT) + +/* Boot information identifier. */ +#define FFA_BOOT_INFO_TYPE_ID_FDT U(0x0) +#define FFA_BOOT_INFO_TYPE_ID_HOB U(0x1) + +#define FFA_BOOT_INFO_TYPE_ID_MASK U(0x3F) +#define FFA_BOOT_INFO_TYPE_ID_SHIFT U(0x0) +#define FFA_BOOT_INFO_TYPE_ID(type) \ + (((type) & FFA_BOOT_INFO_TYPE_ID_MASK) \ + << FFA_BOOT_INFO_TYPE_ID_SHIFT) + +/* Format of Flags Name field. */ +#define FFA_BOOT_INFO_FLAG_NAME_STRING U(0x0) +#define FFA_BOOT_INFO_FLAG_NAME_UUID U(0x1) + +#define FFA_BOOT_INFO_FLAG_NAME_MASK U(0x3) +#define FFA_BOOT_INFO_FLAG_NAME_SHIFT U(0x0) +#define FFA_BOOT_INFO_FLAG_NAME(type) \ + (((type) & FFA_BOOT_INFO_FLAG_NAME_MASK)\ + << FFA_BOOT_INFO_FLAG_NAME_SHIFT) + +/* Format of Flags Contents field. */ +#define FFA_BOOT_INFO_FLAG_CONTENT_ADR U(0x0) +#define FFA_BOOT_INFO_FLAG_CONTENT_VAL U(0x1) + +#define FFA_BOOT_INFO_FLAG_CONTENT_MASK U(0x1) +#define FFA_BOOT_INFO_FLAG_CONTENT_SHIFT U(0x2) +#define FFA_BOOT_INFO_FLAG_CONTENT(content) \ + (((content) & FFA_BOOT_INFO_FLAG_CONTENT_MASK) \ + << FFA_BOOT_INFO_FLAG_CONTENT_SHIFT) + +/* Boot information descriptor. */ +struct ffa_boot_info_desc { + uint8_t name[16]; + uint8_t type; + uint8_t reserved; + uint16_t flags; + uint32_t size_boot_info; + uint64_t content; +}; + +/* Boot information header. */ +struct ffa_boot_info_header { + uint32_t signature; /* 0xFFA */ + uint32_t version; + uint32_t size_boot_info_blob; + uint32_t size_boot_info_desc; + uint32_t count_boot_info_desc; + uint32_t offset_boot_info_desc; + uint64_t reserved; +}; + +/* FF-A Partition Info Get related macros. */ +#define FFA_PARTITION_INFO_GET_PROPERTIES_V1_0_MASK U(0x7) +#define FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT U(8) +#define FFA_PARTITION_INFO_GET_AARCH32_STATE U(0) +#define FFA_PARTITION_INFO_GET_AARCH64_STATE U(1) + +/** + * Holds information returned for each partition by the FFA_PARTITION_INFO_GET + * interface. + */ +struct ffa_partition_info_v1_0 { + uint16_t ep_id; + uint16_t execution_ctx_count; + uint32_t properties; +}; + +/* Extended structure for FF-A v1.1. */ +struct ffa_partition_info_v1_1 { + uint16_t ep_id; + uint16_t execution_ctx_count; + uint32_t properties; + uint32_t uuid[4]; +}; + #endif /* FFA_SVC_H */ diff --git a/include/services/oem/chromeos/widevine_smc_handlers.h b/include/services/oem/chromeos/widevine_smc_handlers.h new file mode 100644 index 0000000000..a5251d76ce --- /dev/null +++ b/include/services/oem/chromeos/widevine_smc_handlers.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024, The ChromiumOS Authors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CROS_WIDEVINE_SMC_HANDLERS_H +#define CROS_WIDEVINE_SMC_HANDLERS_H + +#include <lib/smccc.h> + +/******************************************************************************* + * Defines for CrOS OEM Service queries + ******************************************************************************/ + +/* 0xC300C050 - 0xC300C05F are CrOS OEM service calls */ +#define CROS_OEM_SMC_ID 0xC050 +#define CROS_OEM_SMC_CALL_ID(func_num) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + ((SMC_64) << FUNCID_CC_SHIFT) | (OEN_OEM_START << FUNCID_OEN_SHIFT) | \ + (CROS_OEM_SMC_ID) | ((func_num) & FUNCID_NUM_MASK)) + +enum cros_drm_set { + CROS_DRM_SET_TPM_AUTH_PUB = 0U, + CROS_DRM_SET_HARDWARE_UNIQUE_KEY = 1U, + CROS_DRM_SET_ROOT_OF_TRUST = 2U, +}; + +/******************************************************************************* + * Defines for runtime services func ids + ******************************************************************************/ + +/* Sets the TPM auth public key. The maximum size is 128 bytes. + * |x1| is the length of the data, |x2| is the physical address of the data. + */ +#define CROS_OEM_SMC_DRM_SET_TPM_AUTH_PUB_FUNC_ID \ + CROS_OEM_SMC_CALL_ID(CROS_DRM_SET_TPM_AUTH_PUB) + +/* Sets the hardware unique key. The maximum size is 32 bytes. + * |x1| is the length of the data, |x2| is the physical address of the data. + */ +#define CROS_OEM_SMC_DRM_SET_HARDWARE_UNIQUE_KEY_FUNC_ID \ + CROS_OEM_SMC_CALL_ID(CROS_DRM_SET_HARDWARE_UNIQUE_KEY) + +/* Sets the widevine root of trust. The maximum size is 32 bytes. + * |x1| is the length of the data, |x2| is the physical address of the data. + */ +#define CROS_OEM_SMC_DRM_SET_ROOT_OF_TRUST_FUNC_ID \ + CROS_OEM_SMC_CALL_ID(CROS_DRM_SET_ROOT_OF_TRUST) + +#define is_cros_oem_smc(_call_id) (((_call_id) & 0xFFF0U) == CROS_OEM_SMC_ID) + +struct cros_oem_data { + uint8_t *buffer; + const uint32_t max_length; + uint32_t length; +}; + +extern struct cros_oem_data cros_oem_tpm_auth_pk; + +extern struct cros_oem_data cros_oem_huk; + +extern struct cros_oem_data cros_oem_rot; + +#endif /* CROS_WIDEVINE_SMC_HANDLERS_H */ diff --git a/include/services/rmm_core_manifest.h b/include/services/rmm_core_manifest.h new file mode 100644 index 0000000000..b89de9f287 --- /dev/null +++ b/include/services/rmm_core_manifest.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RMM_CORE_MANIFEST_H +#define RMM_CORE_MANIFEST_H + +#include <assert.h> +#include <stddef.h> +#include <stdint.h> + +#include <lib/cassert.h> + +#define RMMD_MANIFEST_VERSION_MAJOR U(0) +#define RMMD_MANIFEST_VERSION_MINOR U(2) + +/* + * Manifest version encoding: + * - Bit[31] RES0 + * - Bits [30:16] Major version + * - Bits [15:0] Minor version + */ +#define SET_RMMD_MANIFEST_VERSION(_major, _minor) \ + ((((_major) & 0x7FFF) << 16) | ((_minor) & 0xFFFF)) + +#define RMMD_MANIFEST_VERSION SET_RMMD_MANIFEST_VERSION( \ + RMMD_MANIFEST_VERSION_MAJOR, \ + RMMD_MANIFEST_VERSION_MINOR) + +#define RMMD_GET_MANIFEST_VERSION_MAJOR(_version) \ + ((_version >> 16) & 0x7FFF) + +#define RMMD_GET_MANIFEST_VERSION_MINOR(_version) \ + (_version & 0xFFFF) + +/* NS DRAM bank structure */ +struct ns_dram_bank { + uintptr_t base; /* Base address */ + uint64_t size; /* Size of bank */ +}; + +CASSERT(offsetof(struct ns_dram_bank, base) == 0UL, + rmm_manifest_base_unaligned); +CASSERT(offsetof(struct ns_dram_bank, size) == 8UL, + rmm_manifest_size_unaligned); + +/* NS DRAM layout info structure */ +struct ns_dram_info { + uint64_t num_banks; /* Number of NS DRAM banks */ + struct ns_dram_bank *banks; /* Pointer to ns_dram_bank[] */ + uint64_t checksum; /* Checksum of ns_dram_info data */ +}; + +CASSERT(offsetof(struct ns_dram_info, num_banks) == 0UL, + rmm_manifest_num_banks_unaligned); +CASSERT(offsetof(struct ns_dram_info, banks) == 8UL, + rmm_manifest_dram_data_unaligned); +CASSERT(offsetof(struct ns_dram_info, checksum) == 16UL, + rmm_manifest_checksum_unaligned); + +/* Boot manifest core structure as per v0.2 */ +struct rmm_manifest { + uint32_t version; /* Manifest version */ + uint32_t padding; /* RES0 */ + uintptr_t plat_data; /* Manifest platform data */ + struct ns_dram_info plat_dram; /* Platform NS DRAM data */ +}; + +CASSERT(offsetof(struct rmm_manifest, version) == 0UL, + rmm_manifest_version_unaligned); +CASSERT(offsetof(struct rmm_manifest, plat_data) == 8UL, + rmm_manifest_plat_data_unaligned); +CASSERT(offsetof(struct rmm_manifest, plat_dram) == 16UL, + rmm_manifest_plat_dram_unaligned); + +#endif /* RMM_CORE_MANIFEST_H */ diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h new file mode 100644 index 0000000000..a567d28557 --- /dev/null +++ b/include/services/rmmd_svc.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RMMD_SVC_H +#define RMMD_SVC_H + +#include <lib/smccc.h> +#include <lib/utils_def.h> + +/* STD calls FNUM Min/Max ranges */ +#define RMI_FNUM_MIN_VALUE U(0x150) +#define RMI_FNUM_MAX_VALUE U(0x18F) + +/* Construct RMI fastcall std FID from offset */ +#define SMC64_RMI_FID(_offset) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + (SMC_64 << FUNCID_CC_SHIFT) | \ + (OEN_STD_START << FUNCID_OEN_SHIFT) | \ + (((RMI_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \ + << FUNCID_NUM_SHIFT)) + +#define is_rmi_fid(fid) __extension__ ({ \ + __typeof__(fid) _fid = (fid); \ + ((GET_SMC_NUM(_fid) >= RMI_FNUM_MIN_VALUE) && \ + (GET_SMC_NUM(_fid) <= RMI_FNUM_MAX_VALUE) && \ + (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST) && \ + (GET_SMC_CC(_fid) == SMC_64) && \ + (GET_SMC_OEN(_fid) == OEN_STD_START) && \ + ((_fid & 0x00FE0000) == 0U)); }) + +/* + * RMI_FNUM_REQ_COMPLETE is the only function in the RMI range that originates + * from the Realm world and is handled by the RMMD. The RMI functions are + * always invoked by the Normal world, forwarded by RMMD and handled by the + * RMM. + */ + /* 0x18F */ +#define RMM_RMI_REQ_COMPLETE SMC64_RMI_FID(U(0x3F)) + +/* RMM_BOOT_COMPLETE arg0 error codes */ +#define E_RMM_BOOT_SUCCESS (0) +#define E_RMM_BOOT_UNKNOWN (-1) +#define E_RMM_BOOT_VERSION_MISMATCH (-2) +#define E_RMM_BOOT_CPUS_OUT_OF_RANGE (-3) +#define E_RMM_BOOT_CPU_ID_OUT_OF_RANGE (-4) +#define E_RMM_BOOT_INVALID_SHARED_BUFFER (-5) +#define E_RMM_BOOT_MANIFEST_VERSION_NOT_SUPPORTED (-6) +#define E_RMM_BOOT_MANIFEST_DATA_ERROR (-7) + +/* The SMC in the range 0x8400 0191 - 0x8400 01AF are reserved for RSIs.*/ + +/* + * EL3 - RMM SMCs used for requesting RMMD services. These SMCs originate in Realm + * world and return to Realm world. + * + * These are allocated from 0x8400 01B0 - 0x8400 01CF in the RMM Service range. + */ +#define RMMD_EL3_FNUM_MIN_VALUE U(0x1B0) +#define RMMD_EL3_FNUM_MAX_VALUE U(0x1CF) + +/* Construct RMM_EL3 fastcall std FID from offset */ +#define SMC64_RMMD_EL3_FID(_offset) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + (SMC_64 << FUNCID_CC_SHIFT) | \ + (OEN_STD_START << FUNCID_OEN_SHIFT) | \ + (((RMMD_EL3_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \ + << FUNCID_NUM_SHIFT)) + +/* The macros below are used to identify GTSI calls from the SMC function ID */ +#define is_rmmd_el3_fid(fid) __extension__ ({ \ + __typeof__(fid) _fid = (fid); \ + ((GET_SMC_NUM(_fid) >= RMMD_EL3_FNUM_MIN_VALUE) &&\ + (GET_SMC_NUM(_fid) <= RMMD_EL3_FNUM_MAX_VALUE) &&\ + (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST) && \ + (GET_SMC_CC(_fid) == SMC_64) && \ + (GET_SMC_OEN(_fid) == OEN_STD_START) && \ + ((_fid & 0x00FE0000) == 0U)); }) + + /* 0x1B0 - 0x1B1 */ +#define RMM_GTSI_DELEGATE SMC64_RMMD_EL3_FID(U(0)) +#define RMM_GTSI_UNDELEGATE SMC64_RMMD_EL3_FID(U(1)) + +/* Return error codes from RMM-EL3 SMCs */ +#define E_RMM_OK 0 +#define E_RMM_UNK -1 +#define E_RMM_BAD_ADDR -2 +#define E_RMM_BAD_PAS -3 +#define E_RMM_NOMEM -4 +#define E_RMM_INVAL -5 + +/* Return error codes from RMI SMCs */ +#define RMI_SUCCESS 0 +#define RMI_ERROR_INPUT 1 + +/* Acceptable SHA sizes for Challenge object */ +#define SHA256_DIGEST_SIZE 32U +#define SHA384_DIGEST_SIZE 48U +#define SHA512_DIGEST_SIZE 64U + +/* + * Retrieve Realm attestation key from EL3. Only P-384 ECC curve key is + * supported. The arguments to this SMC are : + * arg0 - Function ID. + * arg1 - Realm attestation key buffer Physical address. + * arg2 - Realm attestation key buffer size (in bytes). + * arg3 - The type of the elliptic curve to which the requested + * attestation key belongs to. The value should be one of the + * defined curve types. + * The return arguments are : + * ret0 - Status / error. + * ret1 - Size of the realm attestation key if successful. + */ + /* 0x1B2 */ +#define RMM_ATTEST_GET_REALM_KEY SMC64_RMMD_EL3_FID(U(2)) + +/* + * Retrieve Platform token from EL3. + * The arguments to this SMC are : + * arg0 - Function ID. + * arg1 - Platform attestation token buffer Physical address. (The challenge + * object is passed in this buffer.) + * arg2 - Platform attestation token buffer size (in bytes). + * arg3 - Challenge object size (in bytes). It has to be one of the defined + * SHA hash sizes. + * The return arguments are : + * ret0 - Status / error. + * ret1 - Size of the platform token if successful. + */ + /* 0x1B3 */ +#define RMM_ATTEST_GET_PLAT_TOKEN SMC64_RMMD_EL3_FID(U(3)) + +/* ECC Curve types for attest key generation */ +#define ATTEST_KEY_CURVE_ECC_SECP384R1 0 + +/* + * RMM_BOOT_COMPLETE originates on RMM when the boot finishes (either cold + * or warm boot). This is handled by the RMM-EL3 interface SMC handler. + * + * RMM_BOOT_COMPLETE FID is located at the end of the available range. + */ + /* 0x1CF */ +#define RMM_BOOT_COMPLETE SMC64_RMMD_EL3_FID(U(0x1F)) + +/* + * The major version number of the RMM Boot Interface implementation. + * Increase this whenever the semantics of the boot arguments change making it + * backwards incompatible. + */ +#define RMM_EL3_IFC_VERSION_MAJOR (U(0)) + +/* + * The minor version number of the RMM Boot Interface implementation. + * Increase this when a bug is fixed, or a feature is added without + * breaking compatibility. + */ +#define RMM_EL3_IFC_VERSION_MINOR (U(2)) + +#define RMM_EL3_INTERFACE_VERSION \ + (((RMM_EL3_IFC_VERSION_MAJOR << 16) & 0x7FFFF) | \ + RMM_EL3_IFC_VERSION_MINOR) + +#define RMM_EL3_IFC_VERSION_GET_MAJOR(_version) (((_version) >> 16) \ + & 0x7FFF) +#define RMM_EL3_IFC_VERSION_GET_MAJOR_MINOR(_version) ((_version) & 0xFFFF) + +#ifndef __ASSEMBLER__ +#include <stdint.h> + +int rmmd_setup(void); +uint64_t rmmd_rmi_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); + +uint64_t rmmd_rmm_el3_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); + +#endif /* __ASSEMBLER__ */ +#endif /* RMMD_SVC_H */ diff --git a/include/services/sdei.h b/include/services/sdei.h index 063ed6f286..c12a182f01 100644 --- a/include/services/sdei.h +++ b/include/services/sdei.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -137,4 +137,7 @@ void sdei_init(void); /* Public API to dispatch an event to Normal world */ int sdei_dispatch_event(int ev_num); +/* Public API to check how many SDEI events are registered. */ +int sdei_get_registered_event_count(void); + #endif /* SDEI_H */ diff --git a/include/services/spmc_svc.h b/include/services/spmc_svc.h new file mode 100644 index 0000000000..8ee61e90f3 --- /dev/null +++ b/include/services/spmc_svc.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPMC_SVC_H +#define SPMC_SVC_H + +#ifndef __ASSEMBLER__ +#include <stdint.h> + +#include <lib/utils_def.h> +#include <services/ffa_svc.h> +#include <services/spm_core_manifest.h> + +int spmc_setup(void); +void spmc_populate_attrs(spmc_manifest_attribute_t *spmc_attrs); +void *spmc_get_config_addr(void); + +void spmc_set_config_addr(uintptr_t soc_fw_config); + +uint64_t spmc_smc_handler(uint32_t smc_fid, + bool secure_origin, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); + +static inline bool is_spmc_at_el3(void) +{ + return SPMC_AT_EL3 == 1; +} + +#endif /* __ASSEMBLER__ */ + +#endif /* SPMC_SVC_H */ diff --git a/include/services/spmd_svc.h b/include/services/spmd_svc.h index 1e7e6aa87c..95f0707536 100644 --- a/include/services/spmd_svc.h +++ b/include/services/spmd_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,14 @@ #include <stdint.h> int spmd_setup(void); +uint64_t spmd_ffa_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); uint64_t spmd_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, @@ -20,6 +28,14 @@ uint64_t spmd_smc_handler(uint32_t smc_fid, void *cookie, void *handle, uint64_t flags); +uint64_t spmd_smc_switch_state(uint32_t smc_fid, + bool secure_origin, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *handle, + uint64_t flags); #endif /* __ASSEMBLER__ */ #endif /* SPMD_SVC_H */ diff --git a/include/services/trng_svc.h b/include/services/trng_svc.h index ed4d557ca5..92417c22dd 100644 --- a/include/services/trng_svc.h +++ b/include/services/trng_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ #define ARM_TRNG_FEATURES U(0x84000051) #define ARM_TRNG_GET_UUID U(0x84000052) #define ARM_TRNG_RND32 U(0x84000053) -#define ARM_TRNG_RND64 U(0xc4000053) +#define ARM_TRNG_RND64 U(0xC4000053) /* TRNG version numbers */ #define TRNG_VERSION_MAJOR (0x1) @@ -30,19 +30,17 @@ #define TRNG_E_NO_ENTROPY (-3) #define TRNG_E_NOT_IMPLEMENTED (-4) -#if TRNG_SUPPORT +/* TRNG Entropy Bit Numbers */ +#define TRNG_RND32_ENTROPY_MAXBITS (96U) +#define TRNG_RND64_ENTROPY_MAXBITS (192U) + +/* Public API to perform the initial TRNG entropy setup */ void trng_setup(void); + +/* Public API to verify function id is part of TRNG */ bool is_trng_fid(uint32_t smc_fid); -#else -static inline void trng_setup(void) -{ -} - -static inline bool is_trng_fid(uint32_t smc_fid) -{ - return false; -} -#endif + +/* Handler to be called to handle TRNG smc calls */ uintptr_t trng_smc_handler( uint32_t smc_fid, u_register_t x1, diff --git a/include/services/trp/platform_trp.h b/include/services/trp/platform_trp.h new file mode 100644 index 0000000000..756e9db6c5 --- /dev/null +++ b/include/services/trp/platform_trp.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_TRP_H +#define PLATFORM_TRP_H + +#include <services/rmm_core_manifest.h> + +struct rmm_manifest; + +/******************************************************************************* + * Mandatory TRP functions (only if platform contains a TRP) + ******************************************************************************/ +void trp_early_platform_setup(struct rmm_manifest *manifest); + +#endif /* PLATFORM_TRP_H */ diff --git a/include/services/trp/trp_helpers.h b/include/services/trp/trp_helpers.h new file mode 100644 index 0000000000..83ec74040f --- /dev/null +++ b/include/services/trp/trp_helpers.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRP_HELPERS_H +#define TRP_HELPERS_H + +/* Definitions to help the assembler access the SMC/ERET args structure */ +#define TRP_ARGS_SIZE TRP_ARGS_END +#define TRP_ARG0 0x0 +#define TRP_ARG1 0x8 +#define TRP_ARG2 0x10 +#define TRP_ARG3 0x18 +#define TRP_ARG4 0x20 +#define TRP_ARG5 0x28 +#define TRP_ARG6 0x30 +#define TRP_ARG7 0x38 +#define TRP_ARGS_END 0x40 + +#ifndef __ASSEMBLER__ + +#include <platform_def.h> + +/* Data structure to hold SMC arguments */ +typedef struct trp_args { + uint64_t regs[TRP_ARGS_END >> 3]; +} __aligned(CACHE_WRITEBACK_GRANULE) trp_args_t; + +trp_args_t *set_smc_args(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); + +__dead2 void trp_boot_abort(uint64_t err); + +/* TRP SMC result registers X0-X4 */ +#define TRP_SMC_RESULT_REGS 5 + +struct trp_smc_result { + unsigned long long x[TRP_SMC_RESULT_REGS]; +}; + +#endif /* __ASSEMBLER __ */ +#endif /* TRP_HELPERS_H */ diff --git a/include/tools_share/cca_oid.h b/include/tools_share/cca_oid.h new file mode 100644 index 0000000000..8c53ef9552 --- /dev/null +++ b/include/tools_share/cca_oid.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CCA_OID_H +#define CCA_OID_H + +/* Reuse the Object IDs defined by TBBR for certificate extensions. */ +#include "tbbr_oid.h" + +/* + * Assign arbitrary Object ID values that do not conflict with any of the + * TBBR reserved OIDs. + */ +/* Platform root-of-trust public key */ +#define PROT_PK_OID "1.3.6.1.4.1.4128.2100.1102" +/* Secure World root-of-trust public key */ +#define SWD_ROT_PK_OID "1.3.6.1.4.1.4128.2100.1103" +/* Core Secure World public key */ +#define CORE_SWD_PK_OID "1.3.6.1.4.1.4128.2100.1104" +/* Platform public key */ +#define PLAT_PK_OID "1.3.6.1.4.1.4128.2100.1105" +/* Realm Monitor Manager (RMM) Hash */ +#define RMM_HASH_OID "1.3.6.1.4.1.4128.2100.1106" + +/* CCAFirmwareNVCounter - Non-volatile counter extension */ +#define CCA_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.3" + +/* + * First undef previous definitions from tbbr_oid.h. + * CCA ROTPK authenticates BL31 and its configuration image in + * CCA CoT. + **/ +#undef BL31_IMAGE_KEY_OID +#undef SOC_FW_CONFIG_KEY_OID +#undef HW_CONFIG_KEY_OID +#define BL31_IMAGE_KEY_OID ZERO_OID +#define SOC_FW_CONFIG_KEY_OID ZERO_OID +#define HW_CONFIG_KEY_OID ZERO_OID +#define RMM_IMAGE_KEY_OID ZERO_OID + +#endif /* CCA_OID_H */ diff --git a/include/tools_share/dualroot_oid.h b/include/tools_share/dualroot_oid.h index 3e88a6d229..3762c7937b 100644 --- a/include/tools_share/dualroot_oid.h +++ b/include/tools_share/dualroot_oid.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/tools_share/firmware_image_package.h b/include/tools_share/firmware_image_package.h index dc65cc6263..b73eec79c7 100644 --- a/include/tools_share/firmware_image_package.h +++ b/include/tools_share/firmware_image_package.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,12 @@ {{0x4f, 0x51, 0x1d, 0x11}, {0x2b, 0xe5}, {0x4e, 0x49}, 0xb4, 0xc5, {0x83, 0xc2, 0xf7, 0x15, 0x84, 0x0a} } #define UUID_TRUSTED_FWU_CERT \ {{0x71, 0x40, 0x8a, 0xb2}, {0x18, 0xd6}, {0x87, 0x4c}, 0x8b, 0x2e, {0xc6, 0xdc, 0xcd, 0x50, 0xf0, 0x96} } +#define UUID_CCA_CONTENT_CERT \ + {{0x36, 0xd8, 0x3d, 0x85}, {0x76, 0x1d}, {0x4d, 0xaf}, 0x96, 0xf1, {0xcd, 0x99, 0xd6, 0x56, 0x9b, 0x00} } +#define UUID_CORE_SWD_KEY_CERT \ + {{0x52, 0x22, 0x2d, 0x31}, {0x82, 0x0f}, {0x49, 0x4d}, 0x8b, 0xbc, {0xea, 0x68, 0x25, 0xd3, 0xc3, 0x5a} } +#define UUID_PLAT_KEY_CERT \ + {{0xd4, 0x3c, 0xd9, 0x02}, {0x5b, 0x9f}, {0x41, 0x2e}, 0x8a, 0xc6, {0x92, 0xb6, 0xd1, 0x8b, 0xe6, 0x0d} } #define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \ {{0x5f, 0xf9, 0xec, 0x0b}, {0x4d, 0x22}, {0x3e, 0x4d}, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } #define UUID_SCP_FIRMWARE_SCP_BL2 \ @@ -38,6 +44,8 @@ {{0x8e, 0xa8, 0x7b, 0xb1}, {0xcf, 0xa2}, {0x3f, 0x4d}, 0x85, 0xfd, {0xe7, 0xbb, 0xa5, 0x02, 0x20, 0xd9} } #define UUID_NON_TRUSTED_FIRMWARE_BL33 \ {{0xd6, 0xd0, 0xee, 0xa7}, {0xfc, 0xea}, {0xd5, 0x4b}, 0x97, 0x82, {0x99, 0x34, 0xf2, 0x34, 0xb6, 0xe4} } +#define UUID_REALM_MONITOR_MGMT_FIRMWARE \ + {{0x6c, 0x07, 0x62, 0xa6}, {0x12, 0xf2}, {0x4b, 0x56}, 0x92, 0xcb, {0xba, 0x8f, 0x63, 0x36, 0x06, 0xd9} } /* Key certificates */ #define UUID_ROT_KEY_CERT \ {{0x86, 0x2d, 0x1d, 0x72}, {0xf8, 0x60}, {0xe4, 0x11}, 0x92, 0x0b, {0x8b, 0xe7, 0x62, 0x16, 0x0f, 0x24} } diff --git a/include/tools_share/sptool.h b/include/tools_share/sptool.h deleted file mode 100644 index 53668e09c7..0000000000 --- a/include/tools_share/sptool.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018-2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef SPTOOL_H -#define SPTOOL_H - -#include <stdint.h> - -/* 4 Byte magic name "SPKG" */ -#define SECURE_PARTITION_MAGIC 0x474B5053 - -/* Header for a secure partition package. */ -struct sp_pkg_header { - uint32_t magic; - uint32_t version; - uint32_t pm_offset; - uint32_t pm_size; - uint32_t img_offset; - uint32_t img_size; -}; - -#endif /* SPTOOL_H */ diff --git a/include/tools_share/tbbr_oid.h b/include/tools_share/tbbr_oid.h index 52b43ab3e3..1a2e35536c 100644 --- a/include/tools_share/tbbr_oid.h +++ b/include/tools_share/tbbr_oid.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef TBBR_OID_H #define TBBR_OID_H +#include "zero_oid.h" + #define MAX_OID_NAME_LEN 30 /* @@ -160,6 +162,20 @@ #define SP_PKG7_HASH_OID "1.3.6.1.4.1.4128.2100.1307" #define SP_PKG8_HASH_OID "1.3.6.1.4.1.4128.2100.1308" +/* + * Public Keys present in SOC FW content certificates authenticate BL31 and + * its configuration. + */ +#define BL31_IMAGE_KEY_OID SOC_FW_CONTENT_CERT_PK_OID +#define SOC_FW_CONFIG_KEY_OID SOC_FW_CONTENT_CERT_PK_OID +#define HW_CONFIG_KEY_OID ZERO_OID + +#define SCP_BL2_IMAGE_KEY_OID SCP_FW_CONTENT_CERT_PK_OID +#define BL32_IMAGE_KEY_OID TRUSTED_OS_FW_CONTENT_CERT_PK_OID +#define TOS_FW_CONFIG_KEY_OID TRUSTED_OS_FW_CONTENT_CERT_PK_OID +#define BL33_IMAGE_KEY_OID NON_TRUSTED_FW_CONTENT_CERT_PK_OID +#define NT_FW_CONFIG_KEY_OID NON_TRUSTED_FW_CONTENT_CERT_PK_OID + #ifdef PLAT_DEF_OID #include <platform_oid.h> #endif diff --git a/include/tools_share/uuid.h b/include/tools_share/uuid.h index 2ced3a3fab..3445f20265 100644 --- a/include/tools_share/uuid.h +++ b/include/tools_share/uuid.h @@ -27,13 +27,15 @@ */ /* - * Portions copyright (c) 2014-2020, ARM Limited and Contributors. + * Portions copyright (c) 2014-2023, Arm Limited and Contributors. * All rights reserved. */ #ifndef UUID_H #define UUID_H +#include <stdint.h> + /* Length of a node address (an IEEE 802 address). */ #define _UUID_NODE_LEN 6 diff --git a/include/tools_share/zero_oid.h b/include/tools_share/zero_oid.h new file mode 100644 index 0000000000..9b83094286 --- /dev/null +++ b/include/tools_share/zero_oid.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ZERO_OID_H +#define ZERO_OID_H + +#define ZERO_OID "0.0.0.0.0.0.0.0.0" + +#endif /* ZERO_OID_H */ |