diff options
Diffstat (limited to 'include/drivers')
-rw-r--r-- | include/drivers/arm/tzc400.h | 16 | ||||
-rw-r--r-- | include/drivers/brcm/i2c/i2c.h | 161 | ||||
-rw-r--r-- | include/drivers/brcm/i2c/i2c_regs.h | 271 | ||||
-rw-r--r-- | include/drivers/marvell/mochi/cp110_setup.h | 9 | ||||
-rw-r--r-- | include/drivers/nxp/flexspi/flash_info.h | 61 | ||||
-rw-r--r-- | include/drivers/nxp/flexspi/fspi_api.h | 122 | ||||
-rw-r--r-- | include/drivers/nxp/flexspi/xspi_error_codes.h | 28 | ||||
-rw-r--r-- | include/drivers/nxp/smmu/nxp_smmu.h | 30 | ||||
-rw-r--r-- | include/drivers/rambus/trng_ip_76.h | 18 |
9 files changed, 708 insertions, 8 deletions
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h index 32aeb03502..5f8a48f570 100644 --- a/include/drivers/arm/tzc400.h +++ b/include/drivers/arm/tzc400.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -65,8 +65,8 @@ #define FAIL_CONTROL_NS_SECURE U(0) #define FAIL_CONTROL_NS_NONSECURE U(1) #define FAIL_CONTROL_PRIV_SHIFT 20 -#define FAIL_CONTROL_PRIV_PRIV U(0) -#define FAIL_CONTROL_PRIV_UNPRIV U(1) +#define FAIL_CONTROL_PRIV_UNPRIV U(0) +#define FAIL_CONTROL_PRIV_PRIV U(1) /* * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. @@ -80,11 +80,8 @@ /* Filter enable bits in a TZC */ #define TZC_400_REGION_ATTR_F_EN_MASK U(0xf) -#define TZC_400_REGION_ATTR_FILTER_BIT(x) \ - ((U(1) << (x)) << TZC_REGION_ATTR_F_EN_SHIFT) -#define TZC_400_REGION_ATTR_FILTER_BIT_ALL \ - (TZC_400_REGION_ATTR_F_EN_MASK << \ - TZC_REGION_ATTR_F_EN_SHIFT) +#define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x)) +#define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK /* * All TZC region configuration registers are placed one after another. It @@ -93,6 +90,8 @@ #define TZC_400_REGION_SIZE U(0x20) #define TZC_400_ACTION_OFF U(0x4) +#define FILTER_OFFSET U(0x10) + #ifndef __ASSEMBLER__ #include <cdefs.h> @@ -113,6 +112,7 @@ void tzc400_configure_region(unsigned int filters, void tzc400_set_action(unsigned int action); void tzc400_enable_filters(void); void tzc400_disable_filters(void); +int tzc400_it_handler(void); static inline void tzc_init(uintptr_t base) { diff --git a/include/drivers/brcm/i2c/i2c.h b/include/drivers/brcm/i2c/i2c.h new file mode 100644 index 0000000000..24d42e208a --- /dev/null +++ b/include/drivers/brcm/i2c/i2c.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2016 - 2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef I2C_H +#define I2C_H + +#include <stdint.h> + +#define I2C_SPEED_100KHz 100000 +#define I2C_SPEED_400KHz 400000 +#define I2C_SPEED_DEFAULT I2C_SPEED_100KHz + +/* + * Function Name: i2c_probe + * + * Description: + * This function probes the I2C bus for the existence of the specified + * device. + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_probe(uint32_t bus_id, uint8_t devaddr); + +/* + * Function Name: i2c_init + * + * Description: + * This function initializes the SMBUS. + * + * Parameters: + * bus_id - I2C bus ID + * speed - I2C bus speed in Hz + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_init(uint32_t bus_id, int speed); + +/* + * Function Name: i2c_set_bus_speed + * + * Description: + * This function configures the SMBUS speed + * + * Parameters: + * bus_id - I2C bus ID + * speed - I2C bus speed in Hz + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_set_bus_speed(uint32_t bus_id, uint32_t speed); + +/* + * Function Name: i2c_get_bus_speed + * + * Description: + * This function returns the SMBUS speed. + * + * Parameters: + * bus_id - I2C bus ID + * + * Return: + * Bus speed in Hz, 0 on failure + */ +uint32_t i2c_get_bus_speed(uint32_t bus_id); + +/* + * Function Name: i2c_recv_byte + * + * Description: + * This function reads I2C data from a device without specifying + * a command regsiter. + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * value - Data Read + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value); + +/* + * Function Name: i2c_send_byte + * + * Description: + * This function send I2C data to a device without specifying + * a command regsiter. + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * value - Data Send + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_send_byte(uint32_t bus_id, uint8_t devaddr, uint8_t value); + +/* + * Function Name: i2c_read + * + * Description: + * This function reads I2C data from a device with a designated + * command register + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * addr - Register Offset + * alen - Address Length, 1 for byte, 2 for word (not supported) + * buffer - Data Buffer + * len - Data Length in bytes + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_read(uint32_t bus_id, + uint8_t devaddr, + uint32_t addr, + int alen, + uint8_t *buffer, + int len); + +/* + * Function Name: i2c_write + * + * Description: + * This function write I2C data to a device with a designated + * command register + * + * Parameters: + * bus_id - I2C bus ID + * devaddr - Device Address + * addr - Register Offset + * alen - Address Length, 1 for byte, 2 for word (not supported) + * buffer - Data Buffer + * len - Data Length in bytes + * + * Return: + * 0 on success, or -1 on failure. + */ +int i2c_write(uint32_t bus_id, + uint8_t devaddr, + uint32_t addr, + int alen, + uint8_t *buffer, + int len); + + +#endif /* I2C_H */ diff --git a/include/drivers/brcm/i2c/i2c_regs.h b/include/drivers/brcm/i2c/i2c_regs.h new file mode 100644 index 0000000000..74ea82411d --- /dev/null +++ b/include/drivers/brcm/i2c/i2c_regs.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2016 - 2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef I2C_REGS +#define I2C_REGS + +/* SMBUS Config register */ +#define SMB_CFG_REG 0x0U + +#define SMB_CFG_RST_MASK 0x80000000U +#define SMB_CFG_RST_SHIFT 31U + +#define SMB_CFG_SMBEN_MASK 0x40000000U +#define SMB_CFG_SMBEN_SHIFT 30U + +#define SMB_CFG_BITBANGEN_MASK 0x20000000U +#define SMB_CFG_BITBANGEN_SHIFT 29U + +#define SMB_CFG_EN_NIC_SMBADDR0_MASK 0x10000000U +#define SMB_CFG_EN_NIC_SMBADDR0_SHIFT 28U + +#define SMB_CFG_PROMISCMODE_MASK 0x08000000U +#define SMB_CFG_PROMISCMODE_SHIFT 27U + +#define SMB_CFG_TSTMPCNTEN_MASK 0x04000000U +#define SMB_CFG_TSTMPCNTEN_SHIFT 26U + +#define SMB_CFG_MSTRRTRYCNT_MASK 0x000F0000U +#define SMB_CFG_MSTRRTRYCNT_SHIFT 16U + +/* SMBUS Timing config register */ +#define SMB_TIMGCFG_REG 0x4U + +#define SMB_TIMGCFG_MODE400_MASK 0x80000000U +#define SMB_TIMGCFG_MODE400_SHIFT 31U + +#define SMB_TIMGCFG_RNDSLVSTR_MASK 0x7F000000U +#define SMB_TIMGCFG_RNDSLVSTR_SHIFT 24U + +#define SMB_TIMGCFG_PERSLVSTR_MASK 0x00FF0000U +#define SMB_TIMGCFG_PERSLVSTR_SHIFT 16U + +#define SMB_TIMGCFG_IDLTIME_MASK 0x0000FF00U +#define SMB_TIMGCFG_IDLTIME_SHIFT 8U + +/* SMBUS Slave address register */ +#define SMB_ADDR_REG 0x8U + +#define SMB_EN_NIC_SMBADDR3_MASK 0x80000000U +#define SMB_EN_NIC_SMBADDR3_SHIFT 31U + +#define SMB_NIC_SMBADDR3_MASK 0x7F000000U +#define SMB_NIC_SMBADDR3_SHIFT 24U + +#define SMB_EN_NIC_SMBADDR2_MASK 0x00800000U +#define SMB_EN_NIC_SMBADDR2_SHIFT 23U + +#define SMB_NIC_SMBADDR2_MASK 0x007F0000U +#define SMB_NIC_SMBADDR2_SHIFT 16U + +#define SMB_EN_NIC_SMBADDR1_MASK 0x00008000U +#define SMB_EN_NIC_SMBADDR1_SHIFT 15U + +#define SMB_NIC_SMBADDR1_MASK 0x00007F00U +#define SMB_NIC_SMBADDR1_SHIFT 8U + +#define SMB_EN_NIC_SMBADDR0_MASK 0x00000080U +#define SMB_EN_NIC_SMBADDR0_SHIFT 7U + +#define SMB_NIC_SMBADDR0_MASK 0x0000007FU +#define SMB_NIC_SMBADDR0_SHIFT 0U + +/* SMBUS Master FIFO control register */ +#define SMB_MSTRFIFOCTL_REG 0xCU + +#define SMB_MSTRRXFIFOFLSH_MASK 0x80000000U +#define SMB_MSTRRXFIFOFLSH_SHIFT 31U + +#define SMB_MSTRTXFIFOFLSH_MASK 0x40000000U +#define SMB_MSTRTXFIFOFLSH_SHIFT 30U + +#define SMB_MSTRRXPKTCNT_MASK 0x007F0000U +#define SMB_MSTRRXPKTCNT_SHIFT 16U + +#define SMB_MSTRRXFIFOTHR_MASK 0x00003F00U +#define SMB_MSTRRXFIFOTHR_SHIFT 8U + +/* SMBUS Slave FIFO control register */ +#define SMB_SLVFIFOCTL_REG 0x10U + +#define SMB_SLVRXFIFOFLSH_MASK 0x80000000U +#define SMB_SLVRXFIFOFLSH_SHIFT 31U + +#define SMB_SLVTXFIFOFLSH_MASK 0x40000000U +#define SMB_SLVTXFIFOFLSH_SHIFT 30U + +#define SMB_SLVRXPKTCNT_MASK 0x007F0000U +#define SMB_SLVRXPKTCNT_SHIFT 16U + +#define SMB_SLVRXFIFOTHR_MASK 0x00003F00U +#define SMB_SLVRXFIFOTHR_SHIFT 8U + +/* SMBUS Bit-bang mode control register */ +#define SMB_BITBANGCTL_REG 0x14U + +#define SMB_SMBCLKIN_MASK 0x80000000U +#define SMB_SMBCLKIN_SHIFT 31U + +#define SMB_SMBCLKOUTEN_MASK 0x40000000U +#define SMB_SMBCLKOUTEN_SHIFT 30U + +#define SMB_SMBDATAIN_MASK 0x20000000U +#define SMB_SMBDATAIN_SHIFT 29U + +#define SMB_SMBDATAOUTEN_MASK 0x10000000U +#define SMB_SMBDATAOUTEN_SHIFT 28U + +/* SMBUS Master command register */ +#define SMB_MSTRCMD_REG 0x30U + +#define SMB_MSTRSTARTBUSYCMD_MASK 0x80000000U +#define SMB_MSTRSTARTBUSYCMD_SHIFT 31U + +#define SMB_MSTRABORT_MASK 0x40000000U +#define SMB_MSTRABORT_SHIFT 30U + +#define SMB_MSTRSTS_MASK 0x0E000000U +#define SMB_MSTRSTS_SHIFT 25U + +#define SMB_MSTRSMBUSPROTO_MASK 0x00001E00U +#define SMB_MSTRSMBUSPROTO_SHIFT 9U + +#define SMB_MSTRPEC_MASK 0x00000100U +#define SMB_MSTRPEC_SHIFT 8U + +#define SMB_MSTRRDBYTECNT_MASK 0x000000FFU +#define SMB_MSTRRDBYTECNT_SHIFT 0U + +/* SMBUS Slave command register */ +#define SMB_SLVCMD_REG 0x34U + +#define SMB_SLVSTARTBUSYCMD_MASK 0x80000000U +#define SMB_SLVSTARTBUSYCMD_SHIFT 31U + +#define SMB_SLVABORT_MASK 0x40000000U +#define SMB_SLVABORT_SHIFT 30U + +#define SMB_SLVSTS_MASK 0x03800000U +#define SMB_SLVSTS_SHIFT 23U + +#define SMB_SLVPEC_MASK 0x00000100U +#define SMB_SLVPEC_SHIFT 8U + +/* SMBUS Event enable register */ +#define SMB_EVTEN_REG 0x38U + +#define SMB_MSTRRXFIFOFULLEN_MASK 0x80000000U +#define SMB_MSTRRXFIFOFULLEN_SHIFT 31U + +#define SMB_MSTRRXFIFOTHRHITEN_MASK 0x40000000U +#define SMB_MSTRRXFIFOTHRHITEN_SHIFT 30U + +#define SMB_MSTRRXEVTEN_MASK 0x20000000U +#define SMB_MSTRRXEVTEN_SHIFT 29U + +#define SMB_MSTRSTARTBUSYEN_MASK 0x10000000U +#define SMB_MSTRSTARTBUSYEN_SHIFT 28U + +#define SMB_MSTRTXUNDEN_MASK 0x08000000U +#define SMB_MSTRTXUNDEN_SHIFT 27U + +#define SMB_SLVRXFIFOFULLEN_MASK 0x04000000U +#define SMB_SLVRXFIFOFULLEN_SHIFT 26U + +#define SMB_SLVRXFIFOTHRHITEN_MASK 0x02000000U +#define SMB_SLVRXFIFOTHRHITEN_SHIFT 25U + +#define SMB_SLVRXEVTEN_MASK 0x01000000U +#define SMB_SLVRXEVTEN_SHIFT 24U + +#define SMB_SLVSTARTBUSYEN_MASK 0x00800000U +#define SMB_SLVSTARTBUSYEN_SHIFT 23U + +#define SMB_SLVTXUNDEN_MASK 0x00400000U +#define SMB_SLVTXUNDEN_SHIFT 22U + +#define SMB_SLVRDEVTEN_MASK 0x00200000U +#define SMB_SLVRDEVTEN_SHIFT 21U + +/* SMBUS Event status register */ +#define SMB_EVTSTS_REG 0x3CU + +#define SMB_MSTRRXFIFOFULLSTS_MASK 0x80000000U +#define SMB_MSTRRXFIFOFULLSTS_SHIFT 31U + +#define SMB_MSTRRXFIFOTHRHITSTS_MASK 0x40000000U +#define SMB_MSTRRXFIFOTHRHITSTS_SHIFT 30U + +#define SMB_MSTRRXEVTSTS_MASK 0x20000000U +#define SMB_MSTRRXEVTSTS_SHIFT 29U + +#define SMB_MSTRSTARTBUSYSTS_MASK 0x10000000U +#define SMB_MSTRSTARTBUSYSTS_SHIFT 28U + +#define SMB_MSTRTXUNDSTS_MASK 0x08000000U +#define SMB_MSTRTXUNDSTS_SHIFT 27U + +#define SMB_SLVRXFIFOFULLSTS_MASK 0x04000000U +#define SMB_SLVRXFIFOFULLSTS_SHIFT 26U + +#define SMB_SLVRXFIFOTHRHITSTS_MASK 0x02000000U +#define SMB_SLVRXFIFOTHRHITSTS_SHIFT 25U + +#define SMB_SLVRXEVTSTS_MASK 0x01000000U +#define SMB_SLVRXEVTSTS_SHIFT 24U + +#define SMB_SLVSTARTBUSYSTS_MASK 0x00800000U +#define SMB_SLVSTARTBUSYSTS_SHIFT 23U + +#define SMB_SLVTXUNDSTS_MASK 0x00400000U +#define SMB_SLVTXUNDSTS_SHIFT 22U + +#define SMB_SLVRDEVTSTS_MASK 0x00200000U +#define SMB_SLVRDEVTSTS_SHIFT 21U + +/* SMBUS Master data write register */ +#define SMB_MSTRDATAWR_REG 0x40U + +#define SMB_MSTRWRSTS_MASK 0x80000000U +#define SMB_MSTRWRSTS_SHIFT 31U + +#define SMB_MSTRWRDATA_MASK 0x000000FFU +#define SMB_MSTRWRDATA_SHIFT 0U + +/* SMBUS Master data read register */ +#define SMB_MSTRDATARD_REG 0x44U + +#define SMB_MSTRRDSTS_MASK 0xC0000000U +#define SMB_MSTRRDSTS_SHIFT 30U + +#define SMB_MSTRRDPECERR_MASK 0x20000000U +#define SMB_MSTRRDPECERR_SHIFT 29U + +#define SMB_MSTRRDDATA_MASK 0x000000FFU +#define SMB_MSTRRDDATA_SHIFT 0U + +/* SMBUS Slave data write register */ +#define SMB_SLVDATAWR_REG 0x48U + +#define SMB_SLVWRSTS_MASK 0x80000000U +#define SMB_SLVWRSTS_SHIFT 31U + +#define SMB_SLVWRDATA_MASK 0x000000FFU +#define SMB_SLVWRDATA_SHIFT 0U + +/* SMBUS Slave data read register */ +#define SMB_SLVDATARD_REG 0x4CU + +#define SMB_SLVRDSTS_MASK 0xC0000000U +#define SMB_SLVRDSTS_SHIFT 30U + +#define SMB_SLVRDERRSTS_MASK 0x30000000U +#define SMB_SLVRDERRSTS_SHIFT 28U + +#define SMB_SLVRDDATA_MASK 0x000000FFU +#define SMB_SLVRDDATA_SHIFT 0U + +#endif /* I2C_REGS */ diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h index 11dc4e0201..4a69257264 100644 --- a/include/drivers/marvell/mochi/cp110_setup.h +++ b/include/drivers/marvell/mochi/cp110_setup.h @@ -31,6 +31,9 @@ #define MAX_STREAM_ID_PER_CP (0x10) #define STREAM_ID_BASE (0x40) +#define MVEBU_SECUREBOOT_CTRL_REG (MVEBU_RFU_BASE + 0x4730) +#define MVEBU_SECUREBOOT_EN_MASK BIT(0) + static inline uint32_t cp110_device_id_get(uintptr_t base) { /* Returns: @@ -50,6 +53,12 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base) MVEBU_DEVICE_REV_OFFSET; } +static inline uint32_t is_secure(void) +{ + return !!(mmio_read_32(MVEBU_SECUREBOOT_CTRL_REG) & + MVEBU_SECUREBOOT_EN_MASK); +} + void cp110_init(uintptr_t cp110_base, uint32_t stream_id); void cp110_ble_init(uintptr_t cp110_base); void cp110_amb_init(uintptr_t base); diff --git a/include/drivers/nxp/flexspi/flash_info.h b/include/drivers/nxp/flexspi/flash_info.h new file mode 100644 index 0000000000..6df79c9613 --- /dev/null +++ b/include/drivers/nxp/flexspi/flash_info.h @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2020 NXP + */ + +/** + * @Flash info + * + */ +#ifndef FLASH_INFO_H +#define FLASH_INFO_H + +#define SZ_16M_BYTES 0x1000000U + +#if defined(CONFIG_MT25QU512A) +#define F_SECTOR_64K 0x10000U +#define F_PAGE_256 0x100U +#define F_SECTOR_4K 0x1000U +#define F_FLASH_SIZE_BYTES 0x4000000U +#define F_SECTOR_ERASE_SZ F_SECTOR_64K +#ifdef CONFIG_FSPI_4K_ERASE +#define F_SECTOR_ERASE_SZ F_SECTOR_4K +#endif + +#elif defined(CONFIG_MX25U25645G) +#define F_SECTOR_64K 0x10000U +#define F_PAGE_256 0x100U +#define F_SECTOR_4K 0x1000U +#define F_FLASH_SIZE_BYTES 0x2000000U +#define F_SECTOR_ERASE_SZ F_SECTOR_64K +#ifdef CONFIG_FSPI_4K_ERASE +#define F_SECTOR_ERASE_SZ F_SECTOR_4K +#endif + +#elif defined(CONFIG_MX25U51245G) +#define F_SECTOR_64K 0x10000U +#define F_PAGE_256 0x100U +#define F_SECTOR_4K 0x1000U +#define F_FLASH_SIZE_BYTES 0x4000000U +#define F_SECTOR_ERASE_SZ F_SECTOR_64K +#ifdef CONFIG_FSPI_4K_ERASE +#define F_SECTOR_ERASE_SZ F_SECTOR_4K +#endif + +#elif defined(CONFIG_MT35XU512A) +#define F_SECTOR_128K 0x20000U +#define F_SECTOR_32K 0x8000U +#define F_PAGE_256 0x100U +#define F_SECTOR_4K 0x1000U +#define F_FLASH_SIZE_BYTES 0x4000000U +#define F_SECTOR_ERASE_SZ F_SECTOR_128K +#ifdef CONFIG_FSPI_4K_ERASE +#define F_SECTOR_ERASE_SZ F_SECTOR_4K +#endif + +#ifdef NXP_WARM_BOOT +#define FLASH_WR_COMP_WAIT_BY_NOP_COUNT 0x20000 +#endif + +#endif +#endif /* FLASH_INFO_H */ diff --git a/include/drivers/nxp/flexspi/fspi_api.h b/include/drivers/nxp/flexspi/fspi_api.h new file mode 100644 index 0000000000..d0de5432f1 --- /dev/null +++ b/include/drivers/nxp/flexspi/fspi_api.h @@ -0,0 +1,122 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +/*! + * @file fspi_api.h + * @brief This file contains the FlexSPI/FSPI API to communicate + * to attached Slave device. + * @addtogroup FSPI_API + * @{ + */ + +#ifndef FSPI_API_H +#define FSPI_API_H + +#if DEBUG_FLEXSPI +#define SZ_57M 0x3900000u +#endif + +/*! + * Basic set of APIs. + */ + +/*! + * @details AHB read/IP Read, decision to be internal to API + * Minimum Read size = 1Byte + * @param[in] src_off source offset from where data to read from flash + * @param[out] des Destination location where data needs to be copied + * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits + * + * @return XSPI_SUCCESS or error code + */ +int xspi_read(uint32_t src_off, uint32_t *des, uint32_t len); +/*! + * @details Sector erase, Minimum size + * 256KB(0x40000)/128KB(0x20000)/64K(0x10000)/4K(0x1000) + * depending upon flash, Calls xspi_wren() internally + * @param[out] erase_offset Destination erase location on flash which + * has to be erased, needs to be multiple of 0x40000/0x20000/0x10000 + * @param[in] erase_len length in bytes in Hex like 0x100000 for 1MB, minimum + * erase size is 1 sector(0x40000/0x20000/0x10000) + * + * @return XSPI_SUCCESS or error code + */ +int xspi_sector_erase(uint32_t erase_offset, uint32_t erase_len); +/*! + * @details IP write, For writing data to flash, calls xspi_wren() internally. + * Single/multiple page write can start @any offset, but performance will be low + * due to ERRATA + * @param[out] dst_off Destination location on flash where data needs to + * be written + * @param[in] src source offset from where data to be read + * @param[in] len length in bytes,where 1-word=4-bytes/32-bits + * + * @return XSPI_SUCCESS or error code + */ +int xspi_write(uint32_t dst_off, void *src, uint32_t len); +/*! + * @details fspi_init, Init function. + * @param[in] uint32_t base_reg_addr + * @param[in] uint32_t flash_start_addr + * + * @return XSPI_SUCCESS or error code + */ +int fspi_init(uint32_t base_reg_addr, uint32_t flash_start_addr); +/*! + * @details is_flash_busy, Check if any erase or write or lock is + * pending on flash/slave + * @param[in] void + * + * @return TRUE/FLASE + */ +bool is_flash_busy(void); + +/*! + * Advanced set of APIs. + */ + +/*! + * @details Write enable, to be used by advance users only. + * Step 1 for sending write commands to flash. + * @param[in] dst_off destination offset where data will be written + * + * @return XSPI_SUCCESS or error code + */ +int xspi_wren(uint32_t dst_off); +/*! + * @details AHB read, meaning direct memory mapped access to flash, + * Minimum Read size = 1Byte + * @param[in] src_off source offset from where data to read from flash, + * needs to be word aligned + * @param[out] des Destination location where data needs to be copied + * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits + * + * @return XSPI_SUCCESS or error code + */ +int xspi_ahb_read(uint32_t src_off, uint32_t *des, uint32_t len); +/*! + * @details IP read, READ via RX buffer from flash, minimum READ size = 1Byte + * @param[in] src_off source offset from where data to be read from flash + * @param[out] des Destination location where data needs to be copied + * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits + * + * @return XSPI_SUCCESS or error code + */ +int xspi_ip_read(uint32_t src_off, uint32_t *des, uint32_t len); +/*! + * @details CHIP erase, Erase complete chip in one go + * + * @return XSPI_SUCCESS or error code + */ +int xspi_bulk_erase(void); + +/*! + * Add test cases to confirm flash read/erase/write functionality. + */ +void fspi_test(uint32_t fspi_test_addr, uint32_t size, int extra); +#endif /* FSPI_API_H */ diff --git a/include/drivers/nxp/flexspi/xspi_error_codes.h b/include/drivers/nxp/flexspi/xspi_error_codes.h new file mode 100644 index 0000000000..18b31eb8a6 --- /dev/null +++ b/include/drivers/nxp/flexspi/xspi_error_codes.h @@ -0,0 +1,28 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* error codes */ +#ifndef XSPI_ERROR_CODES_H +#define XSPI_ERROR_CODES_H + +#include <errno.h> + +typedef enum { + XSPI_SUCCESS = 0, + XSPI_READ_FAIL = ELAST + 1, + XSPI_ERASE_FAIL, + XSPI_IP_READ_FAIL, + XSPI_AHB_READ_FAIL, + XSPI_IP_WRITE_FAIL, + XSPI_AHB_WRITE_FAIL, + XSPI_BLOCK_TIMEOUT, + XSPI_UNALIGN_ADDR, + XSPI_UNALIGN_SIZE, +} XSPI_STATUS_CODES; +#undef ELAST +#define ELAST XSPI_STATUS_CODES.XSPI_UNALIGN_SIZE +#endif diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h new file mode 100644 index 0000000000..d64c33b206 --- /dev/null +++ b/include/drivers/nxp/smmu/nxp_smmu.h @@ -0,0 +1,30 @@ +/* + * Copyright 2018-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef NXP_SMMU_H +#define NXP_SMMU_H + +#define SMMU_SCR0 (0x0) +#define SMMU_NSCR0 (0x400) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 + +static inline void bypass_smmu(uintptr_t smmu_base_addr) +{ + uint32_t val; + + val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) & + ~(SCR0_USFCFG_MASK); + mmio_write_32((smmu_base_addr + SMMU_SCR0), val); + + val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & + ~(SCR0_USFCFG_MASK); + mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); +} + +#endif diff --git a/include/drivers/rambus/trng_ip_76.h b/include/drivers/rambus/trng_ip_76.h new file mode 100644 index 0000000000..6de8fc73e4 --- /dev/null +++ b/include/drivers/rambus/trng_ip_76.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, Marvell Technology Group Ltd. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef __TRNG_IP_76_H__ +#define __TRNG_IP_76_H__ + +#include <stdbool.h> +#include <stdint.h> + +int32_t eip76_rng_read_rand_buf(void *data, bool wait); +int32_t eip76_rng_probe(uintptr_t base_addr); +int32_t eip76_rng_get_random(uint8_t *data, uint32_t len); + +#endif /* __TRNG_IP_76_H__ */ |