diff options
Diffstat (limited to 'drivers/renesas')
-rw-r--r-- | drivers/renesas/rcar/scif/scif.S | 176 |
1 files changed, 88 insertions, 88 deletions
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S index ae26cc4023..beb8dd8383 100644 --- a/drivers/renesas/rcar/scif/scif.S +++ b/drivers/renesas/rcar/scif/scif.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,43 +9,43 @@ #include <console_macros.S> #include <drivers/renesas/rcar/console/console.h> -#define SCIF_INTERNAL_CLK 0 -#define SCIF_EXTARNAL_CLK 1 -#define SCIF_CLK SCIF_INTERNAL_CLK +#define SCIF_INTERNAL_CLK 0 +#define SCIF_EXTARNAL_CLK 1 +#define SCIF_CLK SCIF_INTERNAL_CLK /* product register */ -#define PRR (0xFFF00044) -#define PRR_PRODUCT_MASK (0x00007F00) -#define PRR_CUT_MASK (0x000000FF) -#define PRR_PRODUCT_H3_VER_10 (0x00004F00) -#define PRR_PRODUCT_E3 (0x00005700) -#define PRR_PRODUCT_D3 (0x00005800) +#define PRR (0xFFF00044) +#define PRR_PRODUCT_MASK (0x00007F00) +#define PRR_CUT_MASK (0x000000FF) +#define PRR_PRODUCT_H3_VER_10 (0x00004F00) +#define PRR_PRODUCT_E3 (0x00005700) +#define PRR_PRODUCT_D3 (0x00005800) /* module stop */ -#define CPG_BASE (0xE6150000) -#define CPG_SMSTPCR2 (0x0138) -#define CPG_SMSTPCR3 (0x013C) +#define CPG_BASE (0xE6150000) +#define CPG_SMSTPCR2 (0x0138) +#define CPG_SMSTPCR3 (0x013C) #define CPG_MSTPSR2 (0x0040) -#define CPG_MSTPSR3 (0x0048) -#define MSTP207 (1 << 7) -#define MSTP310 (1 << 10) -#define CPG_CPGWPR (0x0900) +#define CPG_MSTPSR3 (0x0048) +#define MSTP207 (1 << 7) +#define MSTP310 (1 << 10) +#define CPG_CPGWPR (0x0900) /* scif */ -#define SCIF0_BASE (0xE6E60000) -#define SCIF2_BASE (0xE6E88000) -#define SCIF_SCSMR (0x00) -#define SCIF_SCBRR (0x04) -#define SCIF_SCSCR (0x08) -#define SCIF_SCFTDR (0x0C) -#define SCIF_SCFSR (0x10) -#define SCIF_SCFRDR (0x14) -#define SCIF_SCFCR (0x18) -#define SCIF_SCFDR (0x1C) -#define SCIF_SCSPTR (0x20) -#define SCIF_SCLSR (0x24) -#define SCIF_DL (0x30) -#define SCIF_CKS (0x34) +#define SCIF0_BASE (0xE6E60000) +#define SCIF2_BASE (0xE6E88000) +#define SCIF_SCSMR (0x00) +#define SCIF_SCBRR (0x04) +#define SCIF_SCSCR (0x08) +#define SCIF_SCFTDR (0x0C) +#define SCIF_SCFSR (0x10) +#define SCIF_SCFRDR (0x14) +#define SCIF_SCFCR (0x18) +#define SCIF_SCFDR (0x1C) +#define SCIF_SCSPTR (0x20) +#define SCIF_SCLSR (0x24) +#define SCIF_DL (0x30) +#define SCIF_CKS (0x34) #if RCAR_LSI == RCAR_V3M #define SCIF_BASE SCIF0_BASE @@ -60,70 +60,71 @@ #endif /* mode pin */ -#define RST_MODEMR (0xE6160060) -#define MODEMR_MD12 (0x00001000) +#define RST_MODEMR (0xE6160060) +#define MODEMR_MD12 (0x00001000) -#define SCSMR_CA_MASK (1 << 7) -#define SCSMR_CA_ASYNC (0x0000) -#define SCSMR_CHR_MASK (1 << 6) -#define SCSMR_CHR_8 (0x0000) -#define SCSMR_PE_MASK (1 << 5) -#define SCSMR_PE_DIS (0x0000) -#define SCSMR_STOP_MASK (1 << 3) -#define SCSMR_STOP_1 (0x0000) -#define SCSMR_CKS_MASK (3 << 0) -#define SCSMR_CKS_DIV1 (0x0000) -#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \ +#define SCSMR_CA_MASK (1 << 7) +#define SCSMR_CA_ASYNC (0x0000) +#define SCSMR_CHR_MASK (1 << 6) +#define SCSMR_CHR_8 (0x0000) +#define SCSMR_PE_MASK (1 << 5) +#define SCSMR_PE_DIS (0x0000) +#define SCSMR_STOP_MASK (1 << 3) +#define SCSMR_STOP_1 (0x0000) +#define SCSMR_CKS_MASK (3 << 0) +#define SCSMR_CKS_DIV1 (0x0000) +#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \ SCSMR_CHR_8 + \ SCSMR_PE_DIS + \ SCSMR_STOP_1 + \ SCSMR_CKS_DIV1) -#define SCBRR_115200BPS (17) -#define SCBRR_115200BPSON (16) -#define SCBRR_115200BPS_E3_SSCG (15) -#define SCBRR_230400BPS (8) +#define SCBRR_115200BPS (17) +#define SCBRR_115200BPSON (16) +#define SCBRR_115200BPS_E3_SSCG (15) +#define SCBRR_230400BPS (8) -#define SCSCR_TE_MASK (1 << 5) -#define SCSCR_TE_DIS (0x0000) -#define SCSCR_TE_EN (0x0020) -#define SCSCR_RE_MASK (1 << 4) -#define SCSCR_RE_DIS (0x0000) -#define SCSCR_RE_EN (0x0010) -#define SCSCR_CKE_MASK (3 << 0) -#define SCSCR_CKE_INT (0x0000) -#define SCSCR_CKE_BRG (0x0002) +#define SCSCR_TE_MASK (1 << 5) +#define SCSCR_TE_DIS (0x0000) +#define SCSCR_TE_EN (0x0020) +#define SCSCR_RE_MASK (1 << 4) +#define SCSCR_RE_DIS (0x0000) +#define SCSCR_RE_EN (0x0010) +#define SCSCR_CKE_MASK (3 << 0) +#define SCSCR_CKE_INT (0x0000) +#define SCSCR_CKE_BRG (0x0002) #if SCIF_CLK == SCIF_EXTARNAL_CLK -#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG) +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG) #else -#define SCFSR_TEND_MASK (1 << 6) -#define SCFSR_TEND_TRANS_END (0x0040) -#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT) +#define SCFSR_TEND_MASK (1 << 6) +#define SCFSR_TEND_TRANS_END (0x0040) +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT) #endif -#define SCFSR_INIT_DATA (0x0000) -#define SCFCR_TTRG_MASK (3 << 4) -#define SCFCR_TTRG_8 (0x0000) -#define SCFCR_TTRG_0 (0x0030) -#define SCFCR_TFRST_MASK (1 << 2) -#define SCFCR_TFRST_DIS (0x0000) -#define SCFCR_TFRST_EN (0x0004) -#define SCFCR_RFRS_MASK (1 << 1) -#define SCFCR_RFRS_DIS (0x0000) -#define SCFCR_RFRS_EN (0x0002) -#define SCFCR_INIT_DATA (SCFCR_TTRG_8) -#define SCFDR_T_MASK (0x1f << 8) -#define DL_INIT_DATA (8) -#define CKS_CKS_DIV_MASK (1 << 15) -#define CKS_CKS_DIV_CLK (0x0000) -#define CKS_XIN_MASK (1 << 14) -#define CKS_XIN_SCIF_CLK (0x0000) -#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK) +#define SCFSR_INIT_DATA (0x0000) +#define SCFCR_TTRG_MASK (3 << 4) +#define SCFCR_TTRG_8 (0x0000) +#define SCFCR_TTRG_0 (0x0030) +#define SCFCR_TFRST_MASK (1 << 2) +#define SCFCR_TFRST_DIS (0x0000) +#define SCFCR_TFRST_EN (0x0004) +#define SCFCR_RFRS_MASK (1 << 1) +#define SCFCR_RFRS_DIS (0x0000) +#define SCFCR_RFRS_EN (0x0002) +#define SCFCR_INIT_DATA (SCFCR_TTRG_8) +#define SCFDR_T_MASK (0x1f << 8) +#define DL_INIT_DATA (8) +#define CKS_CKS_DIV_MASK (1 << 15) +#define CKS_CKS_DIV_CLK (0x0000) +#define CKS_XIN_MASK (1 << 14) +#define CKS_XIN_SCIF_CLK (0x0000) +#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK) .globl console_rcar_register .globl console_rcar_init .globl console_rcar_putc .globl console_rcar_flush - /* ----------------------------------------------- + /* + * ----------------------------------------------- * int console_rcar_register( * uintptr_t base, uint32_t clk, uint32_t baud, * console_t *console) @@ -154,7 +155,7 @@ register_fail: ret x7 endfunc console_rcar_register - /* ----------------------------------------------- + /* * int console_rcar_init(unsigned long base_addr, * unsigned int uart_clk, unsigned int baud_rate) * Function to initialize the console without a @@ -166,7 +167,6 @@ endfunc console_rcar_register * w2 - Baud rate * Out: return 1 on success * Clobber list : x1, x2 - * ----------------------------------------------- */ func console_rcar_init ldr x0, =CPG_BASE @@ -188,8 +188,10 @@ func console_rcar_init ldrh w1, [x0, #SCIF_SCFCR] orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN) strh w1, [x0, #SCIF_SCFCR] - /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER - in SCLSR, then clear them to 0 */ + /* + * Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER + * in SCLSR, then clear them to 0 + */ mov w1, #SCFSR_INIT_DATA strh w1, [x0, #SCIF_SCFSR] mov w1, #0 @@ -265,7 +267,7 @@ func console_rcar_init ret endfunc console_rcar_init - /* -------------------------------------------------------- + /* * int console_rcar_putc(int c, unsigned int base_addr) * Function to output a character over the console. It * returns the character printed on success or -1 on error. @@ -273,7 +275,6 @@ endfunc console_rcar_init * x1 - pointer to console_t structure * Out : return -1 on error else return character. * Clobber list : x2 - * -------------------------------------------------------- */ func console_rcar_putc ldr x1, =SCIF_BASE @@ -304,12 +305,11 @@ func console_rcar_putc ret endfunc console_rcar_putc - /* --------------------------------------------- + /* * void console_rcar_flush(void) * Function to force a write of all buffered * data that hasn't been output. It returns void * Clobber list : x0, x1 - * --------------------------------------------- */ func console_rcar_flush ldr x0, =SCIF_BASE |