diff options
Diffstat (limited to 'drivers/renesas')
26 files changed, 383 insertions, 149 deletions
diff --git a/drivers/renesas/common/common.c b/drivers/renesas/common/common.c index 9b7c1eb16c..a0aa4808d6 100644 --- a/drivers/renesas/common/common.c +++ b/drivers/renesas/common/common.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <lib/mmio.h> +#include "cpg_registers.h" #include "rcar_private.h" #if IMAGE_BL31 @@ -16,7 +17,7 @@ void cpg_write(uintptr_t regadr, uint32_t regval) { uint32_t value = regval; - mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value); + mmio_write_32(CPG_CPGWPR, ~value); mmio_write_32(regadr, value); } diff --git a/drivers/renesas/common/console/rcar_console.S b/drivers/renesas/common/console/rcar_console.S index 29baa67a4a..b683d7bfb9 100644 --- a/drivers/renesas/common/console/rcar_console.S +++ b/drivers/renesas/common/console/rcar_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,7 +63,7 @@ endfunc console_rcar_register * --------------------------------------------- */ func console_rcar_init - mov w0, #0 + mov w0, #1 ret endfunc console_rcar_init diff --git a/drivers/renesas/common/console/rcar_printf.c b/drivers/renesas/common/console/rcar_printf.c index ad074fe059..6af10eeca2 100644 --- a/drivers/renesas/common/console/rcar_printf.c +++ b/drivers/renesas/common/console/rcar_printf.c @@ -24,7 +24,7 @@ /* * The log is initialized and used before BL31 xlat tables are initialized, * therefore the log memory is a device memory at that point. Make sure the - * memory is correclty aligned and accessed only with up-to 32bit, aligned, + * memory is correctly aligned and accessed only with up-to 32bit, aligned, * writes. */ CASSERT((RCAR_BL31_LOG_BASE & 0x7) == 0, assert_bl31_log_base_unaligned); diff --git a/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c index a49510ed5d..f0113f1110 100644 --- a/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c +++ b/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -11,7 +11,11 @@ #include "rcar_def.h" #include "../ddr_regs.h" -#define RCAR_DDR_VERSION "rev.0.01" +#define RCAR_DDR_VERSION "rev.0.02" + +/* Average periodic refresh interval[ns]. Support 3900,7800 */ +#define REFRESH_RATE 3900 + #if RCAR_LSI != RCAR_D3 #error "Don't have DDR initialize routine." @@ -44,7 +48,7 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBTR16, 0x09210507); mmio_write_32(DBSC_DBTR17, 0x040E0000); mmio_write_32(DBSC_DBTR18, 0x00000200); - mmio_write_32(DBSC_DBTR19, 0x012B004B); + mmio_write_32(DBSC_DBTR19, 0x0129004B); mmio_write_32(DBSC_DBTR20, 0x020000FB); mmio_write_32(DBSC_DBTR21, 0x00040004); mmio_write_32(DBSC_DBBL, 0x00000000); @@ -54,8 +58,8 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); - mmio_write_32(DBSC_SCFCTST0, 0x0D020D04); - mmio_write_32(DBSC_SCFCTST1, 0x0306040C); + mmio_write_32(DBSC_SCFCTST0, 0x0C050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0305030C); mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); @@ -101,7 +105,9 @@ static void init_ddr_d3_1866(void) ; mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89); + mmio_write_32(DBSC_DBPDRGD_0, + (uint32_t) (REFRESH_RATE * 928 / 125) - 400 + + 0x0A300000); mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); @@ -117,7 +123,11 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0); + if (REFRESH_RATE > 3900) { + mmio_write_32(DBSC_DBPDRGD_0, 0x00000020); + } else { + mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0); + } mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); @@ -225,8 +235,10 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); r2 = mmio_read_32(DBSC_DBPDRGD_0); mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); @@ -296,8 +308,10 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - mmio_write_32(DBSC_DBCALCNF, 0x0100401B); - mmio_write_32(DBSC_DBRFCNF1, 0x00080E23); + mmio_write_32(DBSC_DBCALCNF, + (uint32_t) (64000000 / REFRESH_RATE) + 0x01000000); + mmio_write_32(DBSC_DBRFCNF1, + (uint32_t) (REFRESH_RATE * 116 / 125) + 0x00080000); mmio_write_32(DBSC_DBRFCNF2, 0x00010000); mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); @@ -346,6 +360,19 @@ static void init_ddr_d3_1600(void) { uint32_t i, r2, r3, r5, r6, r7, r12; + mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); + mmio_write_32(CPG_CPGWPCR, 0xA5A50000); + + mmio_write_32(CPG_SRCR4, 0x20000000); + + mmio_write_32(0xE61500DC, 0xe2200000); + while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) + ; + + mmio_write_32(CPG_SRSTCLR4, 0x20000000); + + mmio_write_32(CPG_CPGWPCR, 0xA5A50001); + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); mmio_write_32(DBSC_DBKIND, 0x00000007); mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); @@ -363,14 +390,14 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBTR10, 0x0000000C); mmio_write_32(DBSC_DBTR11, 0x0000000A); mmio_write_32(DBSC_DBTR12, 0x00120012); - mmio_write_32(DBSC_DBTR13, 0x000000D0); + mmio_write_32(DBSC_DBTR13, 0x000000CE); mmio_write_32(DBSC_DBTR14, 0x00140005); mmio_write_32(DBSC_DBTR15, 0x00050004); mmio_write_32(DBSC_DBTR16, 0x071F0305); mmio_write_32(DBSC_DBTR17, 0x040C0000); mmio_write_32(DBSC_DBTR18, 0x00000200); mmio_write_32(DBSC_DBTR19, 0x01000040); - mmio_write_32(DBSC_DBTR20, 0x020000D8); + mmio_write_32(DBSC_DBTR20, 0x020000D6); mmio_write_32(DBSC_DBTR21, 0x00040004); mmio_write_32(DBSC_DBBL, 0x00000000); mmio_write_32(DBSC_DBODT0, 0x00000001); @@ -379,8 +406,8 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); - mmio_write_32(DBSC_SCFCTST0, 0x0D020C04); - mmio_write_32(DBSC_SCFCTST1, 0x0305040C); + mmio_write_32(DBSC_SCFCTST0, 0x0D050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0306030C); mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); @@ -426,13 +453,14 @@ static void init_ddr_d3_1600(void) ; mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0); + mmio_write_32(DBSC_DBPDRGD_0, + (uint32_t) (REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); @@ -442,7 +470,11 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD_0, 0x00000098); + if (REFRESH_RATE > 3900) { + mmio_write_32(DBSC_DBPDRGD_0, 0x00000018); + } else { + mmio_write_32(DBSC_DBPDRGD_0, 0x00000098); + } mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); @@ -549,9 +581,11 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); @@ -620,8 +654,10 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - mmio_write_32(DBSC_DBCALCNF, 0x0100401B); - mmio_write_32(DBSC_DBRFCNF1, 0x00080C30); + mmio_write_32(DBSC_DBCALCNF, + (uint32_t) (64000000 / REFRESH_RATE) + 0x01000000); + mmio_write_32(DBSC_DBRFCNF1, + (uint32_t) (REFRESH_RATE * 99 / 125) + 0x00080000); mmio_write_32(DBSC_DBRFCNF2, 0x00010000); mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); @@ -693,7 +729,7 @@ int32_t rcar_dram_init(void) ddr_mbps = 1600; } - NOTICE("BL2: DDR%d\n", ddr_mbps); + NOTICE("BL2: DDR%d(%s)\n", ddr_mbps, RCAR_DDR_VERSION); return 0; } diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c index aa3bc245b7..3f6a9484de 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -1180,6 +1180,11 @@ static void regif_pll_wa(void) ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_TOP_PLL_CTRL )); + if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_LOW_FREQ_SEL)) { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_LOW_FREQ_SEL), + _cnf_DDR_PHY_ADR_G_REGSET[0x7f & ddr_regdef_adr( + _reg_PHY_LP4_BOOT_LOW_FREQ_SEL)]); + } } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), @@ -2856,6 +2861,16 @@ static uint32_t pll3_freq(uint32_t on) timeout = wait_freqchgreq(1); + if ((!((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))) && (on)) { + if (((1600U * ddr_mbpsdiv) < ddr_mbps) || (prr_product == PRR_PRODUCT_M3)) { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x01421142U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000142U); + } else { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x03421342U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000342U); + } + } + if (timeout) { return 1; } @@ -4147,7 +4162,13 @@ int32_t rcar_dram_init(void) } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ - data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; + data_l = mmio_read_32(THS1_THCTR); + if (data_l & 0x00000040U) { + data_l = data_l & 0xFFFFFFBEU; + } else { + data_l = data_l | BIT(1); + } + mmio_write_32(THS1_THCTR, data_l); /* Judge product and cut */ diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c index 45b6b088c1..bbb0200866 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c @@ -12,6 +12,9 @@ #if (RZG_SOC == 1) #define BOARDNUM 4 #else + +#include <board.h> + #define BOARDNUM 22 #endif /* RZG_SOC == 1 */ #define BOARD_JUDGE_AUTO @@ -1967,6 +1970,44 @@ static uint32_t rzg2_board_judge(void) } #endif /* RZG_SOC == 1 */ +#if (RZG_SOC == 0) && (RCAR_DRAM_LPDDR4_MEMCONF != 0) +static uint32_t ddr_rank_judge(void) +{ + uint32_t brd; + +#if (RCAR_DRAM_MEMRANK == 0) + int32_t ret; + uint32_t type = 0U; + uint32_t rev = 0U; + + brd = 99U; + ret = rcar_get_board_type(&type, &rev); + if ((ret == 0) && (rev != 0xFFU)) { + if (type == (uint32_t)BOARD_SALVATOR_XS) { + if (rev == 0x11U) { + brd = 14U; + } else { + brd = 8U; + } + } else if (type == (uint32_t)BOARD_STARTER_KIT_PRE) { + if (rev == 0x21U) { + brd = 14U; + } else { + brd = 8U; + } + } + } +#elif (RCAR_DRAM_MEMRANK == 1) + brd = 14U; +#elif (RCAR_DRAM_MEMRANK == 2) + brd = 8U; +#else +#error Invalid value was set to RCAR_DRAM_MEMRANK +#endif /* (RCAR_DRAM_MEMRANK == 0) */ + return brd; +} +#endif /* (RCAR_DRAM_LPDDR4_MEMCONF != 0) */ + static uint32_t _board_judge(void) { uint32_t brd; @@ -1985,7 +2026,7 @@ static uint32_t _board_judge(void) #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) brd = 7; #else - brd = 8; + brd = ddr_rank_judge(); #endif } } else if (prr_product == PRR_PRODUCT_M3) { @@ -2039,7 +2080,7 @@ static uint32_t _board_judge(void) #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) brd = 7; #else - brd = 8; + brd = ddr_rank_judge(); #endif } } else if (prr_product == PRR_PRODUCT_M3N) { diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h index 56363eb997..328adbfe4c 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_DDR_VERSION "rev.0.40" +#define RCAR_DDR_VERSION "rev.0.42" #define DRAM_CH_CNT 0x04 #define SLICE_CNT 0x04 #define CS_CNT 0x02 diff --git a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h index e5258af6c6..5a662ec313 100644 --- a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h +++ b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -230,8 +230,8 @@ static const uint32_t /*0693*/ 0x00000000, /*0694*/ 0x00000000, /*0695*/ 0x00005064, - /*0696*/ 0x01421142, - /*0697*/ 0x00000142, + /*0696*/ 0x05421542, + /*0697*/ 0x00000542, /*0698*/ 0x00000000, /*0699*/ 0x000f1100, /*069a*/ 0x0f110f11, @@ -240,12 +240,12 @@ static const uint32_t /*069d*/ 0x0002c000, /*069e*/ 0x02c002c0, /*069f*/ 0x000002c0, - /*06a0*/ 0x03421342, - /*06a1*/ 0x00000342, + /*06a0*/ 0x05421542, + /*06a1*/ 0x00000542, /*06a2*/ 0x00000000, /*06a3*/ 0x00000000, /*06a4*/ 0x05020000, - /*06a5*/ 0x14000000, + /*06a5*/ 0x14000001, /*06a6*/ 0x027f6e00, /*06a7*/ 0x047f027f, /*06a8*/ 0x00027f6e, diff --git a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h index b491f0e917..482a2a5ce7 100644 --- a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h +++ b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -210,8 +210,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = { /*0b8b*/ 0x01010100, /*0b8c*/ 0x00000600, /*0b8d*/ 0x50640000, - /*0b8e*/ 0x01421142, - /*0b8f*/ 0x00000142, + /*0b8e*/ 0x03421342, + /*0b8f*/ 0x00000342, /*0b90*/ 0x00000000, /*0b91*/ 0x000f1600, /*0b92*/ 0x0f160f16, diff --git a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h index fb3032deeb..436c1a0bb1 100644 --- a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h +++ b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -230,8 +230,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { /*0b93*/ 0x00000000, /*0b94*/ 0x00000000, /*0b95*/ 0x00005064, - /*0b96*/ 0x01421142, - /*0b97*/ 0x00000142, + /*0b96*/ 0x05421542, + /*0b97*/ 0x00000542, /*0b98*/ 0x00000000, /*0b99*/ 0x000f1600, /*0b9a*/ 0x0f160f16, @@ -241,12 +241,12 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { /*0b9e*/ 0x02c002c0, /*0b9f*/ 0x000002c0, /*0ba0*/ 0x08040201, - /*0ba1*/ 0x03421342, - /*0ba2*/ 0x00000342, + /*0ba1*/ 0x05421542, + /*0ba2*/ 0x00000542, /*0ba3*/ 0x00000000, /*0ba4*/ 0x00000000, /*0ba5*/ 0x05030000, - /*0ba6*/ 0x00010700, + /*0ba6*/ 0x00010701, /*0ba7*/ 0x00000014, /*0ba8*/ 0x00027f6e, /*0ba9*/ 0x047f027f, diff --git a/drivers/renesas/common/emmc/emmc_cmd.c b/drivers/renesas/common/emmc/emmc_cmd.c index d255bffc9f..02fc26bba9 100644 --- a/drivers/renesas/common/emmc/emmc_cmd.c +++ b/drivers/renesas/common/emmc/emmc_cmd.c @@ -254,8 +254,7 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); state = ESTATE_ISSUE_CMD; - /* through */ - + /* fallthrough */ case ESTATE_ISSUE_CMD: /* ARG */ SETR_32(SD_ARG, mmc_drv_obj.cmd_info.arg); @@ -454,8 +453,8 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) SETR_32(SD_STOP, 0x00000000U); mmc_drv_obj.during_dma_transfer = FALSE; } - /* through */ + /* fallthrough */ case ESTATE_ERROR: if (err_not_care_flag == TRUE) { mmc_drv_obj.during_cmd_processing = FALSE; diff --git a/drivers/renesas/common/emmc/emmc_hal.h b/drivers/renesas/common/emmc/emmc_hal.h index 0a8551719f..4e6942fafd 100644 --- a/drivers/renesas/common/emmc/emmc_hal.h +++ b/drivers/renesas/common/emmc/emmc_hal.h @@ -512,7 +512,7 @@ typedef struct { /* maximum block count which can be transferred at once */ uint32_t max_block_count; - /* maximum clock frequence in Hz supported by HW */ + /* maximum clock frequency in Hz supported by HW */ uint32_t max_clock_freq; /* maximum data bus width supported by HW */ diff --git a/drivers/renesas/common/emmc/emmc_init.c b/drivers/renesas/common/emmc/emmc_init.c index 354aa3c82a..c0ec600f5f 100644 --- a/drivers/renesas/common/emmc/emmc_init.c +++ b/drivers/renesas/common/emmc/emmc_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ #include "emmc_registers.h" #include "emmc_def.h" #include "rcar_private.h" +#include "cpg_registers.h" st_mmc_base mmc_drv_obj; @@ -87,11 +88,11 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void) SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */ - dataL = mmio_read_32(CPG_SMSTPCR3); + dataL = mmio_read_32(SMSTPCR3); if ((dataL & CPG_MSTP_MMC) == 0U) { dataL |= (CPG_MSTP_MMC); mmio_write_32(CPG_CPGWPR, (~dataL)); - mmio_write_32(CPG_SMSTPCR3, dataL); + mmio_write_32(SMSTPCR3, dataL); } return result; @@ -100,7 +101,7 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void) static EMMC_ERROR_CODE emmc_dev_init(void) { /* Enable clock supply to eMMC. */ - mstpcr_write(CPG_SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC); + mstpcr_write(SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC); /* Set SD clock */ mmio_write_32(CPG_CPGWPR, ~((uint32_t) (BIT9 | BIT0))); /* SD phy 200MHz */ diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h index 7fae5e4063..67d285d0a0 100644 --- a/drivers/renesas/common/emmc/emmc_registers.h +++ b/drivers/renesas/common/emmc/emmc_registers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,19 +50,6 @@ #define BIT30 (0x40000000U) #define BIT31 (0x80000000U) -/* Clock Pulse Generator (CPG) registers */ -#define CPG_BASE (0xE6150000U) -/* Module stop status register 3 */ -#define CPG_MSTPSR3 (CPG_BASE + 0x0048U) -/* System module stop control register 3 */ -#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU) -/* SDHI2 clock frequency control register */ -#define CPG_SD2CKCR (CPG_BASE + 0x0268U) -/* SDHI3 clock frequency control register */ -#define CPG_SD3CKCR (CPG_BASE + 0x026CU) -/* CPG Write Protect Register */ -#define CPG_CPGWPR (CPG_BASE + 0x0900U) - #if USE_MMC_CH == MMC_CH0 #define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */ #else /* USE_MMC_CH == MMC_CH0 */ diff --git a/drivers/renesas/common/iic_dvfs/iic_dvfs.c b/drivers/renesas/common/iic_dvfs/iic_dvfs.c index e1c9a5bd4d..bf80697285 100644 --- a/drivers/renesas/common/iic_dvfs/iic_dvfs.c +++ b/drivers/renesas/common/iic_dvfs/iic_dvfs.c @@ -517,7 +517,7 @@ RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data) uint32_t err = 0U; mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS); - mmio_write_8(IIC_DVFS_REG_ICCR, 0U); + mmio_write_8(IIC_DVFS_REG_ICCR, 1U); again: switch (state) { case DVFS_START: @@ -557,7 +557,7 @@ RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data) uint32_t err = 0U; mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS); - mmio_write_8(IIC_DVFS_REG_ICCR, 0U); + mmio_write_8(IIC_DVFS_REG_ICCR, 1U); again: switch (state) { case DVFS_START: diff --git a/drivers/renesas/common/io/io_rcar.c b/drivers/renesas/common/io/io_rcar.c index c3e8319de4..66662c111f 100644 --- a/drivers/renesas/common/io/io_rcar.c +++ b/drivers/renesas/common/io/io_rcar.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -84,6 +84,29 @@ typedef struct { #define RCAR_COUNT_LOAD_BL33 (2U) #define RCAR_COUNT_LOAD_BL33X (3U) +#define CHECK_IMAGE_AREA_CNT (7U) +#define BOOT_BL2_ADDR (0xE6304000U) +#define BOOT_BL2_LENGTH (0x19000U) + +typedef struct { + uintptr_t dest; + uintptr_t length; +} addr_loaded_t; + +static addr_loaded_t addr_loaded[CHECK_IMAGE_AREA_CNT] = { + [0] = {BOOT_BL2_ADDR, BOOT_BL2_LENGTH}, + [1] = {BL31_BASE, RCAR_TRUSTED_SRAM_SIZE}, +#ifndef SPD_NONE + [2] = {BL32_BASE, BL32_SIZE} +#endif +}; + +#ifndef SPD_NONE +static uint32_t addr_loaded_cnt = 3; +#else +static uint32_t addr_loaded_cnt = 2; +#endif + static const plat_rcar_name_offset_t name_offset[] = { {BL31_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(0, 0, 0)}, @@ -151,6 +174,9 @@ int32_t rcar_get_certificate(const int32_t name, uint32_t *cert) return -EINVAL; } +#define MFISBTSTSR (0xE6260604U) +#define MFISBTSTSR_BOOT_PARTITION (0x00000010U) + static int32_t file_to_offset(const int32_t name, uintptr_t *offset, uint32_t *cert, uint32_t *no_load, uintptr_t *partition) @@ -169,6 +195,9 @@ static int32_t file_to_offset(const int32_t name, uintptr_t *offset, } *offset = rcar_image_header[addr]; + + if (mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) + *offset += 0x800000; *cert = RCAR_CERT_SIZE; *cert *= RCAR_ATTR_GET_CERTOFF(name_offset[i].attr); *cert += RCAR_SDRAM_certESS; @@ -238,8 +267,16 @@ void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *dst) dstl = cert + RCAR_CERT_INFO_DST_OFFSET; break; } + val = mmio_read_32(size); + if (val > (UINT32_MAX / 4)) { + ERROR("BL2: %s[%d] uint32 overflow!\n", + __func__, __LINE__); + *dst = 0; + *len = 0; + return; + } - *len = mmio_read_32(size) * 4U; + *len = val * 4U; dsth = dstl + 4U; *dst = ((uintptr_t) mmio_read_32(dsth) << 32) + ((uintptr_t) mmio_read_32(dstl)); @@ -247,7 +284,14 @@ void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *dst) } size = cert + RCAR_CERT_INFO_SIZE_OFFSET; - *len = mmio_read_32(size) * 4U; + val = mmio_read_32(size); + if (val > (UINT32_MAX / 4)) { + ERROR("BL2: %s[%d] uint32 overflow!\n", __func__, __LINE__); + *dst = 0; + *len = 0; + return; + } + *len = val * 4U; dstl = cert + RCAR_CERT_INFO_DST_OFFSET; dsth = dstl + 4U; *dst = ((uintptr_t) mmio_read_32(dsth) << 32) + @@ -260,17 +304,18 @@ static int32_t check_load_area(uintptr_t dst, uintptr_t len) uintptr_t dram_start, dram_end; uintptr_t prot_start, prot_end; int32_t result = IO_SUCCESS; + int n; - dram_start = legacy ? DRAM1_BASE : DRAM_40BIT_BASE; + dram_start = legacy ? DRAM1_NS_BASE : DRAM_40BIT_BASE; - dram_end = legacy ? DRAM1_BASE + DRAM1_SIZE : + dram_end = legacy ? DRAM1_NS_BASE + DRAM1_NS_SIZE : DRAM_40BIT_BASE + DRAM_40BIT_SIZE; prot_start = legacy ? DRAM_PROTECTED_BASE : DRAM_40BIT_PROTECTED_BASE; prot_end = prot_start + DRAM_PROTECTED_SIZE; - if (dst < dram_start || dst > dram_end - len) { + if (dst < dram_start || len > dram_end || dst > dram_end - len) { ERROR("BL2: dst address is on the protected area.\n"); result = IO_FAIL; goto done; @@ -280,12 +325,54 @@ static int32_t check_load_area(uintptr_t dst, uintptr_t len) if (dst >= prot_start && dst < prot_end) { ERROR("BL2: dst address is on the protected area.\n"); result = IO_FAIL; + goto done; } - if (dst < prot_start && dst > prot_start - len) { - ERROR("BL2: loaded data is on the protected area.\n"); + if (len > prot_start || (dst < prot_start && dst > prot_start - len)) { + ERROR("BL2: %s[%d] loaded data is on the protected area.\n", + __func__, __LINE__); result = IO_FAIL; + goto done; + } + + if (addr_loaded_cnt >= CHECK_IMAGE_AREA_CNT) { + ERROR("BL2: max loadable non secure images reached\n"); + result = IO_FAIL; + goto done; } + + addr_loaded[addr_loaded_cnt].dest = dst; + addr_loaded[addr_loaded_cnt].length = len; + for (n = 0; n < addr_loaded_cnt; n++) { + /* + * Check if next image invades a previous loaded image + * + * IMAGE n: area from previous image: dest| IMAGE n |length + * IMAGE n+1: area from next image: dst | IMAGE n |len + * + * 1. check: + * | IMAGE n | + * | IMAGE n+1 | + * 2. check: + * | IMAGE n | + * | IMAGE n+1 | + * 3. check: + * | IMAGE n | + * | IMAGE n+1 | + */ + if (((dst >= addr_loaded[n].dest) && + (dst <= addr_loaded[n].dest + addr_loaded[n].length)) || + ((dst + len >= addr_loaded[n].dest) && + (dst + len <= addr_loaded[n].dest + addr_loaded[n].length)) || + ((dst <= addr_loaded[n].dest) && + (dst + len >= addr_loaded[n].dest + addr_loaded[n].length))) { + ERROR("BL2: next image overlap a previous image area.\n"); + result = IO_FAIL; + goto done; + } + } + addr_loaded_cnt++; + done: if (result == IO_FAIL) { ERROR("BL2: Out of range : dst=0x%lx len=0x%lx\n", dst, len); @@ -374,7 +461,7 @@ static int32_t load_bl33x(void) static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name) { - uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {0UL}; + static uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {0UL}; uintptr_t handle; ssize_t offset; uint32_t i; @@ -417,35 +504,35 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name) WARN("Firmware Image Package header failed to seek\n"); goto error; } -#if RCAR_BL2_DCACHE == 1 - inv_dcache_range((uint64_t) header, sizeof(header)); -#endif + rc = io_read(handle, (uintptr_t) &header, sizeof(header), &cnt); if (rc != IO_SUCCESS) { WARN("Firmware Image Package header failed to read\n"); goto error; } - rcar_image_number = header[0]; - for (i = 0; i < rcar_image_number + 2; i++) { - rcar_image_header[i] = header[i * 2 + 1]; - rcar_image_header_prttn[i] = header[i * 2 + 2]; - } +#if RCAR_BL2_DCACHE == 1 + inv_dcache_range((uint64_t) header, sizeof(header)); +#endif + rcar_image_number = header[0]; if (rcar_image_number == 0 || rcar_image_number > RCAR_MAX_BL3X_IMAGE) { WARN("Firmware Image Package header check failed.\n"); + rc = IO_FAIL; goto error; } + for (i = 0; i < rcar_image_number + 2; i++) { + rcar_image_header[i] = header[i * 2 + 1]; + rcar_image_header_prttn[i] = header[i * 2 + 2]; + } + rc = io_seek(handle, IO_SEEK_SET, offset + RCAR_SECTOR6_CERT_OFFSET); if (rc != IO_SUCCESS) { WARN("Firmware Image Package header failed to seek cert\n"); goto error; } -#if RCAR_BL2_DCACHE == 1 - inv_dcache_range(RCAR_SDRAM_certESS, - RCAR_CERT_SIZE * (2 + rcar_image_number)); -#endif + rc = io_read(handle, RCAR_SDRAM_certESS, RCAR_CERT_SIZE * (2 + rcar_image_number), &cnt); if (rc != IO_SUCCESS) { @@ -453,6 +540,11 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name) goto error; } +#if RCAR_BL2_DCACHE == 1 + inv_dcache_range(RCAR_SDRAM_certESS, + RCAR_CERT_SIZE * (2 + rcar_image_number)); +#endif + rcar_cert_load = RCAR_CERT_LOAD; error: @@ -506,13 +598,6 @@ static int32_t rcar_file_open(io_dev_info_t *info, const uintptr_t file_spec, rcar_read_certificate((uint64_t) cert, &len, &dst); - /* Baylibre: HACK */ - if (spec->offset == BL31_IMAGE_ID && len < RCAR_TRUSTED_SRAM_SIZE) { - WARN("%s,%s\n", "r-car ignoring the BL31 size from certificate", - "using RCAR_TRUSTED_SRAM_SIZE instead"); - len = RCAR_TRUSTED_SRAM_SIZE; - } - current_file.partition = partition; current_file.no_load = noload; current_file.offset = offset; diff --git a/drivers/renesas/common/pfc_regs.h b/drivers/renesas/common/pfc_regs.h index 418773366c..36084f5502 100644 --- a/drivers/renesas/common/pfc_regs.h +++ b/drivers/renesas/common/pfc_regs.h @@ -146,10 +146,10 @@ #define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U) #define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU) -/* Pin functon base address */ +/* Pin function base address */ #define PFC_BASE (0xE6060000U) -/* Pin functon registers */ +/* Pin function registers */ #define PFC_PMMR (PFC_BASE + 0x0000U) #define PFC_GPSR0 (PFC_BASE + 0x0100U) #define PFC_GPSR1 (PFC_BASE + 0x0104U) diff --git a/drivers/renesas/common/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c index c0f015f04b..b60ccab276 100644 --- a/drivers/renesas/common/pwrc/pwrc.c +++ b/drivers/renesas/common/pwrc/pwrc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,6 +20,7 @@ #include "pwrc.h" #include "rcar_def.h" #include "rcar_private.h" +#include "cpg_registers.h" /* * Someday there will be a generic power controller api. At the moment each @@ -43,6 +44,7 @@ RCAR_INSTANTIATE_LOCK #define CPU_PWR_OFF (0x00000003U) #define RCAR_PSTR_MASK (0x00000003U) #define ST_ALL_STANDBY (0x00003333U) +#define SYSCEXTMASK_EXTMSK0 (0x00000001U) /* Suspend to ram */ #define DBSC4_REG_BASE (0xE6790000U) #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U) @@ -154,7 +156,7 @@ IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END); IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START); #endif -uint32_t rcar_pwrc_status(uint64_t mpidr) +uint32_t rcar_pwrc_status(u_register_t mpidr) { uint32_t ret = 0; uint64_t cm, cpu; @@ -186,10 +188,12 @@ done: return ret; } -static void scu_power_up(uint64_t mpidr) +static void scu_power_up(u_register_t mpidr) { uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer; uint32_t c, sysc_reg_bit; + uint32_t lsi_product; + uint32_t lsi_cut; c = rcar_pwrc_get_mpidr_cluster(mpidr); reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR; @@ -204,6 +208,17 @@ static void scu_power_up(uint64_t mpidr) if (mmio_read_32(reg_cpumcr) != 0) mmio_write_32(reg_cpumcr, 0); + lsi_product = mmio_read_32((uintptr_t)RCAR_PRR); + lsi_cut = lsi_product & PRR_CUT_MASK; + lsi_product &= PRR_PRODUCT_MASK; + + if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) || + lsi_product == PRR_PRODUCT_H3 || + lsi_product == PRR_PRODUCT_M3N || + lsi_product == PRR_PRODUCT_E3) { + mmio_setbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0); + } + mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit); mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit); @@ -215,12 +230,20 @@ static void scu_power_up(uint64_t mpidr) while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0) ; - mmio_write_32(RCAR_SYSCISR, sysc_reg_bit); + mmio_write_32(RCAR_SYSCISCR, sysc_reg_bit); + + if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) || + lsi_product == PRR_PRODUCT_H3 || + lsi_product == PRR_PRODUCT_M3N || + lsi_product == PRR_PRODUCT_E3) { + mmio_clrbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0); + } + while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0) ; } -void rcar_pwrc_cpuon(uint64_t mpidr) +void rcar_pwrc_cpuon(u_register_t mpidr) { uint32_t res_data, on_data; uintptr_t res_reg, on_reg; @@ -238,14 +261,14 @@ void rcar_pwrc_cpuon(uint64_t mpidr) scu_power_up(mpidr); cpu = mpidr & MPIDR_CPU_MASK; on_data = 1 << cpu; - mmio_write_32(RCAR_CPGWPR, ~on_data); + mmio_write_32(CPG_CPGWPR, ~on_data); mmio_write_32(on_reg, on_data); mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu)))); rcar_lock_release(); } -void rcar_pwrc_cpuoff(uint64_t mpidr) +void rcar_pwrc_cpuoff(u_register_t mpidr) { uint32_t c; uintptr_t reg; @@ -260,13 +283,13 @@ void rcar_pwrc_cpuoff(uint64_t mpidr) if (read_mpidr_el1() != mpidr) panic(); - mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF); + mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF); mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF); rcar_lock_release(); } -void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr) +void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr) { uint32_t c, shift_irq, shift_fiq; uintptr_t reg; @@ -281,12 +304,12 @@ void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr) shift_irq = WUP_IRQ_SHIFT + cpu; shift_fiq = WUP_FIQ_SHIFT + cpu; - mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) & - ~((uint32_t) 1 << shift_fiq)); + mmio_clrbits_32(reg, ((uint32_t) 1 << shift_irq) | + ((uint32_t) 1 << shift_fiq)); rcar_lock_release(); } -void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr) +void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr) { uint32_t c, shift_irq, shift_fiq; uintptr_t reg; @@ -301,12 +324,35 @@ void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr) shift_irq = WUP_IRQ_SHIFT + cpu; shift_fiq = WUP_FIQ_SHIFT + cpu; - mmio_write_32(reg, ((uint32_t) 1 << shift_irq) | + mmio_setbits_32(reg, ((uint32_t) 1 << shift_irq) | ((uint32_t) 1 << shift_fiq)); rcar_lock_release(); } -void rcar_pwrc_clusteroff(uint64_t mpidr) +void rcar_pwrc_all_disable_interrupt_wakeup(void) +{ + uint32_t cpu_num; + u_register_t cl, cpu, mpidr; + + const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = { + RCAR_CLUSTER_CA57, + RCAR_CLUSTER_CA53 + }; + + for (cl = 0; cl < PLATFORM_CLUSTER_COUNT; cl++) { + cpu_num = rcar_pwrc_get_cpu_num(cluster[cl]); + for (cpu = 0; cpu < cpu_num; cpu++) { + mpidr = ((cl << MPIDR_AFFINITY_BITS) | cpu); + if (mpidr == rcar_boot_mpidr) { + rcar_pwrc_enable_interrupt_wakeup(mpidr); + } else { + rcar_pwrc_disable_interrupt_wakeup(mpidr); + } + } + } +} + +void rcar_pwrc_clusteroff(u_register_t mpidr) { uint32_t c, product, cut, reg; uintptr_t dst; @@ -753,14 +799,14 @@ void rcar_pwrc_code_copy_to_system_ram(void) memcpy((void *)sram.base, code.base, code.len); flush_dcache_range((uint64_t) sram.base, code.len); + attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE; + ret = xlat_change_mem_attributes(sram.base, sram.len, attr); + assert(ret == 0); + /* Invalidate instruction cache */ plat_invalidate_icache(); dsb(); isb(); - - attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE; - ret = xlat_change_mem_attributes(sram.base, sram.len, attr); - assert(ret == 0); } uint32_t rcar_pwrc_get_cluster(void) @@ -778,7 +824,7 @@ uint32_t rcar_pwrc_get_cluster(void) return RCAR_CLUSTER_A53A57; } -uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr) +uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr) { uint32_t c = rcar_pwrc_get_cluster(); @@ -831,7 +877,7 @@ done: } #endif -int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr) +int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr) { uint64_t i; uint64_t j; diff --git a/drivers/renesas/common/pwrc/pwrc.h b/drivers/renesas/common/pwrc/pwrc.h index f73099b0b5..eefa62ff26 100644 --- a/drivers/renesas/common/pwrc/pwrc.h +++ b/drivers/renesas/common/pwrc/pwrc.h @@ -38,19 +38,22 @@ #define RCAR_CLUSTER_CA53 (1U) #define RCAR_CLUSTER_CA57 (2U) +extern u_register_t rcar_boot_mpidr; + #ifndef __ASSEMBLER__ -void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr); -void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr); -void rcar_pwrc_clusteroff(uint64_t mpidr); -void rcar_pwrc_cpuoff(uint64_t mpidr); -void rcar_pwrc_cpuon(uint64_t mpidr); -int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr); +void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr); +void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr); +void rcar_pwrc_all_disable_interrupt_wakeup(void); +void rcar_pwrc_clusteroff(u_register_t mpidr); +void rcar_pwrc_cpuoff(u_register_t mpidr); +void rcar_pwrc_cpuon(u_register_t mpidr); +int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr); void rcar_pwrc_setup(void); -uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr); -uint32_t rcar_pwrc_status(uint64_t mpidr); +uint32_t rcar_pwrc_get_cpu_wkr(u_register_t mpidr); +uint32_t rcar_pwrc_status(u_register_t mpidr); uint32_t rcar_pwrc_get_cluster(void); -uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr); +uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr); uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type); void rcar_pwrc_restore_timer_state(void); void plat_secondary_reset(void); diff --git a/drivers/renesas/common/rom/rom_api.c b/drivers/renesas/common/rom/rom_api.c index fda28150e9..4eede17ce9 100644 --- a/drivers/renesas/common/rom/rom_api.c +++ b/drivers/renesas/common/rom/rom_api.c @@ -11,7 +11,7 @@ #include "rcar_def.h" #include "rom_api.h" -typedef uint32_t(*rom_secure_boot_api_f) (uint32_t *key, uint32_t *cert, +typedef uint32_t(*rom_secure_boot_api_f) (uint32_t key, uint32_t cert, rom_read_flash_f pFuncReadFlash); typedef uint32_t(*rom_get_lcs_api_f) (uint32_t *lcs); @@ -68,7 +68,7 @@ static uint32_t get_table_index(void) return index; } -uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert, +uint32_t rcar_rom_secure_boot_api(uint32_t key, uint32_t cert, rom_read_flash_f read_flash) { static const uintptr_t rom_api_table[API_TABLE_MAX] = { diff --git a/drivers/renesas/common/rom/rom_api.h b/drivers/renesas/common/rom/rom_api.h index 1d5b03d7f5..4b1008032e 100644 --- a/drivers/renesas/common/rom/rom_api.h +++ b/drivers/renesas/common/rom/rom_api.h @@ -24,7 +24,7 @@ #define LCS_FA (0x7U) typedef uint32_t(*rom_read_flash_f) (uint64_t src, uint8_t *dst, uint32_t len); -uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert, +uint32_t rcar_rom_secure_boot_api(uint32_t key, uint32_t cert, rom_read_flash_f f); uint32_t rcar_rom_get_lcs(uint32_t *lcs); diff --git a/drivers/renesas/common/scif/scif.S b/drivers/renesas/common/scif/scif.S index beb8dd8383..72b5b4bea0 100644 --- a/drivers/renesas/common/scif/scif.S +++ b/drivers/renesas/common/scif/scif.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,7 +79,7 @@ SCSMR_STOP_1 + \ SCSMR_CKS_DIV1) #define SCBRR_115200BPS (17) -#define SCBRR_115200BPSON (16) +#define SCBRR_115200BPS_D3_SSCG (16) #define SCBRR_115200BPS_E3_SSCG (15) #define SCBRR_230400BPS (8) @@ -216,26 +216,38 @@ func console_rcar_init and w1, w1, #PRR_PRODUCT_MASK mov w2, #PRR_PRODUCT_D3 cmp w1, w2 - beq 4f + beq 5f and w1, w1, #PRR_PRODUCT_MASK mov w2, #PRR_PRODUCT_E3 cmp w1, w2 - bne 5f + bne 4f + /* When SSCG(MD12) on (E3) */ ldr x1, =RST_MODEMR ldr w1, [x1] and w1, w1, #MODEMR_MD12 mov w2, #MODEMR_MD12 cmp w1, w2 - bne 5f + bne 4f + /* When SSCG(MD12) on (E3) */ mov w1, #SCBRR_115200BPS_E3_SSCG b 2f 5: - mov w1, #SCBRR_115200BPS + /* In case of D3 */ + ldr x1, =RST_MODEMR + ldr w1, [x1] + and w1, w1, #MODEMR_MD12 + mov w2, #MODEMR_MD12 + cmp w1, w2 + bne 4f + + /* When SSCG(MD12) on (D3) */ + mov w1, #SCBRR_115200BPS_D3_SSCG b 2f 4: - mov w1, #SCBRR_115200BPSON + /* In case of H3/M3/M3N or when SSCG(MD12) is off in E3/D3 */ + mov w1, #SCBRR_115200BPS b 2f 3: mov w1, #SCBRR_230400BPS diff --git a/drivers/renesas/common/watchdog/swdt.c b/drivers/renesas/common/watchdog/swdt.c index 1a351ca175..29ef6f4309 100644 --- a/drivers/renesas/common/watchdog/swdt.c +++ b/drivers/renesas/common/watchdog/swdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -78,7 +78,7 @@ static void swdt_disable(void) void rcar_swdt_init(void) { uint32_t rmsk, sr; -#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RZ_G2E) +#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RZ_G2E) uint32_t reg, val, product_cut, chk_data; reg = mmio_read_32(RCAR_PRR); @@ -96,6 +96,8 @@ void rcar_swdt_init(void) #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E) mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k); +#elif (RCAR_LSI == RCAR_D3) + mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_8p13k); #else val = WTCNT_UPPER_BYTE; diff --git a/drivers/renesas/rcar/board/board.c b/drivers/renesas/rcar/board/board.c index cd194ff9f7..dbbaed659e 100644 --- a/drivers/renesas/rcar/board/board.c +++ b/drivers/renesas/rcar/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights * reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -30,9 +30,9 @@ #define BOARD_CODE_SHIFT (0x03) #define BOARD_ID_UNKNOWN (0xFF) -#define SXS_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } +#define SXS_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define SX_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } -#define SKP_ID { 0x10U, 0x10U, 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } +#define SKP_ID { 0x10U, 0x10U, 0x20U, 0x21U, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define SK_ID { 0x10U, 0x30U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } diff --git a/drivers/renesas/rcar/board/board.h b/drivers/renesas/rcar/board/board.h index 51a8e306fb..23469114f3 100644 --- a/drivers/renesas/rcar/board/board.h +++ b/drivers/renesas/rcar/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights + * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights * reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -11,13 +11,13 @@ #define BOARD_SALVATOR_X (0x00) #define BOARD_KRIEK (0x01) #define BOARD_STARTER_KIT (0x02) +#define BOARD_EAGLE (0x03) #define BOARD_SALVATOR_XS (0x04) +#define BOARD_DRAAK (0x07) #define BOARD_EBISU (0x08) #define BOARD_STARTER_KIT_PRE (0x0B) -#define BOARD_EBISU_4D (0x0DU) -#define BOARD_DRAAK (0x0EU) -#define BOARD_EAGLE (0x0FU) -#define BOARD_UNKNOWN (BOARD_EAGLE + 1U) +#define BOARD_EBISU_4D (0x0D) +#define BOARD_UNKNOWN (BOARD_EBISU_4D + 1U) #define BOARD_REV_UNKNOWN (0xFF) diff --git a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c index 6063758074..5de4f1f655 100644 --- a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c +++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c @@ -12,7 +12,7 @@ #include "rcar_private.h" #include "../pfc_regs.h" -/* Pin functon bit */ +/* Pin function bit */ #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21) #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20) #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19) |